From 2086948a7b06ac238c4ff0c9263c1e578e900fdd Mon Sep 17 00:00:00 2001
From: Sebastian Huber <sebastian.huber@embedded-brains.de>
Date: Fri, 11 May 2018 06:54:59 +0200
Subject: riscv: Add dummy SMP support

Update #3433.
---
 bsps/riscv/riscv/start/start.S | 10 ++++++++++
 1 file changed, 10 insertions(+)

(limited to 'bsps')

diff --git a/bsps/riscv/riscv/start/start.S b/bsps/riscv/riscv/start/start.S
index 58bc57dc12..1d0bde164b 100644
--- a/bsps/riscv/riscv/start/start.S
+++ b/bsps/riscv/riscv/start/start.S
@@ -52,6 +52,11 @@ SYM(_start):
 	la	gp, __global_pointer$
 	.option	pop
 
+#ifdef RTEMS_SMP
+	csrr	s0, mhartid
+	bnez	s0, .Lloop_forever
+#endif
+
 	la	t0, ISR_Handler
 	csrw	mtvec, t0
 
@@ -70,6 +75,11 @@ SYM(_start):
 
 	j	boot_card
 
+#ifdef RTEMS_SMP
+.Lloop_forever:
+	j	.Lloop_forever
+#endif
+
 	.align	4
 bsp_start_vector_table_begin:
 	.word	_RISCV_Exception_default /* User int */
-- 
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