bsps: Move make/custom/* files to bsps

Adjust various build files.  Remove automatic generation of the
c/src/lib/libbsp/*/acinclude.m4 files from bootstrap script.

This patch is a part of the BSP source reorganization.

Update #3285.

13 files changed, 87 insertions, 0 deletions

diff --git a/bsps/v850/gdbv850sim/config/v850e1sim-testsuite.tcfg b/bsps/v850/gdbv850sim/config/v850e1sim-testsuite.tcfg
new file mode 100644
index 0000000000..4bec8f5bbc
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850e1sim-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/bsps/v850/gdbv850sim/config/v850e1sim.cfg b/bsps/v850/gdbv850sim/config/v850e1sim.cfg
new file mode 100644
index 0000000000..7aefdcf31c
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850e1sim.cfg
@@ -0,0 +1,7 @@
+#
+#  Base Config file for the v850 GDB Simulator as v850e1
+#
+
+CPU_CFLAGS = -mv850e1
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/bsps/v850/gdbv850sim/config/v850e2sim-testsuite.tcfg b/bsps/v850/gdbv850sim/config/v850e2sim-testsuite.tcfg
new file mode 100644
index 0000000000..4bec8f5bbc
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850e2sim-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/bsps/v850/gdbv850sim/config/v850e2sim.cfg b/bsps/v850/gdbv850sim/config/v850e2sim.cfg
new file mode 100644
index 0000000000..0313ab82cd
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850e2sim.cfg
@@ -0,0 +1,7 @@
+#
+#  Base Config file for the v850 GDB Simulator as v850e2
+#
+
+CPU_CFLAGS = -mv850e2
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/bsps/v850/gdbv850sim/config/v850e2v3sim-testsuite.tcfg b/bsps/v850/gdbv850sim/config/v850e2v3sim-testsuite.tcfg
new file mode 100644
index 0000000000..4bec8f5bbc
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850e2v3sim-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/bsps/v850/gdbv850sim/config/v850e2v3sim.cfg b/bsps/v850/gdbv850sim/config/v850e2v3sim.cfg
new file mode 100644
index 0000000000..ac2740ed52
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850e2v3sim.cfg
@@ -0,0 +1,7 @@
+#
+#  Base Config file for the v850 GDB Simulator as v850e2v3
+#
+
+CPU_CFLAGS = -mv850e2v3
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/bsps/v850/gdbv850sim/config/v850esim-testsuite.tcfg b/bsps/v850/gdbv850sim/config/v850esim-testsuite.tcfg
new file mode 100644
index 0000000000..4bec8f5bbc
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850esim-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/bsps/v850/gdbv850sim/config/v850esim.cfg b/bsps/v850/gdbv850sim/config/v850esim.cfg
new file mode 100644
index 0000000000..0c0a4a9bed
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850esim.cfg
@@ -0,0 +1,7 @@
+#
+#  Base Config file for the v850 GDB Simulator as v850e
+#
+
+CPU_CFLAGS = -mv850e
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/bsps/v850/gdbv850sim/config/v850essim-testsuite.tcfg b/bsps/v850/gdbv850sim/config/v850essim-testsuite.tcfg
new file mode 100644
index 0000000000..4bec8f5bbc
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850essim-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/bsps/v850/gdbv850sim/config/v850essim.cfg b/bsps/v850/gdbv850sim/config/v850essim.cfg
new file mode 100644
index 0000000000..77594591ec
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850essim.cfg
@@ -0,0 +1,7 @@
+#
+#  Base Config file for the v850 GDB Simulator as v850es
+#
+
+CPU_CFLAGS = -mv850es
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/bsps/v850/gdbv850sim/config/v850sim-testsuite.tcfg b/bsps/v850/gdbv850sim/config/v850sim-testsuite.tcfg
new file mode 100644
index 0000000000..4bec8f5bbc
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850sim-testsuite.tcfg
@@ -0,0 +1,5 @@
+#
+# The simulator does not have a tick interrupt.
+#
+
+include: testdata/require-tick-isr.tcfg
diff --git a/bsps/v850/gdbv850sim/config/v850sim.cfg b/bsps/v850/gdbv850sim/config/v850sim.cfg
new file mode 100644
index 0000000000..9dcc918423
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850sim.cfg
@@ -0,0 +1,8 @@
+#
+#  Base Config file for the v850 GDB Simulator as v850
+#
+
+# This is the same as not specifying a CPU model flag.
+CPU_CFLAGS = -mv850
+
+include $(RTEMS_ROOT)/make/custom/v850sim.inc
diff --git a/bsps/v850/gdbv850sim/config/v850sim.inc b/bsps/v850/gdbv850sim/config/v850sim.inc
new file mode 100644
index 0000000000..8b363ea2ec
--- /dev/null
+++ b/bsps/v850/gdbv850sim/config/v850sim.inc
@@ -0,0 +1,14 @@
+#
+#  Shared config file for the v850 GDB Simulator
+#
+#  CPU_CFLAGS is set by each specific variant.
+
+include $(RTEMS_ROOT)/make/custom/default.cfg
+
+RTEMS_CPU=v850
+
+# optimize flag: typically -O2
+CFLAGS_OPTIMIZE_V = -O2 -g
+CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections
+
+LDFLAGS = -Wl,--gc-sections