diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2023-09-19 14:28:00 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2023-09-26 09:02:48 -0500 |
| commit | 41d43cef6c6d1f41e626c7a45b088f608656ee6a (patch) | |
| tree | 649bb4ad8fa37867729ce77f8fd8bf25f0dbb60b /bsps/shared | |
| parent | bsps/xnandpsu: Don't rely on usleep for polling (diff) | |
| download | rtems-41d43cef6c6d1f41e626c7a45b088f608656ee6a.tar.bz2 | |
bsps/xnandpsu: Ensure buffer cache sync
When a buffer is modified by both hardware components such as DMA and by
software components, the buffer cache state must be kept in sync so that
data is not accidentally thrown away during future invalidations.
Diffstat (limited to 'bsps/shared')
| -rw-r--r-- | bsps/shared/dev/nand/xnandpsu.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/bsps/shared/dev/nand/xnandpsu.c b/bsps/shared/dev/nand/xnandpsu.c index 9e9f8959cf..e140364ce8 100644 --- a/bsps/shared/dev/nand/xnandpsu.c +++ b/bsps/shared/dev/nand/xnandpsu.c @@ -1619,6 +1619,12 @@ s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf) } if (PartialBytes > 0U) { (void)Xil_MemCpy(DestBufPtr, BufPtr + Col, NumBytes); +#ifdef __rtems__ + /* The destination buffer is touched by hardware, synchronize */ + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)(void *)DestBufPtr, NumBytes); + } +#endif } DestBufPtr += NumBytes; OffsetVar += NumBytes; |