From 41d43cef6c6d1f41e626c7a45b088f608656ee6a Mon Sep 17 00:00:00 2001 From: Kinsey Moore Date: Tue, 19 Sep 2023 14:28:00 -0500 Subject: bsps/xnandpsu: Ensure buffer cache sync When a buffer is modified by both hardware components such as DMA and by software components, the buffer cache state must be kept in sync so that data is not accidentally thrown away during future invalidations. --- bsps/shared/dev/nand/xnandpsu.c | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'bsps/shared') diff --git a/bsps/shared/dev/nand/xnandpsu.c b/bsps/shared/dev/nand/xnandpsu.c index 9e9f8959cf..e140364ce8 100644 --- a/bsps/shared/dev/nand/xnandpsu.c +++ b/bsps/shared/dev/nand/xnandpsu.c @@ -1619,6 +1619,12 @@ s32 XNandPsu_Read(XNandPsu *InstancePtr, u64 Offset, u64 Length, u8 *DestBuf) } if (PartialBytes > 0U) { (void)Xil_MemCpy(DestBufPtr, BufPtr + Col, NumBytes); +#ifdef __rtems__ + /* The destination buffer is touched by hardware, synchronize */ + if (InstancePtr->Config.IsCacheCoherent == 0) { + Xil_DCacheFlushRange((INTPTR)(void *)DestBufPtr, NumBytes); + } +#endif } DestBufPtr += NumBytes; OffsetVar += NumBytes; -- cgit v1.2.3