bsps: Move benchmark timer to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

3 files changed, 655 insertions, 0 deletions

diff --git a/bsps/sh/gensh1/btimer/btimer.c b/bsps/sh/gensh1/btimer/btimer.c
new file mode 100644
index 0000000000..94a834cb1e
--- /dev/null
+++ b/bsps/sh/gensh1/btimer/btimer.c
@@ -0,0 +1,195 @@
+/**
+ * @file
+ * @brief Timer for the Hitachi SH 703X
+ */
+
+/*
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+
+#include <rtems/score/sh_io.h>
+#include <rtems/score/ispsh7032.h>
+#include <rtems/score/iosh7032.h>
+
+extern uint32_t bsp_clicks_per_second;
+
+#define I_CLK_PHI_1     0
+#define I_CLK_PHI_2     1
+#define I_CLK_PHI_4     2
+#define I_CLK_PHI_8     3
+
+/*
+ * Set I_CLK_PHI to one of the I_CLK_PHI_X values from above to choose
+ * a PHI/X clock rate.
+ */
+
+#define I_CLK_PHI       I_CLK_PHI_4
+#define CLOCK_SCALE     (1<<I_CLK_PHI)
+
+#define ITU1_STARTMASK 	0xfd
+#define ITU1_SYNCMASK 	0xfd
+#define ITU1_MODEMASK 	0xfd
+#define ITU1_TCRMASK 	(0x00 | I_CLK_PHI)
+#define ITU1_TIORMASK 	0x88
+#define ITU1_STAT_MASK 	0xf8
+#define ITU1_TIERMASK 	0xfc
+#define IPRC_ITU1_MASK	0xfff0
+
+#ifndef ITU1_PRIO
+#define ITU1_PRIO 15
+#endif
+
+#define ITU1_VECTOR OVI1_ISP_V
+
+extern rtems_isr timerisr(void);
+
+static uint32_t   Timer_interrupts;
+
+bool benchmark_timer_find_average_overhead;
+
+static uint32_t   Timer_HZ ;
+
+void benchmark_timer_initialize( void )
+{
+  uint8_t                temp8;
+  uint16_t               temp16;
+  rtems_interrupt_level  level;
+  rtems_isr             *ignored;
+
+  Timer_HZ = bsp_clicks_per_second / CLOCK_SCALE ;
+
+  /*
+   *  Timer has never overflowed.  This may not be necessary on some
+   *  implemenations of timer but ....
+   */
+
+  Timer_interrupts /* .i */ = 0;
+  rtems_interrupt_disable( level );
+
+  /*
+   *  Somehow start the timer
+   */
+  /* stop Timer 1  */
+  temp8 = read8(ITU_TSTR) & ITU1_STARTMASK;
+  write8( temp8, ITU_TSTR );
+
+  /* initialize counter 1 */
+  write16( 0, ITU_TCNT1 );
+
+  /* Timer 1 is independent of other timers */
+  temp8 = read8(ITU_TSNC) & ITU1_SYNCMASK;
+  write8( temp8, ITU_TSNC );
+
+  /* Timer 1, normal mode */
+  temp8 = read8(ITU_TMDR) & ITU1_MODEMASK;
+  write8( temp8, ITU_TMDR );
+
+  /* Use a Phi/X counter */
+  write8( ITU1_TCRMASK, ITU_TCR1 );
+
+  /* gra and grb are not used */
+  write8( ITU1_TIORMASK, ITU_TIOR1 );
+
+  /* reset all status flags */
+  temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
+  write8( temp8, ITU_TSR1 );
+
+  /* enable overflow interrupt */
+  write8( ITU1_TIERMASK, ITU_TIER1 );
+
+  /* set interrupt priority */
+  temp16 = read16(INTC_IPRC) & IPRC_ITU1_MASK;
+  temp16 |= ITU1_PRIO;
+  write16( temp16, INTC_IPRC );
+
+  /* initialize ISR */
+  _CPU_ISR_install_raw_handler( ITU1_VECTOR, timerisr, &ignored );
+  rtems_interrupt_enable( level );
+
+  /* start timer 1 */
+  temp8 = read8(ITU_TSTR) | ~ITU1_STARTMASK;
+  write8( temp8, ITU_TSTR );
+}
+
+/*
+ *  The following controls the behavior of benchmark_timer_read().
+ *
+ *  AVG_OVERHEAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      1  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in microseconds. */
+#define LEAST_VALID       0 /* 20 */ /* Don't trust a clicks value lower than this */
+
+benchmark_timer_t benchmark_timer_read( void )
+{
+  uint32_t   cclicks;
+  uint32_t   total ;
+  /*
+   *  Read the timer and see how many clicks it has been since we started.
+   */
+
+
+  cclicks = read16( ITU_TCNT1 );    /* XXX: read some HW here */
+
+  /*
+   *  Total is calculated by taking into account the number of timer overflow
+   *  interrupts since the timer was initialized and clicks since the last
+   *  interrupts.
+   */
+
+  total = cclicks + Timer_interrupts * 65536;
+
+  if ( benchmark_timer_find_average_overhead )
+    return total / CLOCK_SCALE;          /* in XXX microsecond units */
+  else
+  {
+    if ( total < LEAST_VALID )
+      return 0;            /* below timer resolution */
+  /*
+   *  Somehow convert total into microseconds
+   */
+    return (total / CLOCK_SCALE - AVG_OVERHEAD);
+  }
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+  benchmark_timer_find_average_overhead = find_flag;
+}
+
+/* Timer 1 is used */
+
+#pragma interrupt
+void timerisr( void )
+{
+  uint8_t   temp8;
+
+  /* reset the flags of the status register */
+  temp8 = read8(ITU_TSR1) & ITU1_STAT_MASK;
+  write8( temp8, ITU_TSR1 );
+
+  Timer_interrupts += 1;
+}
diff --git a/bsps/sh/gensh2/btimer/btimer.c b/bsps/sh/gensh2/btimer/btimer.c
new file mode 100644
index 0000000000..152c99b1aa
--- /dev/null
+++ b/bsps/sh/gensh2/btimer/btimer.c
@@ -0,0 +1,191 @@
+/**
+ *  @file
+ *  @brief Timer for the Hitachi SH 704X
+ */
+
+/*
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+
+#include <rtems/score/sh_io.h>
+#include <rtems/score/iosh7045.h>
+
+extern uint32_t bsp_clicks_per_second;
+
+/*
+ *  We use a Phi/4 timer
+ */
+#define SCALE (Timer_MHZ/4)
+
+#define MTU1_STARTMASK 	0xfd
+#define MTU1_SYNCMASK 	0xfd
+#define MTU1_MODEMASK 	0xc0
+#define MTU1_TCRMASK 	0x01
+#define MTU1_TIORMASK 	0x88
+#define MTU1_STAT_MASK 	0xf8
+#define MTU1_TIERMASK 	0xfc
+#define IPRC_MTU1_MASK	0xfff0
+
+#ifndef MTU1_PRIO
+#define MTU1_PRIO 15
+#endif
+
+#define MTU1_VECTOR 86
+
+extern rtems_isr timerisr(void);
+
+static uint32_t   Timer_interrupts;
+
+bool benchmark_timer_find_average_overhead;
+
+static uint32_t   Timer_MHZ ;
+
+void benchmark_timer_initialize( void )
+{
+  uint8_t                temp8;
+  uint16_t               temp16;
+  rtems_interrupt_level  level;
+  rtems_isr	        *ignored;
+
+  Timer_MHZ = bsp_clicks_per_second / 1000000 ;
+
+  /*
+   *  Timer has never overflowed.  This may not be necessary on some
+   *  implemenations of timer but ....
+   */
+
+  Timer_interrupts /* .i */ = 0;
+  rtems_interrupt_disable( level );
+
+  /*
+   *  Somehow start the timer
+   */
+  /* stop Timer 1  */
+  temp8 = read8(MTU_TSTR) & MTU1_STARTMASK;
+  write8( temp8, MTU_TSTR );
+
+  /* initialize counter 1 */
+  write16( 0, MTU_TCNT1);
+
+  /* Timer 1 is independent of other timers */
+  temp8 = read8(MTU_TSYR) & MTU1_SYNCMASK;
+  write8( temp8, MTU_TSYR );
+
+  /* Timer 1, normal mode */
+  temp8 = read8(MTU_TMDR1) & MTU1_MODEMASK;
+  write8( temp8, MTU_TMDR1 );
+
+  /* x0000000
+   * |||||+++--- Internal Clock
+   * |||++------ Count on rising edge
+   * |++-------- disable TCNT clear
+   * +---------- don`t care
+   */
+  write8( MTU1_TCRMASK, MTU_TCR1 );
+
+  /* gra and grb are not used */
+  write8( MTU1_TIORMASK, MTU_TIOR1 );
+
+  /* reset all status flags */
+  temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
+  write8( temp8, MTU_TSR1 );
+
+  /* enable overflow interrupt */
+  write8( MTU1_TIERMASK, MTU_TIER1 );
+
+  /* set interrupt priority */
+  temp16 = read16(INTC_IPRC) & IPRC_MTU1_MASK;
+  temp16 |= MTU1_PRIO;
+  write16( temp16, INTC_IPRC);
+
+  /* initialize ISR */
+  _CPU_ISR_install_raw_handler( MTU1_VECTOR, timerisr, &ignored );
+  rtems_interrupt_enable( level );
+
+  /* start timer 1 */
+  temp8 = read8(MTU_TSTR) | ~MTU1_STARTMASK;
+  write8( temp8, MTU_TSTR );
+}
+
+/*
+ *  The following controls the behavior of benchmark_timer_read().
+ *
+ *  AVG_OVERHEAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      1  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in microseconds. */
+#define LEAST_VALID       0 /* 20 */ /* Don't trust a clicks value lower than this */
+
+benchmark_timer_t benchmark_timer_read( void )
+{
+  uint32_t   clicks;
+  uint32_t   total ;
+  /*
+   *  Read the timer and see how many clicks it has been since we started.
+   */
+
+
+  clicks = read16( MTU_TCNT1 );   /* XXX: read some HW here */
+
+  /*
+   *  Total is calculated by taking into account the number of timer overflow
+   *  interrupts since the timer was initialized and clicks since the last
+   *  interrupts.
+   */
+
+  total = clicks + Timer_interrupts * 65536;
+
+  if ( benchmark_timer_find_average_overhead )
+    return total / SCALE;          /* in XXX microsecond units */
+  else
+  {
+    if ( total < LEAST_VALID )
+      return 0;            /* below timer resolution */
+  /*
+   *  Somehow convert total into microseconds
+   */
+    return (total / SCALE - AVG_OVERHEAD) ;
+  }
+}
+
+void benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+  benchmark_timer_find_average_overhead = find_flag;
+}
+
+/* Timer 1 is used */
+
+#pragma interrupt
+void timerisr( void )
+{
+  uint8_t   temp8;
+
+  /* reset the flags of the status register */
+  temp8 = read8(MTU_TSR1) & MTU1_STAT_MASK;
+  write8( temp8, MTU_TSR1 );
+
+  Timer_interrupts += 1;
+}
diff --git a/bsps/sh/gensh4/btimer/btimer.c b/bsps/sh/gensh4/btimer/btimer.c
new file mode 100644
index 0000000000..ef462c780c
--- /dev/null
+++ b/bsps/sh/gensh4/btimer/btimer.c
@@ -0,0 +1,269 @@
+/**
+ *  @file
+ *  @brief Timer driver for the Hitachi SH 7750
+ */
+
+/*
+ *  Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
+ *  Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <rtems/btimer.h>
+
+#include <rtems/score/sh_io.h>
+#include <rtems/score/iosh7750.h>
+
+extern uint32_t bsp_clicks_per_second;
+
+#ifndef TIMER_PRIO
+#define TIMER_PRIO 15
+#endif
+
+/* Timer prescaler division ratio */
+#define TIMER_PRESCALER 4
+#define TCR1_TPSC       SH7750_TCR_TPSC_DIV4
+
+#define TIMER_VECTOR SH7750_EVT_TO_NUM(SH7750_EVT_TUNI1)
+
+extern rtems_isr timerisr(void);
+
+static uint32_t   Timer_interrupts;
+
+/* Counter should be divided to this value to obtain time in microseconds */
+static uint32_t   microseconds_divider;
+
+/* Interrupt period in microseconds */
+static uint32_t   microseconds_per_int;
+
+bool benchmark_timer_find_average_overhead;
+
+/* benchmark_timer_initialize --
+ *     Initialize Timer 1 to operate as a RTEMS benchmark timer:
+ *        - determine timer clock frequency
+ *        - install timer interrupt handler
+ *        - configure the Timer 1 hardware
+ *        - start the timer
+ *
+ * PARAMETERS:
+ *     none
+ *
+ * RETURNS:
+ *     none
+ */
+void
+benchmark_timer_initialize(void)
+{
+    uint8_t               temp8;
+    uint16_t              temp16;
+    rtems_interrupt_level level;
+    rtems_isr            *ignored;
+    int                   cpudiv = 1;
+    int                   tidiv = 1;
+
+    Timer_interrupts  = 0;
+    rtems_interrupt_disable(level);
+
+    /* Get CPU frequency divider from clock unit */
+    switch (read16(SH7750_FRQCR) & SH7750_FRQCR_IFC)
+    {
+        case SH7750_FRQCR_IFCDIV1:
+            cpudiv = 1;
+            break;
+
+        case SH7750_FRQCR_IFCDIV2:
+            cpudiv = 2;
+            break;
+
+        case SH7750_FRQCR_IFCDIV3:
+            cpudiv = 3;
+            break;
+
+        case SH7750_FRQCR_IFCDIV4:
+            cpudiv = 4;
+            break;
+
+        case SH7750_FRQCR_IFCDIV6:
+            cpudiv = 6;
+            break;
+
+        case SH7750_FRQCR_IFCDIV8:
+            cpudiv = 8;
+            break;
+
+        default:
+            rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
+    }
+
+    /* Get peripheral module frequency divider from clock unit */
+    switch (read16(SH7750_FRQCR) & SH7750_FRQCR_PFC)
+    {
+        case SH7750_FRQCR_PFCDIV2:
+            tidiv = 2 * TIMER_PRESCALER;
+            break;
+
+        case SH7750_FRQCR_PFCDIV3:
+            tidiv = 3 * TIMER_PRESCALER;
+            break;
+
+        case SH7750_FRQCR_PFCDIV4:
+            tidiv = 4 * TIMER_PRESCALER;
+            break;
+
+        case SH7750_FRQCR_PFCDIV6:
+            tidiv = 6 * TIMER_PRESCALER;
+            break;
+
+        case SH7750_FRQCR_PFCDIV8:
+            tidiv = 8 * TIMER_PRESCALER;
+            break;
+
+        default:
+            rtems_fatal_error_occurred( RTEMS_NOT_CONFIGURED);
+    }
+
+    microseconds_divider = bsp_clicks_per_second * cpudiv / (tidiv * 1000000);
+    microseconds_per_int = 0xFFFFFFFF / microseconds_divider;
+
+    /*
+     *  Hardware specific initialization
+     */
+
+    /* Stop the Timer 0 */
+    temp8 = read8(SH7750_TSTR);
+    temp8 &= ~SH7750_TSTR_STR1;
+    write8(temp8, SH7750_TSTR);
+
+    /* Establish interrupt handler */
+    _CPU_ISR_install_raw_handler( TIMER_VECTOR, timerisr, &ignored );
+
+    /* Reset timer constant and counter */
+    write32(0xFFFFFFFF, SH7750_TCOR1);
+    write32(0xFFFFFFFF, SH7750_TCNT1);
+
+    /* Select timer mode */
+    write16(
+        SH7750_TCR_UNIE |        /* Enable Underflow Interrupt */
+        SH7750_TCR_CKEG_RAISE |  /* Count on rising edge */
+        TCR1_TPSC,               /* Timer prescaler ratio */
+        SH7750_TCR1);
+
+    /* Set timer interrupt priority */
+    temp16 = read16(SH7750_IPRA);
+    temp16 = (temp16 & ~SH7750_IPRA_TMU1) | (TIMER_PRIO << SH7750_IPRA_TMU1_S);
+    write16(temp16, SH7750_IPRA);
+
+
+    rtems_interrupt_enable(level);
+
+    /* Start the Timer 1 */
+    temp8 = read8(SH7750_TSTR);
+    temp8 |= SH7750_TSTR_STR1;
+    write8(temp8, SH7750_TSTR);
+
+}
+
+/*
+ *  The following controls the behavior of benchmark_timer_read().
+ *
+ *  AVG_OVERHEAD is the overhead for starting and stopping the timer.  It
+ *  is usually deducted from the number returned.
+ *
+ *  LEAST_VALID is the lowest number this routine should trust.  Numbers
+ *  below this are "noise" and zero is returned.
+ */
+
+#define AVG_OVERHEAD      0  /* It typically takes X.X microseconds */
+                             /* (Y countdowns) to start/stop the timer. */
+                             /* This value is in microseconds. */
+#define LEAST_VALID       0 /* 20 */ /* Don't trust a clicks value lower than this */
+
+/* benchmark_timer_read --
+ *     Read timer value in microsecond units since timer start.
+ *
+ * PARAMETERS:
+ *     none
+ *
+ * RETURNS:
+ *     number of microseconds since timer has been started
+ */
+benchmark_timer_t
+benchmark_timer_read(void)
+{
+    uint32_t              clicks;
+    uint32_t              ints;
+    uint32_t              total;
+    rtems_interrupt_level level;
+    uint32_t              tcr;
+
+
+    rtems_interrupt_disable(level);
+
+    clicks = 0xFFFFFFFF - read32(SH7750_TCNT1);
+    tcr = read32(SH7750_TCR1);
+    ints = Timer_interrupts;
+
+    rtems_interrupt_enable(level);
+
+    /* Handle the case when timer overflowed but interrupt was not processed */
+    if ((clicks > 0xFF000000) && ((tcr & SH7750_TCR_UNF) != 0))
+    {
+        ints++;
+    }
+
+    total = microseconds_per_int * ints + (clicks / microseconds_divider);
+
+    if ( benchmark_timer_find_average_overhead )
+        return total;          /* in microsecond units */
+    else
+    {
+        if ( total < LEAST_VALID )
+            return 0;            /* below timer resolution */
+        /*
+         *  Somehow convert total into microseconds
+         */
+        return (total - AVG_OVERHEAD) ;
+    }
+}
+
+/* benchmark_timer_disable_subtracting_average_overhead --
+ *     This routine is invoked by the "Check Timer" (tmck) test in the
+ *     RTEMS Timing Test Suite. It makes the benchmark_timer_read routine not
+ *     subtract the overhead required to initialize and read the benchmark
+ *     timer.
+ *
+ * PARAMETERS:
+ *     find_flag - boolean flag, true if overhead must not be subtracted.
+ *
+ * RETURNS:
+ *     none
+ */
+void
+benchmark_timer_disable_subtracting_average_overhead(bool find_flag)
+{
+    benchmark_timer_find_average_overhead = find_flag;
+}
+
+/* timerisr --
+ *     Timer interrupt handler routine. This function invoked on timer
+ *     underflow event; once per 2^32 clocks. It should reset the timer
+ *     event and increment timer interrupts counter.
+ */
+void
+timerisr(void)
+{
+  uint8_t   temp8;
+
+  /* reset the flags of the status register */
+  temp8 = read8(SH7750_TCR1) & ~SH7750_TCR_UNF;
+  write8(temp8, SH7750_TCR1);
+
+  Timer_interrupts += 1;
+}