bsps: Move startup files to bsps

Adjust build support files to new directory layout.

This patch is a part of the BSP source reorganization.

Update #3285.

23 files changed, 3698 insertions, 0 deletions

diff --git a/bsps/sh/gensh1/start/bsp_specs b/bsps/sh/gensh1/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/sh/gensh1/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/sh/gensh1/start/cpu_asm.c b/bsps/sh/gensh1/start/cpu_asm.c
new file mode 100644
index 0000000000..99d9cc9a6a
--- /dev/null
+++ b/bsps/sh/gensh1/start/cpu_asm.c
@@ -0,0 +1,181 @@
+/*
+ *  This file contains the basic algorithms for all assembly code used
+ *  in an specific CPU port of RTEMS.  These algorithms must be implemented
+ *  in assembly language
+ *
+ *  NOTE:  This port uses a C file with inline assembler instructions
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ */
+
+/*
+ *  This is supposed to be an assembly file.  This means that system.h
+ *  and cpu.h should not be included in a "real" cpu_asm file.  An
+ *  implementation in assembly should include "cpu_asm.h"
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/percpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/threaddispatch.h>
+#include <rtems/score/sh.h>
+#include <rtems/score/ispsh7032.h>
+
+#include <rtems/score/ispsh7032.h>
+#include <rtems/score/iosh7032.h>
+#include <rtems/score/sh_io.h>
+
+/* from cpu_isps.c */
+extern proc_ptr         _Hardware_isr_Table[];
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  unsigned long    *_old_stack_ptr;
+#endif
+
+register unsigned long  *stack_ptr __asm__ ("r15");
+
+/*
+ * sh_set_irq_priority
+ *
+ * this function sets the interrupt level of the specified interrupt
+ *
+ * parameters:
+ *             - irq : interrupt number
+ *             - prio: priority to set for this interrupt number
+ *
+ * returns:    0 if ok
+ *             -1 on error
+ */
+
+unsigned int sh_set_irq_priority(
+  unsigned int irq,
+  unsigned int prio )
+{
+  uint32_t         shiftcount;
+  uint32_t         prioreg;
+  uint16_t         temp16;
+  ISR_Level        level;
+
+  /*
+   * first check for valid interrupt
+   */
+  if (( irq > 113) || (_Hardware_isr_Table[irq] == _dummy_isp))
+    return -1;
+  /*
+   * check for valid irq priority
+   */
+  if ( prio > 15 )
+    return -1;
+
+  /*
+   * look up appropriate interrupt priority register
+   */
+  if ( irq > 71)
+    {
+      irq = irq - 72;
+      shiftcount = 12 - ((irq & ~0x03) % 16);
+
+      switch( irq / 16)
+	{
+	case 0: { prioreg = INTC_IPRC; break;}
+	case 1: { prioreg = INTC_IPRD; break;}
+	case 2: { prioreg = INTC_IPRE; break;}
+	default: return -1;
+	}
+    }
+  else
+    {
+      shiftcount = 12 - 4 * ( irq % 4);
+      if ( irq > 67)
+	prioreg = INTC_IPRB;
+      else
+	prioreg = INTC_IPRA;
+    }
+
+  /*
+   * Set the interrupt priority register
+   */
+  _ISR_Local_disable( level );
+
+    temp16 = read16( prioreg);
+    temp16 &= ~( 15 << shiftcount);
+    temp16 |= prio << shiftcount;
+    write16( temp16, prioreg);
+
+  _ISR_Local_enable( level );
+
+  return 0;
+}
+
+/*
+ *  This routine provides the RTEMS interrupt management.
+ */
+
+void __ISR_Handler( uint32_t   vector)
+{
+  ISR_Level level;
+
+  _ISR_Local_disable( level );
+
+  _Thread_Dispatch_disable();
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if ( _ISR_Nest_level == 0 )
+    {
+      /* Install irq stack */
+      _old_stack_ptr = stack_ptr;
+      stack_ptr = _CPU_Interrupt_stack_high;
+    }
+
+#endif
+
+  _ISR_Nest_level++;
+
+  _ISR_Local_enable( level );
+
+  /* call isp */
+  if ( _ISR_Vector_table[ vector])
+    (*_ISR_Vector_table[ vector ])( vector );
+
+  _ISR_Local_disable( level );
+
+  _Thread_Dispatch_unnest( _Per_CPU_Get() );
+
+  _ISR_Nest_level--;
+
+#if(CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+
+  if ( _ISR_Nest_level == 0 )
+    /* restore old stack pointer */
+    stack_ptr = _old_stack_ptr;
+#endif
+
+  _ISR_Local_enable( level );
+
+  if ( _ISR_Nest_level )
+    return;
+
+  if ( !_Thread_Dispatch_is_enabled() ) {
+    return;
+  }
+
+  if ( _Thread_Dispatch_necessary ) {
+    _Thread_Dispatch();
+  }
+}
diff --git a/bsps/sh/gensh1/start/ispsh7032.c b/bsps/sh/gensh1/start/ispsh7032.c
new file mode 100644
index 0000000000..05ba2f1e90
--- /dev/null
+++ b/bsps/sh/gensh1/start/ispsh7032.c
@@ -0,0 +1,248 @@
+/*
+ * This file contains the isp frames for the user interrupts.
+ * From these procedures __ISR_Handler is called with the vector number
+ * as argument.
+ *
+ * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
+ * some releases of gcc doesn't properly handle #pragma interrupt, if a
+ * file contains both isrs and normal functions.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/ispsh7032.h>
+
+/*
+ * This is an exception vector table
+ *
+ * It has the same structure like the actual vector table (vectab)
+ */
+proc_ptr _Hardware_isr_Table[256]={
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+_nmi_isp, _usb_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+/* trapa 0 -31 */
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+/* irq 64 ... */
+_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,
+_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
+_dma0_isp, _dummy_isp, _dma1_isp, _dummy_isp,
+_dma2_isp, _dummy_isp, _dma3_isp, _dummy_isp,
+_imia0_isp, _imib0_isp, _ovi0_isp, _dummy_isp,
+_imia1_isp, _imib1_isp, _ovi1_isp, _dummy_isp,
+_imia2_isp, _imib2_isp, _ovi2_isp, _dummy_isp,
+_imia3_isp, _imib3_isp, _ovi3_isp, _dummy_isp,
+_imia4_isp, _imib4_isp, _ovi4_isp, _dummy_isp,
+_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp,
+_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
+_prt_isp, _adu_isp, _dummy_isp, _dummy_isp,
+_wdt_isp,
+/* 113 */ _dref_isp
+};
+
+#define Str(a)#a
+
+/*
+ * Some versions of gcc and all version of egcs at least until egcs-1.1b
+ * are not able to handle #pragma interrupt correctly if more than 1 isr is
+ * contained in a file and when optimizing.
+ * We try to work around this problem by using the macro below.
+ */
+#define isp( name, number, func)\
+__asm__ (".global _"Str(name)"\n\t" \
+     "_"Str(name)":       \n\t" \
+     "    mov.l r0,@-r15   \n\t" \
+     "    mov.l r1,@-r15   \n\t" \
+     "    mov.l r2,@-r15   \n\t" \
+     "    mov.l r3,@-r15   \n\t" \
+     "    mov.l r4,@-r15   \n\t" \
+     "    mov.l r5,@-r15   \n\t" \
+     "    mov.l r6,@-r15   \n\t" \
+     "    mov.l r7,@-r15   \n\t" \
+     "    mov.l r14,@-r15  \n\t" \
+     "    sts.l pr,@-r15   \n\t" \
+     "    sts.l mach,@-r15 \n\t" \
+     "    sts.l macl,@-r15 \n\t" \
+     "    mov r15,r14      \n\t" \
+     "    mov.l "Str(name)"_k, r1\n\t" \
+     "    jsr @r1           \n\t" \
+     "    mov #"Str(number)", r4\n\t" \
+     "    mov   r14,r15    \n\t" \
+     "    lds.l @r15+,macl \n\t" \
+     "    lds.l @r15+,mach \n\t" \
+     "    lds.l @r15+,pr   \n\t" \
+     "    mov.l @r15+,r14  \n\t" \
+     "    mov.l @r15+,r7   \n\t" \
+     "    mov.l @r15+,r6   \n\t" \
+     "    mov.l @r15+,r5   \n\t" \
+     "    mov.l @r15+,r4   \n\t" \
+     "    mov.l @r15+,r3   \n\t" \
+     "    mov.l @r15+,r2   \n\t" \
+     "    mov.l @r15+,r1   \n\t" \
+     "    mov.l @r15+,r0   \n\t" \
+     "    rte              \n\t" \
+     "    nop              \n\t" \
+     "    .align 2         \n\t" \
+     #name"_k: \n\t" \
+     ".long "Str(func));
+
+/************************************************
+ * Dummy interrupt service procedure for
+ * interrupts being not allowed --> Trap 34
+ ************************************************/
+__asm__ (" .section .text\n\
+.global __dummy_isp\n\
+__dummy_isp:\n\
+      mov.l r14,@-r15\n\
+      mov   r15, r14\n\
+      trapa #34\n\
+      mov.l @r15+,r14\n\
+      rte\n\
+      nop");
+
+/*****************************
+ * Non maskable interrupt
+ *****************************/
+isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * User break controller
+ *****************************/
+isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
+
+/*****************************
+ *  External interrupts 0-7
+ *****************************/
+isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
+isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
+isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
+isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
+isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
+isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
+isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
+isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * DMA - controller
+ *****************************/
+isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
+isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
+isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
+isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Interrupt timer unit
+ *****************************/
+
+/*****************************
+ * Timer 0
+ *****************************/
+isp( _imia0_isp, IMIA0_ISP_V, ___ISR_Handler);
+isp( _imib0_isp, IMIB0_ISP_V, ___ISR_Handler);
+isp( _ovi0_isp,  OVI0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 1
+ *****************************/
+isp( _imia1_isp, IMIA1_ISP_V, ___ISR_Handler);
+isp( _imib1_isp, IMIB1_ISP_V, ___ISR_Handler);
+isp( _ovi1_isp,  OVI1_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 2
+ *****************************/
+isp( _imia2_isp, IMIA2_ISP_V, ___ISR_Handler);
+isp( _imib2_isp, IMIB2_ISP_V, ___ISR_Handler);
+isp( _ovi2_isp,  OVI2_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 3
+ *****************************/
+isp( _imia3_isp, IMIA3_ISP_V, ___ISR_Handler);
+isp( _imib3_isp, IMIB3_ISP_V, ___ISR_Handler);
+isp( _ovi3_isp,  OVI3_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 4
+ *****************************/
+isp( _imia4_isp, IMIA4_ISP_V, ___ISR_Handler);
+isp( _imib4_isp, IMIB4_ISP_V, ___ISR_Handler);
+isp( _ovi4_isp,  OVI4_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Serial interfaces
+ *****************************/
+
+/*****************************
+ * Serial interface 0
+ *****************************/
+isp( _eri0_isp,  ERI0_ISP_V, ___ISR_Handler);
+isp( _rxi0_isp,  RXI0_ISP_V, ___ISR_Handler);
+isp( _txi0_isp,  TXI0_ISP_V, ___ISR_Handler);
+isp( _tei0_isp,  TEI0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Serial interface 1
+ *****************************/
+isp( _eri1_isp,  ERI1_ISP_V, ___ISR_Handler);
+isp( _rxi1_isp,  RXI1_ISP_V, ___ISR_Handler);
+isp( _txi1_isp,  TXI1_ISP_V, ___ISR_Handler);
+isp( _tei1_isp,  TEI1_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Parity control unit of
+ * the bus state controller
+ *****************************/
+isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * Analog digital converter
+ * ADC
+ ******************************/
+isp( _adu_isp,  ADU_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ *  Watchdog timer
+ ******************************/
+isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * DRAM refresh control unit
+ * of bus state controller
+ ******************************/
+isp( _dref_isp,  DREF_ISP_V, ___ISR_Handler);
diff --git a/bsps/sh/gensh1/start/linkcmds b/bsps/sh/gensh1/start/linkcmds
new file mode 100644
index 0000000000..d268d4cfc7
--- /dev/null
+++ b/bsps/sh/gensh1/start/linkcmds
@@ -0,0 +1,230 @@
+/*
+ * This is an adapted linker script from egcs-1.0.1 
+ *
+ * Memory layout for an SH 7032 with main memory in area 2
+ * This memory layout it very similar to that used for Hitachi's
+ * EVB with CMON in rom
+ *
+ * NOTE: The ram start address may vary, all other start addresses are fixed
+ *       Not suiteable for gdb's simulator
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x0a040000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 512K;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+
+MEMORY
+{
+  rom           : o = 0x00000000, l = 128k
+  onchip_peri	: o = 0x05000000, l = 512
+  ram           : o = 0x0A040000, l = 512k  /* enough to link all tests */
+
+  onchip_ram    : o = 0x0f000000, l = 8k
+}
+
+SECTIONS
+{
+  /* boot vector table */
+  .monvects 0x00000000 (NOLOAD): {
+    _monvects = . ;
+  } > rom
+
+  /* monitor play area */
+  .monram 0x0A040000 (NOLOAD) : 
+  {
+  _ramstart = .;
+  } > ram 
+
+  /* monitor vector table */
+  .vects   0x0A042000 (NOLOAD) : {
+    _vectab = . ;
+    *(.vects);
+  }
+
+  /* Read-only sections, merged into text segment: */
+
+  . = 0x0a044000 ;
+  .interp        : { *(.interp) 	}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .gnu.version   : { *(.gnu.version)	}
+  .gnu.version_d : { *(.gnu.version_d)	}
+  .gnu.version_r : { *(.gnu.version_r)	}
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    } >ram
+  .rel.text      :
+    { *(.rel.text) *(.rel.gnu.linkonce.t*) }
+  .rel.data      :
+    { *(.rel.data) *(.rel.gnu.linkonce.d*) }
+  .rel.rodata    :
+    { *(.rel.rodata*) *(.rel.gnu.linkonce.r*) }
+  .rel.got       : { *(.rel.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rel.init      : { *(.rel.init)	}
+  .rel.fini      : { *(.rel.fini)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .plt      	 : { *(.plt)	}
+  .text   .   	 :
+  {
+    _start = .;
+    *(.text*)
+    *(.stub)
+
+    /*
+     * Special FreeBSD sysctl sections.
+     */
+    . = ALIGN (16);
+    __start_set_sysctl_set = .;
+    ___start_set_sysctl_set = .;
+    *(set_sysc*);   /* set_sysctl_* but name is truncated by SH-coff */
+    __stop_set_sysctl_set = ABSOLUTE(.);
+    ___stop_set_sysctl_set = ABSOLUTE(.);
+    *(set_doma*);   /* set_domain_* but name is truncated by SH-coff */
+    *(set_pseu*);   /* set_pseudo_* but name is truncated by SH-coff */
+
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  } > ram
+  _etext = .;
+  PROVIDE (etext = .);
+  .init    .  : { KEEP(*(.init))    } > ram =0
+  .fini    .  : { KEEP(*(.fini))    } > ram =0
+  .ctors   .  : { KEEP(*(.ctors))    } > ram =0
+  .dtors   .  : { KEEP(*(.dtors))    } > ram =0
+  .rodata  .  : { *(.rodata*) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram
+  .rodata1 .  : { *(.rodata1) } > ram
+  .tdata : {
+    __TLS_Data_begin = .;
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    __TLS_Data_end = .;
+  } > ram
+  .tbss : {
+    __TLS_BSS_begin = .;
+    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+    __TLS_BSS_end = .;
+  } > ram
+  __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+  __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+  __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+  __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+  __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+  __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(128) + (. & (128 - 1));
+  .data  .  :
+  {
+    *(.data*)
+    KEEP (*(SORT(.rtemsrwset.*)))
+    *(.gcc_exc*)
+    ___EH_FRAME_BEGIN__ = .;
+    *(.eh_fram*)
+    ___EH_FRAME_END__ = .;
+    LONG(0);
+    *(.gcc_except_table*)
+    *(.gnu.linkonce.d*)
+    CONSTRUCTORS
+  } > ram
+  .data1  . : { *(.data1) }
+  .got     .      : { *(.got.plt) *(.got) }
+  .dynamic .      : { *(.dynamic) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata   .  : { *(.sdata) }
+  _edata  =  .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .sbss    .  : { *(.sbss*) *(.scommon) }
+  .bss     .  :
+  {
+   *(.dynbss)
+   *(.bss .bss* .gnu.linkonce.b*)
+   *(COMMON)
+  } > ram
+  _end = . ;
+  PROVIDE (end = .);
+
+  _WorkAreaBase = . ;
+
+  _CPU_Interrupt_stack_low  = 0x0f000000 ;
+  _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  stack : { _stack = .; *(.stack) } > onchip_ram
+  /* These must appear regardless of  .  */
+}
diff --git a/bsps/sh/gensh2/start/bsp_specs b/bsps/sh/gensh2/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/sh/gensh2/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/sh/gensh2/start/cpu_asm.c b/bsps/sh/gensh2/start/cpu_asm.c
new file mode 100644
index 0000000000..47bc859dbd
--- /dev/null
+++ b/bsps/sh/gensh2/start/cpu_asm.c
@@ -0,0 +1,182 @@
+/*
+ *  This file contains the basic algorithms for all assembly code used
+ *  in an specific CPU port of RTEMS.  These algorithms must be implemented
+ *  in assembly language
+ *
+ *  NOTE:  This port uses a C file with inline assembler instructions
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+/*
+ *  This is supposed to be an assembly file.  This means that system.h
+ *  and cpu.h should not be included in a "real" cpu_asm file.  An
+ *  implementation in assembly should include "cpu_asm.h"
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/threaddispatch.h>
+#include <rtems/score/sh.h>
+
+#include <rtems/score/ispsh7045.h>
+#include <rtems/score/iosh7045.h>
+#include <rtems/score/sh_io.h>
+
+/* from cpu_isps.c */
+extern proc_ptr         _Hardware_isr_Table[];
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  unsigned long    *_old_stack_ptr;
+#endif
+
+register unsigned long  *stack_ptr __asm__ ("r15");
+
+/*
+ * sh_set_irq_priority
+ *
+ * this function sets the interrupt level of the specified interrupt
+ *
+ * parameters:
+ *             - irq : interrupt number
+ *             - prio: priority to set for this interrupt number
+ *
+ * returns:    0 if ok
+ *             -1 on error
+ */
+
+unsigned int sh_set_irq_priority(
+  unsigned int irq,
+  unsigned int prio )
+{
+  uint32_t   shiftcount;
+  uint32_t   prioreg;
+  uint16_t   temp16;
+  ISR_Level  level;
+
+  /*
+   * first check for valid interrupt
+   */
+  if (( irq > 156) || (irq < 64) || (_Hardware_isr_Table[irq] == _dummy_isp))
+    return -1;
+  /*
+   * check for valid irq priority
+   */
+  if ( prio > 15 )
+    return -1;
+
+  /*
+   * look up appropriate interrupt priority register
+   */
+  if ( irq > 71)
+    {
+      irq = irq - 72;
+      shiftcount = 12 - ((irq & ~0x03) % 16);
+
+      switch( irq / 16)
+	{
+	case 0: { prioreg = INTC_IPRC; break;}
+	case 1: { prioreg = INTC_IPRD; break;}
+	case 2: { prioreg = INTC_IPRE; break;}
+	case 3: { prioreg = INTC_IPRF; break;}
+	case 4: { prioreg = INTC_IPRG; break;}
+	case 5: { prioreg = INTC_IPRH; break;}
+	default: return -1;
+	}
+    }
+  else
+    {
+      shiftcount = 12 - 4 * ( irq % 4);
+      if ( irq > 67)
+	prioreg = INTC_IPRB;
+      else
+	prioreg = INTC_IPRA;
+    }
+
+  /*
+   * Set the interrupt priority register
+   */
+  _ISR_Local_disable( level );
+
+    temp16 = read16( prioreg);
+    temp16 &= ~( 15 << shiftcount);
+    temp16 |= prio << shiftcount;
+    write16( temp16, prioreg);
+
+  _ISR_Local_enable( level );
+
+  return 0;
+}
+
+/*
+ *  This routine provides the RTEMS interrupt management.
+ */
+
+void __ISR_Handler( uint32_t   vector)
+{
+  ISR_Level level;
+
+  _ISR_Local_disable( level );
+
+  _Thread_Dispatch_disable();
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if ( _ISR_Nest_level == 0 )
+    {
+      /* Install irq stack */
+      _old_stack_ptr = stack_ptr;
+      stack_ptr = _CPU_Interrupt_stack_high;
+    }
+
+#endif
+
+  _ISR_Nest_level++;
+
+  _ISR_Local_enable( level );
+
+  /* call isp */
+  if ( _ISR_Vector_table[ vector])
+    (*_ISR_Vector_table[ vector ])( vector );
+
+  _ISR_Local_disable( level );
+
+  _Thread_Dispatch_unnest( _Per_CPU_Get() );
+
+  _ISR_Nest_level--;
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+
+  if ( _ISR_Nest_level == 0 )
+    /* restore old stack pointer */
+    stack_ptr = _old_stack_ptr;
+#endif
+
+  _ISR_Local_enable( level );
+
+  if ( _ISR_Nest_level )
+    return;
+
+  if ( !_Thread_Dispatch_is_enabled() ) {
+    return;
+  }
+
+  if ( _Thread_Dispatch_necessary ) {
+    _Thread_Dispatch();
+  }
+}
diff --git a/bsps/sh/gensh2/start/hw_init.c b/bsps/sh/gensh2/start/hw_init.c
new file mode 100644
index 0000000000..f3cbb54ecf
--- /dev/null
+++ b/bsps/sh/gensh2/start/hw_init.c
@@ -0,0 +1,112 @@
+/*
+ *  hw_init.c: set up sh7045F internal subunits
+ *             Pin and memory assignments assume
+ *             target is Hitachi SH7045F EVB ("lcevb")
+ *
+ *             Provides two initialization routines:
+ *             A. 'void early_hw_init(void)' for 'start.S'
+ *                sets up hw needed for early RTEMS boot, and
+ *             B. 'void bsp_hw_init(void)' for 'bspstart.c'
+ *                sets up hardware used by this BSP.
+ *
+ *  Author: John M. Mills (jmills@tga.com)
+ *  COPYRIGHT(c) 2000, TGA Technologies, Inc
+ *                     Norcross, GA 30071 U.S.A
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  Adapted from Hitachi EVB7045F tutorial files by:
+ *  John M. Mills (jmills@tga.com)
+ *  TGA Technologies, Inc.
+ *  100 Pinnacle Way, Suite 140
+ *  Norcross, GA 30071 U.S.A.
+ *
+ *
+ *  This file may be copied and distributed in accordance
+ *  the above-referenced license. It is provided for critique and
+ *  developmental purposes without any warranty nor representation
+ *  by the authors or by TGA Technologies.
+ */
+
+#include <bsp.h>
+
+#include <stdlib.h>
+
+#include <rtems/libio.h>
+#include <rtems/score/sh_io.h>
+#include <rtems/score/iosh7045.h>
+
+/* exported entries */
+extern void bsp_hw_init (void);
+extern void early_hw_init (void);
+
+/*  called from 'start.S' on "#ifdef START_HW_INIT" */
+void early_hw_init (void)
+{
+#ifdef STANDALONE_EVB
+  /* STANDALONE_EVB minimally sets up bus and DRAM here */
+  /* no STANDALONE_EVB accepts defaults from debug monitor */
+
+  /* FIXME: replace 'magic numbers' with logical names */
+
+  write16(0x2020, BSC_BCR1);  /* Bus width access - 32-bit on CS1 */
+  write16(0xF3DD, BSC_BCR2);  /* Idle cycles CS3-CS0 - 0 idle cycles*/
+  write16(0xFF3F, BSC_WCR1);  /* Waits for CS3-CS0 - 3 waits on CS1 */
+  write16(0x000F, BSC_WCR2);  /* Waits for DRAM/DMA access - default */
+  write16(0x0000, BSC_DCR);   /* DRAM control - default */
+  write16(0x0000, BSC_RTCSR); /* DRAM refresh - default */
+  write16(0x0000, BSC_RTCNT); /* DRAM refresh counter - default*/
+  write16(0x0000, BSC_RTCOR); /* DRAM refresh compare match - default */
+#endif
+
+  /*  add early-init functions here */
+
+};
+
+/*  to be called from 'bspstart.c' */
+void bsp_hw_init (void)
+{
+  uint16_t   temp16;
+
+#ifdef STANDALONE_EVB
+  /* STANDALONE_EVB: sets up PFC */
+  /* no STANDALONE_EVB: accepts defaults, adds RESET */
+
+  /* FIXME: replace 'magic numbers' */
+
+  write16(0x5000, PFC_PACRH);  /* Pin function controller - WRHH, WRHL */
+  write16(0x1550, PFC_PACRL1); /* Pin fun. controller - WRH,WRL,RD,CS1 */
+  write16(0x0000, PFC_PBCR1);  /* Pin function controller - default */
+  write16(0x2005, PFC_PBCR2);  /* Pin fcn. controller - A18,A17,A16 */
+  write16(0xFFFF, PFC_PCCR);   /* Pin function controller - A15-A0  */
+  write16(0x5555, PFC_PDCRH1); /* Pin function controller - D31-D24 */
+  write16(0x5555, PFC_PDCRH2); /* Pin function controller - D23-D16 */
+  write16(0xFFFF, PFC_PDCRL);  /* Pin function controller - D15-D0  */
+  write16(0x0000, PFC_IFCR);   /* Pin function controller - default */
+  write16(0x0000, PFC_PACRL2); /* default disconnects all I/O pins;*/
+	                       /*  [re-connected by DEVICE_open()] */
+#endif
+
+  /* default hardware setup for SH7045F EVB */
+
+  /* PFC: General I/O except pin 13 (reset): */
+  temp16 = read16(PFC_PECR1);
+  temp16 |= 0x0800;
+  write16(temp16, PFC_PECR1);
+
+  /* All I/O lines bits 7-0: */
+  write16(0x00, PFC_PECR2);
+
+  /* P5 (LED) out, all other pins in: */
+  temp16 = read16(PFC_PEIOR);
+  temp16 |= 0x0020;
+  write16(temp16, PFC_PEIOR);
+
+}
diff --git a/bsps/sh/gensh2/start/ispsh7045.c b/bsps/sh/gensh2/start/ispsh7045.c
new file mode 100644
index 0000000000..4e6dabed3f
--- /dev/null
+++ b/bsps/sh/gensh2/start/ispsh7045.c
@@ -0,0 +1,310 @@
+/*
+ * This file contains the isp frames for the user interrupts.
+ * From these procedures __ISR_Handler is called with the vector number
+ * as argument.
+ *
+ * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
+ * some releases of gcc doesn't properly handle #pragma interrupt, if a
+ * file contains both isrs and normal functions.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *	Modified to reflect isp entries for sh7045 processor:
+ *	John M. Mills (jmills@tga.com)
+ *	TGA Technologies, Inc.
+ *      100 Pinnacle Way, Suite 140
+ *	Norcross, GA 30071 U.S.A.
+ *	August, 1999
+ *
+ *	This modified file may be copied and distributed in accordance
+ *	the above-referenced license. It is provided for critique and
+ *	developmental purposes without any warranty nor representation
+ *	by the authors or by TGA Technologies.
+ */
+
+#include <rtems/system.h>
+
+/*
+ * This is a exception vector table
+ *
+ * It has the same structure as the actual vector table (vectab)
+ */
+
+
+/* SH-2 ISR Table */
+#include <rtems/score/ispsh7045.h>
+
+proc_ptr _Hardware_isr_Table[256]={
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,		/* PWRon Reset, Maual Reset,...*/
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+_nmi_isp, _usb_isp,                               /* irq 11, 12*/
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp,
+/* trapa 0 -31 */
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_irq0_isp, _irq1_isp, _irq2_isp, _irq3_isp,   /* external H/W: irq 64-71 */
+_irq4_isp, _irq5_isp, _irq6_isp, _irq7_isp,
+_dma0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DMAC: irq 72-87*/
+_dma1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dma2_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dma3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua0_isp, _mtub0_isp, _mtuc0_isp, _mtud0_isp, /* MTUs: irq 88-127 */
+_mtuv0_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua1_isp, _mtub1_isp, _dummy_isp, _dummy_isp,
+_mtuv1_isp, _mtuu1_isp, _dummy_isp, _dummy_isp,
+_mtua2_isp, _mtub2_isp, _dummy_isp, _dummy_isp,
+_mtuv2_isp, _mtuu2_isp, _dummy_isp, _dummy_isp,
+_mtua3_isp, _mtub3_isp, _mtuc3_isp, _mtud3_isp,
+_mtuv3_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_mtua4_isp, _mtub4_isp, _mtuc4_isp, _mtud4_isp,
+_mtuv4_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_eri0_isp, _rxi0_isp, _txi0_isp, _tei0_isp, /* SCI0-1: irq 128-135*/
+_eri1_isp, _rxi1_isp, _txi1_isp, _tei1_isp,
+_adi0_isp, _adi1_isp, _dummy_isp, _dummy_isp, /* ADC0-1: irq 136-139*/
+_dtci_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* DTU: irq 140-143 */
+_cmt0_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* CMT0-1: irq 144-151 */
+_cmt1_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_wdt_isp, /* WDT: irq 152*/
+_bsc_isp, _dummy_isp, _dummy_isp, /* BSC: irq 153-155*/
+_oei_isp, /* I/O Port: irq 156*/
+};
+
+#define Str(a)#a
+
+/*
+ * Some versions of gcc and all version of egcs at least until egcs-1.1b
+ * are not able to handle #pragma interrupt correctly if more than 1 isr is
+ * contained in a file and when optimizing.
+ * We try to work around this problem by using the macro below.
+ */
+#define isp( name, number, func)\
+__asm__ (".global _"Str(name)"\n\t"\
+     "_"Str(name)":       \n\t"\
+     "    mov.l r0,@-r15   \n\t"\
+     "    mov.l r1,@-r15   \n\t"\
+     "    mov.l r2,@-r15   \n\t"\
+     "    mov.l r3,@-r15   \n\t"\
+     "    mov.l r4,@-r15   \n\t"\
+     "    mov.l r5,@-r15   \n\t"\
+     "    mov.l r6,@-r15   \n\t"\
+     "    mov.l r7,@-r15   \n\t"\
+     "    mov.l r14,@-r15  \n\t"\
+     "    sts.l pr,@-r15   \n\t"\
+     "    sts.l mach,@-r15 \n\t"\
+     "    sts.l macl,@-r15 \n\t"\
+     "    mov r15,r14      \n\t"\
+     "    mov.l "Str(name)"_v, r2 \n\t"\
+     "    mov.l "Str(name)"_k, r1\n\t"\
+     "    jsr @r1           \n\t"\
+     "    mov   r2,r4      \n\t"\
+     "    mov   r14,r15    \n\t"\
+     "    lds.l @r15+,macl \n\t"\
+     "    lds.l @r15+,mach \n\t"\
+     "    lds.l @r15+,pr   \n\t"\
+     "    mov.l @r15+,r14  \n\t"\
+     "    mov.l @r15+,r7   \n\t"\
+     "    mov.l @r15+,r6   \n\t"\
+     "    mov.l @r15+,r5   \n\t"\
+     "    mov.l @r15+,r4   \n\t"\
+     "    mov.l @r15+,r3   \n\t"\
+     "    mov.l @r15+,r2   \n\t"\
+     "    mov.l @r15+,r1   \n\t"\
+     "    mov.l @r15+,r0   \n\t"\
+     "    rte              \n\t"\
+     "    nop              \n\t"\
+     "    .align 2         \n\t"\
+     #name"_k: \n\t"\
+     ".long "Str(func)"\n\t"\
+     #name"_v: \n\t"\
+     ".long "Str(number));
+
+/************************************************
+ * Dummy interrupt service procedure for
+ * interrupts being not allowed --> Trap 34
+ ************************************************/
+__asm__ (" .section .text\n\
+.global __dummy_isp\n\
+__dummy_isp:\n\
+      mov.l r14,@-r15\n\
+      mov   r15, r14\n\
+      trapa #34\n\
+      mov.l @r15+,r14\n\
+      rte\n\
+      nop");
+
+/*******************************************************************
+ *     ISP Vector Table for sh7045 family of processors            *
+ *******************************************************************/
+
+
+/*****************************
+ * Non maskable interrupt
+ *****************************/
+isp( _nmi_isp, NMI_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * User break controller
+ *****************************/
+isp( _usb_isp, USB_ISP_V, ___ISR_Handler);
+
+/*****************************
+ *  External interrupts 0-7
+ *****************************/
+isp( _irq0_isp, IRQ0_ISP_V, ___ISR_Handler);
+isp( _irq1_isp, IRQ1_ISP_V, ___ISR_Handler);
+isp( _irq2_isp, IRQ2_ISP_V, ___ISR_Handler);
+isp( _irq3_isp, IRQ3_ISP_V, ___ISR_Handler);
+isp( _irq4_isp, IRQ4_ISP_V, ___ISR_Handler);
+isp( _irq5_isp, IRQ5_ISP_V, ___ISR_Handler);
+isp( _irq6_isp, IRQ6_ISP_V, ___ISR_Handler);
+isp( _irq7_isp, IRQ7_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * DMA - controller
+ *****************************/
+isp( _dma0_isp, DMA0_ISP_V, ___ISR_Handler);
+isp( _dma1_isp, DMA1_ISP_V, ___ISR_Handler);
+isp( _dma2_isp, DMA2_ISP_V, ___ISR_Handler);
+isp( _dma3_isp, DMA3_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Match timer unit
+ *****************************/
+
+/*****************************
+ * Timer 0
+ *****************************/
+isp( _mtua0_isp, MTUA0_ISP_V, ___ISR_Handler);
+isp( _mtub0_isp, MTUB0_ISP_V, ___ISR_Handler);
+isp( _mtuc0_isp, MTUC0_ISP_V, ___ISR_Handler);
+isp( _mtud0_isp, MTUD0_ISP_V, ___ISR_Handler);
+isp( _mtuv0_isp, MTUV0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 1
+ *****************************/
+isp( _mtua1_isp, MTUA1_ISP_V, ___ISR_Handler);
+isp( _mtub1_isp, MTUB1_ISP_V, ___ISR_Handler);
+isp( _mtuv1_isp, MTUV1_ISP_V, ___ISR_Handler);
+isp( _mtuu1_isp, MTUU1_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 2
+ *****************************/
+isp( _mtua2_isp, MTUA2_ISP_V, ___ISR_Handler);
+isp( _mtub2_isp, MTUB2_ISP_V, ___ISR_Handler);
+isp( _mtuv2_isp, MTUV2_ISP_V, ___ISR_Handler);
+isp( _mtuu2_isp, MTUU2_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 3
+ *****************************/
+isp( _mtua3_isp, MTUA3_ISP_V, ___ISR_Handler);
+isp( _mtub3_isp, MTUB3_ISP_V, ___ISR_Handler);
+isp( _mtuc3_isp, MTUC3_ISP_V, ___ISR_Handler);
+isp( _mtud3_isp, MTUD3_ISP_V, ___ISR_Handler);
+isp( _mtuv3_isp, MTUV3_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Timer 4
+ *****************************/
+isp( _mtua4_isp, MTUA4_ISP_V, ___ISR_Handler);
+isp( _mtub4_isp, MTUB4_ISP_V, ___ISR_Handler);
+isp( _mtuc4_isp, MTUC4_ISP_V, ___ISR_Handler);
+isp( _mtud4_isp, MTUD4_ISP_V, ___ISR_Handler);
+isp( _mtuv4_isp, MTUV4_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Serial interfaces
+ *****************************/
+
+/*****************************
+ * Serial interface 0
+ *****************************/
+isp( _eri0_isp,  ERI0_ISP_V, ___ISR_Handler);
+isp( _rxi0_isp,  RXI0_ISP_V, ___ISR_Handler);
+isp( _txi0_isp,  TXI0_ISP_V, ___ISR_Handler);
+isp( _tei0_isp,  TEI0_ISP_V, ___ISR_Handler);
+
+/*****************************
+ * Serial interface 1
+ *****************************/
+isp( _eri1_isp,  ERI1_ISP_V, ___ISR_Handler);
+isp( _rxi1_isp,  RXI1_ISP_V, ___ISR_Handler);
+isp( _txi1_isp,  TXI1_ISP_V, ___ISR_Handler);
+isp( _tei1_isp,  TEI1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * A/D converters
+ * ADC0-1
+ ******************************/
+isp( _adi0_isp,  ADI0_ISP_V, ___ISR_Handler);
+isp( _adi1_isp,  ADI1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ *  Data transfer controller
+ ******************************/
+isp( _dtci_isp,  DTC_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ *  Counter match timer
+ ******************************/
+isp( _cmt0_isp,  CMT0_ISP_V, ___ISR_Handler);
+isp( _cmt1_isp,  CMT1_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ *  Watchdog timer
+ ******************************/
+isp( _wdt_isp,  WDT_ISP_V, ___ISR_Handler);
+
+
+/******************************
+ * DRAM refresh control unit
+ * of bus state controller
+ ******************************/
+isp( _bsc_isp,  CMI_ISP_V, ___ISR_Handler);
+
+/******************************
+ *  I/O port
+ ******************************/
+isp( _oei_isp,  OEI_ISP_V, ___ISR_Handler);
+
+
+/*****************************
+ * Parity control unit of
+ * the bus state controller
+ * NOT PROVIDED IN SH-2
+ *****************************/
+/* isp( _prt_isp,  PRT_ISP_V, ___ISR_Handler); */
diff --git a/bsps/sh/gensh2/start/linkcmds b/bsps/sh/gensh2/start/linkcmds
new file mode 100644
index 0000000000..2c4d44a941
--- /dev/null
+++ b/bsps/sh/gensh2/start/linkcmds
@@ -0,0 +1,241 @@
+/*
+ * This is an adapted linker script from egcs-1.0.1 
+ *
+ * Memory layout for an SH7045F with main memory in area 2
+ * This memory layout it very similar to that used for Hitachi's
+ * EVB with CMON in FLASH
+ *
+ * NOTE: The ram start address may vary, all other start addresses are fixed
+ *       Not suiteable for gdb's simulator
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *	Modified to reflect SH7045F processor and EVB:
+ *	John M. Mills (jmills@tga.com)
+ *	TGA Technologies, Inc.
+ *      100 Pinnacle Way, Suite 140
+ *	Norcross, GA 30071 U.S.A.
+ *
+ *	This modified file may be copied and distributed in accordance
+ *	the above-referenced license. It is provided for critique and
+ *	developmental purposes without any warranty nor representation
+ *	by the authors or by TGA Technologies.
+ */
+
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+/* These assignments load code into SH7045F EVB SRAM for monitor debugging */
+
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00440000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 512K;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+
+MEMORY
+{
+  rom           : o = 0x00400000, l = 0x00040000
+  ram           : o = 0x00440000, l = 0x00080000
+  onchip_peri   : o = 0xFFFF8000, l = 0x00000800
+  onchip_ram    : o = 0xFFFFF000, l = 0x00001000
+}
+
+/* Sections are defined for RAM loading and monitor debugging */
+SECTIONS
+{
+  /* boot vector table */
+  .monvects 0x00400000 (NOLOAD): {
+    _monvects = . ;
+  } > rom
+
+  /* monitor play area */
+  .monram 0x00440000 (NOLOAD) : 
+  {
+  _ramstart = .;
+  } > ram 
+
+  /* monitor vector table */
+  .vects   0x00442000 (NOLOAD) : {
+    _vectab = . ;
+    *(.vects);
+  }
+
+  /* Read-only sections, merged into text segment: */
+
+  . = 0x00444000 ;
+  .interp        : { *(.interp) 	}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .gnu.version   : { *(.gnu.version)	}
+  .gnu.version_d : { *(.gnu.version_d)	}
+  .gnu.version_r : { *(.gnu.version_r)	}
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    } >ram
+  .rel.text      :
+    { *(.rel.text) *(.rel.gnu.linkonce.t*) }
+  .rel.data      :
+    { *(.rel.data) *(.rel.gnu.linkonce.d*) }
+  .rel.rodata    :
+    { *(.rel.rodata*) *(.rel.gnu.linkonce.r*) }
+  .rel.got       : { *(.rel.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rel.init      : { *(.rel.init)	}
+  .rel.fini      : { *(.rel.fini)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .plt      	 : { *(.plt)	}
+  .text   .   	 :
+  {
+    _start = .;
+    *(.text*)
+    *(.stub)
+
+    /*
+     * Special FreeBSD sysctl sections.
+     */
+    . = ALIGN (16);
+    ___start_set_sysctl_set = .;
+    *(set_sysc*);   /* set_sysctl_* but name is truncated by SH-coff */
+    ___stop_set_sysctl_set = ABSOLUTE(.);
+    *(set_doma*);   /* set_domain_* but name is truncated by SH-coff */
+    *(set_pseu*);   /* set_pseudo_* but name is truncated by SH-coff */
+
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  } > ram
+  _etext = .;
+  PROVIDE (etext = .);
+  .init    .  : { KEEP(*(.init))    } > ram =0
+  .fini    .  : { KEEP(*(.fini))    } > ram =0
+  .ctors   .  : { KEEP(*(.ctors))    } > ram =0
+  .dtors   .  : { KEEP(*(.dtors))    } > ram =0
+  .rodata  .  : { *(.rodata*) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram
+  .rodata1 .  : { *(.rodata1) } > ram
+  .tdata : {
+    __TLS_Data_begin = .;
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    __TLS_Data_end = .;
+  } > ram
+  .tbss : {
+    __TLS_BSS_begin = .;
+    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+    __TLS_BSS_end = .;
+  } > ram
+  __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+  __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+  __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+  __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+  __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+  __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(128) + (. & (128 - 1));
+  .data  .  :
+  {
+    *(.data*)
+    KEEP (*(SORT(.rtemsrwset.*)))
+    *(.gcc_exc*)
+    ___EH_FRAME_BEGIN__ = .;
+    *(.eh_fram*)
+    ___EH_FRAME_END__ = .;
+    LONG(0);
+    *(.gcc_except_table*)
+    *(.gnu.linkonce.d*)
+    CONSTRUCTORS
+  } > ram
+  .data1  . : { *(.data1) }
+  .got     .      : { *(.got.plt) *(.got) }
+  .dynamic .      : { *(.dynamic) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata   .  : { *(.sdata) }
+  _edata  =  .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .sbss    .  : { *(.sbss*) *(.scommon) }
+  .bss     .  :
+  {
+   *(.dynbss)
+   *(.bss .bss* .gnu.linkonce.b*)
+   *(COMMON)
+  } > ram
+  _end = . ;
+  PROVIDE (end = .);
+
+  _WorkAreaBase = . ;
+
+  _CPU_Interrupt_stack_low  = 0xFFFFF000;
+  _CPU_Interrupt_stack_high = 0xFFFFFFFF;
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram
+  /* These must appear regardless of  .  */
+}
diff --git a/bsps/sh/gensh2/start/linkcmds.ram b/bsps/sh/gensh2/start/linkcmds.ram
new file mode 100644
index 0000000000..c5349398ff
--- /dev/null
+++ b/bsps/sh/gensh2/start/linkcmds.ram
@@ -0,0 +1,244 @@
+/*
+ * This is an adapted linker script from egcs-1.0.1 
+ *
+ * Memory layout for an SH7045F with main memory in area 2
+ * This memory layout it very similar to that used for Hitachi's
+ * EVB with CMON in FLASH
+ *
+ * NOTE: The ram start address may vary, all other start addresses are fixed
+ *       Not suiteable for gdb's simulator
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *	Modified to reflect SH7045F processor and EVB:
+ *	John M. Mills (jmills@tga.com)
+ *	TGA Technologies, Inc.
+ *      100 Pinnacle Way, Suite 140
+ *	Norcross, GA 30071 U.S.A.
+ *
+ *	This modified file may be copied and distributed in accordance
+ *	the above-referenced license. It is provided for critique and
+ *	developmental purposes without any warranty nor representation
+ *	by the authors or by TGA Technologies.
+ */
+
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+/* These assignments load code into SH7045F EVB SRAM for monitor debugging */
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00440000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 512K;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+
+MEMORY
+{
+  rom           : o = 0x00400000, l = 0x00040000
+  ram           : o = 0x00440000, l = 0x00080000
+  onchip_peri   : o = 0xFFFF8000, l = 0x00000800
+  onchip_ram    : o = 0xFFFFF000, l = 0x00001000
+}
+
+/* Sections are defined for RAM loading and monitor debugging */
+SECTIONS
+{
+  /* boot vector table */
+  .monvects 0x00400000 (NOLOAD): {
+    _monvects = . ;
+  } > rom
+
+  /* monitor play area */
+  .monram 0x00440000 (NOLOAD) : 
+  {
+  _ramstart = .;
+  } > ram 
+
+  /* monitor vector table */
+  .vects   0x00442000 (NOLOAD) : {
+    _vectab = . ;
+    *(.vects);
+  }
+
+  /* Read-only sections, merged into text segment: */
+
+  . = 0x00444000 ;
+  .interp        : { *(.interp) 	}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .gnu.version   : { *(.gnu.version)	}
+  .gnu.version_d : { *(.gnu.version_d)	}
+  .gnu.version_r : { *(.gnu.version_r)	}
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    } >ram
+  .rel.text      :
+    { *(.rel.text) *(.rel.gnu.linkonce.t*) }
+  .rel.data      :
+    { *(.rel.data) *(.rel.gnu.linkonce.d*) }
+  .rel.rodata    :
+    { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
+  .rel.got       : { *(.rel.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rel.init      : { *(.rel.init)	}
+  .rel.fini      : { *(.rel.fini)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .init          : { *(.init)	} =0
+  .plt      	 : { *(.plt)	}
+  .text   .   	 :
+  {
+    *(.text*)
+    *(.stub)
+
+    /*
+     * Special FreeBSD sysctl sections.
+     */
+    . = ALIGN (16);
+    ___start_set_sysctl_set = .;
+    *(set_sysc*);   /* set_sysctl_* but name is truncated by SH-coff */
+    ___stop_set_sysctl_set = ABSOLUTE(.);
+    *(set_doma*);   /* set_domain_* but name is truncated by SH-coff */
+    *(set_pseudo_*);
+
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  } > ram
+  _etext = .;
+  PROVIDE (etext = .);
+  .fini    .  : { *(.fini)    } > ram =0
+  .rodata  .  : { *(.rodata) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram
+  .rodata1 .  : { *(.rodata1) } > ram
+  .tdata : {
+    __TLS_Data_begin = .;
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    __TLS_Data_end = .;
+  } > ram
+  .tbss : {
+    __TLS_BSS_begin = .;
+    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+    __TLS_BSS_end = .;
+  } > ram
+  __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+  __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+  __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+  __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+  __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+  __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(128) + (. & (128 - 1));
+  .data  .  :
+  {
+    *(.data)
+    KEEP (*(SORT(.rtemsrwset.*)))
+    *(.gnu.linkonce.d*)
+    CONSTRUCTORS
+  } > ram
+  .data1  . : { *(.data1) }
+  .ctors  .       :
+  {
+    ___ctors = .;
+    *(.ctors)
+    ___ctors_end = .;
+  }
+  .dtors  .       :
+  {
+    ___dtors = .;
+    *(.dtors)
+    ___dtors_end = .;
+  }
+  .got     .      : { *(.got.plt) *(.got) }
+  .dynamic .      : { *(.dynamic) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata   .  : { *(.sdata) }
+  _edata  =  .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .sbss    .  : { *(.sbss*) *(.scommon) }
+  .bss     .  :
+  {
+   *(.dynbss)
+   *(.bss .bss* .gnu.linkonce.b*)
+   *(COMMON)
+  } > ram
+  _end = . ;
+  PROVIDE (end = .);
+
+  _WorkAreaBase = . ;
+  . = 0x00480000 ;
+
+  _CPU_Interrupt_stack_low  = 0xFFFFF000;
+  _CPU_Interrupt_stack_high = 0xFFFFFFFF;
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram
+  /* These must appear regardless of  .  */
+}
diff --git a/bsps/sh/gensh2/start/linkcmds.rom b/bsps/sh/gensh2/start/linkcmds.rom
new file mode 100644
index 0000000000..4934c10269
--- /dev/null
+++ b/bsps/sh/gensh2/start/linkcmds.rom
@@ -0,0 +1,248 @@
+/*
+ * This is an adapted linker script from egcs-1.0.1 
+ *
+ * Memory layout for an SH7045F with main memory in area 2
+ * This memory layout it very similar to that used for Hitachi's
+ * EVB with CMON in FLASH
+ *
+ * NOTE: The ram start address may vary, all other start addresses are fixed
+ *       Not suiteable for gdb's simulator
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *	Modified to reflect SH7045F processor and EVB:
+ *	John M. Mills (jmills@tga.com)
+ *	TGA Technologies, Inc.
+ *      100 Pinnacle Way, Suite 140
+ *	Norcross, GA 30071 U.S.A.
+ *
+ *	This modified file may be copied and distributed in accordance
+ *	the above-referenced license. It is provided for critique and
+ *	developmental purposes without any warranty nor representation
+ *	by the authors or by TGA Technologies.
+ */
+
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+/* These asignments represent actual SH7045F EVB architecture */
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00400000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 0x0008000;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+
+MEMORY
+{
+  rom           : o = 0x00000000, l = 0x00040000
+  ram           : o = 0x00400000, l = 0x00080000
+  onchip_peri   : o = 0xFFFF8000, l = 0x00000800
+  onchip_ram    : o = 0xFFFFF000, l = 0x00001000
+}
+
+
+/* Sections are defined for RAM loading and monitor debugging */
+SECTIONS
+{
+  /* boot vector table */
+  .monvects 0x00000000 (NOLOAD): {
+    _monvects = . ;
+  } > rom
+
+  /* monitor play area */
+  .monram 0x00400000 (NOLOAD) : 
+  {
+  _ramstart = .;
+  } > ram 
+
+  /* monitor vector table */
+  .vects   0x00402000 (NOLOAD) : {
+    _vectab = . ;
+    *(.vects);
+  }
+
+  /* Read-only sections, merged into text segment: */
+
+  . = 0x00404000 ;
+  .interp        : { *(.interp) 	}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .gnu.version   : { *(.gnu.version)	}
+  .gnu.version_d : { *(.gnu.version_d)	}
+  .gnu.version_r : { *(.gnu.version_r)	}
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    } >ram
+  .rel.text      :
+    { *(.rel.text) *(.rel.gnu.linkonce.t*) }
+  .rel.data      :
+    { *(.rel.data) *(.rel.gnu.linkonce.d*) }
+  .rel.rodata    :
+    { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
+  .rel.got       : { *(.rel.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rel.init      : { *(.rel.init)	}
+  .rel.fini      : { *(.rel.fini)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .init          : { *(.init)	} =0
+  .plt      	 : { *(.plt)	}
+  .text   .   	 :
+  {
+    *(.text*)
+    *(.stub)
+
+    /*
+     * Special FreeBSD sysctl sections.
+     */
+    . = ALIGN (16);
+    ___start_set_sysctl_set = .;
+    *(set_sysc*);   /* set_sysctl_* but name is truncated by SH-coff */
+    ___stop_set_sysctl_set = ABSOLUTE(.);
+    *(set_doma*);   /* set_domain_* but name is truncated by SH-coff */
+    *(set_pseudo_*);
+
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  } > ram
+  _etext = .;
+  PROVIDE (etext = .);
+  .fini    .  : { *(.fini)    } > ram =0
+  .rodata  .  : { *(.rodata) KEEP (*(SORT(.rtemsroset.*))) *(.gnu.linkonce.r*) } > ram
+  .rodata1 .  : { *(.rodata1) } > ram
+  .tdata : {
+    __TLS_Data_begin = .;
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    __TLS_Data_end = .;
+  } > ram
+  .tbss : {
+    __TLS_BSS_begin = .;
+    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+    __TLS_BSS_end = .;
+  } > ram
+  __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+  __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+  __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+  __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+  __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+  __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(128) + (. & (128 - 1));
+  .data  .  :
+  {
+    *(.data)
+    KEEP (*(SORT(.rtemsrwset.*)))
+    *(.gnu.linkonce.d*)
+    CONSTRUCTORS
+  } > ram
+  .data1  . : { *(.data1) }
+  .ctors  .       :
+  {
+    ___ctors = .;
+    *(.ctors)
+    ___ctors_end = .;
+  }
+  .dtors  .       :
+  {
+    ___dtors = .;
+    *(.dtors)
+    ___dtors_end = .;
+  }
+  .got     .      : { *(.got.plt) *(.got) }
+  .dynamic .      : { *(.dynamic) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata   .  : { *(.sdata) }
+  _edata  =  .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .sbss    .  : { *(.sbss*) *(.scommon) }
+  .bss     .  :
+  {
+   *(.dynbss)
+   *(.bss .bss* .gnu.linkonce.b*)
+   *(COMMON)
+  } > ram
+  _end = . ;
+  PROVIDE (end = .);
+
+  _HeapStart = . ;
+  . = . + 1024 * 20 ;
+  PROVIDE( _HeapEnd = . );
+
+  _WorkAreaBase = . ;
+
+  _CPU_Interrupt_stack_low  = 0xFFFFF000;
+  _CPU_Interrupt_stack_high = 0xFFFFFFFF;
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+  .stack 0xFFFFFEC0 : { _stack = .; *(.stack) } > onchip_ram
+  /* These must appear regardless of  .  */
+}
diff --git a/bsps/sh/gensh4/start/bsp_specs b/bsps/sh/gensh4/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/sh/gensh4/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/sh/gensh4/start/cpu_asm.c b/bsps/sh/gensh4/start/cpu_asm.c
new file mode 100644
index 0000000000..52a033bb75
--- /dev/null
+++ b/bsps/sh/gensh4/start/cpu_asm.c
@@ -0,0 +1,105 @@
+/*
+ *  This file contains the basic algorithms for all assembly code used
+ *  in an specific CPU port of RTEMS.  These algorithms must be implemented
+ *  in assembly language
+ *
+ *  NOTE:  This port uses a C file with inline assembler instructions
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+/*
+ *  This is supposed to be an assembly file.  This means that system.h
+ *  and cpu.h should not be included in a "real" cpu_asm file.  An
+ *  implementation in assembly should include "cpu_asm.h"
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/threaddispatch.h>
+#include <rtems/score/sh.h>
+#include <rtems/score/ispsh7750.h>
+#include <rtems/score/iosh7750.h>
+#include <rtems/score/sh4_regs.h>
+#include <rtems/score/sh_io.h>
+
+/* from cpu_isps.c */
+extern proc_ptr         _Hardware_isr_Table[];
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  unsigned long    *_old_stack_ptr;
+#endif
+
+register unsigned long  *stack_ptr __asm__ ("r15");
+
+/*
+ *  This routine provides the RTEMS interrupt management.
+ */
+
+void __ISR_Handler( uint32_t   vector)
+{
+  ISR_Level level;
+
+  _ISR_Local_disable( level );
+
+   _Thread_Dispatch_disable();
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if ( _ISR_Nest_level == 0 )
+    {
+      /* Install irq stack */
+      _old_stack_ptr = stack_ptr;
+      stack_ptr = _CPU_Interrupt_stack_high;
+    }
+
+#endif
+
+  _ISR_Nest_level++;
+
+  _ISR_Local_enable( level );
+
+  /* call isp */
+  if ( _ISR_Vector_table[ vector])
+    (*_ISR_Vector_table[ vector ])( vector );
+
+  _ISR_Local_disable( level );
+
+  _Thread_Dispatch_enable( _Per_CPU_Get() );
+
+  _ISR_Nest_level--;
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if ( _ISR_Nest_level == 0 )
+    /* restore old stack pointer */
+    stack_ptr = _old_stack_ptr;
+#endif
+
+  _ISR_Local_enable( level );
+
+  if ( _ISR_Nest_level )
+    return;
+
+  if ( !_Thread_Dispatch_is_enabled() ) {
+    return;
+  }
+
+  if ( _Thread_Dispatch_necessary ) {
+    _Thread_Dispatch();
+  }
+}
diff --git a/bsps/sh/gensh4/start/ispsh7750.c b/bsps/sh/gensh4/start/ispsh7750.c
new file mode 100644
index 0000000000..5a1282f583
--- /dev/null
+++ b/bsps/sh/gensh4/start/ispsh7750.c
@@ -0,0 +1,317 @@
+/*
+ * SH7750 interrupt support.
+ *
+ * Copyright (C) 2001 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ *  Based on work:
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *	Modified to reflect isp entries for sh7045 processor:
+ *	John M. Mills (jmills@tga.com)
+ *	TGA Technologies, Inc.
+ *      100 Pinnacle Way, Suite 140
+ *	Norcross, GA 30071 U.S.A.
+ *	August, 1999
+ *
+ *	This modified file may be copied and distributed in accordance
+ *	the above-referenced license. It is provided for critique and
+ *	developmental purposes without any warranty nor representation
+ *	by the authors or by TGA Technologies.
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/isr.h>
+
+/*
+ * This is a exception vector table
+ *
+ * It has the same structure as the actual vector table (vectab)
+ */
+
+
+#include <rtems/score/ispsh7750.h>
+#include <rtems/score/sh4_regs.h>
+#include <rtems/score/sh7750_regs.h>
+
+/* VBR register contents saved on startup -- used to hook exception by debug
+ * agent */
+void *_VBR_Saved;
+
+#define __STRINGIFY1__(x) #x
+#define __STRINGIFY__(x) __STRINGIFY1__(x)
+
+#define STOP_TIMER \
+     "        mov.l TSTR_k,r0      \n"                             \
+     "        mov.b @r0,r1         \n"                             \
+     "        and   #" __STRINGIFY__(~SH7750_TSTR_STR0) ",r1\n"    \
+     "        mov.b r1,@r0         \n"
+
+#define START_TIMER \
+     "        mov.l TSTR_k,r0      \n"                             \
+     "        mov.b @r0,r1         \n"                             \
+     "        or    #" __STRINGIFY__(SH7750_TSTR_STR0) ",r1\n"     \
+     "        mov.b r1,@r0         \n"
+
+__asm__ ("        .text\n"
+     "        .balign 256\n"
+     "        .global __vbr_base\n"
+     "__vbr_base:\n"
+     "        .org __vbr_base + 0x100\n"
+     "vbr_100:\n"
+     "        mov.l  r0,@-r15\n"
+     "        mov.l  r1,@-r15\n"
+     "        mov.l  __VBR_Saved100_k, r0\n"
+     "        mov.l  offset100_k,r1\n"
+     "        mov.l  @r0,r0\n"
+     "        add    r1,r0\n"
+     "        mov.l  @r15+,r1\n"
+     "        jmp    @r0\n"
+     "        mov.l  @r15+,r0\n"
+     "        .align 2\n"
+     "__VBR_Saved100_k:\n"
+     "        .long __VBR_Saved\n"
+     "offset100_k:\n"
+     "        .long  0x100\n"
+
+     "        .org __vbr_base + 0x400\n"
+     "vbr_400:\n"
+     "        mov.l  r0,@-r15\n"
+     "        mov.l  r1,@-r15\n"
+     "        mov.l  __VBR_Saved400_k, r0\n"
+     "        mov.l  offset400_k,r1\n"
+     "        mov.l  @r0,r0\n"
+     "        add    r1,r0\n"
+     "        mov.l  @r15+,r1\n"
+     "        jmp    @r0\n"
+     "        mov.l  @r15+,r0\n"
+     "        .align 2\n"
+     "__VBR_Saved400_k:\n"
+     "        .long __VBR_Saved\n"
+     "offset400_k:\n"
+     "        .long  0x400\n"
+
+     "        .org __vbr_base + 0x600\n"
+     "vbr_600:\n"
+     "    mov.l r0,@-r15   \n"
+     "    mov.l r1,@-r15   \n"
+     "    stc   sr,r0      \n"
+     "    mov.l __vbr_600_sr_and_k,r1\n"
+     "    and   r1,r0      \n"
+     "    mov.l __vbr_600_sr_or_k,r1\n"
+     "    or    r1,r0      \n"
+     "    ldc   r0,sr      \n"
+     "    ldc.l @r15+,r1_bank\n"
+     "    ldc.l @r15+,r0_bank\n"
+     "    mov.l r0,@-r15   \n"
+     "    mov.l r1,@-r15   \n"
+     "    mov.l r2,@-r15   \n"
+     "    mov.l r3,@-r15   \n"
+     "    mov.l r4,@-r15   \n"
+     "    mov.l r5,@-r15   \n"
+     "    mov.l r6,@-r15   \n"
+     "    mov.l r7,@-r15   \n"
+#if 0
+     "    mov.l r8,@-r15   \n"
+     "    mov.l r9,@-r15   \n"
+     "    mov.l r10,@-r15  \n"
+     "    mov.l r11,@-r15  \n"
+     "    mov.l r12,@-r15  \n"
+     "    mov.l r13,@-r15  \n"
+#endif
+     "    mov.l r14,@-r15  \n"
+     "    sts.l fpscr,@-r15\n"
+     "    sts.l fpul,@-r15 \n"
+     "    mov.l __ISR_temp_fpscr_k,r0   \n"
+     "    lds   r0,fpscr   \n"
+     "    fmov  fr0,@-r15  \n"
+     "    fmov  fr1,@-r15  \n"
+     "    fmov  fr2,@-r15  \n"
+     "    fmov  fr3,@-r15  \n"
+     "    fmov  fr4,@-r15  \n"
+     "    fmov  fr5,@-r15  \n"
+     "    fmov  fr6,@-r15  \n"
+     "    fmov  fr7,@-r15  \n"
+     "    fmov  fr8,@-r15  \n"
+     "    fmov  fr9,@-r15  \n"
+     "    fmov  fr10,@-r15 \n"
+     "    fmov  fr11,@-r15 \n"
+     "    fmov  fr12,@-r15 \n"
+     "    fmov  fr13,@-r15 \n"
+     "    fmov  fr14,@-r15 \n"
+     "    fmov  fr15,@-r15 \n"
+
+     "    sts.l pr,@-r15   \n"
+     "    sts.l mach,@-r15 \n"
+     "    sts.l macl,@-r15 \n"
+     "    stc.l spc,@-r15  \n"
+     "    stc.l ssr,@-r15  \n"
+     "    mov r15,r14      \n"
+#if 0
+     "    stc   ssr,r0     \n"
+     "    ldc   r0,sr      \n"
+#endif
+     "    mov.l __ISR_Handler_k, r1\n"
+     "    mov.l _INTEVT_k,r4\n"
+     "    mov.l @r4,r4     \n"
+     "    shlr2 r4         \n"
+     "    shlr  r4         \n"
+
+     "    mov.l _ISR_Table_k,r0\n"
+     "    mov.l @r0,r0     \n"
+     "    add   r4,r0      \n"
+     "    mov.l @r0,r0     \n"
+     "    cmp/eq #0,r0     \n"
+     "    bt    _ipl_hook  \n"
+
+
+     "    jsr @r1          \n"
+     "     shlr2 r4        \n"
+     "    mov   r14,r15    \n"
+     "    ldc.l @r15+,ssr  \n"
+     "    ldc.l @r15+,spc  \n"
+     "    lds.l @r15+,macl \n"
+     "    lds.l @r15+,mach \n"
+     "    lds.l @r15+,pr   \n"
+     "    mov.l __ISR_temp_fpscr_k,r0   \n"
+     "    lds   r0,fpscr   \n"
+
+     "    fmov  @r15+,fr15 \n"
+     "    fmov  @r15+,fr14 \n"
+     "    fmov  @r15+,fr13 \n"
+     "    fmov  @r15+,fr12 \n"
+     "    fmov  @r15+,fr11 \n"
+     "    fmov  @r15+,fr10 \n"
+     "    fmov  @r15+,fr9  \n"
+     "    fmov  @r15+,fr8  \n"
+     "    fmov  @r15+,fr7  \n"
+     "    fmov  @r15+,fr6  \n"
+     "    fmov  @r15+,fr5  \n"
+     "    fmov  @r15+,fr4  \n"
+     "    fmov  @r15+,fr3  \n"
+     "    fmov  @r15+,fr2  \n"
+     "    fmov  @r15+,fr1  \n"
+     "    fmov  @r15+,fr0  \n"
+     "    lds.l @r15+,fpul \n"
+     "    lds.l @r15+,fpscr\n"
+     "    mov.l @r15+,r14  \n"
+#if 0
+     "    mov.l @r15+,r13  \n"
+     "    mov.l @r15+,r12  \n"
+     "    mov.l @r15+,r11  \n"
+     "    mov.l @r15+,r10  \n"
+     "    mov.l @r15+,r9   \n"
+     "    mov.l @r15+,r8   \n"
+#endif
+
+     "    mov.l @r15+,r7   \n"
+     "    mov.l @r15+,r6   \n"
+     "    mov.l @r15+,r5   \n"
+     "    mov.l @r15+,r4   \n"
+     "    mov.l @r15+,r3   \n"
+     "    mov.l @r15+,r2   \n"
+     "    mov.l @r15+,r1   \n"
+     "    mov.l @r15+,r0   \n"
+     "    rte              \n"
+     "    nop              \n"
+     "    .align 2         \n"
+     "__vbr_600_sr_and_k:    \n"
+     "    .long " __STRINGIFY__(~(SH4_SR_RB | SH4_SR_BL)) "\n"
+     "__vbr_600_sr_or_k:     \n"
+     "    .long " __STRINGIFY__(SH4_SR_IMASK) "\n"
+     "__ISR_Handler_k:     \n"
+     "    .long ___ISR_Handler\n"
+     "_INTEVT_k:           \n"
+     "    .long " __STRINGIFY__(SH7750_INTEVT) "\n"
+     "_ISR_Table_k:        \n"
+     "    .long   __ISR_Vector_table\n"
+
+     "_ipl_hook:           \n"
+     "    mov   r14,r15    \n"
+     "    ldc.l @r15+,ssr  \n"
+     "    ldc.l @r15+,spc  \n"
+     "    lds.l @r15+,macl \n"
+     "    lds.l @r15+,mach \n"
+     "    lds.l @r15+,pr   \n"
+     "    mov.l __ISR_temp_fpscr_k,r0   \n"
+     "    lds   r0,fpscr   \n"
+     "    fmov  @r15+,fr15 \n"
+     "    fmov  @r15+,fr14 \n"
+     "    fmov  @r15+,fr13 \n"
+     "    fmov  @r15+,fr12 \n"
+     "    fmov  @r15+,fr11 \n"
+     "    fmov  @r15+,fr10 \n"
+     "    fmov  @r15+,fr9  \n"
+     "    fmov  @r15+,fr8  \n"
+     "    fmov  @r15+,fr7  \n"
+     "    fmov  @r15+,fr6  \n"
+     "    fmov  @r15+,fr5  \n"
+     "    fmov  @r15+,fr4  \n"
+     "    fmov  @r15+,fr3  \n"
+     "    fmov  @r15+,fr2  \n"
+     "    fmov  @r15+,fr1  \n"
+     "    fmov  @r15+,fr0  \n"
+     "    lds.l @r15+,fpul \n"
+     "    lds.l @r15+,fpscr\n"
+     "    mov.l @r15+,r14  \n"
+
+     "    mov.l @r15+,r13  \n"
+     "    mov.l @r15+,r12  \n"
+     "    mov.l @r15+,r11  \n"
+     "    mov.l @r15+,r10  \n"
+     "    mov.l @r15+,r9   \n"
+     "    mov.l @r15+,r8   \n"
+
+
+     "    mov.l @r15+,r7   \n"
+     "    mov.l @r15+,r6   \n"
+     "    mov.l @r15+,r5   \n"
+     "    mov.l @r15+,r4   \n"
+     "    mov.l @r15+,r3   \n"
+     "    mov.l @r15+,r2   \n"
+     "    mov.l  __VBR_Saved600_k, r0\n"
+     "    mov.l  offset600_k,r1\n"
+     "    mov.l  @r0,r0\n"
+     "    add    r1,r0\n"
+     "    mov.l  @r15+,r1\n"
+     "    jmp    @r0\n"
+     "    mov.l  @r15+,r0\n"
+     "    .align 2\n"
+     "__ISR_temp_fpscr_k:  \n"
+     "    .long  " __STRINGIFY__(SH4_FPSCR_PR) " \n"
+     "__VBR_Saved600_k:\n"
+     "        .long __VBR_Saved\n"
+     "offset600_k:\n"
+     "        .long  0x600\n"
+
+ );
+
+
+/************************************************
+ * Dummy interrupt service procedure for
+ * interrupts being not allowed --> Trap 2
+ ************************************************/
+__asm__ (" .section .text\n\
+.global __dummy_isp\n\
+__dummy_isp:\n\
+      mov.l r14,@-r15\n\
+      mov   r15, r14\n\
+      trapa #2\n\
+      mov.l @r15+,r14\n\
+      rte\n\
+      nop");
diff --git a/bsps/sh/gensh4/start/linkcmds b/bsps/sh/gensh4/start/linkcmds
new file mode 100644
index 0000000000..de6bb05693
--- /dev/null
+++ b/bsps/sh/gensh4/start/linkcmds
@@ -0,0 +1,193 @@
+/*
+ * This file contains GNU linker directives for an general SH4 
+ * board.
+ *
+ * Variations in memory size and allocation can be made by
+ * overriding some values with linker command-line arguments.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x80000000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 4M;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+
+/*
+ * Area assignments:
+ *     Area 0: Flash memory, SRAM interface
+ *     Area 1: GDC
+ *     Area 2: SDRAM
+ *     Area 3-6: unused
+ */
+MEMORY
+{
+  ram           : o = 0x88100000, l = 7M
+  rom           : o = 0x80000000, l = 4M
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .text      :
+  {
+    _start = .;
+    *(.text*)
+
+    /*
+     * Special FreeBSD sysctl sections.
+     */
+    . = ALIGN (16);
+    ___start_set_sysctl_set = .;
+    *(set_sysc*);   /* set_sysctl_* but name is truncated by SH-coff */
+    ___stop_set_sysctl_set = ABSOLUTE(.);
+    *(set_doma*);   /* set_domain_* but name is truncated by SH-coff */
+    *(set_pseu*);   /* set_pseudo_* but name is truncated by SH-coff */
+
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  } > ram
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    } >ram
+  _etext = .;
+  PROVIDE (etext = .);
+  .init    .  : { KEEP(*(.init))    } > ram =0
+  .fini    .  : { KEEP(*(.fini))    } > ram =0
+  .ctors   .  : { KEEP(*(.ctors))    } > ram =0
+  .dtors   .  : { KEEP(*(.dtors))    } > ram =0
+  .rodata   : 
+  { 
+    *(.rodata) 
+    *(.rodata.*) 
+    KEEP (*(SORT(.rtemsroset.*)))
+    *(.gnu.linkonce.r*) 
+  } > ram
+  .tdata : {
+    __TLS_Data_begin = .;
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    __TLS_Data_end = .;
+  } > ram
+  .tbss : {
+    __TLS_BSS_begin = .;
+    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+    __TLS_BSS_end = .;
+  } > ram
+  __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+  __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+  __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+  __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+  __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+  __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(128) + (. & (128 - 1));
+  .data    :
+  {
+    copy_start = .;
+    *(.data*)
+    KEEP (*(SORT(.rtemsrwset.*)))
+    *(.gcc_exc*)
+    ___EH_FRAME_BEGIN__ = .;
+    *(.eh_fram*)
+    ___EH_FRAME_END__ = .;
+    LONG(0);
+    *(.gcc_except_table*)
+    *(.gnu.linkonce.d*)
+    SORT(CONSTRUCTORS)
+    copy_end = .;
+  } > ram
+  .eh_frame : { *(.eh_frame) } > ram
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .bss       :
+  {
+   __bss_start = .;
+   *(.dynbss)
+   *(.bss .bss* .gnu.linkonce.b*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+   __bss_end = .;
+  } > ram
+
+  .stack . : {
+    . = . + 4096;
+  }
+
+  . = ALIGN(16);
+  _WorkAreaBase = . ;
+
+  . = ALIGN(16);
+  _CPU_Interrupt_stack_low  = . ;
+  _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack : { _stack = .; *(.stack) }
+  /* These must appear regardless of  .  */
+}
diff --git a/bsps/sh/gensh4/start/linkcmds.rom b/bsps/sh/gensh4/start/linkcmds.rom
new file mode 100644
index 0000000000..13c6096af1
--- /dev/null
+++ b/bsps/sh/gensh4/start/linkcmds.rom
@@ -0,0 +1,239 @@
+/*
+ * This file contains GNU linker directives for an general SH4 
+ * board.
+ *
+ * Variations in memory size and allocation can be made by
+ * overriding some values with linker command-line arguments.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+
+OUTPUT_FORMAT("elf32-shl", "elf32-shl",
+	      "elf32-shl")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x88000000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 8M;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : (2 * 1024 * 1024);
+
+/*
+ * Area assignments:
+ *     Area 0: Flash memory, SRAM interface
+ *     Area 1: GDC
+ *     Area 2: SDRAM
+ *     Area 3-6: unused
+ */
+MEMORY
+{
+/*
+ * Real values
+ */
+  ram           : o = 0x88000000, l = 8M
+  rom           : o = 0x80000000, l = 4M
+/*
+ * Fake values to test from gdb
+ */
+/*
+  ram           : o = 0x88100000, l = 4M
+  rom           : o = 0x88500000, l = 3M
+*/
+}
+
+SECTIONS
+{
+  /* Read-only sections, merged into text segment: */
+  .init          : 
+  { 
+    KEEP (*(.init))
+  } =0
+  .text      :
+  {
+    *(.text*)
+
+    /*
+     * Special FreeBSD sysctl sections.
+     */
+    . = ALIGN (16);
+    ___start_set_sysctl_set = .;
+    *(set_sysc*);   /* set_sysctl_* but name is truncated by SH-coff */
+    ___stop_set_sysctl_set = ABSOLUTE(.);
+    *(set_doma*);   /* set_domain_* but name is truncated by SH-coff */
+    *(set_pseudo_*);
+
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  } > rom
+  _etext = .;
+  PROVIDE (etext = .);
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    } >ram
+  .fini      :
+  {
+    KEEP (*(.fini))
+  } =0
+  .rodata   : 
+  { 
+    *(.rodata) 
+    *(.rodata.*) 
+    KEEP (*(SORT(.rtemsroset.*)))
+    *(.gnu.linkonce.r*) 
+    . = ALIGN(32);
+  } > rom
+  .tdata : {
+    __TLS_Data_begin = .;
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    __TLS_Data_end = .;
+  } > rom
+  .tbss : {
+    __TLS_BSS_begin = .;
+    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+    __TLS_BSS_end = .;
+  } > rom
+  __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+  __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+  __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+  __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+  __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+  __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+  .ctors   : 
+  {
+    ___ctors = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    ___ctors_end = .;
+  } > rom
+   .dtors         :
+  {
+    ___dtors = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    ___dtors_end = .;
+    copy_start_in_rom = .;
+  } > rom
+
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(128) + (. & (128 - 1));
+  .data     : AT(LOADADDR(.dtors) + SIZEOF(.dtors))
+  {
+    copy_start = .;
+    *(.data)
+    *(.data.*)
+    KEEP (*(SORT(.rtemsrwset.*)))
+    *(.gnu.linkonce.d*)
+    SORT(CONSTRUCTORS)
+    copy_end = .;
+  } > ram
+  .eh_frame : { *(.eh_frame) } > ram
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .bss       :
+  {
+   __bss_start = .;
+   *(.dynbss)
+   *(.bss .bss* .gnu.linkonce.b*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+   __bss_end = .;
+  } > ram
+
+  . = ALIGN(16);
+  _WorkAreaBase = . ;
+
+  . = ALIGN(16);
+  .stack . : {
+     stack_start = .;
+     . = . + 4096;
+     stack_end = .;
+  }
+
+  . = ALIGN(16);
+  _CPU_Interrupt_stack_low  = . ;
+  _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack : { _stack = .; *(.stack) }
+  /* These must appear regardless of  .  */
+}
diff --git a/bsps/sh/gensh4/start/linkcmds.rom2ram b/bsps/sh/gensh4/start/linkcmds.rom2ram
new file mode 100644
index 0000000000..cc14d4e98d
--- /dev/null
+++ b/bsps/sh/gensh4/start/linkcmds.rom2ram
@@ -0,0 +1,243 @@
+/*
+ * This file contains GNU linker directives for an general SH4 
+ * board.
+ *
+ * Variations in memory size and allocation can be made by
+ * overriding some values with linker command-line arguments.
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+
+OUTPUT_FORMAT("elf32-shl", "elf32-shl",
+	      "elf32-shl")
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+/* Do we need any of these for elf?
+   __DYNAMIC = 0;    */
+
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x88000000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 8M;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : (2 * 1024 * 1024);
+
+/*
+ * Area assignments:
+ *     Area 0: Flash memory, SRAM interface
+ *     Area 1: GDC
+ *     Area 2: SDRAM
+ *     Area 3-6: unused
+ */
+MEMORY
+{
+/*
+ * Real values
+ */
+  ram           : o = 0x88000000, l = 8M
+  rom           : o = 0x80000000, l = 4M
+/*
+ * Fake values to test from gdb
+ */
+/*
+  ram           : o = 0x88100000, l = 4M
+  rom           : o = 0x88500000, l = 3M
+*/
+}
+
+SECTIONS
+{
+  rom : {
+    copy_start_in_rom = .;
+  } >rom
+
+  /* Read-only sections, merged into text segment: */
+  .init          : 
+  { 
+    KEEP (*(.init))
+  } =0
+  .text      : AT(copy_start_in_rom)
+  {
+    copy_start = .;
+    *(.text*)
+
+    /*
+     * Special FreeBSD sysctl sections.
+     */
+    . = ALIGN (16);
+    ___start_set_sysctl_set = .;
+    *(set_sysc*);   /* set_sysctl_* but name is truncated by SH-coff */
+    ___stop_set_sysctl_set = ABSOLUTE(.);
+    *(set_doma*);   /* set_domain_* but name is truncated by SH-coff */
+    *(set_pseudo_*);
+
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  } > ram
+  _etext = .;
+  PROVIDE (etext = .);
+  .fini      :
+  {
+    KEEP (*(.fini))
+  } =0
+  .rodata   :  AT(LOADADDR(.text) + SIZEOF(.text))
+  { 
+    *(.rodata) 
+    *(.rodata.*) 
+    KEEP (*(SORT(.rtemsroset.*)))
+    *(.gnu.linkonce.r*) 
+    . = ALIGN(32);
+  } > ram
+  .tdata : {
+    __TLS_Data_begin = .;
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    __TLS_Data_end = .;
+  } > ram
+  .tbss : {
+    __TLS_BSS_begin = .;
+    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+    __TLS_BSS_end = .;
+  } > ram
+  __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+  __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+  __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+  __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+  __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+  __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+  .ctors   :  AT(LOADADDR(.rodata) + SIZEOF(.rodata))
+  {
+    ___ctors = .;
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    /* We don't want to include the .ctor section from
+       from the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+    ___ctors_end = .;
+  } > ram
+   .dtors         : AT(LOADADDR(.ctors) + SIZEOF(.ctors))
+  {
+    ___dtors = .;
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+    ___dtors_end = .;
+  } > ram
+
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(128) + (. & (128 - 1));
+  .data     : AT(LOADADDR(.dtors) + SIZEOF(.dtors))
+  {
+    *(.data)
+    *(.data.*)
+    KEEP (*(SORT(.rtemsrwset.*)))
+    *(.gnu.linkonce.d*)
+    SORT(CONSTRUCTORS)
+    copy_end = .;
+  } > ram
+  .eh_frame : { *(.eh_frame) } > ram
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .bss       :
+  {
+   __bss_start = .;
+   *(.dynbss)
+   *(.bss .bss* .gnu.linkonce.b*)
+   *(COMMON)
+   /* Align here to ensure that the .bss section occupies space up to
+      _end.  Align after .bss to ensure correct alignment even if the
+      .bss section disappears because there are no input sections.  */
+   . = ALIGN(32 / 8);
+   __bss_end = .;
+  } > ram
+
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    } >ram
+  . = ALIGN(16);
+
+  _WorkAreaBase = . ;
+
+  . = ALIGN(16);
+  .stack . : {
+     stack_start = .;
+     . = . + 4096;
+     stack_end = .;
+  }
+
+  . = ALIGN(16);
+  _CPU_Interrupt_stack_low  = . ;
+  _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+  .stack : { _stack = .; *(.stack) }
+  /* These must appear regardless of  .  */
+}
diff --git a/bsps/sh/shared/start/bspstart.c b/bsps/sh/shared/start/bspstart.c
new file mode 100644
index 0000000000..57b2c9e1ef
--- /dev/null
+++ b/bsps/sh/shared/start/bspstart.c
@@ -0,0 +1,63 @@
+/*
+ *  This routine does the bulk of the system initialization.
+ */
+
+/*
+ *  COPYRIGHT (c) 2001.
+ *  Ralf Corsepius (corsepiu@faw.uni-ulm.de).
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ *
+ *  COPYRIGHT (c) 2001.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <rtems/score/percpu.h>
+
+uint32_t bsp_clicks_per_second;
+
+#ifndef START_HW_INIT
+  void bsp_hw_init(void);
+#endif
+
+/*
+ *  bsp_start
+ *
+ *  This routine does the bulk of the system initialization.
+ */
+void bsp_start( void )
+{
+  /*
+   * For real boards you need to setup the hardware
+   * and need to copy the vector table from rom to ram.
+   *
+   * Depending on the board this can either be done from inside the rom
+   * startup code, rtems startup code or here.
+   */
+
+  #ifndef START_HW_INIT
+    /* board hardware setup here, or from 'start.S' */
+    bsp_hw_init();
+  #endif
+
+  /*
+   *  initialize the interrupt stack for this BSP
+   */
+  #if ( CPU_ALLOCATE_INTERRUPT_STACK == FALSE )
+    _CPU_Interrupt_stack_low = &CPU_Interrupt_stack_low;
+    _CPU_Interrupt_stack_high = &CPU_Interrupt_stack_high;
+  #endif
+
+  /*
+   *  initialize the device driver parameters
+   */
+  bsp_clicks_per_second = CPU_CLOCK_RATE_HZ;
+}
diff --git a/bsps/sh/shsim/start/bsp_specs b/bsps/sh/shsim/start/bsp_specs
new file mode 100644
index 0000000000..87638cc027
--- /dev/null
+++ b/bsps/sh/shsim/start/bsp_specs
@@ -0,0 +1,9 @@
+%rename endfile old_endfile
+%rename startfile old_startfile
+
+*startfile:
+%{!qrtems: %(old_startfile)} \
+%{!nostdlib: %{qrtems: crti.o%s crtbegin.o%s}}
+
+*endfile:
+%{!qrtems: %(old_endfile)} %{qrtems: crtend.o%s crtn.o%s}
diff --git a/bsps/sh/shsim/start/cpu_asm.c b/bsps/sh/shsim/start/cpu_asm.c
new file mode 100644
index 0000000000..2ca8926a24
--- /dev/null
+++ b/bsps/sh/shsim/start/cpu_asm.c
@@ -0,0 +1,83 @@
+/*
+ *  Support for SuperH Simulator in GDB
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2008.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems/system.h>
+#include <rtems/score/cpu.h>
+#include <rtems/score/isr.h>
+#include <rtems/score/percpu.h>
+#include <rtems/score/threaddispatch.h>
+#include <rtems/score/sh.h>
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  unsigned long    *_old_stack_ptr;
+#endif
+
+register unsigned long  *stack_ptr __asm__ ("r15");
+
+void __ISR_Handler(uint32_t vector);
+
+/*
+ *  This routine provides the RTEMS interrupt management.
+ */
+void __ISR_Handler( uint32_t   vector)
+{
+  ISR_Level level;
+
+  _ISR_Local_disable( level );
+
+  _Thread_Dispatch_disable();
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+  if ( _ISR_Nest_level == 0 )
+    {
+      /* Install irq stack */
+      _old_stack_ptr = stack_ptr;
+      stack_ptr = _CPU_Interrupt_stack_high;
+    }
+
+#endif
+
+  _ISR_Nest_level++;
+
+  _ISR_Local_enable( level );
+
+  /* call isp */
+  if ( _ISR_Vector_table[ vector])
+    (*_ISR_Vector_table[ vector ])( vector );
+
+  _ISR_Local_disable( level );
+
+  _Thread_Dispatch_unnest( _Per_CPU_Get() );
+
+  _ISR_Nest_level--;
+
+#if (CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE)
+
+  if ( _ISR_Nest_level == 0 )
+    /* restore old stack pointer */
+    stack_ptr = _old_stack_ptr;
+#endif
+
+  _ISR_Local_enable( level );
+
+  if ( _ISR_Nest_level )
+    return;
+
+  if ( !_Thread_Dispatch_is_enabled() ) {
+    return;
+  }
+
+  if ( _Thread_Dispatch_necessary ) {
+    _Thread_Dispatch();
+  }
+}
diff --git a/bsps/sh/shsim/start/ispshgdb.c b/bsps/sh/shsim/start/ispshgdb.c
new file mode 100644
index 0000000000..09843172d9
--- /dev/null
+++ b/bsps/sh/shsim/start/ispshgdb.c
@@ -0,0 +1,146 @@
+/*
+ * This file contains the isp frames for the user interrupts.
+ * From these procedures __ISR_Handler is called with the vector number
+ * as argument.
+ *
+ * __ISR_Handler is kept in a separate file (cpu_asm.c), because a bug in
+ * some releases of gcc doesn't properly handle #pragma interrupt, if a
+ * file contains both isrs and normal functions.
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
+ *           Bernd Becker (becker@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 1997-1998, FAW Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE
+ *
+ *
+ *  COPYRIGHT (c) 1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ *
+ *  Modified to reflect dummy isp entries for GDB SH simulator by Joel.
+ */
+
+#include <rtems/system.h>
+
+/*
+ * This is a exception vector table
+ *
+ * It has the same structure as the actual vector table (vectab)
+ */
+
+void _dummy_isp(uint32_t);
+
+proc_ptr _Hardware_isr_Table[256]={
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,	/* PWRon Reset, Maual Reset,...*/
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+/* trapa 0 -31 */
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp,
+_dummy_isp, _dummy_isp, _dummy_isp, _dummy_isp, /* irq 152-155*/
+_dummy_isp
+};
+
+#define Str(a)#a
+
+/*
+ * Some versions of gcc and all version of egcs at least until egcs-1.1b
+ * are not able to handle #pragma interrupt correctly if more than 1 isr is
+ * contained in a file and when optimizing.
+ * We try to work around this problem by using the macro below.
+ */
+#define isp( name, number, func)\
+__asm__ (".global _"Str(name)"\n\t"\
+     "_"Str(name)":       \n\t"\
+     "    mov.l r0,@-r15   \n\t"\
+     "    mov.l r1,@-r15   \n\t"\
+     "    mov.l r2,@-r15   \n\t"\
+     "    mov.l r3,@-r15   \n\t"\
+     "    mov.l r4,@-r15   \n\t"\
+     "    mov.l r5,@-r15   \n\t"\
+     "    mov.l r6,@-r15   \n\t"\
+     "    mov.l r7,@-r15   \n\t"\
+     "    mov.l r14,@-r15  \n\t"\
+     "    sts.l pr,@-r15   \n\t"\
+     "    sts.l mach,@-r15 \n\t"\
+     "    sts.l macl,@-r15 \n\t"\
+     "    mov r15,r14      \n\t"\
+     "    mov.l "Str(name)"_v, r2 \n\t"\
+     "    mov.l "Str(name)"_k, r1\n\t"\
+     "    jsr @r1           \n\t"\
+     "    mov   r2,r4      \n\t"\
+     "    mov   r14,r15    \n\t"\
+     "    lds.l @r15+,macl \n\t"\
+     "    lds.l @r15+,mach \n\t"\
+     "    lds.l @r15+,pr   \n\t"\
+     "    mov.l @r15+,r14  \n\t"\
+     "    mov.l @r15+,r7   \n\t"\
+     "    mov.l @r15+,r6   \n\t"\
+     "    mov.l @r15+,r5   \n\t"\
+     "    mov.l @r15+,r4   \n\t"\
+     "    mov.l @r15+,r3   \n\t"\
+     "    mov.l @r15+,r2   \n\t"\
+     "    mov.l @r15+,r1   \n\t"\
+     "    mov.l @r15+,r0   \n\t"\
+     "    rte              \n\t"\
+     "    nop              \n\t"\
+     "    .align 2         \n\t"\
+     #name"_k: \n\t"\
+     ".long "Str(func)"\n\t"\
+     #name"_v: \n\t"\
+     ".long "Str(number));
+
+/************************************************
+ * Dummy interrupt service procedure for
+ * interrupts being not allowed --> Trap 34
+ ************************************************/
+__asm__ (" .section .text\n\
+.global __dummy_isp\n\
+__dummy_isp:\n\
+      mov.l r14,@-r15\n\
+      mov   r15, r14\n\
+      trapa #34\n\
+      mov.l @r15+,r14\n\
+      rte\n\
+      nop");
+
diff --git a/bsps/sh/shsim/start/linkcmds b/bsps/sh/shsim/start/linkcmds
new file mode 100644
index 0000000000..41c7245da0
--- /dev/null
+++ b/bsps/sh/shsim/start/linkcmds
@@ -0,0 +1,255 @@
+/*
+ * Memory layout for an SH 7032 with main memory in area 0
+ *
+ * NOTES: 
+ * + All RAM/ROM areas are mapped onto area 0, because gdb's simulator
+ * is not able to simulate memory areas but area 0. Area 5 (on-chip
+ * peripherials) can not be mapped onto area 0 and will cause SIGILL 
+ * exceptions.
+ * + Assumed to be compatible with other SH-cpu family members (eg. SH7045)
+ *
+ *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de)
+ *
+ *  COPYRIGHT (c) 2001, Ralf Corsepius, Ulm, Germany
+ *
+ *  This program is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+ */
+
+OUTPUT_ARCH(sh)
+ENTRY(_start)
+STARTUP(start.o)
+
+_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00000000;
+_RamSize = DEFINED(_RamSize) ? _RamSize : 16M;
+_HeapSize = DEFINED(_HeapSize) ? _HeapSize : 0x0;
+
+MEMORY
+{
+/* Real memory layout submitted
+  rom           : o = 0x00000000, l = 128k
+  ram           : o = 0x00040000, l = 256k
+*/
+
+/* Memory layout which links all tests */
+  rom           : o = 0x01000000, l = 512k
+  ram           : o = 0x00040000, l = 512k
+
+  onchip_peri	: o = 0x05000000, l = 512
+}
+
+SECTIONS
+{
+  /* boot vector table */
+  .monvects (NOLOAD) :
+  { 
+    _monvects = . ;
+  } > rom
+
+  /* monitor play area */
+  .monram 0x00040000 (NOLOAD) : 
+  {
+  _ramstart = .;
+  } > ram 
+
+  /* monitor vector table */
+  .vects   0x00042000 (NOLOAD) : {
+    _vectab = . ;
+    *(.vects);
+  }
+
+  /* Read-only sections, merged into text segment: */
+
+  . = 0x00044000 ;
+  .interp        : { *(.interp) 	}
+  .hash          : { *(.hash)		}
+  .dynsym        : { *(.dynsym)		}
+  .dynstr        : { *(.dynstr)		}
+  .gnu.version   : { *(.gnu.version)	}
+  .gnu.version_d : { *(.gnu.version_d)	}
+  .gnu.version_r : { *(.gnu.version_r)	}
+  .rela.dyn       :
+    {
+      *(.rela.init)
+      *(.rela.text .rela.text.* .rela.gnu.linkonce.t.*)
+      *(.rela.fini)
+      *(.rela.rodata .rela.rodata.* .rela.gnu.linkonce.r.*)
+      *(.rela.data .rela.data.* .rela.gnu.linkonce.d.*)
+      *(.rela.tdata .rela.tdata.* .rela.gnu.linkonce.td.*)
+      *(.rela.tbss .rela.tbss.* .rela.gnu.linkonce.tb.*)
+      *(.rela.ctors)
+      *(.rela.dtors)
+      *(.rela.got)
+      *(.rela.sdata .rela.sdata.* .rela.gnu.linkonce.s.*)
+      *(.rela.sbss .rela.sbss.* .rela.gnu.linkonce.sb.*)
+      *(.rela.sdata2 .rela.sdata2.* .rela.gnu.linkonce.s2.*)
+      *(.rela.sbss2 .rela.sbss2.* .rela.gnu.linkonce.sb2.*)
+      *(.rela.bss .rela.bss.* .rela.gnu.linkonce.b.*)
+    } >ram
+  .rel.text      :
+    { *(.rel.text) *(.rel.gnu.linkonce.t*) }
+  .rel.data      :
+    { *(.rel.data) *(.rel.gnu.linkonce.d*) }
+  .rel.rodata    :
+    { *(.rel.rodata) *(.rel.gnu.linkonce.r*) }
+  .rel.got       : { *(.rel.got)		}
+  .rel.ctors     : { *(.rel.ctors)	}
+  .rel.dtors     : { *(.rel.dtors)	}
+  .rel.init      : { *(.rel.init)	}
+  .rel.fini      : { *(.rel.fini)	}
+  .rel.bss       : { *(.rel.bss)		}
+  .rel.plt       : { *(.rel.plt)		}
+  .plt      	 : { *(.plt)	}
+  .text   .   	 :
+  {
+    _start = .;
+    *(.text*)
+    *(.stub)
+
+    /*
+     * Special FreeBSD sysctl sections.
+     */
+    . = ALIGN (16);
+    ___start_set_sysctl_set = .;
+    *(set_sysc*);   /* set_sysctl_* but name is truncated by SH-coff */
+    ___stop_set_sysctl_set = ABSOLUTE(.);
+    *(set_doma*);   /* set_domain_* but name is truncated by SH-coff */
+    *(set_pseu*);   /* set_pseudo_* but name is truncated by SH-coff */
+
+    /* .gnu.warning sections are handled specially by elf32.em.  */
+    *(.gnu.warning)
+    *(.gnu.linkonce.t*)
+  } > ram
+  .init           :
+  {
+    KEEP (*(.init))
+  } >ram
+  .fini           :
+  {
+    KEEP (*(.fini))
+  } >ram
+  _etext = .;
+  PROVIDE (etext = .);
+  .rodata  .  : { *(.rodata*) .rodata.* *(.gnu.linkonce.r*) } > ram
+  .rodata1 .  : { *(.rodata1) } > ram
+  .tdata : {
+    __TLS_Data_begin = .;
+    *(.tdata .tdata.* .gnu.linkonce.td.*)
+    __TLS_Data_end = .;
+  } > ram
+  .tbss : {
+    __TLS_BSS_begin = .;
+    *(.tbss .tbss.* .gnu.linkonce.tb.*) *(.tcommon)
+    __TLS_BSS_end = .;
+  } > ram
+  .init    .  : { KEEP(*(.init))    } > ram =0
+  .fini    .  : { KEEP(*(.fini))    } > ram =0
+  .ctors   .  : { KEEP(*(.ctors))    } > ram =0
+  .dtors   .  : { KEEP(*(.dtors))    } > ram =0
+  __TLS_Data_size = __TLS_Data_end - __TLS_Data_begin;
+  __TLS_Data_begin = __TLS_Data_size != 0 ? __TLS_Data_begin : __TLS_BSS_begin;
+  __TLS_Data_end = __TLS_Data_size != 0 ? __TLS_Data_end : __TLS_BSS_begin;
+  __TLS_BSS_size = __TLS_BSS_end - __TLS_BSS_begin;
+  __TLS_Size = __TLS_BSS_end - __TLS_Data_begin;
+  __TLS_Alignment = MAX (ALIGNOF (.tdata), ALIGNOF (.tbss));
+  /* Adjust the address for the data segment.  We want to adjust up to
+     the same address within the page on the next page up.  */
+  . = ALIGN(128) + (. & (128 - 1));
+  .data  .  :
+  {
+    *(.data*)
+    *(.gcc_exc*)
+    ___EH_FRAME_BEGIN__ = .;
+    *(.eh_fram*)
+    ___EH_FRAME_END__ = .;
+    LONG(0);
+    *(.gcc_except_table*)
+    *(.gnu.linkonce.d*)
+    CONSTRUCTORS
+  } > ram
+  .data1  . : { *(.data1) }
+  .rtemsroset : {
+    /* for pre rtems-libbsd FreeBSD code */
+    __start_set_sysctl_set = .;
+    *(set_sysctl_*);
+    __stop_set_sysctl_set = .;
+    *(set_domain_*);
+    *(set_pseudo_*);
+
+    KEEP (*(SORT(.rtemsroset.*)))
+  } >ram
+  .rtemsrwset : {
+    KEEP (*(SORT(.rtemsrwset.*)))
+  } >ram
+
+  .got     .      : { *(.got.plt) *(.got) }
+  .dynamic .      : { *(.dynamic) }
+  /* We want the small data sections together, so single-instruction offsets
+     can access them all, and initialized data all before uninitialized, so
+     we can shorten the on-disk segment size.  */
+  .sdata   .  : { *(.sdata) }
+  _edata  =  .;
+  PROVIDE (edata = .);
+  __bss_start = .;
+  .sbss    .  : { *(.sbss*) *(.scommon) }
+  .bss     .  :
+  {
+   *(.dynbss)
+   *(.bss .bss* .gnu.linkonce.b*)
+   *(COMMON)
+  } > ram
+  _end = . ;
+  PROVIDE (end = .);
+
+  .stack : { 
+    . += 0x1000;
+    *(.stack)
+    _stack = .;
+  } > ram
+  _stack = .;
+
+  _WorkAreaBase = . ;
+
+  _CPU_Interrupt_stack_low  = 0x00080000 ;
+  _CPU_Interrupt_stack_high = _CPU_Interrupt_stack_low + 4096 ;
+
+  /* Stabs debugging sections.  */
+  .stab 0 : { *(.stab) }
+  .stabstr 0 : { *(.stabstr) }
+  .stab.excl 0 : { *(.stab.excl) }
+  .stab.exclstr 0 : { *(.stab.exclstr) }
+  .stab.index 0 : { *(.stab.index) }
+  .stab.indexstr 0 : { *(.stab.indexstr) }
+  .comment 0 : { *(.comment) }
+  /* DWARF debug sections.
+     Symbols in the DWARF debugging sections are relative to the beginning
+     of the section so we begin them at 0.  */
+  /* DWARF 1 */
+  .debug          0 : { *(.debug) }
+  .line           0 : { *(.line) }
+  /* GNU DWARF 1 extensions */
+  .debug_srcinfo  0 : { *(.debug_srcinfo) }
+  .debug_sfnames  0 : { *(.debug_sfnames) }
+  /* DWARF 1.1 and DWARF 2 */
+  .debug_aranges  0 : { *(.debug_aranges) }
+  .debug_pubnames 0 : { *(.debug_pubnames) }
+  /* DWARF 2 */
+  .debug_info     0 : { *(.debug_info) }
+  .debug_abbrev   0 : { *(.debug_abbrev) }
+  .debug_line     0 : { *(.debug_line) }
+  .debug_frame    0 : { *(.debug_frame) }
+  .debug_str      0 : { *(.debug_str) }
+  .debug_loc      0 : { *(.debug_loc) }
+  .debug_macinfo  0 : { *(.debug_macinfo) }
+  /* SGI/MIPS DWARF 2 extensions */
+  .debug_weaknames 0 : { *(.debug_weaknames) }
+  .debug_funcnames 0 : { *(.debug_funcnames) }
+  .debug_typenames 0 : { *(.debug_typenames) }
+  .debug_varnames  0 : { *(.debug_varnames) }
+
+/*
+  .stack 0x00081ff0 : { _stack = .; *(.stack) } > onchip_ram
+*/
+  /* These must appear regardless of  .  */
+}
diff --git a/bsps/sh/shsim/start/sysexit.c b/bsps/sh/shsim/start/sysexit.c
new file mode 100644
index 0000000000..dde20f35e8
--- /dev/null
+++ b/bsps/sh/shsim/start/sysexit.c
@@ -0,0 +1,22 @@
+/*
+ *  This file contains the simulator specific exit trap.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2014.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bsp.h>
+#include <bsp/syscall.h>
+
+int errno; /* assumed to exist by exit_k() */
+
+int _sys_exit (int n)
+{
+  return __trap34 (SYS_exit, n, 0, 0);
+}