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| author | Padmarao Begari <padmarao.begari@microchip.com> | 2022-09-19 18:30:26 +0530 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-09-20 12:00:51 -0500 |
| commit | 6b0d3c987349d188b65e9fc8229daeba247928c5 (patch) | |
| tree | 4f6f37aaab9be619b82612eb4f000a42549488ca /bsps/riscv/shared/start/start.S | |
| parent | spec/build/bsps: Add dtb support (diff) | |
| download | rtems-6b0d3c987349d188b65e9fc8229daeba247928c5.tar.bz2 | |
bsps/riscv: Add Microchip PolarFire SoC BSP variant
The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
Diffstat (limited to '')
| -rw-r--r-- | bsps/riscv/shared/start/start.S | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/bsps/riscv/shared/start/start.S b/bsps/riscv/shared/start/start.S index 3702f8ac2f..47bb485847 100644 --- a/bsps/riscv/shared/start/start.S +++ b/bsps/riscv/shared/start/start.S @@ -65,6 +65,8 @@ SYM(_start): LADDR sp, _ISR_Stack_area_begin LADDR t2, _ISR_Stack_size csrr s0, mhartid + li t3, RISCV_BOOT_HARTID + sub s0, s0, t3 LADDR t0, _Per_CPU_Information slli t1, s0, PER_CPU_CONTROL_SIZE_LOG2 add s1, t0, t1 |