From 6b0d3c987349d188b65e9fc8229daeba247928c5 Mon Sep 17 00:00:00 2001 From: Padmarao Begari Date: Mon, 19 Sep 2022 18:30:26 +0530 Subject: bsps/riscv: Add Microchip PolarFire SoC BSP variant The Microchip PolarFire SoC support is implemented as a riscv BSP variant to boot with any individual hart(cpu core) or SMP based on the boot HARTID configurable and support components are 4 CPU Cores (U54), Interrupt controller (PLIC), Timer (CLINT), UART. --- bsps/riscv/shared/start/start.S | 2 ++ 1 file changed, 2 insertions(+) (limited to 'bsps/riscv/shared/start/start.S') diff --git a/bsps/riscv/shared/start/start.S b/bsps/riscv/shared/start/start.S index 3702f8ac2f..47bb485847 100644 --- a/bsps/riscv/shared/start/start.S +++ b/bsps/riscv/shared/start/start.S @@ -65,6 +65,8 @@ SYM(_start): LADDR sp, _ISR_Stack_area_begin LADDR t2, _ISR_Stack_size csrr s0, mhartid + li t3, RISCV_BOOT_HARTID + sub s0, s0, t3 LADDR t0, _Per_CPU_Information slli t1, s0, PER_CPU_CONTROL_SIZE_LOG2 add s1, t0, t1 -- cgit v1.2.3