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| author | Hesham Almatary <hesham.almatary@cl.cam.ac.uk> | 2022-12-18 15:07:16 +0000 |
|---|---|---|
| committer | Hesham Almatary <hesham.almatary@cl.cam.ac.uk> | 2022-12-23 09:21:14 +0000 |
| commit | 88b80a5fd0035d4f2a5c752c0159a989812d29c8 (patch) | |
| tree | 5b80f8e95ce822c90f877bf7ed12c3834d633e0e /bsps/riscv/riscv/start | |
| parent | spec/build/riscv: Start all riscv/riscv BSPs at 0x80000000 (diff) | |
| download | rtems-88b80a5fd0035d4f2a5c752c0159a989812d29c8.tar.bz2 | |
RISC-V: Always probe for HTIF and remove RISCV_ENABLE_HTIF_SUPPORT
Updates #4779
Diffstat (limited to 'bsps/riscv/riscv/start')
| -rw-r--r-- | bsps/riscv/riscv/start/bsp_fatal_halt.c | 11 |
1 files changed, 7 insertions, 4 deletions
diff --git a/bsps/riscv/riscv/start/bsp_fatal_halt.c b/bsps/riscv/riscv/start/bsp_fatal_halt.c index fb0787c606..cd7c5f20c5 100644 --- a/bsps/riscv/riscv/start/bsp_fatal_halt.c +++ b/bsps/riscv/riscv/start/bsp_fatal_halt.c @@ -38,14 +38,17 @@ void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error ) int node; volatile uint32_t *sifive_test; -#if RISCV_ENABLE_HTIF_SUPPORT != 0 - htif_poweroff(); -#endif + fdt = bsp_fdt_get(); + + node = fdt_node_offset_by_compatible(fdt, -1, "ucb,htif0"); + + if (node != -1) + htif_poweroff(); + #if RISCV_ENABLE_MPFS_SUPPORT != 0 for(;;); #endif - fdt = bsp_fdt_get(); node = fdt_node_offset_by_compatible(fdt, -1, "sifive,test0"); sifive_test = riscv_fdt_get_address(fdt, node); |