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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-19 12:11:19 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-25 10:07:43 +0200 |
| commit | 8db3f0e878b7f008ad05716f501220509662e2c4 (patch) | |
| tree | d55db59defa95096a3ef156427822a9f8744ab58 /bsps/riscv/riscv/irq/irq.c | |
| parent | riscv: New CPU_Exception_frame (diff) | |
| download | rtems-8db3f0e878b7f008ad05716f501220509662e2c4.tar.bz2 | |
riscv: Rework exception handling
Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.
Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.
Update #3433.
Diffstat (limited to 'bsps/riscv/riscv/irq/irq.c')
| -rw-r--r-- | bsps/riscv/riscv/irq/irq.c | 28 |
1 files changed, 25 insertions, 3 deletions
diff --git a/bsps/riscv/riscv/irq/irq.c b/bsps/riscv/riscv/irq/irq.c index ac4f1ca115..61cf13153b 100644 --- a/bsps/riscv/riscv/irq/irq.c +++ b/bsps/riscv/riscv/irq/irq.c @@ -7,7 +7,7 @@ */ /* - * RISCV CPU Dependent Source + * Copyright (c) 2018 embedded brains GmbH * * Copyright (c) 2015 University of York. * Hesham Almatary <hesham@alumni.york.ac.uk> @@ -35,11 +35,33 @@ */ #include <bsp/irq.h> +#include <bsp/fatal.h> #include <bsp/irq-generic.h> -rtems_status_code bsp_interrupt_facility_initialize() +#include <rtems/score/percpu.h> + +void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self) +{ + /* + * Get rid of the most significant bit which indicates if the exception was + * caused by an interrupt or not. + */ + mcause <<= 1; + + if (mcause == (RISCV_INTERRUPT_TIMER_MACHINE << 1)) { + bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_TIMER); + } else if (mcause == (RISCV_INTERRUPT_EXTERNAL_MACHINE << 1)) { + /* TODO: Handle PLIC interrupt */ + } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) { + bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE); + } else { + bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION); + } +} + +rtems_status_code bsp_interrupt_facility_initialize(void) { - return RTEMS_NOT_IMPLEMENTED; + return RTEMS_SUCCESSFUL; } void bsp_interrupt_vector_enable(rtems_vector_number vector) |