riscv: Use zicsr architecture extension

This is required for ISA 2.0 support, see chapter

"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0

in

RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA

1 files changed, 7 insertions, 1 deletions

diff --git a/bsps/riscv/griscv/clock/clockdrv.c b/bsps/riscv/griscv/clock/clockdrv.c
index 4cf15fe4f8..a5b7b15760 100644
--- a/bsps/riscv/griscv/clock/clockdrv.c
+++ b/bsps/riscv/griscv/clock/clockdrv.c
@@ -187,7 +187,13 @@ CPU_Counter_ticks _CPU_Counter_read( void )
 {
   unsigned long timec;
 
-  __asm__ volatile ( "csrr %0, time" : "=&r" ( timec ) );
+  __asm__ volatile (
+    ".option push\n"
+    ".option arch, +zicsr\n"
+    "csrr %0, time\n"
+    ".option pop" :
+    "=&r" ( timec )
+  );
 
   return timec;
 }