Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

6 files changed, 1294 insertions, 0 deletions

diff --git a/bsps/powerpc/qoriq/include/bsp/intercom.h b/bsps/powerpc/qoriq/include/bsp/intercom.h
new file mode 100644
index 0000000000..39b2ba938e
--- /dev/null
+++ b/bsps/powerpc/qoriq/include/bsp/intercom.h
@@ -0,0 +1,125 @@
+/**
+ * @file
+ *
+ * @ingroup QorIQInterCom
+ *
+ * @brief Inter-Processor Communication API.
+ */
+
+/*
+ * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_QORIQ_INTERCOM_H
+#define LIBBSP_POWERPC_QORIQ_INTERCOM_H
+
+#include <rtems.h>
+#include <rtems/chain.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup QorIQInterCom QorIQ - Inter-Processor Communication Support
+ *
+ * @ingroup QorIQ
+ *
+ * @brief Inter-processor communication support.
+ *
+ * @{
+ */
+
+uint32_t qoriq_spin_lock(uint32_t *lock);
+
+void qoriq_spin_unlock(uint32_t *lock, uint32_t msr);
+
+#define INTERCOM_CORE_COUNT 2
+
+#define INTERCOM_SERVICE_COUNT 8
+
+typedef enum {
+	INTERCOM_TYPE_MPCI,
+	INTERCOM_TYPE_UART_0,
+	INTERCOM_TYPE_UART_1,
+	INTERCOM_TYPE_NETWORK,
+	INTERCOM_TYPE_CUSTOM_0,
+	INTERCOM_TYPE_CUSTOM_1,
+	INTERCOM_TYPE_CUSTOM_2,
+	INTERCOM_TYPE_CUSTOM_3,
+	INTERCOM_TYPE_CUSTOM_4
+} intercom_type;
+
+typedef enum {
+	INTERCOM_SIZE_64 = 0,
+	INTERCOM_SIZE_512,
+	INTERCOM_SIZE_2K,
+	INTERCOM_SIZE_4K
+} intercom_size;
+
+typedef struct intercom_packet {
+	union {
+		struct intercom_packet *next;
+		rtems_chain_node node;
+	} glue;
+	intercom_type type_index;
+	intercom_size size_index;
+	uint32_t flags;
+	size_t size;
+	uint32_t cache_line_alignment [2];
+	char data [];
+} intercom_packet;
+
+typedef void (*intercom_service)(intercom_packet *packet, void *arg);
+
+void qoriq_intercom_init(void);
+
+void qoriq_intercom_start(void);
+
+void qoriq_intercom_service_install(intercom_type type, intercom_service service, void *arg);
+
+void qoriq_intercom_service_remove(intercom_type type);
+
+intercom_packet *qoriq_intercom_allocate_packet(intercom_type type, intercom_size size);
+
+void qoriq_intercom_send_packets(int destination_core, intercom_packet *first, intercom_packet *last);
+
+static inline void qoriq_intercom_send_packet(int destination_core, intercom_packet *packet)
+{
+	qoriq_intercom_send_packets(destination_core, packet, packet);
+}
+
+void qoriq_intercom_broadcast_packets(intercom_packet *first, intercom_packet *last);
+
+static inline void qoriq_intercom_broadcast_packet(intercom_packet *packet)
+{
+	qoriq_intercom_broadcast_packets(packet, packet);
+}
+
+void qoriq_intercom_send(int destination_core, intercom_type type, intercom_size size, const void *buf, size_t n);
+
+void qoriq_intercom_free_packet(intercom_packet *packet);
+
+intercom_packet *qoriq_intercom_clone_packet(const intercom_packet *packet);
+
+#ifdef RTEMS_MULTIPROCESSING
+  extern rtems_mpci_table qoriq_intercom_mpci;
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_QORIQ_INTERCOM_H */
diff --git a/bsps/powerpc/qoriq/include/bsp/irq.h b/bsps/powerpc/qoriq/include/bsp/irq.h
new file mode 100644
index 0000000000..e178057950
--- /dev/null
+++ b/bsps/powerpc/qoriq/include/bsp/irq.h
@@ -0,0 +1,401 @@
+/**
+ * @file
+ *
+ * @ingroup QorIQInterrupt
+ *
+ * @brief Interrupt API.
+ */
+
+/*
+ * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_QORIQ_IRQ_H
+#define LIBBSP_POWERPC_QORIQ_IRQ_H
+
+#include <bsp.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+#include <rtems/score/processormask.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef QORIQ_IS_HYPERVISOR_GUEST
+
+#define BSP_INTERRUPT_VECTOR_MAX 1023
+
+#else /* !QORIQ_IS_HYPERVISOR_GUEST */
+
+#define QORIQ_IRQ_ERROR 0
+
+#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT)
+
+#define QORIQ_IRQ_PCI_EXPRESS_1 4
+#define QORIQ_IRQ_PCI_EXPRESS_2 5
+#define QORIQ_IRQ_PCI_EXPRESS_3 6
+#define QORIQ_IRQ_PCI_EXPRESS_4 7
+#define QORIQ_IRQ_PAMU 8
+#define QORIQ_IRQ_IFC 9
+#define QORIQ_IRQ_DMA_CHANNEL_1_1 12
+#define QORIQ_IRQ_DMA_CHANNEL_1_2 13
+#define QORIQ_IRQ_DMA_CHANNEL_1_3 14
+#define QORIQ_IRQ_DMA_CHANNEL_1_4 15
+#define QORIQ_IRQ_DMA_CHANNEL_2_1 16
+#define QORIQ_IRQ_DMA_CHANNEL_2_2 17
+#define QORIQ_IRQ_DMA_CHANNEL_2_3 18
+#define QORIQ_IRQ_DMA_CHANNEL_2_4 19
+#define QORIQ_IRQ_DUART_1 20
+#define QORIQ_IRQ_DUART_2 21
+#define QORIQ_IRQ_DUARL_I2C_1 22
+#define QORIQ_IRQ_DUARL_I2C_2 23
+#define QORIQ_IRQ_PCI_EXPRESS_1_INTA 24
+#define QORIQ_IRQ_PCI_EXPRESS_2_INTA 25
+#define QORIQ_IRQ_PCI_EXPRESS_3_INTA 26
+#define QORIQ_IRQ_PCI_EXPRESS_4_INTA 27
+#define QORIQ_IRQ_USB_1 28
+#define QORIQ_IRQ_USB_2 29
+#define QORIQ_IRQ_ESDHC 32
+#define QORIQ_IRQ_PERF_MON 36
+#define QORIQ_IRQ_ESPI 37
+#define QORIQ_IRQ_GPIO_2 38
+#define QORIQ_IRQ_GPIO_1 39
+#define QORIQ_IRQ_SATA_1 52
+#define QORIQ_IRQ_SATA_2 53
+#define QORIQ_IRQ_DMA_CHANNEL_1_5 60
+#define QORIQ_IRQ_DMA_CHANNEL_1_6 61
+#define QORIQ_IRQ_DMA_CHANNEL_1_7 62
+#define QORIQ_IRQ_DMA_CHANNEL_1_8 63
+#define QORIQ_IRQ_DMA_CHANNEL_2_5 64
+#define QORIQ_IRQ_DMA_CHANNEL_2_6 65
+#define QORIQ_IRQ_DMA_CHANNEL_2_7 66
+#define QORIQ_IRQ_DMA_CHANNEL_2_8 67
+#define QORIQ_IRQ_EVENT_PROC_UNIT_1 68
+#define QORIQ_IRQ_EVENT_PROC_UNIT_2 69
+#define QORIQ_IRQ_GPIO_3 70
+#define QORIQ_IRQ_GPIO_4 71
+#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_1 72
+#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_2 73
+#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_3 74
+#define QORIQ_IRQ_SEC_5_2_JOB_QUEUE_4 75
+#define QORIQ_IRQ_SEC_5_2_GLOBAL_ERROR 76
+#define QORIQ_IRQ_SEC_MON 77
+#define QORIQ_IRQ_EVENT_PROC_UNIT_3 78
+#define QORIQ_IRQ_EVENT_PROC_UNIT_4 79
+#define QORIQ_IRQ_FRAME_MGR 80
+#define QORIQ_IRQ_MDIO_1 84
+#define QORIQ_IRQ_MDIO_2 85
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_0 88
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_0 89
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_1 90
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_1 91
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_2 92
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_2 93
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_3 94
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_3 95
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_4 96
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_4 97
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_5 98
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_5 99
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_6 100
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_6 101
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_7 102
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_7 103
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_8 104
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_8 105
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_9 106
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_9 107
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_10 109
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_10 109
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_11 110
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_11 111
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_12 112
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_12 113
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_13 114
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_13 115
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_14 116
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_14 117
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_15 118
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_15 119
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_16 120
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_16 121
+#define QORIQ_IRQ_QUEUE_MGR_PORTAL_17 122
+#define QORIQ_IRQ_BUFFER_MGR_PORTAL_17 123
+#define QORIQ_IRQ_DMA_CHANNEL_3_1 240
+#define QORIQ_IRQ_DMA_CHANNEL_3_2 241
+#define QORIQ_IRQ_DMA_CHANNEL_3_3 242
+#define QORIQ_IRQ_DMA_CHANNEL_3_4 243
+#define QORIQ_IRQ_DMA_CHANNEL_3_5 244
+#define QORIQ_IRQ_DMA_CHANNEL_3_6 245
+#define QORIQ_IRQ_DMA_CHANNEL_3_7 246
+#define QORIQ_IRQ_DMA_CHANNEL_3_8 247
+
+#define QORIQ_IRQ_EXT_BASE 256
+
+#else /* QORIQ_CHIP_VARIANT */
+
+/**
+ * @defgroup QoriqInterruptP1020 QorIQ - P1020 Internal Interrupt Sources
+ *
+ * @ingroup QorIQInterrupt
+ *
+ * @brief P1020 internal interrupt sources.
+ *
+ * @{
+ */
+
+#define QORIQ_IRQ_ETSEC_TX_1_GROUP_1 1
+#define QORIQ_IRQ_ETSEC_RX_1_GROUP_1 2
+#define QORIQ_IRQ_ETSEC_ER_1_GROUP_1 8
+#define QORIQ_IRQ_ETSEC_TX_3_GROUP_1 9
+#define QORIQ_IRQ_ETSEC_RX_3_GROUP_1 10
+#define QORIQ_IRQ_ETSEC_ER_3_GROUP_1 11
+#define QORIQ_IRQ_ETSEC_TX_2_GROUP_1 35
+#define QORIQ_IRQ_ETSEC_RX_2_GROUP_1 36
+#define QORIQ_IRQ_TDM 46
+#define QORIQ_IRQ_TDM_ERROR 47
+#define QORIQ_IRQ_ETSEC_ER_2_GROUP_1 51
+
+/** @} */
+
+/**
+ * @defgroup QoriqInterruptP2020 QorIQ - P2020 Internal Interrupt Sources
+ *
+ * @ingroup QorIQInterrupt
+ *
+ * @brief P2020 internal interrupt sources.
+ *
+ * @{
+ */
+
+#define QORIQ_IRQ_L2_CACHE 0
+#define QORIQ_IRQ_ECM 1
+#define QORIQ_IRQ_DDR_CONTROLLER 2
+#define QORIQ_IRQ_PCI_EXPRESS_3 8
+#define QORIQ_IRQ_PCI_EXPRESS_2 9
+#define QORIQ_IRQ_PCI_EXPRESS_1 10
+#define QORIQ_IRQ_SRIO_ERR_WRT_1_2 32
+#define QORIQ_IRQ_SRIO_OUT_DOORBELL_1 33
+#define QORIQ_IRQ_SRIO_IN_DOORBELL_1 34
+#define QORIQ_IRQ_SRIO_OUT_MSG_1 37
+#define QORIQ_IRQ_SRIO_IN_MSG_1 38
+#define QORIQ_IRQ_SRIO_OUT_MSG_2 39
+#define QORIQ_IRQ_SRIO_IN_MSG_2 40
+
+/** @} */
+
+/**
+ * @defgroup QoriqInterruptAll QorIQ - Internal Interrupt Sources
+ *
+ * @ingroup QorIQInterrupt
+ *
+ * @brief Internal interrupt sources.
+ *
+ * @{
+ */
+
+#define QORIQ_IRQ_ELBC 3
+#define QORIQ_IRQ_DMA_CHANNEL_1_1 4
+#define QORIQ_IRQ_DMA_CHANNEL_2_1 5
+#define QORIQ_IRQ_DMA_CHANNEL_3_1 6
+#define QORIQ_IRQ_DMA_CHANNEL_4_1 7
+#define QORIQ_IRQ_USB_1 12
+#define QORIQ_IRQ_ETSEC_TX_1 13
+#define QORIQ_IRQ_ETSEC_RX_1 14
+#define QORIQ_IRQ_ETSEC_TX_3 15
+#define QORIQ_IRQ_ETSEC_RX_3 16
+#define QORIQ_IRQ_ETSEC_ER_3 17
+#define QORIQ_IRQ_ETSEC_ER_1 18
+#define QORIQ_IRQ_ETSEC_TX_2 19
+#define QORIQ_IRQ_ETSEC_RX_2 20
+#define QORIQ_IRQ_ETSEC_ER_2 24
+#define QORIQ_IRQ_DUART_1 26
+#define QORIQ_IRQ_I2C 27
+#define QORIQ_IRQ_PERFORMANCE_MONITOR 28
+#define QORIQ_IRQ_SECURITY_1 29
+#define QORIQ_IRQ_USB_2 30
+#define QORIQ_IRQ_GPIO 31
+#define QORIQ_IRQ_SECURITY_2 42
+#define QORIQ_IRQ_ESPI 43
+#define QORIQ_IRQ_ETSEC_IEEE_1588_1 52
+#define QORIQ_IRQ_ETSEC_IEEE_1588_2 53
+#define QORIQ_IRQ_ETSEC_IEEE_1588_3 54
+#define QORIQ_IRQ_ESDHC 56
+#define QORIQ_IRQ_DMA_CHANNEL_1_2 60
+#define QORIQ_IRQ_DMA_CHANNEL_2_2 61
+#define QORIQ_IRQ_DMA_CHANNEL_3_2 62
+#define QORIQ_IRQ_DMA_CHANNEL_4_2 63
+
+/** @} */
+
+#define QORIQ_IRQ_EXT_BASE 64
+
+#endif /* QORIQ_CHIP_VARIANT */
+
+/**
+ * @defgroup QoriqInterruptExternal QorIQ - External Interrupt Sources
+ *
+ * @ingroup QorIQInterrupt
+ *
+ * @brief External interrupt sources.
+ *
+ * @{
+ */
+
+#define QORIQ_IRQ_EXT_0 (QORIQ_IRQ_EXT_BASE + 0)
+#define QORIQ_IRQ_EXT_1 (QORIQ_IRQ_EXT_BASE + 1)
+#define QORIQ_IRQ_EXT_2 (QORIQ_IRQ_EXT_BASE + 2)
+#define QORIQ_IRQ_EXT_3 (QORIQ_IRQ_EXT_BASE + 3)
+#define QORIQ_IRQ_EXT_4 (QORIQ_IRQ_EXT_BASE + 4)
+#define QORIQ_IRQ_EXT_5 (QORIQ_IRQ_EXT_BASE + 5)
+#define QORIQ_IRQ_EXT_6 (QORIQ_IRQ_EXT_BASE + 6)
+#define QORIQ_IRQ_EXT_7 (QORIQ_IRQ_EXT_BASE + 7)
+#define QORIQ_IRQ_EXT_8 (QORIQ_IRQ_EXT_BASE + 8)
+#define QORIQ_IRQ_EXT_9 (QORIQ_IRQ_EXT_BASE + 9)
+#define QORIQ_IRQ_EXT_10 (QORIQ_IRQ_EXT_BASE + 10)
+#define QORIQ_IRQ_EXT_11 (QORIQ_IRQ_EXT_BASE + 11)
+
+/** @} */
+
+/**
+ * @defgroup QoriqInterruptIPI QorIQ - Interprocessor Interrupts
+ *
+ * @ingroup QorIQInterrupt
+ *
+ * @brief Interprocessor interrupts.
+ *
+ * @{
+ */
+
+#define QORIQ_IRQ_IPI_BASE (QORIQ_IRQ_EXT_11 + 1)
+#define QORIQ_IRQ_IPI_0 (QORIQ_IRQ_IPI_BASE + 0)
+#define QORIQ_IRQ_IPI_1 (QORIQ_IRQ_IPI_BASE + 1)
+#define QORIQ_IRQ_IPI_2 (QORIQ_IRQ_IPI_BASE + 2)
+#define QORIQ_IRQ_IPI_3 (QORIQ_IRQ_IPI_BASE + 3)
+
+/** @} */
+
+/**
+ * @defgroup QoriqInterruptIPI QorIQ - Message Interrupts
+ *
+ * @ingroup QorIQInterrupt
+ *
+ * @brief Message interrupts.
+ *
+ * @{
+ */
+
+#define QORIQ_IRQ_MI_BASE (QORIQ_IRQ_IPI_3 + 1)
+#define QORIQ_IRQ_MI_0 (QORIQ_IRQ_MI_BASE + 0)
+#define QORIQ_IRQ_MI_1 (QORIQ_IRQ_MI_BASE + 1)
+#define QORIQ_IRQ_MI_2 (QORIQ_IRQ_MI_BASE + 2)
+#define QORIQ_IRQ_MI_3 (QORIQ_IRQ_MI_BASE + 3)
+#define QORIQ_IRQ_MI_4 (QORIQ_IRQ_MI_BASE + 4)
+#define QORIQ_IRQ_MI_5 (QORIQ_IRQ_MI_BASE + 5)
+#define QORIQ_IRQ_MI_6 (QORIQ_IRQ_MI_BASE + 6)
+#define QORIQ_IRQ_MI_7 (QORIQ_IRQ_MI_BASE + 7)
+
+/** @} */
+
+/**
+ * @defgroup QoriqInterruptIPI QorIQ - Shared Message Signaled Interrupts
+ *
+ * @ingroup QorIQInterrupt
+ *
+ * @brief Shared message signaled interrupts.
+ *
+ * @{
+ */
+
+#define QORIQ_IRQ_MSI_BASE (QORIQ_IRQ_MI_7 + 1)
+#define QORIQ_IRQ_MSI_0 (QORIQ_IRQ_MSI_BASE + 0)
+#define QORIQ_IRQ_MSI_1 (QORIQ_IRQ_MSI_BASE + 1)
+#define QORIQ_IRQ_MSI_2 (QORIQ_IRQ_MSI_BASE + 2)
+#define QORIQ_IRQ_MSI_3 (QORIQ_IRQ_MSI_BASE + 3)
+#define QORIQ_IRQ_MSI_4 (QORIQ_IRQ_MSI_BASE + 4)
+#define QORIQ_IRQ_MSI_5 (QORIQ_IRQ_MSI_BASE + 5)
+#define QORIQ_IRQ_MSI_6 (QORIQ_IRQ_MSI_BASE + 6)
+#define QORIQ_IRQ_MSI_7 (QORIQ_IRQ_MSI_BASE + 7)
+
+/** @} */
+
+/**
+ * @defgroup QoriqInterruptIPI QorIQ - Global Timer Interrupts
+ *
+ * @ingroup QorIQInterrupt
+ *
+ * @brief Global Timer interrupts.
+ *
+ * @{
+ */
+
+#define QORIQ_IRQ_GT_BASE (QORIQ_IRQ_MSI_7 + 1)
+#define QORIQ_IRQ_GT_A_0 (QORIQ_IRQ_GT_BASE + 0)
+#define QORIQ_IRQ_GT_A_1 (QORIQ_IRQ_GT_BASE + 1)
+#define QORIQ_IRQ_GT_A_2 (QORIQ_IRQ_GT_BASE + 2)
+#define QORIQ_IRQ_GT_A_3 (QORIQ_IRQ_GT_BASE + 3)
+#define QORIQ_IRQ_GT_B_0 (QORIQ_IRQ_GT_BASE + 4)
+#define QORIQ_IRQ_GT_B_1 (QORIQ_IRQ_GT_BASE + 5)
+#define QORIQ_IRQ_GT_B_2 (QORIQ_IRQ_GT_BASE + 6)
+#define QORIQ_IRQ_GT_B_3 (QORIQ_IRQ_GT_BASE + 7)
+
+#define BSP_INTERRUPT_VECTOR_MAX QORIQ_IRQ_GT_B_3
+
+/** @} */
+
+#endif /* QORIQ_IS_HYPERVISOR_GUEST */
+
+/**
+ * @defgroup QorIQInterrupt QorIQ - Interrupt Support
+ *
+ * @ingroup QorIQ
+ *
+ * @brief Interrupt support.
+ *
+ * @{
+ */
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+
+#define QORIQ_PIC_PRIORITY_LOWEST 1
+#define QORIQ_PIC_PRIORITY_HIGHEST 15
+#define QORIQ_PIC_PRIORITY_DISABLED 0
+#define QORIQ_PIC_PRIORITY_INVALID (QORIQ_PIC_PRIORITY_HIGHEST + 1)
+#define QORIQ_PIC_PRIORITY_DEFAULT (QORIQ_PIC_PRIORITY_LOWEST + 1)
+#define QORIQ_PIC_PRIORITY_IS_VALID(p) \
+  ((p) >= QORIQ_PIC_PRIORITY_DISABLED && (p) <= QORIQ_PIC_PRIORITY_HIGHEST)
+
+rtems_status_code qoriq_pic_set_priority(
+  rtems_vector_number vector,
+  int new_priority,
+  int *old_priority
+);
+
+void bsp_interrupt_set_affinity(
+  rtems_vector_number vector,
+  const Processor_mask *affinity
+);
+
+void bsp_interrupt_get_affinity(
+  rtems_vector_number vector,
+  Processor_mask *affinity
+);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_QORIQ_IRQ_H */
diff --git a/bsps/powerpc/qoriq/include/bsp/mmu.h b/bsps/powerpc/qoriq/include/bsp/mmu.h
new file mode 100644
index 0000000000..4cacb1b375
--- /dev/null
+++ b/bsps/powerpc/qoriq/include/bsp/mmu.h
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * @ingroup QorIQMMU
+ *
+ * @brief MMU API.
+ */
+
+/*
+ * Copyright (c) 2011-2015 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_QORIQ_MMU_H
+#define LIBBSP_POWERPC_QORIQ_MMU_H
+
+#include <stdint.h>
+#include <stdbool.h>
+
+#include <bspopts.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup QorIQMMU QorIQ - MMU Support
+ *
+ * @ingroup QorIQ
+ *
+ * @brief MMU support.
+ *
+ * @{
+ */
+
+#define QORIQ_MMU_MIN_POWER 12
+#define QORIQ_MMU_MAX_POWER 30
+#define QORIQ_MMU_POWER_STEP 2
+
+typedef struct {
+	uintptr_t begin;
+	uintptr_t last;
+	uint32_t mas1;
+	uint32_t mas2;
+	uint32_t mas3;
+	uint32_t mas7;
+} qoriq_mmu_entry;
+
+typedef struct {
+	int count;
+	qoriq_mmu_entry entries [QORIQ_TLB1_ENTRY_COUNT];
+} qoriq_mmu_context;
+
+void qoriq_mmu_context_init(qoriq_mmu_context *self);
+
+bool qoriq_mmu_add(
+	qoriq_mmu_context *self,
+	uintptr_t begin,
+	uintptr_t last,
+	uint32_t mas1,
+	uint32_t mas2,
+	uint32_t mas3,
+	uint32_t mas7
+);
+
+void qoriq_mmu_partition(qoriq_mmu_context *self, int max_count);
+
+void qoriq_mmu_write_to_tlb1(qoriq_mmu_context *self, int first_tlb);
+
+void qoriq_mmu_change_perm(uint32_t test, uint32_t set, uint32_t clear);
+
+void qoriq_mmu_config(bool boot_processor, int first_tlb, int scratch_tlb);
+
+void qoriq_tlb1_write(
+	int esel,
+	uint32_t mas1,
+	uint32_t mas2,
+	uint32_t mas3,
+	uint32_t mas7,
+	uintptr_t ea,
+	int tsize
+);
+
+void qoriq_tlb1_invalidate(int esel);
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_QORIQ_MMU_H */
diff --git a/bsps/powerpc/qoriq/include/bsp/qoriq.h b/bsps/powerpc/qoriq/include/bsp/qoriq.h
new file mode 100644
index 0000000000..2d28d0aec7
--- /dev/null
+++ b/bsps/powerpc/qoriq/include/bsp/qoriq.h
@@ -0,0 +1,559 @@
+/**
+ * @file
+ *
+ * @ingroup QorIQ
+ *
+ * @brief QorIQ Configuration, Control and Status Registers.
+ */
+
+/*
+ * Copyright (c) 2010-2015 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_QORIQ_QORIQ_H
+#define LIBBSP_POWERPC_QORIQ_QORIQ_H
+
+#include <bsp.h>
+#include <bsp/tsec.h>
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define QORIQ_FILL(a, b, s) uint8_t reserved_ ## b [b - a - sizeof(s)]
+#define QORIQ_RESERVE(a, b) uint8_t reserved_ ## b [b - a]
+
+typedef struct {
+  uint32_t reg;
+  QORIQ_FILL(0x00000, 0x00010, uint32_t);
+} qoriq_pic_reg;
+
+typedef struct {
+  uint32_t ccr;
+  QORIQ_FILL(0x00000, 0x00010, uint32_t);
+  uint32_t bcr;
+  QORIQ_FILL(0x00010, 0x00020, uint32_t);
+  uint32_t vpr;
+  QORIQ_FILL(0x00020, 0x00030, uint32_t);
+  uint32_t dr;
+  QORIQ_FILL(0x00030, 0x00040, uint32_t);
+} qoriq_pic_global_timer;
+
+#define GTCCR_TOG BSP_BBIT32(0)
+#define GTCCR_COUNT_GET(reg) BSP_BFLD32GET(reg, 1, 31)
+
+#define GTBCR_CI BSP_BBIT32(0)
+#define GTBCR_COUNT(val) BSP_BFLD32(val, 1, 31)
+#define GTBCR_COUNT_GET(reg) BSP_BFLD32GET(reg, 1, 31)
+#define GTBCR_COUNT_SET(reg, val) BSP_BFLD32SET(reg, val, 1, 31)
+
+typedef struct {
+  uint32_t misc;
+  QORIQ_FILL(0x00000, 0x00010, uint32_t);
+  uint32_t internal [2];
+  QORIQ_FILL(0x00010, 0x00020, uint32_t [2]);
+} qoriq_pic_bit_field;
+
+typedef struct {
+  uint32_t vpr;
+  QORIQ_FILL(0x00000, 0x00010, uint32_t);
+  uint32_t dr;
+  QORIQ_FILL(0x00010, 0x00020, uint32_t);
+} qoriq_pic_src_cfg;
+
+typedef struct {
+  QORIQ_RESERVE(0x00000, 0x00040);
+  qoriq_pic_reg ipidr [4];
+  uint32_t ctpr;
+  QORIQ_FILL(0x00080, 0x00090, uint32_t);
+  uint32_t whoami;
+  QORIQ_FILL(0x00090, 0x000a0, uint32_t);
+  uint32_t iack;
+  QORIQ_FILL(0x000a0, 0x000b0, uint32_t);
+  uint32_t eoi;
+  QORIQ_FILL(0x000b0, 0x01000, uint32_t);
+} qoriq_pic_per_cpu;
+
+typedef struct {
+  uint32_t brr1;
+  QORIQ_FILL(0x00000, 0x00010, uint32_t);
+  uint32_t brr2;
+  QORIQ_FILL(0x00010, 0x00040, uint32_t);
+  qoriq_pic_reg ipidr [4];
+  uint32_t ctpr;
+  QORIQ_FILL(0x00080, 0x00090, uint32_t);
+  uint32_t whoami;
+  QORIQ_FILL(0x00090, 0x000a0, uint32_t);
+  uint32_t iack;
+  QORIQ_FILL(0x000a0, 0x000b0, uint32_t);
+  uint32_t eoi;
+  QORIQ_FILL(0x000b0, 0x01000, uint32_t);
+  uint32_t frr;
+  QORIQ_FILL(0x01000, 0x01020, uint32_t);
+  uint32_t gcr;
+  QORIQ_FILL(0x01020, 0x01080, uint32_t);
+  uint32_t vir;
+  QORIQ_FILL(0x01080, 0x01090, uint32_t);
+  uint32_t pir;
+  QORIQ_FILL(0x01090, 0x010a0, uint32_t);
+  qoriq_pic_reg ipivpr [4];
+  uint32_t svr;
+  QORIQ_FILL(0x010e0, 0x010f0, uint32_t);
+  uint32_t tfrra;
+  QORIQ_FILL(0x010f0, 0x01100, uint32_t);
+  qoriq_pic_global_timer gta [4];
+  QORIQ_RESERVE(0x01200, 0x01300);
+  uint32_t tcra;
+  QORIQ_FILL(0x01300, 0x01308, uint32_t);
+  uint32_t erqsr;
+  QORIQ_FILL(0x01308, 0x01310, uint32_t);
+  qoriq_pic_bit_field irqsr;
+  qoriq_pic_bit_field cisr;
+  qoriq_pic_bit_field pm [4];
+  QORIQ_RESERVE(0x013d0, 0x01400);
+  qoriq_pic_reg msgr03 [4];
+  QORIQ_RESERVE(0x01440, 0x01500);
+  uint32_t mer03;
+  QORIQ_FILL(0x01500, 0x01510, uint32_t);
+  uint32_t msr03;
+  QORIQ_FILL(0x01510, 0x01600, uint32_t);
+  qoriq_pic_reg msir [8];
+  QORIQ_RESERVE(0x01680, 0x01720);
+  uint32_t msisr;
+  QORIQ_FILL(0x01720, 0x01740, uint32_t);
+  uint32_t msiir;
+  QORIQ_FILL(0x01740, 0x020f0, uint32_t);
+  uint32_t tfrrb;
+  QORIQ_FILL(0x020f0, 0x02100, uint32_t);
+  qoriq_pic_global_timer gtb [4];
+  QORIQ_RESERVE(0x02200, 0x02300);
+  uint32_t tcrb;
+  QORIQ_FILL(0x02300, 0x02400, uint32_t);
+  qoriq_pic_reg msgr47 [4];
+  QORIQ_RESERVE(0x02440, 0x02500);
+  uint32_t mer47;
+  QORIQ_FILL(0x02500, 0x02510, uint32_t);
+  uint32_t msr47;
+  QORIQ_FILL(0x02510, 0x10000, uint32_t);
+  qoriq_pic_src_cfg ei [12];
+  QORIQ_RESERVE(0x10180, 0x10200);
+  qoriq_pic_src_cfg ii_0 [160];
+  qoriq_pic_src_cfg mi [8];
+  QORIQ_RESERVE(0x11700, 0x11c00);
+  qoriq_pic_src_cfg msi [8];
+  QORIQ_RESERVE(0x11d00, 0x13000);
+  qoriq_pic_src_cfg ii_1 [96];
+  QORIQ_RESERVE(0x13c00, 0x20000);
+  qoriq_pic_per_cpu per_cpu [2];
+} qoriq_pic;
+
+#define GTTCR_ROVR(val) BSP_BFLD32(val, 5, 7)
+#define GTTCR_ROVR_GET(reg) BSP_BFLD32GET(reg, 5, 7)
+#define GTTCR_ROVR_SET(reg, val) BSP_BFLD32SET(reg, val, 5, 7)
+#define GTTCR_RTM BSP_BBIT32(15)
+#define GTTCR_CLKR(val) BSP_BFLD32(val, 22, 23)
+#define GTTCR_CLKR_GET(reg) BSP_BFLD32GET(reg, 22, 23)
+#define GTTCR_CLKR_SET(reg, val) BSP_BFLD32SET(reg, val, 22, 23)
+#define GTTCR_CASC(val) BSP_BFLD32(val, 29, 31)
+#define GTTCR_CASC_GET(reg) BSP_BFLD32GET(reg, 29, 31)
+#define GTTCR_CASC_SET(reg, val) BSP_BFLD32SET(reg, val, 29, 31)
+
+typedef struct {
+} qoriq_uart;
+
+typedef struct {
+  uint32_t gpdir;
+  uint32_t gpodr;
+  uint32_t gpdat;
+  uint32_t gpier;
+  uint32_t gpimr;
+  uint32_t gpicr;
+  uint32_t gpibe;
+  QORIQ_RESERVE(0x001c, 0x1000);
+} qoriq_gpio;
+
+typedef struct {
+  QORIQ_RESERVE(0x000, 0x100);
+  uint16_t caplength;
+  uint16_t hciversion;
+  uint32_t hcsparams;
+  uint32_t hccparams;
+  QORIQ_RESERVE(0x10c, 0x120);
+  uint32_t dciversion;
+  uint32_t dccparams;
+  QORIQ_RESERVE(0x128, 0x140);
+  uint32_t usbcmd;
+  uint32_t usbsts;
+  uint32_t usbintr;
+  uint32_t frindex;
+  QORIQ_RESERVE(0x150, 0x154);
+  union {
+    uint32_t periodiclistbase;
+    uint32_t deviceaddr;
+  } perbase_devaddr;
+  union {
+    uint32_t asynclistaddr;
+    uint32_t addr;
+  } async_addr;
+  QORIQ_RESERVE(0x15c, 0x160);
+  uint32_t burstsize;
+  uint32_t txfilltuning;
+  QORIQ_RESERVE(0x168, 0x170);
+  uint32_t viewport;
+  QORIQ_RESERVE(0x174, 0x180);
+  uint32_t configflag;
+  uint32_t portsc1;
+  QORIQ_RESERVE(0x188, 0x1a8);
+  uint32_t usbmode;
+  uint32_t endptsetupstat;
+  uint32_t endpointprime;
+  uint32_t endptflush;
+  uint32_t endptstatus;
+  uint32_t endptcomplete;
+  uint32_t endptctrl[6];
+  QORIQ_RESERVE(0x1d8, 0x400);
+  uint32_t snoop1;
+  uint32_t snoop2;
+  uint32_t age_cnt_thresh;
+  uint32_t pri_ctrl;
+  uint32_t si_ctrl;
+  QORIQ_RESERVE(0x414, 0x500);
+  uint32_t control;
+} qoriq_usb;
+
+typedef struct {
+  uint32_t dsaddr;
+  uint32_t blkattr;
+  uint32_t cmdarg;
+  uint32_t xfertyp;
+  uint32_t cmdrsp0;
+  uint32_t cmdrsp1;
+  uint32_t cmdrsp2;
+  uint32_t cmdrsp3;
+  uint32_t datport;
+  uint32_t prsstat;
+  uint32_t proctl;
+  uint32_t sysctl;
+  uint32_t irqstat;
+  uint32_t irqstaten;
+  uint32_t irqsigen;
+  uint32_t autoc12err;
+  uint32_t hostcapblt;
+  uint32_t wml;
+  QORIQ_FILL(0x00044, 0x00050, uint32_t);
+  uint32_t fevt;
+  QORIQ_FILL(0x00050, 0x000fc, uint32_t);
+  uint32_t hostver;
+  QORIQ_FILL(0x000fc, 0x0040c, uint32_t);
+  uint32_t dcr;
+} qoriq_esdhc;
+
+#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT)
+
+typedef struct {
+	uint32_t ccsrbarh;
+	uint32_t ccsrbarl;
+	uint32_t ccsrar;
+	uint32_t altcbarh;
+	uint32_t altcbarl;
+	uint32_t altcar;
+	uint32_t bstrh;
+	uint32_t bstrl;
+	uint32_t bstar;
+} qoriq_lcc;
+
+#define LCC_BSTAR_EN BSP_BBIT32(0)
+
+typedef struct {
+	uint32_t lawbarh;
+	uint32_t lawbarl;
+	uint32_t lawar;
+	uint32_t reserved_0xc;
+} qoriq_law;
+
+typedef struct {
+  uint32_t reserved_0x0[640];
+  uint32_t qmbm_warmrst;
+} qoriq_dcfg;
+
+typedef struct {
+  QORIQ_RESERVE(0x0000, 0x1000);
+} qoriq_bman;
+
+typedef struct {
+  QORIQ_RESERVE(0x0000, 0x1000);
+} qoriq_qman;
+
+typedef struct {
+  QORIQ_RESERVE(0x000000, 0x100000);
+} qoriq_fman;
+
+typedef struct {
+  qoriq_lcc lcc;
+  QORIQ_FILL(0x000000, 0x000c00, qoriq_lcc);
+  qoriq_law law [32];
+  QORIQ_FILL(0x000c00, 0x001000, qoriq_law [32]);
+  QORIQ_RESERVE(0x001000, 0x040000);
+  qoriq_pic pic;
+  QORIQ_FILL(0x040000, 0x070000, qoriq_pic);
+  QORIQ_RESERVE(0x070000, 0x0e0000);
+  qoriq_dcfg dcfg;
+  QORIQ_FILL(0x0e0000, 0x0e1000, qoriq_dcfg);
+  QORIQ_RESERVE(0x0e1000, 0x114000);
+  qoriq_esdhc esdhc;
+  QORIQ_FILL(0x114000, 0x115000, qoriq_esdhc);
+  QORIQ_RESERVE(0x115000, 0x11c500);
+  qoriq_uart uart_0;
+  QORIQ_FILL(0x11c500, 0x11c600, qoriq_uart);
+  qoriq_uart uart_1;
+  QORIQ_FILL(0x11c600, 0x11d500, qoriq_uart);
+  qoriq_uart uart_2;
+  QORIQ_FILL(0x11d500, 0x11d600, qoriq_uart);
+  qoriq_uart uart_3;
+  QORIQ_FILL(0x11d600, 0x11e000, qoriq_uart);
+  QORIQ_RESERVE(0x11e000, 0x130000);
+  qoriq_gpio gpio[4];
+  QORIQ_RESERVE(0x134000, 0x210000);
+  qoriq_usb usb_1;
+  QORIQ_FILL(0x210000, 0x211000, qoriq_usb);
+  QORIQ_RESERVE(0x211000, 0x318000);
+  qoriq_qman qman;
+  QORIQ_RESERVE(0x319000, 0x31a000);
+  qoriq_bman bman;
+  QORIQ_RESERVE(0x31b000, 0x400000);
+  qoriq_fman fman[2];
+  QORIQ_RESERVE(0x600000, 0x2000000);
+} qoriq_ccsr;
+
+#else /* QORIQ_CHIP_VARIANT */
+
+typedef struct {
+	uint32_t ccsrbar;
+	uint32_t reserved_0;
+	uint32_t altcbar;
+	uint32_t reserved_1;
+	uint32_t altcar;
+	uint32_t reserved_2 [3];
+	uint32_t bptr;
+} qoriq_lcc;
+
+#define CCSRBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 23)
+#define CCSRBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 23)
+#define CCSRBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 23)
+
+#define ALTCBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 23)
+#define ALTCBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 23)
+#define ALTCBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 23)
+
+#define ALTCAR_EN BSP_BBIT32(0)
+#define ALTCAR_TRGT_ID(val) BSP_BFLD32(val, 8, 11)
+#define ALTCAR_TRGT_ID_GET(reg) BSP_BFLD32GET(reg, 8, 11)
+#define ALTCAR_TRGT_ID_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 11)
+
+#define BPTR_EN BSP_BBIT32(0)
+#define BPTR_BOOT_PAGE(val) BSP_BFLD32(val, 8, 31)
+#define BPTR_BOOT_PAGE_GET(reg) BSP_BFLD32GET(reg, 8, 31)
+#define BPTR_BOOT_PAGE_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 31)
+
+typedef struct {
+	uint32_t bar;
+	uint32_t reserved_0;
+	uint32_t ar;
+	uint32_t reserved_1 [5];
+} qoriq_law;
+
+#define LAWBAR_BASE_ADDR(val) BSP_BFLD32(val, 8, 31)
+#define LAWBAR_BASE_ADDR_GET(reg) BSP_BFLD32GET(reg, 8, 31)
+#define LAWBAR_BASE_ADDR_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 31)
+
+#define LAWAR_EN BSP_BBIT32(0)
+#define LAWAR_TRGT(val) BSP_BFLD32(val, 8, 11)
+#define LAWAR_TRGT_GET(reg) BSP_BFLD32GET(reg, 8, 11)
+#define LAWAR_TRGT_SET(reg, val) BSP_BFLD32SET(reg, val, 8, 11)
+#define LAWAR_SIZE(val) BSP_BFLD32(val, 26, 31)
+#define LAWAR_SIZE_GET(reg) BSP_BFLD32GET(reg, 26, 31)
+#define LAWAR_SIZE_SET(reg, val) BSP_BFLD32SET(reg, val, 26, 31)
+
+typedef struct {
+} qoriq_ecm;
+
+typedef struct {
+} qoriq_ddr_controller;
+
+typedef struct {
+} qoriq_i2c;
+
+typedef struct {
+} qoriq_local_bus;
+
+typedef struct {
+} qoriq_spi;
+
+typedef struct {
+} qoriq_pci_express;
+
+typedef struct {
+} qoriq_tdm;
+
+typedef struct {
+} qoriq_l2_cache;
+
+typedef struct {
+} qoriq_dma;
+
+typedef struct {
+} qoriq_tdm_dma;
+
+typedef struct {
+} qoriq_sec;
+
+typedef struct {
+} qoriq_serial_rapid_io;
+
+typedef struct {
+} qoriq_global_utilities;
+
+typedef struct {
+} qoriq_performance_monitor;
+
+typedef struct {
+} qoriq_debug_watchpoint;
+
+typedef struct {
+} qoriq_serdes;
+
+typedef struct {
+} qoriq_boot_rom;
+
+typedef struct {
+  qoriq_lcc lcc;
+  QORIQ_FILL(0x00000, 0x00c08, qoriq_lcc);
+  qoriq_law law [12];
+  QORIQ_FILL(0x00c08, 0x01000, qoriq_law [12]);
+  qoriq_ecm ecm;
+  QORIQ_FILL(0x01000, 0x02000, qoriq_ecm);
+  qoriq_ddr_controller ddr_controller;
+  QORIQ_FILL(0x02000, 0x03000, qoriq_ddr_controller);
+  qoriq_i2c i2c;
+  QORIQ_FILL(0x03000, 0x04000, qoriq_i2c);
+  QORIQ_RESERVE(0x04000, 0x04500);
+  qoriq_uart uart_0;
+  QORIQ_FILL(0x04500, 0x04600, qoriq_uart);
+  qoriq_uart uart_1;
+  QORIQ_FILL(0x04600, 0x04700, qoriq_uart);
+  QORIQ_RESERVE(0x04700, 0x05000);
+  qoriq_local_bus local_bus;
+  QORIQ_FILL(0x05000, 0x06000, qoriq_local_bus);
+  qoriq_spi spi;
+  QORIQ_FILL(0x06000, 0x07000, qoriq_spi);
+  QORIQ_RESERVE(0x07000, 0x08000);
+  qoriq_pci_express pci_express_3;
+  QORIQ_FILL(0x08000, 0x09000, qoriq_pci_express);
+  qoriq_pci_express pci_express_2;
+  QORIQ_FILL(0x09000, 0x0a000, qoriq_pci_express);
+  qoriq_pci_express pci_express_1;
+  QORIQ_FILL(0x0a000, 0x0b000, qoriq_pci_express);
+  QORIQ_RESERVE(0x0b000, 0x0c000);
+  qoriq_dma dma_2;
+  QORIQ_FILL(0x0c000, 0x0d000, qoriq_dma);
+  QORIQ_RESERVE(0x0d000, 0x0f000);
+  qoriq_gpio gpio;
+  QORIQ_RESERVE(0x10000, 0x16000);
+  qoriq_tdm tdm;
+  QORIQ_FILL(0x16000, 0x17000, qoriq_tdm);
+  QORIQ_RESERVE(0x17000, 0x20000);
+  qoriq_l2_cache l2_cache;
+  QORIQ_FILL(0x20000, 0x21000, qoriq_l2_cache);
+  qoriq_dma dma_1;
+  QORIQ_FILL(0x21000, 0x22000, qoriq_dma);
+  qoriq_usb usb_1;
+  QORIQ_FILL(0x22000, 0x23000, qoriq_usb);
+  qoriq_usb usb_2;
+  QORIQ_FILL(0x23000, 0x24000, qoriq_usb);
+  tsec_registers tsec_1;
+  QORIQ_FILL(0x24000, 0x25000, tsec_registers);
+  tsec_registers tsec_2;
+  QORIQ_FILL(0x25000, 0x26000, tsec_registers);
+  tsec_registers tsec_3;
+  QORIQ_FILL(0x26000, 0x27000, tsec_registers);
+  QORIQ_RESERVE(0x27000, 0x2c000);
+  qoriq_tdm_dma tdm_dma;
+  QORIQ_FILL(0x2c000, 0x2d000, qoriq_tdm_dma);
+  QORIQ_RESERVE(0x2d000, 0x2e000);
+  qoriq_esdhc esdhc;
+  QORIQ_FILL(0x2e000, 0x2f000, qoriq_esdhc);
+  QORIQ_RESERVE(0x2f000, 0x30000);
+  qoriq_sec sec;
+  QORIQ_FILL(0x30000, 0x31000, qoriq_sec);
+  QORIQ_RESERVE(0x31000, 0x40000);
+  qoriq_pic pic;
+  QORIQ_FILL(0x40000, 0x80000, qoriq_pic);
+  QORIQ_RESERVE(0x80000, 0xb0000);
+  tsec_registers tsec_1_group_0;
+  QORIQ_FILL(0xb0000, 0xb1000, tsec_registers);
+  tsec_registers tsec_2_group_0;
+  QORIQ_FILL(0xb1000, 0xb2000, tsec_registers);
+  tsec_registers tsec_3_group_0;
+  QORIQ_FILL(0xb2000, 0xb3000, tsec_registers);
+  QORIQ_RESERVE(0xb3000, 0xb4000);
+  tsec_registers tsec_1_group_1;
+  QORIQ_FILL(0xb4000, 0xb5000, tsec_registers);
+  tsec_registers tsec_2_group_1;
+  QORIQ_FILL(0xb5000, 0xb6000, tsec_registers);
+  tsec_registers tsec_3_group_1;
+  QORIQ_FILL(0xb6000, 0xb7000, tsec_registers);
+  QORIQ_RESERVE(0xb7000, 0xc0000);
+  qoriq_serial_rapid_io serial_rapid_io;
+  QORIQ_FILL(0xc0000, 0xe0000, qoriq_serial_rapid_io);
+  qoriq_global_utilities global_utilities;
+  QORIQ_FILL(0xe0000, 0xe1000, qoriq_global_utilities);
+  qoriq_performance_monitor performance_monitor;
+  QORIQ_FILL(0xe1000, 0xe2000, qoriq_performance_monitor);
+  qoriq_debug_watchpoint debug_watchpoint;
+  QORIQ_FILL(0xe2000, 0xe3000, qoriq_debug_watchpoint);
+  qoriq_serdes serdes;
+  QORIQ_FILL(0xe3000, 0xe4000, qoriq_serdes);
+  QORIQ_RESERVE(0xe4000, 0xf0000);
+  qoriq_boot_rom boot_rom;
+  QORIQ_FILL(0xf0000, 0x100000, qoriq_boot_rom);
+} qoriq_ccsr;
+
+#endif /* QORIQ_CHIP_VARIANT */
+
+extern volatile qoriq_ccsr qoriq;
+
+#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT)
+extern uint8_t qoriq_bman_portal[2][16777216];
+extern uint8_t qoriq_qman_portal[2][16777216];
+
+void qoriq_clear_ce_portal(void *base, size_t size);
+void qoriq_clear_ci_portal(void *base, size_t size);
+#endif
+
+static inline void qoriq_reset_qman_and_bman(void)
+{
+#if QORIQ_CHIP_IS_T_VARIANT(QORIQ_CHIP_VARIANT)
+  qoriq.dcfg.qmbm_warmrst = 0x3;
+
+  while ((qoriq.dcfg.qmbm_warmrst & 0x3) != 0) {
+    /* Wait for reset done */
+  }
+#endif
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_QORIQ_QORIQ_H */
diff --git a/bsps/powerpc/qoriq/include/bsp/tsec-config.h b/bsps/powerpc/qoriq/include/bsp/tsec-config.h
new file mode 100644
index 0000000000..b1a70e7486
--- /dev/null
+++ b/bsps/powerpc/qoriq/include/bsp/tsec-config.h
@@ -0,0 +1,36 @@
+/**
+ * @file
+ *
+ * @ingroup QorIQ
+ *
+ * @brief TSEC configuration.
+ */
+
+/*
+ * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H
+#define LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define TSEC_COUNT 3
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_QORIQ_TSEC_CONFIG_H */
diff --git a/bsps/powerpc/qoriq/include/bsp/uart-bridge.h b/bsps/powerpc/qoriq/include/bsp/uart-bridge.h
new file mode 100644
index 0000000000..97e6553b7c
--- /dev/null
+++ b/bsps/powerpc/qoriq/include/bsp/uart-bridge.h
@@ -0,0 +1,72 @@
+/**
+ * @file
+ *
+ * @ingroup QorIQUartBridge
+ *
+ * @brief UART to Intercom bridge API.
+ */
+
+/*
+ * Copyright (c) 2011-2015 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_QORIQ_UART_BRIDGE_H
+#define LIBBSP_POWERPC_QORIQ_UART_BRIDGE_H
+
+#include <rtems/termiostypes.h>
+
+#include <bsp/intercom.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup QorIQUartBridge QorIQ - UART to Intercom Bridge Support
+ *
+ * @ingroup QorIQ
+ *
+ * @brief UART to Intercom bridge support.
+ *
+ * @{
+ */
+
+typedef struct {
+  rtems_termios_device_context base;
+  const char *device_path;
+  intercom_type type;
+  rtems_id transmit_task;
+  rtems_chain_control transmit_fifo;
+} uart_bridge_master_context;
+
+typedef struct {
+  rtems_termios_device_context base;
+  struct rtems_termios_tty *tty;
+  intercom_type type;
+  rtems_id transmit_task;
+  rtems_chain_control transmit_fifo;
+} uart_bridge_slave_context;
+
+bool qoriq_uart_bridge_master_probe(rtems_termios_device_context *base);
+
+extern const rtems_termios_device_handler qoriq_uart_bridge_master;
+
+extern const rtems_termios_device_handler qoriq_uart_bridge_slave;
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* LIBBSP_POWERPC_QORIQ_UART_BRIDGE_H */