Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

27 files changed, 6293 insertions, 0 deletions

diff --git a/bsps/powerpc/gen5200/headers.am b/bsps/powerpc/gen5200/headers.am
new file mode 100644
index 0000000000..7a98ad9ec4
--- /dev/null
+++ b/bsps/powerpc/gen5200/headers.am
@@ -0,0 +1,45 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/ata.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/i2c.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/i2cdrv.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/irq.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/mpc5200.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/mscan-base.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/mscan.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/nvram.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/slicetimer.h
+include_bsp_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/u-boot-config.h
+
+include_bsp_bestcommdir = $(includedir)/bsp/bestcomm
+include_bsp_bestcomm_HEADERS =
+include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h
+include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h
+include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h
+include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h
+include_bsp_bestcomm_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h
+
+include_bsp_bestcomm_includedir = $(includedir)/bsp/bestcomm/include
+include_bsp_bestcomm_include_HEADERS =
+include_bsp_bestcomm_include_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h
+
+include_bsp_bestcomm_include_mgt5200dir = $(includedir)/bsp/bestcomm/include/mgt5200
+include_bsp_bestcomm_include_mgt5200_HEADERS =
+include_bsp_bestcomm_include_mgt5200_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h
+include_bsp_bestcomm_include_mgt5200_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h
+
+include_bsp_bestcomm_task_apidir = $(includedir)/bsp/bestcomm/task_api
+include_bsp_bestcomm_task_api_HEADERS =
+include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h
+include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h
+include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h
+include_bsp_bestcomm_task_api_HEADERS += ../../../../../../bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h
diff --git a/bsps/powerpc/gen5200/include/bsp.h b/bsps/powerpc/gen5200/include/bsp.h
new file mode 100644
index 0000000000..40ac1116c5
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp.h
@@ -0,0 +1,266 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC5200 BSP                              |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below.   |
+| Adaptions, modifications, enhancements and any recent parts of  |
+| the code are:                                                   |
+|                    Copyright (c) 2005                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains board specific definitions                   |
+\*===============================================================*/
+
+#ifndef LIBBSP_POWERPC_GEN5200_BSP_H
+#define LIBBSP_POWERPC_GEN5200_BSP_H
+
+#include <bspopts.h>
+
+#include <libcpu/powerpc-utility.h>
+
+/*
+ * Some symbols defined in the linker command file.
+ */
+
+LINKER_SYMBOL(bsp_ram_start);
+LINKER_SYMBOL(bsp_ram_end);
+LINKER_SYMBOL(bsp_ram_size);
+
+LINKER_SYMBOL(bsp_rom_start);
+LINKER_SYMBOL(bsp_rom_end);
+LINKER_SYMBOL(bsp_rom_size);
+
+LINKER_SYMBOL(bsp_dpram_start);
+LINKER_SYMBOL(bsp_dpram_end);
+LINKER_SYMBOL(bsp_dpram_size);
+
+LINKER_SYMBOL(bsp_section_text_start);
+LINKER_SYMBOL(bsp_section_text_end);
+LINKER_SYMBOL(bsp_section_text_size);
+
+LINKER_SYMBOL(bsp_section_data_start);
+LINKER_SYMBOL(bsp_section_data_end);
+LINKER_SYMBOL(bsp_section_data_size);
+
+LINKER_SYMBOL(bsp_section_bss_start);
+LINKER_SYMBOL(bsp_section_bss_end);
+LINKER_SYMBOL(bsp_section_bss_size);
+
+LINKER_SYMBOL(bsp_interrupt_stack_start);
+LINKER_SYMBOL(bsp_interrupt_stack_end);
+LINKER_SYMBOL(bsp_interrupt_stack_size);
+
+LINKER_SYMBOL(bsp_work_area_start);
+
+LINKER_SYMBOL(MBAR);
+
+/* Provide legacy defines */
+
+#ifdef MPC5200_BOARD_PM520_ZE30
+#define PM520_ZE30
+#endif
+
+#ifdef MPC5200_BOARD_PM520_CR825
+#define PM520_CR825
+#endif
+
+#ifdef MPC5200_BOARD_ICECUBE
+#define icecube
+#endif
+
+#ifdef MPC5200_BOARD_BRS5L
+#define BRS5L
+#endif
+
+/*
+ * distinguish board characteristics
+ */
+/*
+ * for PM520 mdule on a ZE30 carrier
+ */
+#if defined(MPC5200_BOARD_PM520_ZE30)
+#define PM520
+#endif
+/*
+ * for PM520 mdule on a CR825 carrier
+ */
+#if defined(MPC5200_BOARD_PM520_CR825)
+#define PM520
+#endif
+
+#if !defined(HAS_UBOOT)
+  /* we need the low level initialization in start.S*/
+  #define NEED_LOW_LEVEL_INIT
+#endif
+
+#if defined(MPC5200_BOARD_BRS5L)
+/*
+ * IMD Custom Board BRS5L
+ */
+
+#define HAS_NVRAM_93CXX
+
+#elif defined(MPC5200_BOARD_BRS6L)
+  #define MPC5200_BRS6L_FPGA_BEGIN 0x800000
+  #define MPC5200_BRS6L_FPGA_SIZE (64 * 1024)
+  #define MPC5200_BRS6L_FPGA_END \
+    (MPC5200_BRS6L_FPGA_BEGIN + MPC5200_BRS6L_FPGA_SIZE)
+
+  #define MPC5200_BRS6L_MRAM_BEGIN 0xff000000
+  #define MPC5200_BRS6L_MRAM_SIZE (4 * 1024 * 1024)
+  #define MPC5200_BRS6L_MRAM_END \
+    (MPC5200_BRS6L_MRAM_BEGIN + MPC5200_BRS6L_MRAM_SIZE)
+#elif defined (PM520)
+
+/* Nothing special */
+
+#elif defined (MPC5200_BOARD_ICECUBE)
+/*
+ *  Codename: IceCube
+ *  Compatible Boards:
+ *     Freescape MPC5200LITE
+ *     Embedded Planet EP5200
+ */
+
+#elif defined (MPC5200_BOARD_DP2)
+
+/* Nothing special */
+
+#else
+#error "board type not defined"
+#endif
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <bsp/i2cdrv.h>
+#include <bsp/irq.h>
+#include <bsp/vectors.h>
+#include <bsp/u-boot.h>
+#include <bsp/default-initial-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Network driver configuration
+ */
+struct rtems_bsdnet_ifconfig;
+extern int rtems_mpc5200_fec_driver_attach_detach (struct rtems_bsdnet_ifconfig *config, int attaching);
+#define RTEMS_BSP_NETWORK_DRIVER_NAME	"eth1"
+#define RTEMS_BSP_NETWORK_DRIVER_ATTACH	rtems_mpc5200_fec_driver_attach_detach
+
+/* miscellaneous stuff assumed to exist */
+
+/*
+ * We need to decide how much memory will be non-cacheable. This
+ * will mainly be memory that will be used in DMA (network and serial
+ * buffers).
+ */
+/*
+#define NOCACHE_MEM_SIZE 512*1024
+*/
+
+/*
+ *  Device Driver Table Entries
+ */
+
+#ifdef HAS_NVRAM_93CXX
+#define NVRAM_DRIVER_TABLE_ENTRY \
+  { nvram_driver_initialize, nvram_driver_open, nvram_driver_close, \
+    nvram_driver_read, nvram_driver_write, NULL }
+#endif
+
+/*
+ * indicate, that BSP has IDE driver
+ */
+#define RTEMS_BSP_HAS_IDE_DRIVER
+
+/* functions */
+
+/* #define SHOW_MORE_INIT_SETTINGS 1 */
+
+/* ata modes */
+/* #undef ATA_USE_INT */
+#define ATA_USE_INT
+
+/* clock settings */
+#if defined(HAS_UBOOT)
+#define IPB_CLOCK (bsp_uboot_board_info.bi_ipbfreq)
+#define XLB_CLOCK (bsp_uboot_board_info.bi_busfreq)
+#define G2_CLOCK  (bsp_uboot_board_info.bi_intfreq)
+#elif defined(MPC5200_BOARD_BRS5L) || defined(MPC5200_BOARD_BRS6L)
+#define IPB_CLOCK 66000000   /* 66 MHz */
+#define XLB_CLOCK 132000000  /* 132 MHz */
+#define G2_CLOCK  396000000  /* 396 MHz */
+#else
+#define IPB_CLOCK 33000000   /* 33 MHz */
+#define XLB_CLOCK 66000000   /* 66 MHz */
+#define G2_CLOCK  231000000  /* 231 MHz */
+#endif
+
+#if defined(HAS_UBOOT)
+#define GEN5200_CONSOLE_BAUD (bsp_uboot_board_info.bi_baudrate)
+#else
+#define GEN5200_CONSOLE_BAUD 115200
+#endif
+
+/*
+ *  Convert decrement value to tenths of microsecnds (used by
+ *  shared timer driver).
+ *
+ *    + CPU has a XLB_CLOCK bus,
+ *    + There are 4 bus cycles per click
+ *    + We return value in 1/10 microsecond units.
+ *   Modified following equation to integer equation to remove
+ *   floating point math.
+ *   (int) ((float)(_value) / ((XLB_CLOCK/1000000 * 0.1) / 4.0))
+ */
+
+#define BSP_Convert_decrementer( _value ) \
+  (int) (((_value) * 4000) / (XLB_CLOCK/10000))
+
+/* slicetimer settings */
+#define USE_SLICETIMER_0     TRUE
+#define USE_SLICETIMER_1     FALSE
+
+void *bsp_idle_thread( uintptr_t ignored );
+#define BSP_IDLE_TASK_BODY bsp_idle_thread
+
+/* BSP specific IRQ Benchmarking support */
+void BSP_IRQ_Benchmarking_Reset(void);
+void BSP_IRQ_Benchmarking_Report(void);
+
+#if defined(HAS_UBOOT)
+  /* Routine to obtain U-Boot environment variables */
+  const char *bsp_uboot_getenv(
+    const char *name
+  );
+#endif
+
+void cpu_init(void);
+
+int mpc5200_eth_mii_read(
+  int phyAddr,
+  void *arg,
+  unsigned regAddr,
+  uint32_t *retVal
+);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ASM */
+
+#endif /* GEN5200 */
diff --git a/bsps/powerpc/gen5200/include/bsp/ata.h b/bsps/powerpc/gen5200/include/bsp/ata.h
new file mode 100644
index 0000000000..3d8ccfc49a
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/ata.h
@@ -0,0 +1,338 @@
+/*
+ * Copyright (c) 2010-2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef GEN5200_ATA_H
+#define GEN5200_ATA_H
+
+#include "bestcomm.h"
+
+#include <assert.h>
+
+#include <rtems.h>
+#include <rtems/diskdevs.h>
+#include <rtems/bdbuf.h>
+
+#include <libchip/ata_internal.h>
+#include <libchip/ide_ctrl_io.h>
+#include <libchip/ide_ctrl_cfg.h>
+
+#include <libcpu/powerpc-utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define DCTRL_SRST BSP_BBIT8(5)
+#define DCTRL_NIEN BSP_BBIT8(6)
+
+#define DAST_BSY BSP_BBIT8(0)
+#define DAST_DRDY BSP_BBIT8(1)
+#define DAST_DRQ BSP_BBIT8(4)
+#define DAST_ERR BSP_BBIT8(7)
+
+#define DST_BSY BSP_BBIT16(0)
+#define DST_DRDY BSP_BBIT16(1)
+#define DST_DRQ BSP_BBIT16(4)
+#define DST_ERR BSP_BBIT16(7)
+
+#define DDMA_HUT BSP_BBIT8(1)
+#define DDMA_FR BSP_BBIT8(2)
+#define DDMA_FE BSP_BBIT8(3)
+#define DDMA_IE BSP_BBIT8(4)
+#define DDMA_UDMA BSP_BBIT8(5)
+#define DDMA_READ BSP_BBIT8(6)
+#define DDMA_WRITE BSP_BBIT8(7)
+
+#define ATA_SECTOR_SHIFT 9
+
+#define ATA_PER_TRANSFER_SECTOR_COUNT_MAX 256
+
+typedef union {
+  struct {
+    uint8_t alternate_status;
+    uint8_t reserved_0[3];
+    uint16_t data;
+    uint8_t reserved_1[2];
+    uint8_t error;
+    uint8_t reserved_2[3];
+    uint8_t sector_count;
+    uint8_t reserved_3[3];
+    uint8_t sector;
+    uint8_t reserved_4[3];
+    uint8_t cylinder_low;
+    uint8_t reserved_5[3];
+    uint8_t cylinder_high;
+    uint8_t reserved_6[3];
+    uint8_t head;
+    uint8_t reserved_7[3];
+    uint16_t status;
+    uint8_t reserved_8[2];
+  } read;
+
+  struct {
+    uint8_t control;
+    uint8_t reserved_0[3];
+    uint16_t data;
+    uint8_t reserved_1[2];
+    uint8_t feature;
+    uint8_t reserved_2[3];
+    uint8_t sector_count;
+    uint8_t reserved_3[3];
+    uint8_t sector;
+    uint8_t reserved_4[3];
+    uint8_t cylinder_low;
+    uint8_t reserved_5[3];
+    uint8_t cylinder_high;
+    uint8_t reserved_6[3];
+    uint8_t head;
+    uint8_t reserved_7[3];
+    uint8_t command;
+    uint8_t dma_control;
+    uint8_t reserved_8[2];
+  } write;
+} ata_drive_registers;
+
+#define ATA ((volatile ata_drive_registers *) 0xf0003a5c)
+
+static inline bool ata_is_data_request(void)
+{
+  return (ATA->read.alternate_status & DAST_DRQ) != 0;
+}
+
+static inline bool ata_is_drive_ready_for_selection(void)
+{
+  return (ATA->read.alternate_status & (DAST_BSY | DAST_DRQ)) == 0;
+}
+
+static inline void ata_wait_400_nano_seconds(void)
+{
+  ATA->read.alternate_status;
+}
+
+static inline void ata_wait_for_drive_ready(void)
+{
+  while ((ATA->read.alternate_status & (DAST_BSY | DAST_DRQ | DAST_DRDY)) != DAST_DRDY) {
+    /* Wait */
+  }
+}
+
+static inline void ata_wait_for_not_busy(void)
+{
+  ata_wait_400_nano_seconds();
+
+  while ((ATA->read.alternate_status & DAST_BSY) != 0) {
+    /* Wait */
+  }
+}
+
+static inline bool ata_wait_for_data_request(void)
+{
+  ata_wait_400_nano_seconds();
+
+  uint8_t alternate_status;
+  do {
+    alternate_status = ATA->read.alternate_status;
+  } while ((alternate_status & DAST_BSY) == DAST_BSY);
+
+  return (alternate_status & (DAST_ERR | DAST_DRQ)) == DAST_DRQ;
+}
+
+static inline bool ata_check_status(void)
+{
+  return (ATA->read.status & (DST_BSY | DST_ERR)) == 0;
+}
+
+static inline void ata_clear_interrupts(void)
+{
+  ATA->read.status;
+}
+
+static inline uint8_t ata_read_or_write_sectors_command(bool read)
+{
+  return read ? 0x20 : 0x30;
+}
+
+static inline rtems_blkdev_bnum ata_max_transfer_count(rtems_blkdev_bnum sector_count)
+{
+  return sector_count > ATA_PER_TRANSFER_SECTOR_COUNT_MAX ?
+    ATA_PER_TRANSFER_SECTOR_COUNT_MAX
+      : sector_count;
+}
+
+static inline void ata_flush_sector(uint16_t *begin)
+{
+  /* XXX: The dcbi operation does not work properly */
+  rtems_cache_flush_multiple_data_lines(begin, ATA_SECTOR_SIZE);
+}
+
+void ata_reset_device(void);
+
+bool ata_set_transfer_mode(uint8_t mode);
+
+bool ata_execute_io_command(uint8_t command, uint32_t lba, uint32_t sector_count);
+
+static inline bool ata_execute_io_command_with_sg(uint8_t command, const rtems_blkdev_sg_buffer *sg)
+{
+  uint32_t lba = sg->block;
+  uint32_t sector_count = sg->length / ATA_SECTOR_SIZE;
+  return ata_execute_io_command(command, lba, sector_count);
+}
+
+typedef struct {
+  const rtems_blkdev_sg_buffer *sg;
+
+  size_t sg_count;
+
+  rtems_blkdev_bnum sg_buffer_offset_mask;
+
+  int sg_index_shift;
+} ata_sg_context;
+
+static inline void ata_sg_reset(ata_sg_context *self, const rtems_blkdev_sg_buffer *sg, size_t sg_count)
+{
+  self->sg = sg;
+  self->sg_count = sg_count;
+  uint32_t sectors_per_buffer = self->sg[0].length >> ATA_SECTOR_SHIFT;
+  self->sg_buffer_offset_mask = sectors_per_buffer - 1;
+  self->sg_index_shift = __builtin_ffs((int) sectors_per_buffer) - 1;
+}
+
+static inline void ata_sg_create_default(ata_sg_context *self)
+{
+  ata_sg_reset(self, NULL, 0);
+}
+
+static inline void ata_sg_create(ata_sg_context *self, const rtems_blkdev_sg_buffer *sg, size_t sg_count)
+{
+  ata_sg_reset(self, sg, sg_count);
+}
+
+static inline rtems_blkdev_bnum ata_sg_get_start_sector(const ata_sg_context *self)
+{
+  return self->sg[0].block;
+}
+
+static inline rtems_blkdev_bnum ata_sg_get_sector_count(const ata_sg_context *self)
+{
+  return (self->sg_buffer_offset_mask + 1) * self->sg_count;
+}
+
+static inline uint16_t *ata_sg_get_sector_data_begin(const ata_sg_context *self, rtems_blkdev_bnum relative_sector)
+{
+  uint16_t *begin = (uint16_t *)(self->sg[relative_sector >> self->sg_index_shift].buffer);
+
+  return begin + ((relative_sector & self->sg_buffer_offset_mask) << (ATA_SECTOR_SHIFT - 1));
+}
+
+static inline uint16_t *ata_sg_get_sector_data_end(const ata_sg_context *self, uint16_t *begin)
+{
+  return begin + ATA_SECTOR_SIZE / 2;
+}
+
+typedef struct {
+  rtems_id lock;
+
+  bool card_present;
+} ata_driver;
+
+void ata_driver_create(ata_driver *self, const char *device_file_path, rtems_block_device_ioctl io_control);
+
+void ata_driver_destroy(ata_driver *self);
+
+static inline void ata_driver_lock(const ata_driver *self)
+{
+  rtems_status_code sc = rtems_semaphore_obtain(self->lock, RTEMS_WAIT, RTEMS_NO_TIMEOUT);
+  assert(sc == RTEMS_SUCCESSFUL);
+}
+
+static inline void ata_driver_unlock(const ata_driver *self)
+{
+  rtems_status_code sc = rtems_semaphore_release(self->lock);
+  assert(sc == RTEMS_SUCCESSFUL);
+}
+
+static inline bool ata_driver_is_card_present(const ata_driver *self)
+{
+  return self->card_present;
+}
+
+static inline void ata_driver_io_request(
+  ata_driver *self,
+  rtems_blkdev_request *request,
+  bool (*transfer)(ata_driver *, bool, rtems_blkdev_sg_buffer *, size_t)
+)
+{
+  assert(request->req == RTEMS_BLKDEV_REQ_READ || request->req == RTEMS_BLKDEV_REQ_WRITE);
+  bool read = request->req != RTEMS_BLKDEV_REQ_WRITE;
+  rtems_blkdev_sg_buffer *sg = &request->bufs[0];
+  uint32_t sg_count = request->bufnum;
+  ata_driver_lock(self);
+  bool ok = (*transfer)(self, read, sg, sg_count);
+  ata_driver_unlock(self);
+  rtems_status_code sc = ok ? RTEMS_SUCCESSFUL : RTEMS_IO_ERROR;
+  rtems_blkdev_request_done(request, sc);
+}
+
+static inline int ata_driver_io_control(
+  rtems_disk_device *dd,
+  uint32_t cmd,
+  void *arg,
+  bool (*transfer)(ata_driver *, bool, rtems_blkdev_sg_buffer *, size_t)
+)
+{
+  ata_driver *self = (ata_driver *) rtems_disk_get_driver_data(dd);
+
+  switch (cmd) {
+    case RTEMS_BLKIO_REQUEST:
+      ata_driver_io_request(self, (rtems_blkdev_request *) arg, transfer);
+      return 0;
+    case RTEMS_BLKIO_CAPABILITIES:
+      *(uint32_t *) arg = RTEMS_BLKDEV_CAP_MULTISECTOR_CONT;
+      return 0;
+    default:
+      return rtems_blkdev_ioctl(dd, cmd, arg);
+  }
+}
+
+int ata_driver_io_control_pio_polled(
+  rtems_disk_device *dd,
+  uint32_t cmd,
+  void *arg
+);
+
+typedef struct {
+  ata_driver super;
+
+  bestcomm_task task;
+
+  bool read;
+
+  ata_sg_context sg_context;
+
+  rtems_blkdev_bnum transfer_current;
+
+  rtems_blkdev_bnum transfer_end;
+} ata_driver_dma_pio_single;
+
+void ata_driver_dma_pio_single_create(
+  ata_driver_dma_pio_single *self,
+  const char *device_file_path,
+  TaskId task_index
+);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* GEN5200_ATA_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm.h b/bsps/powerpc/gen5200/include/bsp/bestcomm.h
new file mode 100644
index 0000000000..366465565a
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm.h
@@ -0,0 +1,370 @@
+/*
+ * Copyright (c) 2010-2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef GEN5200_BESTCOMM_H
+#define GEN5200_BESTCOMM_H
+
+#include "bestcomm_ops.h"
+
+#include <assert.h>
+
+#include <rtems.h>
+
+#include <bsp/mpc5200.h>
+#include <bsp/bestcomm/bestcomm_api.h>
+#include <bsp/bestcomm/bestcomm_glue.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup BestComm BestComm Support
+ *
+ * @ingroup BestCommm
+ *
+ * @brief BestComm support.
+ *
+ * @{
+ */
+
+typedef struct {
+  uint32_t *tdt_begin;
+  uint32_t *tdt_last;
+  volatile uint32_t (*var_table)[32];
+  uint32_t fdt_and_pragmas;
+  uint32_t reserved_0;
+  uint32_t reserved_1;
+  uint32_t *context_begin;
+  uint32_t reserved_2;
+} bestcomm_task_entry;
+
+#define BESTCOMM_TASK_ENTRY_TABLE ((volatile bestcomm_task_entry *) 0xf0008000)
+
+#define BESTCOMM_IRQ_EVENT RTEMS_EVENT_13
+
+typedef struct {
+  int task_index;
+  rtems_id event_task_id;
+} bestcomm_irq;
+
+void bestcomm_irq_create(bestcomm_irq *self, int task_index);
+
+void bestcomm_irq_destroy(const bestcomm_irq *self);
+
+static inline void bestcomm_irq_enable(const bestcomm_irq *self)
+{
+  bestcomm_glue_irq_enable(self->task_index);
+}
+
+static inline void bestcomm_irq_disable(const bestcomm_irq *self)
+{
+  bestcomm_glue_irq_disable(self->task_index);
+}
+
+static inline void bestcomm_irq_clear(const bestcomm_irq *self)
+{
+  SDMA_CLEAR_IEVENT(&mpc5200.sdma.IntPend, self->task_index);
+}
+
+static inline int bestcomm_irq_get_task_index(const bestcomm_irq *self)
+{
+  return self->task_index;
+}
+
+static inline rtems_id bestcomm_irq_get_event_task_id(const bestcomm_irq *self)
+{
+  return self->event_task_id;
+}
+
+static inline void bestcomm_irq_set_event_task_id(bestcomm_irq *self, rtems_id id)
+{
+  self->event_task_id = id;
+}
+
+static inline void bestcomm_irq_wakeup_event_task(const bestcomm_irq *self)
+{
+  rtems_status_code sc = rtems_event_send(self->event_task_id, BESTCOMM_IRQ_EVENT);
+  assert(sc == RTEMS_SUCCESSFUL);
+}
+
+static inline void bestcomm_irq_wait(const bestcomm_irq *self)
+{
+  rtems_event_set events;
+  rtems_status_code sc = rtems_event_receive(
+    BESTCOMM_IRQ_EVENT,
+    RTEMS_EVENT_ALL | RTEMS_WAIT,
+    RTEMS_NO_TIMEOUT,
+    &events
+  );
+  assert(sc == RTEMS_SUCCESSFUL);
+  assert(events == BESTCOMM_IRQ_EVENT);
+}
+
+static inline bool bestcomm_irq_peek(const bestcomm_irq *self)
+{
+  rtems_event_set events;
+  rtems_status_code sc = rtems_event_receive(0, 0, 0, &events);
+  assert(sc == RTEMS_SUCCESSFUL);
+
+  return (events & BESTCOMM_IRQ_EVENT) != 0;
+}
+
+typedef struct {
+  volatile uint16_t *task_control_register;
+
+  volatile uint32_t (*variable_table)[32];
+
+  TaskId task_index;
+
+  bestcomm_irq irq;
+
+  uint32_t *tdt_begin;
+
+  size_t tdt_opcode_count;
+} bestcomm_task;
+
+void bestcomm_task_create(bestcomm_task *self, TaskId task_index);
+
+void bestcomm_task_create_and_load(
+  bestcomm_task *self,
+  TaskId task_index,
+  const uint32_t *tdt_source_begin,
+  size_t tdt_size
+);
+
+void bestcomm_task_destroy(bestcomm_task *self);
+
+void bestcomm_task_load(bestcomm_task *self, const uint32_t *tdt_source_begin, size_t tdt_size);
+
+static inline void bestcomm_task_set_priority(bestcomm_task *self, int priority)
+{
+  /* Allow higher priority initiator to block current initiator */
+  mpc5200.sdma.ipr[self->task_index] = SDMA_IPR_PRIOR(priority);
+}
+
+static inline void bestcomm_task_irq_enable(const bestcomm_task *self)
+{
+  bestcomm_irq_enable(&self->irq);
+}
+
+static inline void bestcomm_task_irq_disable(const bestcomm_task *self)
+{
+  bestcomm_irq_disable(&self->irq);
+}
+
+static inline void bestcomm_task_irq_clear(const bestcomm_task *self)
+{
+  bestcomm_irq_clear(&self->irq);
+}
+
+static inline rtems_id bestcomm_task_get_event_task_id(const bestcomm_task *self)
+{
+  return bestcomm_irq_get_event_task_id(&self->irq);
+}
+
+static inline void bestcomm_task_set_event_task_id(bestcomm_task *self, rtems_id id)
+{
+  bestcomm_irq_set_event_task_id(&self->irq, id);
+}
+
+static inline void bestcomm_task_associate_with_current_task(bestcomm_task *self)
+{
+  bestcomm_task_set_event_task_id(self, rtems_task_self());
+}
+
+static inline void bestcomm_task_start(const bestcomm_task *self)
+{
+  *self->task_control_register = SDMA_TCR_EN | SDMA_TCR_HIGH_EN;
+}
+
+static inline void bestcomm_task_start_with_autostart(const bestcomm_task *self)
+{
+  *self->task_control_register = (uint16_t)
+    (SDMA_TCR_EN | SDMA_TCR_HIGH_EN | SDMA_TCR_AUTO_START | SDMA_TCR_AS(self->task_index));
+}
+
+static inline void bestcomm_task_stop(const bestcomm_task *self)
+{
+  *self->task_control_register = 0;
+}
+
+static inline void bestcomm_task_wakeup_event_task(const bestcomm_task *self)
+{
+  bestcomm_irq_wakeup_event_task(&self->irq);
+}
+
+static inline void bestcomm_task_wait(const bestcomm_task *self)
+{
+  bestcomm_irq_wait(&self->irq);
+}
+
+static inline bool bestcomm_task_peek(const bestcomm_task *self)
+{
+  return bestcomm_irq_peek(&self->irq);
+}
+
+static inline bool bestcomm_task_is_running(const bestcomm_task *self)
+{
+  return (*self->task_control_register & SDMA_TCR_EN) != 0;
+}
+
+static inline uint32_t bestcomm_get_task_variable(const bestcomm_task *self, size_t index)
+{
+  assert(index < VAR_COUNT);
+  return (*self->variable_table)[index];
+}
+
+static inline volatile uint32_t *bestcomm_task_get_address_of_variable(const bestcomm_task *self, size_t index)
+{
+  assert(index < VAR_COUNT);
+  return &(*self->variable_table)[index];
+}
+
+static inline void bestcomm_task_set_variable(const bestcomm_task *self, size_t index, uint32_t value)
+{
+  assert(index < VAR_COUNT);
+  (*self->variable_table)[index] = value;
+}
+
+static inline uint32_t bestcomm_task_get_increment_and_condition(const bestcomm_task *self, size_t index)
+{
+  assert(index < INC_COUNT);
+  return (*self->variable_table)[INC(index)];
+}
+
+static inline void bestcomm_task_set_increment_and_condition_32(
+  const bestcomm_task *self,
+  size_t index,
+  uint32_t inc_and_cond
+)
+{
+  assert(index < INC_COUNT);
+  (*self->variable_table)[INC(index)] = inc_and_cond;
+}
+
+static inline void bestcomm_task_set_increment_and_condition(
+  const bestcomm_task *self,
+  size_t index,
+  int16_t inc,
+  int cond
+)
+{
+  bestcomm_task_set_increment_and_condition_32(self, index, INC_INIT(cond, inc));
+}
+
+static inline void bestcomm_task_set_increment(const bestcomm_task *self, size_t index, int16_t inc)
+{
+  bestcomm_task_set_increment_and_condition_32(self, index, INC_INIT(0, inc));
+}
+
+void bestcomm_task_clear_variables(const bestcomm_task *self);
+
+static inline uint32_t bestcomm_task_get_opcode(const bestcomm_task *self, size_t index)
+{
+  assert(index < self->tdt_opcode_count);
+  return self->tdt_begin[index];
+}
+
+static inline void bestcomm_task_set_opcode(bestcomm_task *self, size_t index, uint32_t opcode)
+{
+  assert(index < self->tdt_opcode_count);
+  self->tdt_begin[index] = opcode;
+}
+
+static inline void bestcomm_task_set_initiator(const bestcomm_task *self, int initiator)
+{
+  rtems_interrupt_level level;
+  rtems_interrupt_disable(level);
+  *self->task_control_register = BSP_BFLD16SET(*self->task_control_register, initiator, 3, 7);
+  rtems_interrupt_enable(level);
+}
+
+static inline volatile bestcomm_task_entry *bestcomm_task_get_task_entry(const bestcomm_task *self)
+{
+  return &BESTCOMM_TASK_ENTRY_TABLE[self->task_index];
+}
+
+static inline void bestcomm_task_set_pragma(const bestcomm_task *self, int bit_pos, bool enable)
+{
+  volatile bestcomm_task_entry *entry = bestcomm_task_get_task_entry(self);
+  uint32_t mask = BSP_BIT32(bit_pos);
+  uint32_t bit = enable ? mask : 0;
+  entry->fdt_and_pragmas = (entry->fdt_and_pragmas & ~mask) | bit;
+}
+
+static inline void bestcomm_task_enable_precise_increment(const bestcomm_task *self, bool enable)
+{
+  bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_PRECISE_INC, enable);
+}
+
+static inline void bestcomm_task_enable_error_reset(const bestcomm_task *self, bool enable)
+{
+  bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_RST_ERROR_NO, !enable);
+}
+
+static inline void bestcomm_task_enable_pack_data(const bestcomm_task *self, bool enable)
+{
+  bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_PACK, enable);
+}
+
+static inline void bestcomm_task_enable_integer_mode(const bestcomm_task *self, bool enable)
+{
+  bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_INTEGER, enable);
+}
+
+static inline void bestcomm_task_enable_speculative_read(const bestcomm_task *self, bool enable)
+{
+  bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_SPECREAD, enable);
+}
+
+static inline void bestcomm_task_enable_combined_write(const bestcomm_task *self, bool enable)
+{
+  bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_CW, enable);
+}
+
+static inline void bestcomm_task_enable_read_buffer(const bestcomm_task *self, bool enable)
+{
+  bestcomm_task_set_pragma(self, SDMA_PRAGMA_BIT_RL, enable);
+}
+
+static inline volatile uint16_t *bestcomm_task_get_task_control_register(const bestcomm_task *self)
+{
+  return self->task_control_register;
+}
+
+static inline int bestcomm_task_get_task_index(const bestcomm_task *self)
+{
+  return self->task_index;
+}
+
+static inline void bestcomm_task_free_tdt(bestcomm_task *self)
+{
+  bestcomm_free(self->tdt_begin);
+  self->tdt_begin = NULL;
+}
+
+static inline void bestcomm_task_clear_pragmas(const bestcomm_task *self)
+{
+  volatile bestcomm_task_entry *entry = bestcomm_task_get_task_entry(self);
+  entry->fdt_and_pragmas &= ~0xffU;
+}
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* GEN5200_BESTCOMM_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h
new file mode 100644
index 0000000000..f1fa22d1d5
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_api.h
@@ -0,0 +1,460 @@
+#ifndef __BESTCOMM_API_H
+#define __BESTCOMM_API_H 1
+
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+/*!
+ * \file	bestcomm_api.h
+ *
+ * Bestcomm_api.h is the only header necessary for inclusion by user
+ * code. The include path the C compiler searches to find .h files
+ * should contain bestcomm/capi and one of bestcomm/code_dma/image_*.
+ * This second entry selects which set of BestComm tasks will be used.
+ * Of course the appropriate files in image_* must also be compiled and
+ * linked.
+ */
+
+#include <rtems.h>
+
+#include "include/ppctypes.h"
+#include "include/mgt5200/sdma.h"
+#include "task_api/tasksetup_bdtable.h"
+#include "task_api/bestcomm_cntrl.h"
+#include "task_api/bestcomm_api_mem.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * \brief	TaskSetup() debugging
+ *
+ * Define this macro as follows for debugging printf()s to see
+ * what the API receives and sets from the TaskSetupParamSet_t
+ * struct. Implemented in capi/task_api/tasksetup_general.h.
+ *
+ * \verbatim
+ * >0  : print basic debug messages
+ * >=10: also print C-API interface variables
+ * >=20: also print task API interface variables
+ * else: do nothing
+ * \endverbatim
+ */
+#define DEBUG_BESTCOMM_API 0
+
+/*!
+ * \brief	Maximum number of tasks in the system.
+ * This number is hardware-dependent and not user configuration.
+ */
+#define MAX_TASKS 16
+
+/*
+ * This may need to be removed in certain implementations.
+ */
+#ifndef NULL
+# define NULL ((void *)0)
+#endif	/* NULL */
+
+typedef sint8 TaskId;
+typedef sint32 BDIdx;
+
+/*
+ * Special "task IDs" for interrupt handling API functions
+ */
+/*! \brief	Debug interrupt "task ID" */
+#define	DEBUG_INTR_ID	SDMA_INT_BIT_DBG
+
+/*! \brief	TEA interrupt "task ID"	*/
+#define TEA_INTR_ID		SDMA_INT_BIT_TEA
+
+/*! \brief	Task start autostart enable */
+#define TASK_AUTOSTART_ENABLE	1
+
+/*! \brief	Task start autostart disable */
+#define TASK_AUTOSTART_DISABLE	0
+
+/*! \brief	Task start interrupt enable */
+#define TASK_INTERRUPT_ENABLE	1
+
+/*! \brief	Task start interrupt disable */
+#define TASK_INTERRUPT_DISABLE	0
+
+/*
+ * Buffer descriptor flags to pass to TaskBDAssign().
+ */
+/*! \brief	Transmit frame done */
+#define TASK_BD_TFD	(1 << SDMA_DRD_BIT_TFD)
+
+/*! \brief	Interrupt on frame done	*/
+#define TASK_BD_INT	(1 << SDMA_DRD_BIT_INT)
+
+/*!
+ * \brief	Data transfer size
+ */
+typedef enum {
+	SZ_FLEX		= 3,	/*!< invalid for TaskSetupParamSet_t */
+	SZ_UINT8	= 1,	/*!< 1-byte	*/
+	SZ_UINT16	= 2,	/*!< 2-byte	*/
+	SZ_UINT32	= 4		/*!< 4-byte	*/
+} Sz_t;
+
+/*!
+ * \brief	API error codes
+ */
+typedef enum {
+	TASK_ERR_NO_ERR			= -1,	/*!< No error					*/
+	TASK_ERR_NO_INTR		= TASK_ERR_NO_ERR,
+									/*!< No interrupt				*/
+	TASK_ERR_INVALID_ARG	= -2,	/*!< Invalid function argument	*/
+	TASK_ERR_BD_RING_FULL	= -3,	/*!< Buffer descriptor ring full*/
+	TASK_ERR_API_ALREADY_INITIALIZED
+							= -4,	/*!< API has already been initialized */
+	TASK_ERR_SIZE_TOO_LARGE = -5,	/*!< Buffer descriptor cannot support size parameter */
+	TASK_ERR_BD_RING_EMPTY	= -6,	/*!< Buffer descriptor ring is empty*/
+	TASK_ERR_BD_BUSY		= -7,	/*!< The buffer descriptor is in use
+										 by the BestComm			*/
+	TASK_ERR_TASK_RUNNING	= -8	/*!< The task is running.		*/
+
+} TaskErr_t;
+
+/*!
+ * \brief	BestComm initiators
+ *
+ * These are assigned by TaskSetup().
+ */
+typedef enum {
+
+	INITIATOR_ALWAYS	=  0,
+	INITIATOR_SCTMR_0	=  1,
+	INITIATOR_SCTMR_1	=  2,
+	INITIATOR_FEC_RX	=  3,
+	INITIATOR_FEC_TX	=  4,
+	INITIATOR_ATA_RX	=  5,
+	INITIATOR_ATA_TX	=  6,
+	INITIATOR_SCPCI_RX	=  7,
+	INITIATOR_SCPCI_TX	=  8,
+	INITIATOR_PSC3_RX	=  9,
+	INITIATOR_PSC3_TX	= 10,
+	INITIATOR_PSC2_RX	= 11,
+	INITIATOR_PSC2_TX	= 12,
+	INITIATOR_PSC1_RX	= 13,
+	INITIATOR_PSC1_TX	= 14,
+	INITIATOR_SCTMR_2	= 15,
+
+	INITIATOR_SCLPC		= 16,
+	INITIATOR_PSC5_RX	= 17,
+	INITIATOR_PSC5_TX	= 18,
+	INITIATOR_PSC4_RX	= 19,
+	INITIATOR_PSC4_TX	= 20,
+	INITIATOR_I2C2_RX	= 21,
+	INITIATOR_I2C2_TX	= 22,
+	INITIATOR_I2C1_RX	= 23,
+	INITIATOR_I2C1_TX	= 24,
+	INITIATOR_PSC6_RX	= 25,
+	INITIATOR_PSC6_TX	= 26,
+	INITIATOR_IRDA_RX	= 25,
+	INITIATOR_IRDA_TX	= 26,
+	INITIATOR_SCTMR_3	= 27,
+	INITIATOR_SCTMR_4	= 28,
+	INITIATOR_SCTMR_5	= 29,
+	INITIATOR_SCTMR_6	= 30,
+	INITIATOR_SCTMR_7	= 31
+
+} MPC5200Initiator_t;
+
+/*!
+ * \brief	Parameters for TaskSetup()
+ *
+ * All parameters can be hard-coded by the task API. Hard-coded values
+ * will be changed in the struct passed to TaskSetup() for the user to
+ * examine later.
+ */
+typedef struct {
+	uint32	NumBD;			/*!< Number of buffer descriptors				*/
+
+	union {
+	   uint32 MaxBuf;		/*!< Maximum buffer size						*/
+	   uint32 NumBytes;		/*!< Number of bytes to transfer				*/
+	} Size;					/*!< Buffer size union for BD and non-BD tasks	*/
+
+	MPC5200Initiator_t
+			Initiator;		/*!< BestComm initiator (ignored if hard-wired)	*/
+	uint32	StartAddrSrc;	/*!< Address of the DMA source (e.g. a FIFO)	*/
+	sint16	IncrSrc;		/*!< Amount to increment source pointer			*/
+	Sz_t	SzSrc;			/*!< Size of source data access					*/
+	uint32	StartAddrDst;	/*!< Address of the DMA destination (e.g. a FIFO) */
+	sint16	IncrDst;		/*!< Amount to increment data pointer			*/
+	Sz_t	SzDst;			/*!< Size of destination data access			*/
+} TaskSetupParamSet_t;
+
+/*!
+ * \brief	Parameters for TaskDebug()
+ *
+ * TaskDebug() and the contents of this data structure are yet to be
+ * determined.
+ */
+typedef struct {
+	int dummy;				/* Some compilers don't like empty struct typedefs */
+} TaskDebugParamSet_t;
+
+/*!
+ * \brief	Generic buffer descriptor.
+ *
+ * It is generally used as a pointer which should be cast to one of the
+ * other BD types based on the number of buffers per descriptor.
+ */
+typedef struct {
+	uint32 Status;			/*!< Status and length bits		*/
+} TaskBD_t;
+
+/*!
+ * \brief	Single buffer descriptor.
+ */
+typedef struct {
+	uint32 Status;			/*!< Status and length bits		*/
+	uint32 DataPtr[1];		/*!< Pointer to data buffer		*/
+} TaskBD1_t;
+
+/*!
+ * \brief	Dual buffer descriptor.
+ */
+typedef struct {
+	uint32 Status;			/*!< Status and length bits		*/
+	uint32 DataPtr[2];		/*!< Pointer to data buffers	*/
+} TaskBD2_t;
+
+
+
+/***************************
+ * Start of API Prototypes
+ ***************************/
+
+#include "bestcomm_priv.h"
+#include "dma_image.capi.h"
+
+/*!
+ * \brief	Initialize a single task.
+ * \param	TaskName	Type of task to initialize. E.g. PCI transmit,
+ *						ethernet receive, general purpose dual-pointer.
+ *						Values expected can be found in the TaskName_t
+ *						enum defined in dma_image.capi.h.
+ * \param	TaskSetupParams	Task-specific parameters. The user must fill out
+ *						the pertinent parts of a TaskSetupParamSet_t
+ *						data structure.
+ * \returns TaskId task identification token which is a required
+ *			parameter for most other API functions.
+ *
+ * This function returns a task identification token which is a required
+ * parameter for most other API functions.
+ *
+ * Certain values of the structure pointed to by TaskParams are set
+ * as a side-effect based on task type. These may be examined after
+ * a successful call to TaskSetup(). User-specified values may be
+ * overridden.
+ *
+ * TaskId TaskSetup( TaskName_t TaskName,
+ *                   TaskSetupParamSet_t *TaskSetupParams );
+ */
+#define			TaskSetupHelper(TaskName, TaskSetupParams)	\
+				TaskSetup_ ## TaskName (TaskName ## _api, TaskSetupParams)
+#define			TaskSetup(TaskName, TaskSetupParams) \
+				TaskSetupHelper(TaskName, TaskSetupParams)
+
+const char		*TaskVersion(void);
+
+int				TasksInitAPI(uint8 *MBarRef);
+
+int				TasksInitAPI_VM(uint8 *MBarRef, uint8 *MBarPhys);
+
+void			TasksLoadImage(sdma_regs *sdma);
+int				TasksAttachImage(sdma_regs *sdma);
+
+int				TaskStart(TaskId taskId, uint32 autoStartEnable,
+						  TaskId autoStartTask, uint32 intrEnable);
+int				TaskStop(TaskId taskId);
+static int		TaskStatus(TaskId taskId);
+BDIdx			TaskBDAssign(TaskId taskId, void *buffer0, void *buffer1,
+							 int size, uint32 bdFlags);
+BDIdx			TaskBDRelease(TaskId taskId);
+BDIdx			TaskBDReset(TaskId taskId);
+static TaskBD_t	*TaskGetBD(TaskId taskId, BDIdx bd);
+static TaskBD_t	*TaskGetBDRing(TaskId taskId);
+int				TaskDebug(TaskId taskId, TaskDebugParamSet_t *paramSet);
+static int		TaskIntClear(TaskId taskId);
+static TaskId	TaskIntStatus(TaskId taskId);
+static int		TaskIntPending(TaskId taskId);
+static TaskId	TaskIntSource(void);
+static uint16	TaskBDInUse(TaskId taskId);
+
+
+/*!
+ * \brief	Get the enable/disable status of a task.
+ * \param	taskId	Task handle passed back from a successful TaskSetup()
+ * \returns	Boolean true indicates enabled or false indicates disabled
+ *			or invalid taskId.
+ */
+static inline int TaskStatus(TaskId taskId)
+{
+	return SDMA_TASK_STATUS(SDMA_TCR, taskId) & 0x8000;
+}
+
+/*!
+ * \brief	Return a pointer to a buffer descriptor at index BDIdx
+ * \param	taskId	Task handle passed back from a successful TaskSetup()
+ * \param	bd		Buffer descriptor handle returned by
+ *					TaskBDAssign() or TaskBDRelease().
+ * \returns	Pointer to the requested buffer descriptor or NULL on error.
+ *
+ * The returned pointer should be cast to the appropriate buffer
+ * descriptor type, TaskBD1_t or TaskBD2_t.
+ */
+static inline TaskBD_t *TaskGetBD(TaskId taskId, BDIdx bd)
+{
+	void *bdTab;
+
+	bdTab = TaskBDIdxTable[taskId].BDTablePtr;
+	if (TaskBDIdxTable[taskId].numPtr == 1) {
+		return (TaskBD_t *)&(((TaskBD1_t *)bdTab)[bd]);
+	} else {
+		return (TaskBD_t *)&(((TaskBD2_t *)bdTab)[bd]);
+	}
+}
+
+/*!
+ * \brief	Return a pointer to the first buffer descriptor in the ring.
+ * \param	taskId	Task handle passed back from a successful TaskSetup()
+ * \returns	Pointer to the array of buffer descriptors making up the
+ *			ring or NULL on error.
+ *
+ * A device driver author may choose to use this in lieu of
+ * TaskBDAssign()/TaskBDRelease() to get direct access to the
+ * BD ring with the warning that the underlying data structure may change.
+ * Use at one's own discretion.
+ */
+static inline TaskBD_t *TaskGetBDRing(TaskId taskId)
+{
+	return (TaskBD_t *) TaskBDIdxTable[taskId].BDTablePtr;
+}
+
+/*!
+ * \brief	Clear the interrupt for a given BestComm task.
+ * \param	taskId	Task handle passed back from a successful TaskSetup()
+ * \returns	TASK_ERR_NO_ERR (which is not really an error) for success
+ */
+static inline int TaskIntClear(TaskId taskId)
+{
+	SDMA_CLEAR_IEVENT(SDMA_INT_PEND, taskId);
+	return TASK_ERR_NO_ERR;	/* success */
+}
+
+/*!
+ * \brief	Get the interrupt status for a given task.
+ * \param	taskId	Task handle passed back from a successful TaskSetup()
+ * \returns	TASK_ERR_NO_INTR (which is not really an error) for no interrupt
+ *			pending, taskId for a regular interrupt, DEBUG_INTR_ID for
+ *			a debug interrupt and TEA_INTR_ID for a TEA interrupt.
+ *			\b Note: TaskIntStatus() may return 0, but this means that that
+ *			taskId 0 is interrupt pending.
+ */
+static inline TaskId TaskIntStatus(TaskId taskId)
+{
+	uint32 pending;
+
+	pending = SDMA_INT_PENDING(SDMA_INT_PEND, SDMA_INT_MASK);
+
+	if (SDMA_INT_TEST(pending, taskId)) {
+		return taskId;
+	} else if (SDMA_INT_TEST(pending, DEBUG_INTR_ID)) {
+		return DEBUG_INTR_ID;
+	} else if (SDMA_INT_TEST(pending, TEA_INTR_ID)) {
+		return TEA_INTR_ID;
+	}
+
+	return TASK_ERR_NO_INTR;
+}
+
+/*!
+ * \brief	Get the interrupt pending status for a given task.
+ * \param	taskId	Task handle passed back from a successful TaskSetup()
+ * \returns	0 if task does not have a pending interrupt. 1 if the task
+ *			has an interrupt pending.
+ */
+static inline int TaskIntPending(TaskId taskId)
+{
+	uint32 pending;
+
+	pending = SDMA_INT_PENDING(SDMA_INT_PEND, SDMA_INT_MASK);
+	if (SDMA_INT_TEST(pending, taskId)) {
+		return 1;
+	} else {
+		return 0;
+	}
+}
+
+/*!
+ * \brief	Returns the task ID of an interrupting BestComm task.
+ * \returns	TASK_ERR_NO_INTR (which is not really an error) for no interrupt
+ *			pending or the taskId of the interrupting task.
+ *
+ * The user must query TaskIntStatus() to discover if this is a debug
+ * or TEA interrupt. This function is designed for use by an operating
+ * system interrupt handler.
+ */
+static inline TaskId TaskIntSource(void)
+{
+	uint32 pending;
+	uint32 mask = 1 << (MAX_TASKS - 1);
+	TaskId i;
+
+	pending = SDMA_INT_PENDING(SDMA_INT_PEND, SDMA_INT_MASK);
+
+	if (SDMA_INT_TEST(pending, SDMA_INT_BIT_TEA)) {
+		return (TaskId)SDMA_TEA_SOURCE(SDMA_INT_PEND);
+	}
+
+	for (i = (MAX_TASKS - 1); i >= 0; --i, mask >>= 1) {
+		if (pending & mask) {
+			return i;
+		}
+	}
+
+	return TASK_ERR_NO_INTR;
+}
+
+/*!
+ * \brief	Get a count of in-use buffer descriptors.
+ * \param	taskId	Task handle passed back from a successful TaskSetup()
+ * \returns	Count of the current number of BDs in use by the given task.
+ */
+static inline uint16 TaskBDInUse(TaskId taskId)
+{
+	return TaskBDIdxTable[taskId].currBDInUse;
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif	/* __BESTCOMM_API_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h
new file mode 100644
index 0000000000..18827b77c7
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_glue.h
@@ -0,0 +1,114 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC5200 BSP                              |
++-----------------------------------------------------------------+
+|                    Copyright (c) 2004-2005                      |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file declares glue functions to the Freescale BestComm API |
+\*===============================================================*/
+#ifndef _BESTCOMM_GLUE_H
+#define _BESTCOMM_GLUE_H
+
+#include <rtems/irq-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/*=========================================================================*\
+| Function:                                                                 |
+\*-------------------------------------------------------------------------*/
+void bestcomm_glue_irq_enable
+(
+/*-------------------------------------------------------------------------*\
+| Purpose:                                                                  |
+|   enable interrupt for given task number                                  |
++---------------------------------------------------------------------------+
+| Input Parameters:                                                         |
+\*-------------------------------------------------------------------------*/
+ int bestcomm_taskno                           /* task number to enable    */
+ );
+/*-------------------------------------------------------------------------*\
+| Return Value:                                                             |
+|    none                                                                   |
+\*=========================================================================*/
+
+/*=========================================================================*\
+| Function:                                                                 |
+\*-------------------------------------------------------------------------*/
+void bestcomm_glue_irq_disable
+(
+/*-------------------------------------------------------------------------*\
+| Purpose:                                                                  |
+|   disable interrupt for given task number                                 |
++---------------------------------------------------------------------------+
+| Input Parameters:                                                         |
+\*-------------------------------------------------------------------------*/
+ int bestcomm_taskno                           /* task number to disable   */
+ );
+/*-------------------------------------------------------------------------*\
+| Return Value:                                                             |
+|    none                                                                   |
+\*=========================================================================*/
+
+/*=========================================================================*\
+| Function:                                                                 |
+\*-------------------------------------------------------------------------*/
+void bestcomm_glue_irq_install
+(
+/*-------------------------------------------------------------------------*\
+| Purpose:                                                                  |
+|   install given function as bestcomm interrupt handler                    |
++---------------------------------------------------------------------------+
+| Input Parameters:                                                         |
+\*-------------------------------------------------------------------------*/
+ int bestcomm_taskno,                          /* task number for handler  */
+ rtems_interrupt_handler handler,              /* function to call         */
+ void *arg
+ );
+/*-------------------------------------------------------------------------*\
+| Return Value:                                                             |
+|    none                                                                   |
+\*=========================================================================*/
+
+/*=========================================================================*\
+| Function:                                                                 |
+\*-------------------------------------------------------------------------*/
+void bestcomm_glue_init
+(
+/*-------------------------------------------------------------------------*\
+| Purpose:                                                                  |
+|   initialize the bestcomm module (if not yet done):                       |
+|   - load code                                                             |
+|   - initialize registers                                                  |
+|   - initialize bus arbiter                                                |
+|   - initialize interrupt control                                          |
++---------------------------------------------------------------------------+
+| Input Parameters:                                                         |
+\*-------------------------------------------------------------------------*/
+ void /* none */
+ );
+/*-------------------------------------------------------------------------*\
+| Return Value:                                                             |
+|    none                                                                   |
+\*=========================================================================*/
+
+void *bestcomm_malloc(size_t size);
+
+void bestcomm_free(void *ptr);
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* _BESTCOMM_GLUE_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h
new file mode 100644
index 0000000000..102fc082cb
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/bestcomm_priv.h
@@ -0,0 +1,38 @@
+#ifndef __BESTCOMM_PRIV_H
+#define __BESTCOMM_PRIV_H 1
+
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+/*
+ * Global variables necessitated by the TaskSetup_*() location in
+ * separate files from the main code and the inline functions. These are
+ * private data structures that should not be manipulated by API users.
+ */
+
+extern TaskBDIdxTable_t TaskBDIdxTable[MAX_TASKS];
+extern int              TaskRunning[MAX_TASKS];
+extern sint64			MBarPhysOffsetGlobal;
+
+#endif	/* __BESTCOMM_PRIV_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h
new file mode 100644
index 0000000000..6b07cbcb2a
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.capi.h
@@ -0,0 +1,84 @@
+#ifndef __DMA_IMAGE_CAPI_H
+#define __DMA_IMAGE_CAPI_H 1
+
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+
+#include "dma_image.h"
+
+typedef enum {
+	TASK_PCI_TX,
+	TASK_PCI_RX,
+	TASK_FEC_TX,
+	TASK_FEC_RX,
+	TASK_LPC,
+	TASK_ATA,
+	TASK_CRC16_DP_0,
+	TASK_CRC16_DP_1,
+	TASK_GEN_DP_0,
+	TASK_GEN_DP_1,
+	TASK_GEN_DP_2,
+	TASK_GEN_DP_3,
+	TASK_GEN_TX_BD,
+	TASK_GEN_RX_BD,
+	TASK_GEN_DP_BD_0,
+	TASK_GEN_DP_BD_1
+} TaskName_t;
+
+TaskId TaskSetup_TASK_PCI_TX    (TASK_PCI_TX_api_t    *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_PCI_RX    (TASK_PCI_RX_api_t    *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_FEC_TX    (TASK_FEC_TX_api_t    *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_FEC_RX    (TASK_FEC_RX_api_t    *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_LPC       (TASK_LPC_api_t       *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_ATA       (TASK_ATA_api_t       *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_CRC16_DP_0(TASK_CRC16_DP_0_api_t *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_CRC16_DP_1(TASK_CRC16_DP_1_api_t *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_GEN_DP_0  (TASK_GEN_DP_0_api_t  *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_GEN_DP_1  (TASK_GEN_DP_1_api_t  *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_GEN_DP_2  (TASK_GEN_DP_2_api_t  *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_GEN_DP_3  (TASK_GEN_DP_3_api_t  *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_GEN_TX_BD (TASK_GEN_TX_BD_api_t *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_GEN_RX_BD (TASK_GEN_RX_BD_api_t *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_GEN_DP_BD_0(TASK_GEN_DP_BD_0_api_t *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+TaskId TaskSetup_TASK_GEN_DP_BD_1(TASK_GEN_DP_BD_1_api_t *TaskAPI,
+                                 TaskSetupParamSet_t  *TaskSetupParams);
+
+#endif	/* __DMA_IMAGE_CAPI_H */
+
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h
new file mode 100644
index 0000000000..1f8b86cded
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/dma_image.h
@@ -0,0 +1,472 @@
+#ifndef __DMA_IMAGE_H
+#define __DMA_IMAGE_H 1
+
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+
+#include "include/ppctypes.h"
+
+void init_dma_image_TASK_PCI_TX(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_PCI_RX(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_FEC_TX(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_FEC_RX(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_LPC(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_ATA(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_CRC16_DP_0(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_CRC16_DP_1(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_GEN_DP_0(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_GEN_DP_1(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_GEN_DP_2(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_GEN_DP_3(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_GEN_TX_BD(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_GEN_RX_BD(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_GEN_DP_BD_0(uint8 *vMem_taskBar, sint64 vMemOffset);
+void init_dma_image_TASK_GEN_DP_BD_1(uint8 *vMem_taskBar, sint64 vMemOffset);
+
+/* MBAR_TASK_TABLE is the first address of task table */
+#ifndef MBAR_TASK_TABLE
+#define MBAR_TASK_TABLE                     0xf0008000UL
+#endif
+
+/* MBAR_DMA_FREE is the first free address after task table */
+#define MBAR_DMA_FREE                       MBAR_TASK_TABLE + 0x00001500UL
+
+/* TASK_BAR is the first address of the Entry table */
+#define TASK_BAR                            MBAR_TASK_TABLE + 0x00000000UL
+#define TASK_BAR_OFFSET                     0x00000000UL
+
+typedef struct task_info0 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[7];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *AddrDstFIFO;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *AddrPktSizeReg;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *AddrSCStatusReg;
+	volatile uint32 *Bytes;
+	volatile uint32 *IterExtra;
+	volatile uint32 *StartAddrSrc;
+} TASK_PCI_TX_api_t;
+extern TASK_PCI_TX_api_t *TASK_PCI_TX_api;
+
+typedef struct task_info1 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[5];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *AddrPktSizeReg;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *AddrSrcFIFO;
+	volatile sint16 *IncrDst;
+	volatile uint32 *Bytes;
+	volatile uint32 *IterExtra;
+	volatile uint32 *StartAddrDst;
+} TASK_PCI_RX_api_t;
+extern TASK_PCI_RX_api_t *TASK_PCI_RX_api;
+
+typedef struct task_info2 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[22];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *AddrDRD;
+	volatile uint32  AddrDRDIdx;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *AddrDstFIFO;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *AddrEnable;
+	volatile sint16 *IncrSrcMA;
+	volatile uint32 *BDTableBase;
+	volatile uint32 *BDTableLast;
+	volatile uint32 *BDTableStart;
+	volatile uint32 *Bytes;
+} TASK_FEC_TX_api_t;
+extern TASK_FEC_TX_api_t *TASK_FEC_TX_api;
+
+typedef struct task_info3 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[13];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *AddrEnable;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *AddrSrcFIFO;
+	volatile sint16 *IncrDst;
+	volatile uint32 *BDTableBase;
+	volatile sint16 *IncrDstMA;
+	volatile uint32 *BDTableLast;
+	volatile uint32 *BDTableStart;
+	volatile uint32 *Bytes;
+} TASK_FEC_RX_api_t;
+extern TASK_FEC_RX_api_t *TASK_FEC_RX_api;
+
+typedef struct task_info4 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[4];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *Bytes;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *IterExtra;
+	volatile sint16 *IncrDst;
+	volatile sint16 *IncrDstMA;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *StartAddrDst;
+	volatile sint16 *IncrSrcMA;
+	volatile uint32 *StartAddrSrc;
+} TASK_LPC_api_t;
+extern TASK_LPC_api_t *TASK_LPC_api;
+
+typedef struct task_info5 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[7];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *AddrEnable;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *BDTableBase;
+	volatile sint16 *IncrDst;
+	volatile uint32 *BDTableLast;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *BDTableStart;
+	volatile uint32 *Bytes;
+} TASK_ATA_api_t;
+extern TASK_ATA_api_t *TASK_ATA_api;
+
+typedef struct task_info6 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[9];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *Bytes;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *IterExtra;
+	volatile sint16 *IncrDst;
+	volatile sint16 *IncrDstMA;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *StartAddrDst;
+	volatile sint16 *IncrSrcMA;
+	volatile uint32 *StartAddrSrc;
+} TASK_CRC16_DP_0_api_t;
+extern TASK_CRC16_DP_0_api_t *TASK_CRC16_DP_0_api;
+
+typedef struct task_info7 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[9];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *Bytes;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *IterExtra;
+	volatile sint16 *IncrDst;
+	volatile sint16 *IncrDstMA;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *StartAddrDst;
+	volatile sint16 *IncrSrcMA;
+	volatile uint32 *StartAddrSrc;
+} TASK_CRC16_DP_1_api_t;
+extern TASK_CRC16_DP_1_api_t *TASK_CRC16_DP_1_api;
+
+typedef struct task_info8 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[4];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *Bytes;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *IterExtra;
+	volatile sint16 *IncrDst;
+	volatile sint16 *IncrDstMA;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *StartAddrDst;
+	volatile sint16 *IncrSrcMA;
+	volatile uint32 *StartAddrSrc;
+} TASK_GEN_DP_0_api_t;
+extern TASK_GEN_DP_0_api_t *TASK_GEN_DP_0_api;
+
+typedef struct task_info9 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[4];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *Bytes;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *IterExtra;
+	volatile sint16 *IncrDst;
+	volatile sint16 *IncrDstMA;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *StartAddrDst;
+	volatile sint16 *IncrSrcMA;
+	volatile uint32 *StartAddrSrc;
+} TASK_GEN_DP_1_api_t;
+extern TASK_GEN_DP_1_api_t *TASK_GEN_DP_1_api;
+
+typedef struct task_info10 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[4];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *Bytes;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *IterExtra;
+	volatile sint16 *IncrDst;
+	volatile sint16 *IncrDstMA;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *StartAddrDst;
+	volatile sint16 *IncrSrcMA;
+	volatile uint32 *StartAddrSrc;
+} TASK_GEN_DP_2_api_t;
+extern TASK_GEN_DP_2_api_t *TASK_GEN_DP_2_api;
+
+typedef struct task_info11 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[4];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *Bytes;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *IterExtra;
+	volatile sint16 *IncrDst;
+	volatile sint16 *IncrDstMA;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *StartAddrDst;
+	volatile sint16 *IncrSrcMA;
+	volatile uint32 *StartAddrSrc;
+} TASK_GEN_DP_3_api_t;
+extern TASK_GEN_DP_3_api_t *TASK_GEN_DP_3_api;
+
+typedef struct task_info12 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[8];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *AddrDstFIFO;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *AddrEnable;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *BDTableBase;
+	volatile sint16 *IncrSrcMA;
+	volatile uint32 *BDTableLast;
+	volatile uint32 *BDTableStart;
+	volatile uint32 *Bytes;
+} TASK_GEN_TX_BD_api_t;
+extern TASK_GEN_TX_BD_api_t *TASK_GEN_TX_BD_api;
+
+typedef struct task_info13 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[7];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *AddrEnable;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *AddrSrcFIFO;
+	volatile sint16 *IncrDst;
+	volatile uint32 *BDTableBase;
+	volatile uint32 *BDTableLast;
+	volatile uint32 *BDTableStart;
+	volatile uint32 *Bytes;
+} TASK_GEN_RX_BD_api_t;
+extern TASK_GEN_RX_BD_api_t *TASK_GEN_RX_BD_api;
+
+typedef struct task_info14 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[7];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *AddrEnable;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *BDTableBase;
+	volatile sint16 *IncrDst;
+	volatile uint32 *BDTableLast;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *BDTableStart;
+	volatile uint32 *Bytes;
+} TASK_GEN_DP_BD_0_api_t;
+extern TASK_GEN_DP_BD_0_api_t *TASK_GEN_DP_BD_0_api;
+
+typedef struct task_info15 {
+	volatile uint32  TaskNum;
+	volatile uint32 *PtrStartTDT;
+	volatile uint32 *PtrEndTDT;
+	volatile uint32 *PtrVarTab;
+	volatile uint32 *PtrFDT;
+	volatile uint32 *PtrCSave;
+	volatile uint32  NumDRD;
+	volatile uint32 *DRD[7];
+	volatile uint32  NumVar;
+	volatile uint32 *var;
+	volatile uint32  NumInc;
+	volatile uint32 *inc;
+	volatile uint8  *TaskPragma;
+	volatile uint32 *AddrEnable;
+	volatile sint16 *IncrBytes;
+	volatile uint32 *BDTableBase;
+	volatile sint16 *IncrDst;
+	volatile uint32 *BDTableLast;
+	volatile sint16 *IncrSrc;
+	volatile uint32 *BDTableStart;
+	volatile uint32 *Bytes;
+} TASK_GEN_DP_BD_1_api_t;
+extern TASK_GEN_DP_BD_1_api_t *TASK_GEN_DP_BD_1_api;
+
+
+#endif	/* __DMA_IMAGE_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h
new file mode 100644
index 0000000000..9e4b94cd10
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/mgt5200.h
@@ -0,0 +1,61 @@
+#ifndef __MGT5200_MGT5200_H
+#define __MGT5200_MGT5200_H
+
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+#define MBAR_CS         0x0000
+#define MBAR_SDRAM      0x0100
+#define MBAR_CDM        0x0200
+#define MBAR_LPC        0x0300
+#define MBAR_SCTMR      0x0400
+#define MBAR_INT_CTRL   0x0500
+#define MBAR_GPTIMER    0x0600
+#define MBAR_SLTIMER    0x0700
+#define MBAR_RTCLOCK    0x0800
+#define MBAR_MSCAN      0x0900
+#define MBAR_GPIO_STD   0x0B00
+#define MBAR_GPIO_WKUP  0x0C00
+#define MBAR_XCPCI      0x0D00
+#define MBAR_SPI        0x0F00
+#define MBAR_USB        0x1000
+#define MBAR_SDMA       0x1200
+#define MBAR_BDLC       0x1300
+#define MBAR_IR         0x1400
+#define MBAR_XLB_ARB    0x1F00
+#define MBAR_PSC1       0x2000
+#define MBAR_PSC2       0x2200
+#define MBAR_PSC3       0x2400
+#define MBAR_PSC4       0x2600
+#define MBAR_PSC5       0x2800
+#define MBAR_PSC6       0x2C00
+#define MBAR_IRDA       0x2C00
+#define MBAR_ETHERNET   0x3000
+#define MBAR_SCPCI      0x3800
+#define MBAR_ATA        0x3A00
+#define MBAR_SCLPC      0x3C00
+#define MBAR_I2C        0x3D00
+#define MBAR_SRAM       0x8000
+
+#endif /* __MGT5200_MGT5200_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h
new file mode 100644
index 0000000000..52d84777ad
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/mgt5200/sdma.h
@@ -0,0 +1,153 @@
+#ifndef __MGT5200_SDMA_H
+#define __MGT5200_SDMA_H
+
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+typedef struct sdma_register_set {
+    volatile uint32 taskBar;         /* MBAR_SDMA + 0x00 sdTpb */
+    volatile uint32 currentPointer;  /* MBAR_SDMA + 0x04 sdMdeComplex */
+    volatile uint32 endPointer;      /* MBAR_SDMA + 0x08 sdMdeComplex */
+    volatile uint32 variablePointer; /* MBAR_SDMA + 0x0c sdMdeComplex */
+
+    volatile uint8  IntVect1;   /* MBAR_SDMA + 0x10 sdPtd */
+    volatile uint8  IntVect2;   /* MBAR_SDMA + 0x11 sdPtd */
+    volatile uint16 PtdCntrl;   /* MBAR_SDMA + 0x12 sdPtd */
+
+    volatile uint32 IntPend;    /* MBAR_SDMA + 0x14 sdPtd */
+    volatile uint32 IntMask;    /* MBAR_SDMA + 0x18 sdPtd */
+
+    volatile uint32 TCR01;      /* MBAR_SDMA + 0x1c sdPtd */
+    volatile uint32 TCR23;      /* MBAR_SDMA + 0x20 sdPtd */
+    volatile uint32 TCR45;      /* MBAR_SDMA + 0x24 sdPtd */
+    volatile uint32 TCR67;      /* MBAR_SDMA + 0x28 sdPtd */
+    volatile uint32 TCR89;      /* MBAR_SDMA + 0x2c sdPtd */
+    volatile uint32 TCRAB;      /* MBAR_SDMA + 0x30 sdPtd */
+    volatile uint32 TCRCD;      /* MBAR_SDMA + 0x34 sdPtd */
+    volatile uint32 TCREF;      /* MBAR_SDMA + 0x38 sdPtd */
+
+    volatile uint8  IPR0;       /* MBAR_SDMA + 0x3c sdPtd */
+    volatile uint8  IPR1;       /* MBAR_SDMA + 0x3d sdPtd */
+    volatile uint8  IPR2;       /* MBAR_SDMA + 0x3e sdPtd */
+    volatile uint8  IPR3;       /* MBAR_SDMA + 0x3f sdPtd */
+    volatile uint8  IPR4;       /* MBAR_SDMA + 0x40 sdPtd */
+    volatile uint8  IPR5;       /* MBAR_SDMA + 0x41 sdPtd */
+    volatile uint8  IPR6;       /* MBAR_SDMA + 0x42 sdPtd */
+    volatile uint8  IPR7;       /* MBAR_SDMA + 0x43 sdPtd */
+    volatile uint8  IPR8;       /* MBAR_SDMA + 0x44 sdPtd */
+    volatile uint8  IPR9;       /* MBAR_SDMA + 0x45 sdPtd */
+    volatile uint8  IPR10;      /* MBAR_SDMA + 0x46 sdPtd */
+    volatile uint8  IPR11;      /* MBAR_SDMA + 0x47 sdPtd */
+    volatile uint8  IPR12;      /* MBAR_SDMA + 0x48 sdPtd */
+    volatile uint8  IPR13;      /* MBAR_SDMA + 0x49 sdPtd */
+    volatile uint8  IPR14;      /* MBAR_SDMA + 0x4a sdPtd */
+    volatile uint8  IPR15;      /* MBAR_SDMA + 0x4b sdPtd */
+    volatile uint8  IPR16;      /* MBAR_SDMA + 0x4c sdPtd */
+    volatile uint8  IPR17;      /* MBAR_SDMA + 0x4d sdPtd */
+    volatile uint8  IPR18;      /* MBAR_SDMA + 0x4e sdPtd */
+    volatile uint8  IPR19;      /* MBAR_SDMA + 0x4f sdPtd */
+    volatile uint8  IPR20;      /* MBAR_SDMA + 0x50 sdPtd */
+    volatile uint8  IPR21;      /* MBAR_SDMA + 0x51 sdPtd */
+    volatile uint8  IPR22;      /* MBAR_SDMA + 0x52 sdPtd */
+    volatile uint8  IPR23;      /* MBAR_SDMA + 0x53 sdPtd */
+    volatile uint8  IPR24;      /* MBAR_SDMA + 0x54 sdPtd */
+    volatile uint8  IPR25;      /* MBAR_SDMA + 0x55 sdPtd */
+    volatile uint8  IPR26;      /* MBAR_SDMA + 0x56 sdPtd */
+    volatile uint8  IPR27;      /* MBAR_SDMA + 0x57 sdPtd */
+    volatile uint8  IPR28;      /* MBAR_SDMA + 0x58 sdPtd */
+    volatile uint8  IPR29;      /* MBAR_SDMA + 0x59 sdPtd */
+    volatile uint8  IPR30;      /* MBAR_SDMA + 0x5a sdPtd */
+    volatile uint8  IPR31;      /* MBAR_SDMA + 0x5b sdPtd */
+
+    volatile uint32 cReqSelect; /* MBAR_SDMA + 0x5c sdPtd */
+    volatile uint32 taskSize0;  /* MBAR_SDMA + 0x60 sdPtd */
+    volatile uint32 taskSize1;  /* MBAR_SDMA + 0x64 sdPtd */
+    volatile uint32 MDEDebug;   /* MBAR_SDMA + 0x68 sdMdeComplex */
+    volatile uint32 ADSDebug;   /* MBAR_SDMA + 0x6c sdAdsTop */
+    volatile uint32 Value1;     /* MBAR_SDMA + 0x70 sdDbg */
+    volatile uint32 Value2;     /* MBAR_SDMA + 0x74 sdDbg */
+    volatile uint32 Control;    /* MBAR_SDMA + 0x78 sdDbg */
+    volatile uint32 Status;     /* MBAR_SDMA + 0x7c sdDbg */
+    volatile uint32 PTDDebug;   /* MBAR_SDMA + 0x80 sdPtd */
+} sdma_regs;
+
+#define SDMA_PTDCNTRL_TI	0x8000
+#define SDMA_PTDCNTRL_TEA	0x4000
+#define SDMA_PTDCNTRL_HE	0x2000
+#define SDMA_PTDCNTRL_PE	0x0001
+
+#define SDMA_CREQSELECT_REQ31_MASK		(~0xC0000000UL)
+#define SDMA_CREQSELECT_REQ30_MASK		(~0x30000000UL)
+#define SDMA_CREQSELECT_REQ29_MASK		(~0x0C000000UL)
+#define SDMA_CREQSELECT_REQ28_MASK		(~0x03000000UL)
+#define SDMA_CREQSELECT_REQ27_MASK		(~0x00C00000UL)
+#define SDMA_CREQSELECT_REQ26_MASK		(~0x00300000UL)
+#define SDMA_CREQSELECT_REQ25_MASK		(~0x000C0000UL)
+#define SDMA_CREQSELECT_REQ24_MASK		(~0x00030000UL)
+#define SDMA_CREQSELECT_REQ23_MASK		(~0x0000C000UL)
+#define SDMA_CREQSELECT_REQ22_MASK		(~0x00003000UL)
+#define SDMA_CREQSELECT_REQ21_MASK		(~0x00000C00UL)
+#define SDMA_CREQSELECT_REQ20_MASK		(~0x00000300UL)
+#define SDMA_CREQSELECT_REQ19_MASK		(~0x000000C0UL)
+#define SDMA_CREQSELECT_REQ18_MASK		(~0x00000030UL)
+#define SDMA_CREQSELECT_REQ17_MASK		(~0x0000000CUL)
+#define SDMA_CREQSELECT_REQ16_MASK		(~0x00000003UL)
+
+#define SDMA_CREQSELECT_REQ31_ALWAYS31	0xC0000000UL
+#define SDMA_CREQSELECT_REQ30_ALWAYS30	0x30000000UL
+#define SDMA_CREQSELECT_REQ29_ALWAYS29	0x0C000000UL
+#define SDMA_CREQSELECT_REQ28_ALWAYS28	0x03000000UL
+#define SDMA_CREQSELECT_REQ27_ALWAYS27	0x00C00000UL
+#define SDMA_CREQSELECT_REQ26_ALWAYS26	0x00300000UL
+#define SDMA_CREQSELECT_REQ25_ALWAYS25	0x000C0000UL
+#define SDMA_CREQSELECT_REQ24_ALWAYS24	0x00030000UL
+#define SDMA_CREQSELECT_REQ23_ALWAYS23	0x0000C000UL
+#define SDMA_CREQSELECT_REQ22_ALWAYS22	0x00003000UL
+#define SDMA_CREQSELECT_REQ21_ALWAYS21	0x00000C00UL
+#define SDMA_CREQSELECT_REQ20_ALWAYS20	0x00000300UL
+#define SDMA_CREQSELECT_REQ19_ALWAYS19	0x000000C0UL
+#define SDMA_CREQSELECT_REQ18_ALWAYS18	0x00000030UL
+#define SDMA_CREQSELECT_REQ17_ALWAYS17	0x0000000CUL
+#define SDMA_CREQSELECT_REQ16_ALWAYS16	0x00000003UL
+
+#define SDMA_CREQSELECT_REQ31_SCTIMER7	0x00000000UL
+#define SDMA_CREQSELECT_REQ30_SCTIMER6	0x00000000UL
+#define SDMA_CREQSELECT_REQ29_SCTIMER5	0x00000000UL
+#define SDMA_CREQSELECT_REQ28_SCTIMER4	0x00000000UL
+#define SDMA_CREQSELECT_REQ27_SCTIMER3	0x00000000UL
+#define SDMA_CREQSELECT_REQ26_PSC6_TX	0x00000000UL
+#define SDMA_CREQSELECT_REQ25_PSC6_RX	0x00000000UL
+#define SDMA_CREQSELECT_REQ24_I2C1_TX	0x00000000UL
+#define SDMA_CREQSELECT_REQ23_I2C1_RX	0x00000000UL
+#define SDMA_CREQSELECT_REQ22_I2C2_TX	0x00000000UL
+#define SDMA_CREQSELECT_REQ21_I2C2_RX	0x00000000UL
+#define SDMA_CREQSELECT_REQ20_PSC4_TX	0x00000000UL
+#define SDMA_CREQSELECT_REQ19_PSC4_RX	0x00000000UL
+#define SDMA_CREQSELECT_REQ18_PSC5_TX	0x00000000UL
+#define SDMA_CREQSELECT_REQ17_PSC5_RX	0x00000000UL
+#define SDMA_CREQSELECT_REQ16_LP		0x00000000UL
+
+#define SDMA_CREQSELECT_ALWAYS30	0xC0000000UL
+
+#endif /* __MGT5200_SDMA_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h
new file mode 100644
index 0000000000..ff2aed1997
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/include/ppctypes.h
@@ -0,0 +1,43 @@
+#ifndef __PPCTYPES_H
+#define __PPCTYPES_H
+
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+typedef unsigned char		uint8;
+typedef unsigned short		uint16;
+typedef unsigned long		uint32;
+typedef unsigned long long	uint64;
+
+typedef signed char			sint8;
+typedef signed short		sint16;
+typedef signed long			sint32;
+typedef signed long long	sint64;
+
+typedef volatile unsigned char		reg8;
+typedef volatile unsigned short		reg16;
+typedef volatile unsigned long		reg32;
+typedef volatile unsigned long long	reg64;
+
+#endif	/* __PPCTYPES_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h
new file mode 100644
index 0000000000..dc529d6a22
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_api_mem.h
@@ -0,0 +1,67 @@
+#ifndef __TASK_API_BESTCOMM_API_MEM_H
+#define __TASK_API_BESTCOMM_API_MEM_H 1
+
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+#include "../include/mgt5200/mgt5200.h"
+
+/*
+ * An extern global variable is used here for the MBAR since it must
+ * be passed into the API for processes that use virtual memory.
+ */
+extern uint8 *MBarGlobal;
+
+#define SDMA_TASK_BAR      (MBarGlobal+MBAR_SDMA+0x000)
+#define SDMA_INT_PEND      (MBarGlobal+MBAR_SDMA+0x014)
+#define SDMA_INT_MASK      (MBarGlobal+MBAR_SDMA+0x018)
+#define SDMA_TCR           (MBarGlobal+MBAR_SDMA+0x01C)
+#define SDMA_TASK_SIZE     (MBarGlobal+MBAR_SDMA+0x060)
+
+#define PCI_TX_PKT_SIZE    (MBarGlobal+MBAR_SCPCI+0x000)
+#define PCI_TX_NTBIT       (MBarGlobal+MBAR_SCPCI+0x01C)
+#define PCI_TX_FIFO        (MBarGlobal+MBAR_SCPCI+0x040)
+#define PCI_TX_FIFO_STAT   (MBarGlobal+MBAR_SCPCI+0x045)
+#define PCI_TX_FIFO_GRAN   (MBarGlobal+MBAR_SCPCI+0x048)
+#define PCI_TX_FIFO_ALARM  (MBarGlobal+MBAR_SCPCI+0x04E)
+
+#define PCI_RX_PKT_SIZE    (MBarGlobal+MBAR_SCPCI+0x080)
+#define PCI_RX_NTBIT       (MBarGlobal+MBAR_SCPCI+0x09C)
+#define PCI_RX_FIFO        (MBarGlobal+MBAR_SCPCI+0x0C0)
+#define PCI_RX_FIFO_STAT   (MBarGlobal+MBAR_SCPCI+0x0C5)
+#define PCI_RX_FIFO_GRAN   (MBarGlobal+MBAR_SCPCI+0x0C8)
+#define PCI_RX_FIFO_ALARM  (MBarGlobal+MBAR_SCPCI+0x0CE)
+
+
+#define FEC_RX_FIFO        (MBarGlobal+MBAR_ETHERNET+0x184)
+#define FEC_RX_FIFO_STAT   (MBarGlobal+MBAR_ETHERNET+0x188)
+#define FEC_RX_FIFO_GRAN   (MBarGlobal+MBAR_ETHERNET+0x18C)
+#define FEC_RX_FIFO_ALARM  (MBarGlobal+MBAR_ETHERNET+0x198)
+
+#define FEC_TX_FIFO        (MBarGlobal+MBAR_ETHERNET+0x1A4)
+#define FEC_TX_FIFO_STAT   (MBarGlobal+MBAR_ETHERNET+0x1A8)
+#define FEC_TX_FIFO_GRAN   (MBarGlobal+MBAR_ETHERNET+0x1AC)
+#define FEC_TX_FIFO_ALARM  (MBarGlobal+MBAR_ETHERNET+0x1B8)
+
+#endif	/* __TASK_API_BESTCOMM_API_MEM_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h
new file mode 100644
index 0000000000..3712bae3d0
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/bestcomm_cntrl.h
@@ -0,0 +1,282 @@
+#ifndef __TASK_API_BESTCOMM_CNTRL_H
+#define __TASK_API_BESTCOMM_CNTRL_H 1
+
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+/*******************************************************************************
+ * Defines to control SmartDMA and its tasks. These defines are used for the
+ * task build process to minimize disconnects at the task/driver interface.
+ ******************************************************************************/
+
+#define SDMA_INT_BIT_DBG             31          /* debug interrupt bit        */
+#define SDMA_INT_BIT_TEA             28          /* TEA interrupt bit          */
+#define SDMA_INT_BIT_TEA_TASK        24          /* lsb for TEA task number    */
+#define SDMA_INT_BIT_IMPL            0x9000FFFF
+
+#define SDMA_PTDCTRL_BIT_TEA         14          /* TEA detection enable bit   */
+
+#define SDMA_TCR_BIT_AUTO            15          /* auto start bit             */
+#define SDMA_TCR_BIT_HOLD             5          /* hold initiator bit         */
+
+#define SDMA_STAT_BIT_ALARM          17
+#define SDMA_FIFO_ALARM_MASK         0x0020000
+
+#define SDMA_DRD_BIT_TFD             27   /* mark last buffer of frame         */
+#define SDMA_DRD_BIT_INT             26   /* interrupt after buffer processed  */
+#define SDMA_DRD_BIT_INIT            21   /* lsb position of initiator         */
+#define SDMA_DRD_MASK_FLAGS          0x0C000000  /* BD_FLAGS flag bits            */
+#define SDMA_DRD_MASK_LENGTH         0x03FFFFFF  /* BD_FLAGS length mask          */
+#define SDMA_BD_BIT_READY            30          /* Status BD ready bit           */
+#ifdef SAS_COMPILE
+ #define SDMA_BD_MASK_READY          constant(1<<SDMA_BD_BIT_READY)
+#else
+ #define SDMA_BD_MASK_READY          (1<<SDMA_BD_BIT_READY)
+#endif
+#define SDMA_BD_MASK_SIGN            0x7FFFFFFF  /* task code needs Status>0      */
+
+#define SDMA_PRAGMA_BIT_RSV          7  /* reserved pragma bit                    */
+#define SDMA_PRAGMA_BIT_PRECISE_INC  6  /* increment 0=when possible, 1=iter end  */
+#define SDMA_PRAGMA_BIT_RST_ERROR_NO 5  /* don't reset errors on task enable      */
+#define SDMA_PRAGMA_BIT_PACK         4  /* pack data enable                       */
+#define SDMA_PRAGMA_BIT_INTEGER      3  /* data alignment 0=frac(msb), 1=int(lsb) */
+#define SDMA_PRAGMA_BIT_SPECREAD     2  /* XLB speculative read enable            */
+#define SDMA_PRAGMA_BIT_CW           1  /* write line buffer enable               */
+#define SDMA_PRAGMA_BIT_RL           0  /* read line buffer enable                */
+
+#define SDMA_TASK_ENTRY_BYTES       32  /* Bytes per task in entry table  */
+#define SDMA_TASK_GROUP_NUM         16  /* Number of tasks per task group */
+#define SDMA_TASK_GROUP_BYTES       (SDMA_TASK_ENTRY_BYTES*SDMA_TASK_GROUP_NUM)
+
+
+/*******************************************************************************
+ * Task group control macros, use when TaskNum > 15
+ ******************************************************************************/
+#define SDMA_TASKNUM_EXT(OldTaskNum) (OldTaskNum%16)
+
+#define SDMA_TASKBAR_CHANGE(sdma, OldTaskNum) {	\
+	sdma->taskBar += (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \
+}
+
+#define SDMA_TASKBAR_RESTORE(sdma, OldTaskNum) {	\
+	sdma->taskBar -= (((int)(OldTaskNum/SDMA_TASK_GROUP_NUM))*SDMA_TASK_GROUP_BYTES); \
+}
+
+
+/*******************************************************************************
+ * Task control macros
+ ******************************************************************************/
+#define SDMA_TASK_CFG(RegAddr, TaskNum, AutoStart, AutoStartNum) { \
+	*(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)(0x0000     |  \
+									 ((AutoStart!=0)<<7) |  \
+									 (AutoStartNum&0xF)  ); \
+}
+
+#define SDMA_TASK_AUTO_START(RegAddr, TaskNum, AutoStart, AutoStartNum) { \
+	*(((volatile uint16 *)RegAddr)+TaskNum) = (uint16)((*(((volatile uint16 *)RegAddr)+TaskNum) & \
+									 (uint16) 0xff30) | ((uint16)(0x0000 |  \
+									 ((AutoStart!=0)<<7) |  \
+									 (AutoStartNum&0xF))  )); \
+}
+
+#define SDMA_TASK_ENABLE(RegAddr, TaskNum) {	\
+	*(((volatile uint16 *)RegAddr)+TaskNum) |=  (uint16)0x8000; \
+}
+
+#define SDMA_TASK_DISABLE(RegAddr, TaskNum) {	\
+	*(((volatile uint16 *)RegAddr)+TaskNum) &= ~(uint16)0x8000; \
+}
+
+#define SDMA_TASK_STATUS(RegAddr, TaskNum)	\
+	*(((volatile uint16 *)RegAddr)+TaskNum)
+
+
+/*******************************************************************************
+ * Interrupt control macros
+ ******************************************************************************/
+#define SDMA_INT_ENABLE(RegAddr, Bit) \
+  do { \
+    rtems_interrupt_level level; \
+    rtems_interrupt_disable(level); \
+    *((volatile uint32 *) RegAddr) &= ~((uint32) (1 << Bit)); \
+    rtems_interrupt_enable(level); \
+  } while (0)
+
+#define SDMA_INT_DISABLE(RegAddr, Bit) \
+  do { \
+    rtems_interrupt_level level; \
+    rtems_interrupt_disable(level); \
+    *((volatile uint32 *) (RegAddr)) |= ((uint32)(1 << Bit)); \
+    rtems_interrupt_enable(level); \
+  } while (0)
+
+#define SDMA_INT_SOURCE(RegPend, RegMask)	\
+	(*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask))) & (uint32)SDMA_INT_BIT_IMPL)
+
+#define SDMA_INT_PENDING(RegPend, RegMask)	\
+	(*((volatile uint32 *)(RegPend)) & (~*((volatile uint32 *)(RegMask))))
+
+#define SDMA_INT_TEST(IntSource, Bit)	\
+	(((uint32)IntSource) & ((uint32)(1<<Bit)))
+
+/*
+ * define SDMA_INT_FIND to get int bit rather than scan all bits use
+ * cntlzw
+ */
+
+/* Clear the IntPend bit */
+#define SDMA_CLEAR_IEVENT(RegAddr, Bit) {	\
+	*((volatile uint32 *)RegAddr) = ((uint32)(1<<Bit)); \
+}
+
+#define SDMA_GET_PENDINGBIT(sdma, Bit)	\
+	(sdma->IntPend & (uint32)(1<<Bit))
+
+#define SDMA_GET_MASKBIT(sdma, Bit)	\
+	(sdma->IntMask & (uint32)(1<<Bit))
+
+
+/*******************************************************************************
+ * SmartDMA FIFO control macros
+ ******************************************************************************/
+
+/*******************************************************************************
+ * SmartDMA TEA detection control macros
+ ******************************************************************************/
+/* Enable SmartDMA TEA detection and TEA interrupt */
+#define SDMA_TEA_ENABLE(sdma) {								\
+	SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_TEA);				\
+	sdma->PtdCntrl &= ~((uint32)(1<<SDMA_PTDCTRL_BIT_TEA));	\
+}
+
+/* Disable SmartDMA TEA detection and TEA interrupt */
+#define SDMA_TEA_DISABLE(sdma) {							\
+	SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_TEA);				\
+	sdma->PtdCntrl |=  ((uint32)(1<<SDMA_PTDCTRL_BIT_TEA));	\
+}
+
+/* Clear the TEA interrupt */
+#define SDMA_TEA_CLEAR(sdma) {									\
+	sdma->IntPend =  ((uint32)(0x1F<<SDMA_INT_BIT_TEA_TASK));	\
+}
+
+/* Determine which task caused a TEA on the XLB */
+#define SDMA_TEA_SOURCE(RegPend)	\
+	(uint32)(((*(volatile uint32 *)RegPend)>>SDMA_INT_BIT_TEA_TASK) & 0xF)
+
+
+/*******************************************************************************
+ * SmartDMA debug control macros
+ ******************************************************************************/
+/* Enable the SmartDMA debug unit and DBG interrupt */
+/* add sdma->dbg_regs setup? */
+#define SDMA_DBG_ENABLE(sdma) {					\
+	SDMA_INT_ENABLE(sdma, SDMA_INT_BIT_DBG);	\
+}
+
+#define SDMA_DBG_DISABLE(sdma) {				\
+	SDMA_INT_DISABLE(sdma, SDMA_INT_BIT_DBG);	\
+}
+
+/* Clear the debug interrupt */
+#define SDMA_DBG_CLEAR(sdma) {					\
+	SDMA_CLEAR_IEVENT(sdma, SDMA_INT_BIT_DBG);	\
+}
+
+#define SDMA_DBG_MDE(dst, sdma, addr) {	\
+	sdma->MDEDebug = addr;				\
+	dst = sdma->MDEDebug;				\
+}
+
+#define SDMA_DBG_ADS(dst, sdma, addr) {	\
+	sdma->ADSDebug = addr;				\
+	dst = sdma->ADSDebug;				\
+}
+
+#define SDMA_DBG_PTD(dst, sdma, addr) {	\
+	sdma->PTDDebug = addr;				\
+	dst = sdma->PTDDebug;				\
+}
+
+
+/*******************************************************************************
+ * Initiator control macros
+ ******************************************************************************/
+
+/* This macro may not work, getting compile errors */
+/* Set the Transfer Size */
+/* Note that masking the size w/ 0x3 gives the desired value for uint32 */
+/*    (expressed as 4), namely 0. */
+#define SDMA_SET_SIZE(RegAddr, TaskNum, SrcSize, DstSize)			\
+	*(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) =					\
+	(uint8)((*(((volatile uint8 *)RegAddr)+((uint32)(TaskNum/2))) &			\
+			((TaskNum%2) ? 0xf0 : 0x0f)) |							\
+	((uint8)(((SrcSize & 0x3)<<2) |									\
+			( DstSize & 0x3 ) ) <<(4*((int)(1-(TaskNum%2))))));
+
+/* This macro may not work */
+/* Set the Initiator in TCR */
+#define SDMA_SET_INIT(RegAddr, TaskNum, Initiator)					\
+{																	\
+	*(((volatile uint16 *)RegAddr)+TaskNum) &= (uint16)0xE0FF;				\
+	*(((volatile uint16 *)RegAddr)+TaskNum) |= (((0x01F & Initiator)<<8) |	\
+									  (0<<SDMA_TCR_BIT_HOLD));		\
+}
+
+/* Change DRD initiator number */
+#define SDMA_INIT_CHANGE(task, oldInitiator, newInitiator) {		\
+	int i;															\
+	for (i=0; i<task->NumDRD; i++) {								\
+		if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) {	\
+			SDMA_INIT_WRITE(task->DRD[i],newInitiator);				\
+		}															\
+	}																\
+}
+
+/* Set the Initiator Priority */
+#define SDMA_SET_INITIATOR_PRIORITY(sdma, initiator, priority)	\
+	*(((volatile uint8 *)&sdma->IPR0)+initiator) = priority;
+
+
+/* Read DRD initiator number */
+#define SDMA_INIT_READ(PtrDRD)	\
+	(((*(volatile uint32 *)PtrDRD)>>SDMA_DRD_BIT_INIT) & (uint32)0x1F)
+
+/* Write DRD initiator number */
+#define SDMA_INIT_WRITE(PtrDRD, Initiator) {					\
+	*(volatile uint32 *)PtrDRD = ((*(volatile uint32 *)PtrDRD) & 0xFC1FFFFF) |	\
+						(Initiator<<SDMA_DRD_BIT_INIT);			\
+}
+
+/* Change DRD initiator number */
+#define SDMA_INIT_CHANGE(task, oldInitiator, newInitiator) {		\
+	int i;															\
+	for (i=0; i<task->NumDRD; i++) {								\
+		if (SDMA_INIT_READ(task->DRD[i]) == (uint32)oldInitiator) {	\
+			SDMA_INIT_WRITE(task->DRD[i],newInitiator);				\
+		}															\
+	}																\
+}
+
+#endif	/* __TASK_API_BESTCOMM_CNTRL_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h
new file mode 100644
index 0000000000..7f261d21ee
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_bdtable.h
@@ -0,0 +1,86 @@
+#ifndef __TASK_API_TASKSETUP_BDTABLE_H
+#define __TASK_API_TASKSETUP_BDTABLE_H 1
+
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+/*
+ * Table of BD rings for all BestComm tasks indexed by task ID.
+ *
+ *    +-----+------+--------------+    +------+-------+
+ * 0: |numBD|numPtr|BDTablePtr ---|--->|status|dataPtr|
+ *    +-----+------+--------------+    +------+-------+
+ * 1: |numBD|numPtr|BDTablePtr    |    |status|dataPtr|
+ *    +-----+------+--------------+    .      .       .
+ * 2: |numBD|numPtr|BDTablePtr ---|-+  .      .       .
+ *    .            .              . |  .      .       .
+ *    .            .              . |  |status|dataPtr|
+ *    .            .              . |  +------+-------+
+ * 15:|numBD|numPtr|BDTablePtr    | |
+ *    +-----+------+--------------+ |
+ *                                  |
+ *                                  V
+ *                                  +------+--------+--------+
+ *                                  |status|dataPtr0|dataPtr1|
+ *                                  +------+--------+--------+
+ *                                  |status|dataPtr0|dataPtr1|
+ *                                  .      .        .        .
+ *                                  .      .        .        .
+ *                                  .      .        .        .
+ *                                  |status|dataPtr0|dataPtr1|
+ *                                  +------+--------+--------+
+ */
+typedef struct {
+	uint16 numBD;		/* Size of BD ring									*/
+	uint8  numPtr;		/* Number of data buffer pointers per BD			*/
+	uint8  apiConfig;	/* API configuration flags							*/
+	void   *BDTablePtr;	/* Pointer to BD tables, must be cast to TaskBD1_t	*/
+						/*   or TaskBD2_t									*/
+	volatile uint32
+		   *BDStartPtr;	/* Task's current BD pointer. This pointer is
+						 * used to set a task's BD pointer upon startup.
+						 * It is only valid for BD tasks and only after
+						 * TaskSetup() or TaskBDReset() are called. You
+						 * cannot use this to track a task's BD pointer.
+						 */
+	uint16 currBDInUse; /* Current number of buffer descriptors assigned but*/
+						/*   not released yet.                              */
+} TaskBDIdxTable_t;
+
+typedef enum {
+	API_CONFIG_NONE		= 0x00,
+	API_CONFIG_BD_FLAG	= 0x01
+} ApiConfig_t;
+
+/*
+ * Allocates BD table if needed and updates the BD index table.
+ * Do we want to hide this from the C API since it operates on task API?
+ */
+void TaskSetup_BDTable(volatile uint32 *BasePtr,
+                       volatile uint32 *LastPtr,
+                       volatile uint32 *StartPtr,
+                       int TaskNum, uint32 NumBD, uint16 MaxBD,
+                       uint8 NumPtr, ApiConfig_t ApiConfig, uint32 Status );
+
+#endif	/* __TASK_API_TASKSETUP_BDTABLE_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h
new file mode 100644
index 0000000000..be7bb9d7b0
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm/task_api/tasksetup_general.h
@@ -0,0 +1,624 @@
+/******************************************************************************
+*
+* Copyright (c) 2004 Freescale Semiconductor, Inc.
+*
+* Permission is hereby granted, free of charge, to any person obtaining a
+* copy of this software and associated documentation files (the "Software"),
+* to deal in the Software without restriction, including without limitation
+* the rights to use, copy, modify, merge, publish, distribute, sublicense,
+* and/or sell copies of the Software, and to permit persons to whom the
+* Software is furnished to do so, subject to the following conditions:
+*
+* The above copyright notice and this permission notice shall be included
+* in all copies or substantial portions of the Software.
+*
+* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
+* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
+* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+* OTHER DEALINGS IN THE SOFTWARE.
+*
+******************************************************************************/
+
+/*
+ * Task builder generates a set #defines per configured task to
+ * condition this templete file.
+ */
+
+/**********************************************************
+ *
+ * Required #defines:
+ * ------------------
+ * TASKSETUP_NAME:
+ *   TaskSetup function name, set to TaskSetup_<TASK_NAME>
+ * TASK_API:
+ *   task API defined in dma_image.h
+ * MAX_BD:
+ *   <=0 : non-BD task
+ *   else: number of BD in BD table
+ * BD_FLAG:
+ *   0   : no flag implemented for BD
+ *   else: flags can be passed on a per BD basis
+ * MISALIGNED:
+ *   0   : task API supports Bytes%IncrBytes==0
+ *   else: task API supports any parameter settings
+ * AUTO_START:
+ *   <-1       : do not start a task after task completion
+ *   -1        : auto start the task after task completion
+ *   <MAX_TASKS: auto start task with the TaskID = AUTO_START
+ *    else     : do not start a task after task completion
+ * INITIATOR_DATA:
+ *   <0  : runtime configurable
+ *   else: assume INITATOR_DATA equal hard-coded task initiator
+ * TYPE_SRC: (needs to be consistent with Task API)
+ *   FLEX_T  : Task API TYPE_SRC = flex, SzSrc defines size
+ *   UINT8_T : Task API TYPE_SRC = char
+ *   UINT16_T: Task API TASK_SRC = short
+ *   UINT32_T: Task API TASK_SRC = int
+ * INCR_TYPE_SRC:
+ *   0   : FIFO address, do not implement data pointer
+ *   1   : automatic, set INCR_SRC based on SzSrc parameter
+ *   2   : runtime, set INCR_SRC to IncrSrc parameter
+ *   else: used hard-coded INCR_SRC
+ * INCR_SRC:
+ *   INCR_TYPE_SRC=0: force INCR_SRC=0
+ *   else           : use for src pointer increment
+ * TYPE_DST: (needs to be consistent with Task API)
+ *   FLEX_T  : Task API TYPE_DST = flex, SzDst defines size
+ *   UINT8_T : Task API TYPE_DST = char
+ *   UINT16_T: Task API TASK_DST = short
+ *   UINT32_T: Task API TASK_DST = int
+ * INCR_TYPE_DST:
+ *   0   : FIFO address, do not implement data pointer
+ *   1   : automatic, set INCR_DST based on SzDst parameter
+ *   2   : runtime, set INCR_DST to IncrDst parameter
+ *   else: used hard-coded INCR_DST
+ * INCR_DST:
+ *   INCR_TYPE_DST=0: force INCR_DST=0
+ *   else           : use for dst pointer increment
+ * PRECISE_INCREMENT:
+ *   0   : increment when possible
+ *   else: increment at end of iteration
+ * NO_ERROR_RESET:
+ *   0   : reset error flags on task enable
+ *   else: leave error flags unmodified on task enable
+ * PACK_DATA:
+ *   0   : do not pack data
+ *   else: pack data based on data type
+ * INTEGER_MODE:
+ *   0   : type conversions handle as fixed point numbers
+ *   else: type conversions handle as integers
+ * WRITE_LINE_BUFFER:
+ *   0   : do not use write line buffers
+ *   else: enable write line buffers
+ * READ_LINE_BUFFER:
+ *   0   : do not use read line buffers
+ *   else: enable read line buffers
+ * SPEC_READS:
+ *   0   : do not speculatively read
+ *   else: speculatively read data ahead of DMA engine
+ *
+ * Optional #defines:
+ * ------------------
+ * MAX_TASKS:
+ *   1   : #define MAX_TASKS>0
+ *   else: 16
+ * ITERATIONS:
+ *   1   : #define ITERATIONS>0
+ *   else: 1
+ * INCR_BYTES:
+ *   This macro is defined based on following priority:
+ *   1   : INCR_SRC != 0
+ *   2   : DST_TYPE != 0
+ *   3   : #defined INCR_BYTES<0
+ *   else: -4 (SZ_UINT32)
+ * DEBUG_BESTCOMM_API:
+ *   >0  : print basic debug messages
+ *   >=10: also print C-API interface variables
+ *   >=20: also print task API interface variables
+ *   else: do nothing
+ *
+ **********************************************************/
+
+#if defined(__rtems__) || defined(MPC5200_BAPI_LIBC_HEADERS)
+#include <stdlib.h>
+#endif
+
+#include "../dma_image.h"
+
+#include "../bestcomm_api.h"
+#include "tasksetup_bdtable.h"
+
+#include "bestcomm_api_mem.h"
+#include "bestcomm_cntrl.h"
+
+#ifndef  DEBUG_BESTCOMM_API
+ #define DEBUG_BESTCOMM_API 0
+#endif
+
+#ifdef FLEX_T
+ #undef FLEX_T
+#endif
+#define FLEX_T SZ_FLEX
+
+#ifdef UINT8_T
+ #undef UINT8_T
+#endif
+#define UINT8_T SZ_UINT8
+
+#ifdef UINT16_T
+ #undef UINT16_T
+#endif
+#define UINT16_T SZ_UINT16
+
+#ifdef UINT32_T
+ #undef UINT32_T
+#endif
+#define UINT32_T SZ_UINT32
+
+#if (INCR_TYPE_SRC==0)   /* FIFO address, no data pointer */
+ #undef  INCR_SRC
+ #define INCR_SRC     0
+#endif
+
+#if (INCR_TYPE_DST==0)   /* FIFO address, no data pointer */
+ #undef  INCR_DST
+ #define INCR_DST     0
+#endif
+
+#ifndef  MAX_TASKS
+ #define MAX_TASKS   16
+#else
+ #if (MAX_TASKS<=0)
+  #undef  MAX_TASKS
+  #define MAX_TASKS  16
+ #endif
+#endif
+
+#ifndef  ITERATIONS
+ #define ITERATIONS   1
+#else
+ #if (ITERATIONS<=0)
+  #undef  ITERATIONS
+  #define ITERATIONS  1
+ #endif
+#endif
+
+#ifndef   INCR_BYTES
+  #define INCR_BYTES -4
+#else
+ #if (INCR_BYTES>=0)
+  #undef  INCR_BYTES
+  #define INCR_BYTES -4
+ #endif
+#endif
+
+/*
+ * These ifndefs will go away when support in task_capi wrappers
+ * in the image directories
+ */
+#ifndef  PRECISE_INCREMENT
+ #define PRECISE_INCREMENT 0  /* bit=6 SAS->1, increment 0=when possible, 1=at the end of interation */
+#endif
+#ifndef  NO_ERROR_RESET
+ #define NO_ERROR_RESET    0  /* bit=5 SAS->0, do not reset error codes on task enable               */
+#endif
+#ifndef  PACK_DATA
+ #define PACK_DATA         0  /* bit=4 SAS->0, pack data enable                                      */
+#endif
+#ifndef  INTEGER_MODE
+ #define INTEGER_MODE      0  /* bit=3 SAS->0, 0=fractional(msb aligned), 1=integer(lsb aligned)     */
+#endif
+#ifndef  SPEC_READS
+ #define SPEC_READS        1  /* bit=2 SAS->0, XLB speculative read enable                           */
+#endif
+#ifndef  WRITE_LINE_BUFFER
+ #define WRITE_LINE_BUFFER 1  /* bit=1 SAS->0, write line buffer enable                              */
+#endif
+#ifndef  READ_LINE_BUFFER
+ #define READ_LINE_BUFFER  1  /* bit=0 SAS->0, read line buffer enable                               */
+#endif
+#define  SDMA_PRAGMA (0                <<SDMA_PRAGMA_BIT_RSV         ) | \
+                     (PRECISE_INCREMENT<<SDMA_PRAGMA_BIT_PRECISE_INC ) | \
+                     (NO_ERROR_RESET   <<SDMA_PRAGMA_BIT_RST_ERROR_NO) | \
+                     (PACK_DATA        <<SDMA_PRAGMA_BIT_PACK        ) | \
+                     (INTEGER_MODE     <<SDMA_PRAGMA_BIT_INTEGER     ) | \
+                     (SPEC_READS       <<SDMA_PRAGMA_BIT_SPECREAD    ) | \
+                     (WRITE_LINE_BUFFER<<SDMA_PRAGMA_BIT_CW          ) | \
+                     (READ_LINE_BUFFER <<SDMA_PRAGMA_BIT_RL          )
+
+#ifndef  TASKSETUP_NAME
+ #define PREPEND_TASKSETUP(name) TaskSetup_ ## name
+ #define FUNC_PREPEND_TASKSETUP(name) PREPEND_TASKSETUP(name)
+ #define TASKSETUP_NAME FUNC_PREPEND_TASKSETUP(TASK_BASE)
+#endif
+
+#ifndef  TASK_API
+ #define APPEND_API(name) name ## _api_t
+ #define FUNC_APPEND_API(name) APPEND_API(name)
+ #define TASK_API FUNC_APPEND_API(TASK_BASE)
+#endif
+
+#ifndef  INIT_DMA_IMAGE
+ #define PREPEND_INITDMA(name) init_dma_image_ ## name
+ #define FUNC_PREPEND_INITDMA(name) PREPEND_INITDMA(name)
+ #define INIT_DMA_IMAGE FUNC_PREPEND_INITDMA(TASK_BASE)
+#endif
+
+#define DRD_INIT_MASK	0xfc1fffff
+#define DRD_EXT_FLAG	0x40000000
+#define DRD_INIT_OFFSET	21
+
+TaskId TASKSETUP_NAME(TASK_API            *TaskAPI,
+                      TaskSetupParamSet_t *TaskSetupParams)
+{
+	TaskId TaskNum;
+#if ((MAX_BD>0)||(DEBUG_BESTCOMM_API>0))
+	uint32 Status = 0;
+#endif
+#if ((MAX_BD>0)&&((INCR_TYPE_SRC!=0)||(INCR_TYPE_DST!=0))||(DEBUG_BESTCOMM_API>0))
+	uint8  NumPtr = 0;
+#endif
+#if (INITIATOR_DATA<0)	/* runtime configurable */
+	uint32 i, ext;
+#endif
+
+	INIT_DMA_IMAGE((uint8 *)(((sdma_regs *)(SDMA_TASK_BAR))->taskBar), MBarPhysOffsetGlobal);
+
+	TaskNum = (TaskId)SDMA_TASKNUM_EXT(TaskAPI->TaskNum);
+
+	TaskRunning[TaskNum] = 0;
+
+#if (DEBUG_BESTCOMM_API>0)
+	printf("\nBestComm API Debug Display Mode Enabled\n\n");
+	printf("TaskSetup: TaskID=%d\n", TaskNum);
+	if (Status!=0) {
+		printf("TaskSetup: Rx task\n");
+	} else {
+		printf("TaskSetup: Tx or DP task\n");
+	}
+#endif
+
+	/* Set the task pragma settings */
+	*(TaskAPI->TaskPragma)= (uint8) SDMA_PRAGMA;
+
+#if (MAX_BD>0)	/* Buffer Descriptors */
+
+ #if (INCR_TYPE_SRC!=0)
+	++NumPtr;
+ #endif
+ #if (INCR_TYPE_DST!=0)
+	++NumPtr;
+ #endif
+
+ #if (DEBUG_BESTCOMM_API>0)
+	printf("TaskSetup: Using %d buffer descriptors, each with %d data pointers\n", MAX_BD, NumPtr);
+ #endif
+
+	/* Allocate BD table SRAM storage,
+	 * and pass addresses to task API */
+
+	TaskSetup_BDTable(TaskAPI->BDTableBase,
+					  TaskAPI->BDTableLast,
+					  TaskAPI->BDTableStart,
+					  TaskNum,
+					  TaskSetupParams->NumBD,
+					  MAX_BD, NumPtr,
+					  BD_FLAG, Status);
+
+	*TaskAPI->AddrEnable = (uint32)((uint32)(((uint16 *)SDMA_TCR)+TaskNum) + MBarPhysOffsetGlobal);
+
+ #if BD_FLAG
+
+  #if (DEBUG_BESTCOMM_API>0)
+	printf("TaskSetup: Buffer descriptor flags are enabled\n");
+  #endif
+
+	/* always assume 2nd to last DRD */
+	*((TaskAPI->AddrDRD)) = (uint32)((uint32)TaskAPI->DRD[TaskAPI->AddrDRDIdx] + MBarPhysOffsetGlobal);
+ #endif /* #if BD_FLAG */
+
+#else	/* No Buffer Descriptors */
+
+/* #error ATA should not be non-BD */
+
+  #if (DEBUG_BESTCOMM_API>0)
+	printf("TaskSetup: Task will complete %d iterations before disabling\n");
+  #endif
+
+	*((TaskAPI->IterExtra)) = (uint32)(ITERATIONS-1);
+#endif	/* #if (MAX_BD>0) */
+
+/* Setup auto start */
+#if (AUTO_START <= -2 )	/* do not start a task */
+ #if (DEBUG_BESTCOMM_API>0)
+	printf("TaskSetup: Auto task start disabled\n");
+ #endif
+	SDMA_TASK_CFG(SDMA_TCR, TaskNum, 0, TaskNum);
+#elif (AUTO_START <= -1 )	/* restart task */
+ #if (DEBUG_BESTCOMM_API>0)
+	printf("TaskSetup: Auto start task\n");
+ #endif
+	SDMA_TASK_CFG(SDMA_TCR, TaskNum, 1, TaskNum);
+#elif (AUTO_START < MAX_TASKS)	/* start specific task */
+ #if (DEBUG_BESTCOMM_API>0)
+	printf("TaskSetup: Auto start task with TaskID=%d\n", AUTO_START);
+ #endif
+	SDMA_TASK_CFG(SDMA_TCR, TaskNum, 1, AUTO_START);
+#else	/* do not start a task */
+ #if (DEBUG_BESTCOMM_API>0)
+	printf("TaskSetup: Auto task start disabled\n");
+ #endif
+	SDMA_TASK_CFG(SDMA_TCR, TaskNum, 0, TaskNum);
+#endif
+
+#if (INITIATOR_DATA<0)	/* runtime configurable */
+	SDMA_SET_INIT(SDMA_TCR, TaskNum, TaskSetupParams->Initiator);
+
+	/*
+     * Hard-code the task initiator in the DRD to avoid a problem w/ the
+     * hold initiator bit in the TCR.
+	 */
+	ext = 0;
+	for (i = 0; i < TaskAPI->NumDRD; i++) {
+		if (ext == 0)
+		{
+#if (DEBUG_BESTCOMM_API>=10)
+				printf("TaskSetup: DRD[%d] initiator = %d\n", i, ((*(TaskAPI->DRD[i]) & ~DRD_INIT_MASK) >> DRD_INIT_OFFSET));
+#endif
+			if (((*(TaskAPI->DRD[i]) & ~DRD_INIT_MASK) >> DRD_INIT_OFFSET) != INITIATOR_ALWAYS) {
+#if (DEBUG_BESTCOMM_API>=10)
+				printf("TaskSetup: Replacing DRD[%d] initiator with %d\n", i, TaskSetupParams->Initiator);
+#endif
+				*(TaskAPI->DRD[i]) = (*(TaskAPI->DRD[i]) & DRD_INIT_MASK)
+							| (TaskSetupParams->Initiator << DRD_INIT_OFFSET);
+			}
+
+			if ((*(TaskAPI->DRD[i]) & DRD_EXT_FLAG) != 0)
+			{
+				ext = 1;
+			}
+		}
+		else
+		{
+			if ((*(TaskAPI->DRD[i]) & DRD_EXT_FLAG) == 0)
+			{
+				ext = 0;
+			}
+		}
+	}
+
+#else	/* INITIATOR_DATA >= 0 */
+	TaskSetupParams->Initiator = INITIATOR_DATA;
+#endif
+
+#if (DEBUG_BESTCOMM_API>=10)
+	printf("\nTaskSetup: C-API Parameter Settings Passed to TaskSetup:\n");
+	printf("TaskSetup: NumBD        = %d\n", TaskSetupParams->NumBD);
+ #if (MAX_BD>0)
+	printf("TaskSetup: MaxBuf       = %d\n", TaskSetupParams->Size.MaxBuf);
+ #else
+	printf("TaskSetup: NumBytes     = %d\n", TaskSetupParams->Size.NumBytes);
+ #endif
+	printf("TaskSetup: Initiator    = %d\n", TaskSetupParams->Initiator);
+	printf("TaskSetup: StartAddrSrc = 0x%08X\n", TaskSetupParams->StartAddrSrc);
+	printf("TaskSetup: IncrSrc      = %d\n", TaskSetupParams->IncrSrc);
+	printf("TaskSetup: SzSrc        = %d\n", TaskSetupParams->SzSrc);
+	printf("TaskSetup: StartAddrDst = 0x%08X\n", TaskSetupParams->StartAddrDst);
+	printf("TaskSetup: IncrDst      = %d\n", TaskSetupParams->IncrDst);
+	printf("TaskSetup: SzDst        = %d\n", TaskSetupParams->SzDst);
+#endif
+
+#if (DEBUG_BESTCOMM_API>=20)
+	printf("\nTaskSetup: Task-API Parameter Settings Before TaskSetup Initialization:\n");
+	printf("TaskSetup: TaskNum      = %d\n", (TaskAPI->TaskNum));
+	printf("TaskSetup: TaskPragma   = 0x%02X\n", *((TaskAPI->TaskPragma)));
+	printf("TaskSetup: TCR          = 0x%04x\n", SDMA_TASK_STATUS(SDMA_TCR, TaskNum));
+
+ #if (MAX_BD>0)
+	printf("TaskSetup: BDTableBase  = 0x%08X\n", *((TaskAPI->BDTableBase)));
+	printf("TaskSetup: BDTableLast  = 0x%08X\n", *((TaskAPI->BDTableLast)));
+	printf("TaskSetup: BDTableStart = 0x%08X\n", *((TaskAPI->BDTableStart)));
+	printf("TaskSetup: AddrEnable   = 0x%08X\n", *((TaskAPI->AddrEnable)));
+  #if (INCR_TYPE_SRC==0)
+	printf("TaskSetup: AddrSrcFIFO  = 0x%08X\n", *((TaskAPI->AddrSrcFIFO)));
+  #endif
+  #if (INCR_TYPE_DST==0)
+	printf("TaskSetup: AddrDstFIFO  = 0x%08X\n", *((TaskAPI->AddrDstFIFO)));
+  #endif
+  #if (BD_FLAG)
+	printf("TaskSetup: AddrDRD      = 0x%08X\n", *((TaskAPI->AddrDRD)));
+	printf("TaskSetup: AddrDRDIdx   = %d\n", ((TaskAPI->AddrDRDIdx)));
+  #endif
+ #else
+	printf("TaskSetup: IterExtra    = %d\n", *((TaskAPI->IterExtra)));
+  #if (INCR_TYPE_SRC==0)
+	printf("TaskSetup: AddrSrcFIFO  = 0x%08X\n", *((TaskAPI->AddrSrcFIFO)));
+  #else
+	printf("TaskSetup: StartAddrSrc = 0x%08X\n", *((TaskAPI->StartAddrSrc)));
+  #endif
+  #if (INCR_TYPE_DST==0)
+	printf("TaskSetup: AddrDstFIFO  = 0x%08X\n", *((TaskAPI->AddrDstFIFO)));
+  #else
+	printf("TaskSetup: StartAddrDst = 0x%08X\n", *((TaskAPI->StartAddrDst)));
+  #endif
+ #endif
+ #if (INCR_TYPE_SRC!=0)
+	printf("TaskSetup: IncrSrc      = 0x%04X\n", *((TaskAPI->IncrSrc)));
+  #if (MISALIGNED | MISALIGNED_START)
+	printf("TaskSetup: IncrSrcMA    = 0x%04X\n", *((TaskAPI->IncrSrcMA)));
+  #endif
+ #endif
+ #if (INCR_TYPE_DST!=0)
+	printf("TaskSetup: IncrDst      = 0x%04X\n", *((TaskAPI->IncrDst)));
+  #if (MISALIGNED | MISALIGNED_START)
+	printf("TaskSetup: IncrDstMA    = 0x%04X\n", *((TaskAPI->IncrDstMA)));
+  #endif
+ #endif
+	printf("TaskSetup: Bytes        = %d\n", *((TaskAPI->Bytes)));
+	printf("TaskSetup: IncrBytes    = %d\n", *((TaskAPI->IncrBytes)));
+#endif
+
+
+	*((TaskAPI->Bytes)) = (uint32)TaskSetupParams->Size.MaxBuf;
+
+
+#if (TYPE_SRC!=FLEX_T)	/* size fixed in task code */
+	TaskSetupParams->SzSrc = TYPE_SRC;
+#endif
+
+#if (INCR_TYPE_SRC==0)	/* no data pointer */
+	TaskSetupParams->IncrSrc = (sint16)0;
+	*((TaskAPI->AddrSrcFIFO)) = (uint32)TaskSetupParams->StartAddrSrc;
+#else
+
+ #if (INCR_TYPE_SRC==1)	/* automatic */
+	if (TaskSetupParams->IncrSrc!=0) {
+		TaskSetupParams->IncrSrc = (sint16)+TaskSetupParams->SzSrc;
+	} else {
+		TaskSetupParams->IncrSrc = (sint16)+TaskSetupParams->IncrSrc;
+	}
+ #elif (INCR_TYPE_SRC!=2)	/* hard-coded */
+	TaskSetupParams->IncrSrc = (sint16)INCR_SRC;
+ #endif
+ *((TaskAPI->IncrSrc)) = (sint16)TaskSetupParams->IncrSrc;
+
+ #if (MAX_BD>0)	/* pointer in BD Table */
+	/* pass back address of first BD */
+	TaskSetupParams->StartAddrSrc = (uint32)TaskGetBDRing(TaskNum);
+ #else
+	*((TaskAPI->StartAddrSrc)) = (uint32)TaskSetupParams->StartAddrSrc;
+ #endif
+
+ #if MISALIGNED | MISALIGNED_START
+	if (TaskSetupParams->IncrSrc < 0) {
+		*((TaskAPI->IncrSrcMA)) = (sint16)-1;
+	} else if (TaskSetupParams->IncrSrc > 0) {
+		*((TaskAPI->IncrSrcMA)) = (sint16)+1;
+	} else {
+		*((TaskAPI->IncrSrcMA)) = (sint16)0;
+	}
+ #endif
+#endif
+
+
+#if (TYPE_DST!=FLEX_T)	/* size fixed in task code */
+	TaskSetupParams->SzDst = TYPE_DST;
+#endif
+
+#if (INCR_TYPE_DST==0)	/* no data pointer */
+	TaskSetupParams->IncrDst = (sint16)0;
+	*((TaskAPI->AddrDstFIFO)) = (uint32)TaskSetupParams->StartAddrDst;
+#else
+ #if (INCR_TYPE_DST==1)	/* automatic */
+	if (TaskSetupParams->IncrDst!=0) {
+		TaskSetupParams->IncrDst = (sint16)+TaskSetupParams->SzDst;
+	} else {
+		TaskSetupParams->IncrDst = (sint16)+TaskSetupParams->IncrDst;
+	}
+ #elif (INCR_TYPE_DST!=2)	/* hard-coded */
+	TaskSetupParams->IncrDst = (sint16)INCR_DST;
+ #endif
+	*((TaskAPI->IncrDst)) = (sint16)TaskSetupParams->IncrDst;
+
+ #if (MAX_BD>0)
+	/* pass back address of first BD */
+	TaskSetupParams->StartAddrDst = (uint32)TaskGetBDRing(TaskNum);
+ #else
+	*((TaskAPI->StartAddrDst)) = (uint32)TaskSetupParams->StartAddrDst;
+ #endif
+
+ #if MISALIGNED | MISALIGNED_START
+	if (TaskSetupParams->IncrDst < 0) {
+		*((TaskAPI->IncrDstMA)) = (sint16)-1;
+	} else if (TaskSetupParams->IncrDst > 0) {
+		*((TaskAPI->IncrDstMA)) = (sint16)+1;
+	} else {
+		*((TaskAPI->IncrDstMA)) = (sint16)0;
+	}
+ #endif
+#endif
+
+/* always use macro, only affect code with #define TYPE_? flex */
+	SDMA_SET_SIZE(SDMA_TASK_SIZE, TaskNum, TaskSetupParams->SzSrc, TaskSetupParams->SzDst);
+
+
+	if (TaskSetupParams->IncrSrc != 0) {
+		*((TaskAPI->IncrBytes)) = (sint16)-abs(TaskSetupParams->IncrSrc);
+	} else if (TaskSetupParams->IncrDst != 0) {
+		*((TaskAPI->IncrBytes)) = (sint16)-abs(TaskSetupParams->IncrDst);
+	} else {
+		*((TaskAPI->IncrBytes)) = (sint16)-abs(INCR_BYTES);
+	}
+
+
+#if (DEBUG_BESTCOMM_API>=10)
+	printf("\nTaskSetup: C-API Parameter Settings Returned from TaskSetup:\n");
+	printf("TaskSetup: NumBD        = %d\n", TaskSetupParams->NumBD);
+ #if (MAX_BD>0)
+	printf("TaskSetup: MaxBuf       = %d\n", TaskSetupParams->Size.MaxBuf);
+ #else
+	printf("TaskSetup: NumBytes     = %d\n", TaskSetupParams->Size.NumBytes);
+ #endif
+	printf("TaskSetup: Initiator    = %d\n", TaskSetupParams->Initiator);
+	printf("TaskSetup: StartAddrSrc = 0x%08X\n", TaskSetupParams->StartAddrSrc);
+	printf("TaskSetup: IncrSrc      = %d\n", TaskSetupParams->IncrSrc);
+	printf("TaskSetup: SzSrc        = %d\n", TaskSetupParams->SzSrc);
+	printf("TaskSetup: StartAddrDst = 0x%08X\n", TaskSetupParams->StartAddrDst);
+	printf("TaskSetup: IncrDst      = %d\n", TaskSetupParams->IncrDst);
+	printf("TaskSetup: SzDst        = %d\n", TaskSetupParams->SzDst);
+#endif
+
+#if (DEBUG_BESTCOMM_API>=20)
+	printf("\nTaskSetup: Task-API Parameter Settings After TaskSetup Initialization:\n");
+	printf("TaskSetup: TaskNum      = %d\n", ((TaskAPI->TaskNum)));
+	printf("TaskSetup: TaskPragma   = 0x%02X\n", *((TaskAPI->TaskPragma)));
+
+ #if (MAX_BD>0)
+	printf("TaskSetup: BDTableBase  = 0x%08X\n", *((TaskAPI->BDTableBase)));
+	printf("TaskSetup: BDTableLast  = 0x%08X\n", *((TaskAPI->BDTableLast)));
+	printf("TaskSetup: BDTableStart = 0x%08X\n", *((TaskAPI->BDTableStart)));
+	printf("TaskSetup: AddrEnable   = 0x%08X\n", *((TaskAPI->AddrEnable)));
+  #if (INCR_TYPE_SRC==0)
+	printf("TaskSetup: AddrSrcFIFO  = 0x%08X\n", *((TaskAPI->AddrSrcFIFO)));
+  #endif
+  #if (INCR_TYPE_DST==0)
+	printf("TaskSetup: AddrDstFIFO  = 0x%08X\n", *((TaskAPI->AddrDstFIFO)));
+  #endif
+  #if (BD_FLAG)
+	printf("TaskSetup: AddrDRD      = 0x%08X\n", *((TaskAPI->AddrDRD)));
+	printf("TaskSetup: AddrDRDIdx   = %d\n", ((TaskAPI->AddrDRDIdx)));
+  #endif
+ #else
+	printf("TaskSetup: IterExtra    = %d\n", *((TaskAPI->IterExtra)));
+  #if (INCR_TYPE_SRC==0)
+	printf("TaskSetup: AddrSrcFIFO  = 0x%08X\n", *((TaskAPI->AddrSrcFIFO)));
+  #else
+	printf("TaskSetup: StartAddrSrc = 0x%08X\n", *((TaskAPI->StartAddrSrc)));
+  #endif
+  #if (INCR_TYPE_DST==0)
+	printf("TaskSetup: AddrDstFIFO  = 0x%08X\n", *((TaskAPI->AddrDstFIFO)));
+  #else
+	printf("TaskSetup: StartAddrDst = 0x%08X\n", *((TaskAPI->StartAddrDst)));
+  #endif
+ #endif
+ #if (INCR_TYPE_SRC!=0)
+	printf("TaskSetup: IncrSrc      = 0x%04X\n", *((TaskAPI->IncrSrc)));
+  #if (MISALIGNED | MISALIGNED_START)
+	printf("TaskSetup: IncrSrcMA    = 0x%04X\n", *((TaskAPI->IncrSrcMA)));
+  #endif
+ #endif
+ #if (INCR_TYPE_DST!=0)
+	printf("TaskSetup: IncrDst      = 0x%04X\n", *((TaskAPI->IncrDst)));
+  #if (MISALIGNED | MISALIGNED_START)
+	printf("TaskSetup: IncrDstMA    = 0x%04X\n", *((TaskAPI->IncrDstMA)));
+  #endif
+ #endif
+	printf("TaskSetup: Bytes        = %d\n", *((TaskAPI->Bytes)));
+	printf("TaskSetup: IncrBytes    = %d\n", *((TaskAPI->IncrBytes)));
+#endif
+
+	return TaskNum;
+}
diff --git a/bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h b/bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h
new file mode 100644
index 0000000000..2b74adf366
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/bestcomm_ops.h
@@ -0,0 +1,224 @@
+/*
+ * Copyright (c) 2010-2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef BESTCOMM_OPS_H
+#define BESTCOMM_OPS_H
+
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup BestCommOps BestComm Ops
+ *
+ * @ingroup BestComm
+ *
+ * @brief BestComm ops.
+ *
+ * @{
+ */
+
+#define VAR(i) (i)
+#define VAR_COUNT 24
+#define INC(i) (24 + (i))
+#define INC_COUNT 8
+#define IDX(i) (48 + (i))
+#define IDX_COUNT 8
+
+#define COND_ONCE 0
+#define COND_LT 1
+#define COND_GT 2
+#define COND_NE 3
+#define COND_EQ 4
+#define COND_LE 5
+#define COND_GE 6
+#define COND_FOREVER 7
+
+#define INC_INIT(cond, val) \
+  (BSP_FLD32(cond, 29, 31) \
+    | BSP_FLD32((int16_t) (val), 0, 15))
+
+#define TERM_FIRST 0
+#define TERM_SECOND 1
+#define TERM_INIT 2
+#define TERM_UNUSED 3
+
+#define DEREF 1
+
+#define LCD_TERM(val) BSP_FLD32(val, 13, 14)
+
+#define LCD(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) \
+  (BSP_BIT32(31) \
+    | BSP_FLD32(deref0, 29, 29) \
+    | BSP_FLD32(iniidx0, 23, 28) \
+    | BSP_FLD32(deref1, 21, 21) \
+    | BSP_FLD32(iniidx1, 15, 20) \
+    | LCD_TERM(term) \
+    | BSP_FLD32(termop, 6, 11) \
+    | BSP_FLD32(inc0, 3, 5) \
+    | BSP_FLD32(inc1, 0, 2))
+
+#define LCDEXT(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) \
+  (BSP_BIT32(30) \
+    | LCD(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1))
+
+#define LCDPLUS(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1) \
+  (BSP_BIT32(22) \
+    | LCD(deref0, iniidx0, deref1, iniidx1, term, termop, inc0, inc1))
+
+#define LCDINIT(val) \
+  (BSP_BIT32(31) \
+    | BSP_FLD32((val) >> 13, 15, 29) \
+    | LCD_TERM(TERM_INIT) \
+    | BSP_FLD32(val, 0, 12))
+
+#define MORE 0x4
+
+#define TFD 0x2
+
+#define INT 0x1
+
+#define DRD_FLAGS(val) BSP_FLD32(val, 26, 28)
+
+#define INIT_ALWAYS 0
+#define INIT_SCTMR_0 1
+#define INIT_SCTMR_1 2
+#define INIT_FEC_RX 3
+#define INIT_FEC_TX 4
+#define INIT_ATA_RX 5
+#define INIT_ATA_TX 6
+#define INIT_SCPCI_RX 7
+#define INIT_SCPCI_TX 8
+#define INIT_PSC3_RX 9
+#define INIT_PSC3_TX 10
+#define INIT_PSC2_RX 11
+#define INIT_PSC2_TX 12
+#define INIT_PSC1_RX 13
+#define INIT_PSC1_TX 14
+#define INIT_SCTMR_2 15
+#define INIT_SCLPC 16
+#define INIT_PSC5_RX 17
+#define INIT_PSC5_TX 18
+#define INIT_PSC4_RX 19
+#define INIT_PSC4_TX 20
+#define INIT_I2C2_RX 21
+#define INIT_I2C2_TX 22
+#define INIT_I2C1_RX 23
+#define INIT_I2C1_TX 24
+#define INIT_PSC6_RX 25
+#define INIT_PSC6_TX 26
+#define INIT_IRDA_RX 25
+#define INIT_IRDA_TX 26
+#define INIT_SCTMR_3 27
+#define INIT_SCTMR_4 28
+#define INIT_SCTMR_5 29
+#define INIT_SCTMR_6 30
+#define INIT_SCTMR_7 31
+
+#define DRD_INIT(val) BSP_FLD32(val, 21, 25)
+
+#define SZ_8 1
+#define SZ_16 2
+#define SZ_32 0
+#define SZ_DYN 3
+
+#define DRD_RS(val) BSP_FLD32(val, 19, 20)
+
+#define DRD_WS(val) BSP_FLD32(val, 17, 18)
+
+#define DEST_VAR(val) (val)
+#define DEST_IDX(val) (BSP_BIT32(5) | (val))
+#define DEST_DEREF_IDX(val) (BSP_BIT32(5) | BSP_BIT32(4) | (val))
+
+#define SRC_VAR(val) (val)
+#define SRC_INC(val) (BSP_BIT32(5) | (val))
+#define SRC_EU_RESULT (BSP_BIT32(5) | BSP_BIT32(4) | BSP_BIT32(1) | BSP_BIT32(0))
+#define SRC_DEREF_EU_RESULT (BSP_BIT32(6) | BSP_BIT32(4) | BSP_BIT32(1) | BSP_BIT32(0))
+#define SRC_IDX(val) (BSP_BIT32(6) | BSP_BIT32(5) | (val))
+#define SRC_DEREF_IDX(val) (BSP_BIT32(6) | BSP_BIT32(5) | BSP_BIT32(4) | (val))
+#define SRC_NONE (BSP_BIT32(5) | BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(2) | BSP_BIT32(1) | BSP_BIT32(0))
+
+#define DRD1A(flags, init, dest, ws, src, rs) \
+  (DRD_FLAGS(flags) \
+    | DRD_INIT(init) \
+    | DRD_RS(rs) \
+    | DRD_WS(ws) \
+    | BSP_FLD32(dest, 10, 15) \
+    | BSP_FLD32(src, 3, 9))
+
+#define DRD1AEURESULT(flags, init, dest, ws, rs) \
+  (DRD1A(flags, init, rs, ws, dest, SRC_EU_RESULT) \
+    | BSP_FLD32(1, 0, 3))
+
+#define FUNC_LOAD_ACC 0
+#define FUNC_UNLOAD_ACC 1
+#define FUNC_AND 2
+#define FUNC_OR 3
+#define FUNC_XOR 4
+#define FUNC_ANDN 5
+#define FUNC_NOT 6
+#define FUNC_ADD 7
+#define FUNC_SUB 8
+#define FUNC_LSH 9
+#define FUNC_RSH 10
+#define FUNC_CRC8 11
+#define FUNC_CRC16 12
+#define FUNC_CRC32 13
+#define FUNC_ENDIAN32 14
+#define FUNC_ENDIAN16 15
+
+#define DRD2A(flags, func) \
+  (BSP_BIT32(30) | BSP_BIT32(29) \
+    | DRD_FLAGS(flags) \
+    | BSP_FLD32(func, 0, 3))
+
+#define DRD2A5(flags, init, func, ws, rs) \
+  (DRD2A(flags, func) \
+    | DRD_RS(rs) \
+    | DRD_WS(ws) \
+    | DRD_INIT(init))
+
+#define OP_VAR(val) (val)
+#define OP_EU_RESULT (BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(1) | BSP_BIT32(0))
+#define OP_NONE (BSP_BIT32(4) | BSP_BIT32(3) | BSP_BIT32(2) | BSP_BIT32(1) | BSP_BIT32(0))
+#define OP_IDX(val) (BSP_BIT32(5) | (val))
+#define OP_DEREF_IDX(val) (BSP_BIT32(5) | BSP_BIT32(4) | (val))
+
+#define DRD2B1(dest, op0, op1) \
+  (BSP_FLD32(dest, 22, 27) \
+    | BSP_FLD32(SRC_EU_RESULT, 14, 20) \
+    | BSP_FLD32(3, 12, 13) \
+    | BSP_FLD32(op0, 6, 11) \
+    | BSP_FLD32(op1, 0, 5))
+
+#define DRD2B2(op0, op1) \
+  (BSP_BIT32(29) \
+    | BSP_FLD32(3, 26, 27) \
+    | BSP_FLD32(op0, 20, 25) \
+    | BSP_FLD32(op1, 14, 19) \
+    | BSP_FLD32(0, 12, 13) \
+    | BSP_FLD32(OP_NONE, 6, 11) \
+    | BSP_FLD32(OP_NONE, 0, 5))
+
+#define NOP 0x1f8
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* BESTCOMM_OPS_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/i2c.h b/bsps/powerpc/gen5200/include/bsp/i2c.h
new file mode 100644
index 0000000000..e5d7d472dd
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/i2c.h
@@ -0,0 +1,243 @@
+/*
+ * Generic I2C bus interface for RTEMS
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __RTEMS__I2C_H__
+#define __RTEMS__I2C_H__
+
+#include <rtems.h>
+#include <bsp.h>
+/* This header file define the generic interface to i2c buses available in
+ * system. This interface may be used by user applications or i2c-device
+ * drivers (like RTC, NVRAM, etc).
+ *
+ * Functions i2c_initialize and i2c_transfer declared in this header usually
+ * implemented in particular board support package. Usually this
+ * implementation is a simple wrapper or multiplexor to I2C controller
+ * driver which is available in system.  It may be generic "software
+ * controller" I2C driver which control SDA and SCL signals directly (if SDA
+ * and SCL is general-purpose I/O pins), or driver for hardware I2C
+ * controller (standalone or integrated with processors: MBus controller in
+ * ColdFire processors, I2C controller in PowerQUICC and so on).
+ *
+ * i2c_transfer is a very generic low-level function. Higher-level function
+ * i2c_write, i2c_read, i2c_wrrd, i2c_wbrd is defined here too.
+ */
+
+/* I2C Bus Number type */
+typedef uint32_t         i2c_bus_number;
+
+/* I2C device address */
+typedef uint16_t         i2c_address;
+
+/* I2C error codes generated during message transfer */
+typedef enum i2c_message_status {
+    I2C_SUCCESSFUL = 0,
+    I2C_TIMEOUT,
+    I2C_NO_DEVICE,
+    I2C_ARBITRATION_LOST,
+    I2C_NO_ACKNOWLEDGE,
+    I2C_NO_DATA,
+    I2C_RESOURCE_NOT_AVAILABLE
+} i2c_message_status;
+
+/* I2C Message */
+typedef struct i2c_message {
+    i2c_address        addr;   /* I2C slave device address */
+    uint16_t           flags;  /* message flags (see below) */
+    i2c_message_status status; /* message transfer status code */
+    uint16_t           len;    /* Number of bytes to read or write */
+    uint8_t           *buf;    /* pointer to data array */
+} i2c_message;
+
+/* I2C message flag */
+#define I2C_MSG_ADDR_10 (0x01)  /* 10-bit address */
+#define I2C_MSG_WR      (0x02)  /* transfer direction for this message
+                                   from master to slave */
+#define I2C_MSG_ERRSKIP (0x04)  /* Skip message if last transfered message
+                                   is failed */
+/* Type for function which is called when transfer over I2C bus is finished */
+typedef void (*i2c_transfer_done) (void * arg);
+
+/* i2c_initialize --
+ *     I2C driver initialization. This function usually called on device
+ *     driver initialization state, before initialization task. All I2C
+ *     buses are initialized; reasonable slow data transfer rate is
+ *     selected for each bus.
+ *
+ * PARAMETERS:
+ *     major - I2C device major number
+ *     minor - I2C device minor number
+ *     arg - RTEMS driver initialization argument
+ *
+ * RETURNS:
+ *     RTEMS status code
+ */
+rtems_device_driver
+i2c_initialize(rtems_device_major_number major,
+               rtems_device_minor_number minor,
+               void *arg);
+
+/* i2c_select_clock_rate --
+ *     select I2C bus clock rate for specified bus. Some bus controller do not
+ *     allow to select arbitrary clock rate; in this case nearest possible
+ *     slower clock rate is selected.
+ *
+ * PARAMETERS:
+ *     bus - I2C bus number
+ *     bps - data transfer rate for this bytes in bits per second
+ *
+ * RETURNS:
+ *     RTEMS_SUCCESSFUL, if operation performed successfully,
+ *     RTEMS_INVALID_NUMBER, if wrong bus number is specified,
+ *     RTEMS_UNSATISFIED, if bus do not support data transfer rate selection
+ *     or specified data transfer rate could not be used.
+ */
+rtems_status_code
+i2c_select_clock_rate(i2c_bus_number bus, int bps);
+
+/* i2c_transfer --
+ *     Initiate multiple-messages transfer over specified I2C bus or
+ *     put request into queue if bus or some other resource is busy. (This
+ *     is non-blocking function).
+ *
+ * PARAMETERS:
+ *     bus - I2C bus number
+ *     nmsg - number of messages
+ *     msg - pointer to messages array
+ *     done - function which is called when transfer is finished
+ *     done_arg_ptr - arbitrary argument ptr passed to done funciton
+ *
+ * RETURNS:
+ *     RTEMS_SUCCESSFUL if transfer initiated successfully, or error
+ *     code if something failed.
+ */
+rtems_status_code
+i2c_transfer(i2c_bus_number bus, int nmsg, i2c_message *msg,
+             i2c_transfer_done done, void *done_arg);
+
+/* i2c_transfer_wait --
+ *     Initiate I2C bus transfer and block until this transfer will be
+ *     finished. This function wait the semaphore if system in
+ *     SYSTEM_STATE_UP state, or poll done flag in other states.
+ *
+ * PARAMETERS:
+ *     bus - I2C bus number
+ *     msg - pointer to transfer messages array
+ *     nmsg - number of messages in transfer
+ *
+ * RETURNS:
+ *     I2C_SUCCESSFUL, if tranfer finished successfully,
+ *     I2C_RESOURCE_NOT_AVAILABLE, if semaphore operations has failed,
+ *     value of status field of first error-finished message in transfer,
+ *     if something wrong.
+ */
+i2c_message_status
+i2c_transfer_wait(i2c_bus_number bus, i2c_message *msg, int nmsg);
+
+/* i2c_poll --
+ *     Poll I2C bus controller for events and hanle it. This function is
+ *     used when I2C driver operates in poll-driven mode.
+ *
+ * PARAMETERS:
+ *     bus - bus number to be polled
+ *
+ * RETURNS:
+ *     none
+ */
+void
+i2c_poll(i2c_bus_number bus);
+
+/* i2c_write --
+ *     Send single message over specified I2C bus to addressed device and
+ *     wait while transfer is finished.
+ *
+ * PARAMETERS:
+ *     bus  - I2C bus number
+ *     addr - address of I2C device
+ *     buf  - data to be sent to device
+ *     size - data buffer size
+ *
+ * RETURNS:
+ *     transfer status
+ */
+i2c_message_status
+i2c_write(i2c_bus_number bus, i2c_address addr, void *buf, int size);
+
+/* i2c_wrbyte --
+ *     Send single one-byte long message over specified I2C bus to
+ *     addressed device and wait while transfer is finished.
+ *
+ * PARAMETERS:
+ *     bus  - I2C bus number
+ *     addr - address of I2C device
+ *     cmd  - byte message to be sent to device
+ *
+ * RETURNS:
+ *     transfer status
+ */
+i2c_message_status
+i2c_wrbyte(i2c_bus_number bus, i2c_address addr, uint8_t         cmd);
+
+/* i2c_read --
+ *     receive single message over specified I2C bus from addressed device.
+ *     This call will wait while transfer is finished.
+ *
+ * PARAMETERS:
+ *     bus  - I2C bus number
+ *     addr - address of I2C device
+ *     buf  - buffer for received message
+ *     size - receive buffer size
+ *
+ * RETURNS:
+ *     transfer status
+ */
+i2c_message_status
+i2c_read(i2c_bus_number bus, i2c_address addr, void *buf, int size);
+
+/* i2c_wrrd --
+ *     Send message over I2C bus to specified device and receive message
+ *     from the same device during single transfer.
+ *
+ * PARAMETERS:
+ *     bus   - I2C bus number
+ *     addr  - address of I2C device
+ *     bufw  - data to be sent to device
+ *     sizew - send data buffer size
+ *     bufr  - buffer for received message
+ *     sizer - receive buffer size
+ *
+ * RETURNS:
+ *     transfer status
+ */
+i2c_message_status
+i2c_wrrd(i2c_bus_number bus, i2c_address addr, void *bufw, int sizew,
+         void *bufr, int sizer);
+
+/* i2c_wbrd --
+ *     Send one-byte message over I2C bus to specified device and receive
+ *     message from the same device during single transfer.
+ *
+ * PARAMETERS:
+ *     bus   - I2C bus number
+ *     addr  - address of I2C device
+ *     cmd   - one-byte message to be sent over I2C bus
+ *     bufr  - buffer for received message
+ *     sizer - receive buffer size
+ *
+ * RETURNS:
+ *     transfer status
+ */
+i2c_message_status
+i2c_wbrd(i2c_bus_number bus, i2c_address addr, uint8_t         cmd,
+         void *bufr, int sizer);
+
+#endif
diff --git a/bsps/powerpc/gen5200/include/bsp/i2cdrv.h b/bsps/powerpc/gen5200/include/bsp/i2cdrv.h
new file mode 100644
index 0000000000..4b4a1ec141
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/i2cdrv.h
@@ -0,0 +1,35 @@
+/*
+ * i2cdrv.h -- I2C bus driver prototype and definitions
+ *
+ * Copyright (C) 2000 OKTET Ltd., St.-Petersburg, Russia
+ * Author: Victor V. Vengerov <vvv@oktet.ru>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ *
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef __I2CDRV_H__
+#define __I2CDRV_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define I2C_DRIVER_TABLE_ENTRY \
+  { i2cdrv_initialize, NULL, NULL, NULL, NULL, NULL }
+
+/* i2cdrv_initialize --
+ *     I2C driver initialization (rtems I/O driver primitive)
+ */
+rtems_device_driver
+i2cdrv_initialize(rtems_device_major_number major,
+                  rtems_device_minor_number minor,
+                  void *arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __I2CDRV_H__ */
diff --git a/bsps/powerpc/gen5200/include/bsp/irq.h b/bsps/powerpc/gen5200/include/bsp/irq.h
new file mode 100644
index 0000000000..5a0b3bd29e
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/irq.h
@@ -0,0 +1,212 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC5200 BSP                              |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below.   |
+| Adaptions, modifications, enhancements and any recent parts of  |
+| the code are:                                                   |
+|                    Copyright (c) 2005, 2010                     |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains declarations for the irq controller handler  |
+\*===============================================================*/
+/***********************************************************************/
+/*                                                                     */
+/*   Module:       irq.h                                               */
+/*   Date:         07/17/2003                                          */
+/*   Purpose:      RTEMS MPC5x00 CPU interrupt header file             */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Description:  This include file describe the data structure and   */
+/*                 the functions implemented by rtems to write         */
+/*                 interrupt handlers.                                 */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Code                                                              */
+/*   References:   MPC8260ads CPU interrupt header file                */
+/*   Module:       irq.h                                               */
+/*   Project:      RTEMS 4.6.0pre1 / MCF8260ads BSP                    */
+/*   Version       1.1                                                 */
+/*   Date:         10/10/2002                                          */
+/*                                                                     */
+/*   Author(s) / Copyright(s):                                         */
+/*                                                                     */
+/*   Copyright (C) 1999 valette@crf.canon.fr                           */
+/*                                                                     */
+/*   This code is heavilly inspired by the public specification of     */
+/*   STREAM V2 that can be found at:                                   */
+/*                                                                     */
+/*   <http://www.chorus.com/Documentation/index.html> by following     */
+/*   the STREAM API Specification Document link.                       */
+/*                                                                     */
+/*   Modified for mpc8260 by Andy Dachs <a.dachs@sstl.co.uk>           */
+/*   Surrey Satellite Technology Limited                               */
+/*   The interrupt handling on the mpc8260 seems quite different from  */
+/*   the 860 (I don't know the 860 well).  Although some interrupts    */
+/*   are routed via the CPM irq and some are direct to the SIU they    */
+/*   all appear logically the same.Therefore I removed the distinction */
+/*   between SIU and CPM interrupts.                                   */
+/*                                                                     */
+/*   The license and distribution terms for this file may be           */
+/*   found in the file LICENSE in this distribution or at     */
+/*   http://www.rtems.org/license/LICENSE.                        */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Partially based on the code references which are named above.     */
+/*   Adaptions, modifications, enhancements and any recent parts of    */
+/*   the code are under the right of                                   */
+/*                                                                     */
+/*         IPR Engineering, Dachauer Straße 38, D-80335 München        */
+/*                        Copyright(C) 2003                            */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   IPR Engineering makes no representation or warranties with        */
+/*   respect to the performance of this computer program, and          */
+/*   specifically disclaims any responsibility for any damages,        */
+/*   special or consequential, connected with the use of this program. */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Version history:  1.0                                             */
+/*                                                                     */
+/***********************************************************************/
+
+#ifndef LIBBSP_POWERPC_GEN5200_IRQ_H
+#define LIBBSP_POWERPC_GEN5200_IRQ_H
+
+#define PMCE_CE_SHADOW (1U << (31 - 31))
+#define PMCE_CSE_STICKY (1U << (31 - 21))
+#define PMCE_MSE_STICKY (1U << (31 - 10))
+#define PMCE_PSE_STICKY (1U << (31 - 2))
+#define PMCE_CSE_SOURCE(_pmce) (((_pmce) >> 8) & 0x3U)
+#define PMCE_MSE_SOURCE(_pmce) (((_pmce) >> 16) & 0x1fU)
+#define PMCE_PSE_SOURCE(_pmce) (((_pmce) >> 24) & 0x1fU)
+
+/*
+ * Peripheral IRQ handlers related definitions
+ */
+#define BSP_PER_IRQ_NUMBER		22
+#define BSP_PER_IRQ_LOWEST_OFFSET	0
+#define BSP_PER_IRQ_MAX_OFFSET		\
+	(BSP_PER_IRQ_LOWEST_OFFSET + BSP_PER_IRQ_NUMBER - 1) /* 21 */
+/*
+ * Main IRQ handlers related definitions
+ */
+#define BSP_MAIN_IRQ_NUMBER		17
+#define BSP_MAIN_IRQ_LOWEST_OFFSET	BSP_PER_IRQ_MAX_OFFSET + 1 /* 22 */
+#define BSP_MAIN_IRQ_MAX_OFFSET		\
+	(BSP_MAIN_IRQ_LOWEST_OFFSET + BSP_MAIN_IRQ_NUMBER - 1) /* 38 */
+/*
+ * Critical IRQ handlers related definitions
+ */
+#define BSP_CRIT_IRQ_NUMBER		4
+#define BSP_CRIT_IRQ_LOWEST_OFFSET	BSP_MAIN_IRQ_MAX_OFFSET + 1 /* 39 */
+#define BSP_CRIT_IRQ_MAX_OFFSET		\
+	(BSP_CRIT_IRQ_LOWEST_OFFSET + BSP_CRIT_IRQ_NUMBER - 1) /* 42 */
+/*
+ * Summary of SIU interrupts
+ */
+#define BSP_SIU_IRQ_NUMBER		BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 43 */
+#define BSP_SIU_IRQ_LOWEST_OFFSET	BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
+#define BSP_SIU_IRQ_MAX_OFFSET		BSP_CRIT_IRQ_MAX_OFFSET	 /* 42 */
+/*
+ * Processor IRQ handlers related definitions
+ */
+#define BSP_PROCESSOR_IRQ_NUMBER	3
+#define BSP_PROCESSOR_IRQ_LOWEST_OFFSET	BSP_CRIT_IRQ_MAX_OFFSET + 1 /* 44  */
+#define BSP_PROCESSOR_IRQ_MAX_OFFSET	\
+        (BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER - 1) /* 46 */
+/*
+ * Summary
+ */
+#define BSP_IRQ_NUMBER		BSP_PROCESSOR_IRQ_MAX_OFFSET + 1 /* 47 */
+#define BSP_LOWEST_OFFSET	BSP_PER_IRQ_LOWEST_OFFSET /* 0 */
+#define BSP_MAX_OFFSET		BSP_PROCESSOR_IRQ_MAX_OFFSET /* 46 */
+
+#ifndef ASM
+
+#include <rtems.h>
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+/*
+ * index table for the module specific handlers, a few entries are only placeholders
+ */
+typedef enum {
+  BSP_SIU_IRQ_SMARTCOMM		= BSP_PER_IRQ_LOWEST_OFFSET + 0,
+  BSP_SIU_IRQ_PSC1		= BSP_PER_IRQ_LOWEST_OFFSET + 1,
+  BSP_SIU_IRQ_PSC2		= BSP_PER_IRQ_LOWEST_OFFSET + 2,
+  BSP_SIU_IRQ_PSC3		= BSP_PER_IRQ_LOWEST_OFFSET + 3,
+  BSP_SIU_IRQ_PSC6		= BSP_PER_IRQ_LOWEST_OFFSET + 4,
+  BSP_SIU_IRQ_ETH		= BSP_PER_IRQ_LOWEST_OFFSET + 5,
+  BSP_SIU_IRQ_USB		= BSP_PER_IRQ_LOWEST_OFFSET + 6,
+  BSP_SIU_IRQ_ATA		= BSP_PER_IRQ_LOWEST_OFFSET + 7,
+  BSP_SIU_IRQ_PCI_CRT		= BSP_PER_IRQ_LOWEST_OFFSET + 8,
+  BSP_SIU_IRQ_PCI_SC_RX	        = BSP_PER_IRQ_LOWEST_OFFSET + 9,
+  BSP_SIU_IRQ_PCI_SC_TX	        = BSP_PER_IRQ_LOWEST_OFFSET + 10,
+  BSP_SIU_IRQ_PSC4		= BSP_PER_IRQ_LOWEST_OFFSET + 11,
+  BSP_SIU_IRQ_PSC5		= BSP_PER_IRQ_LOWEST_OFFSET + 12,
+  BSP_SIU_IRQ_SPI_MODF	        = BSP_PER_IRQ_LOWEST_OFFSET + 13,
+  BSP_SIU_IRQ_SPI_SPIF	        = BSP_PER_IRQ_LOWEST_OFFSET + 14,
+  BSP_SIU_IRQ_I2C1		= BSP_PER_IRQ_LOWEST_OFFSET + 15,
+  BSP_SIU_IRQ_I2C2		= BSP_PER_IRQ_LOWEST_OFFSET + 16,
+  BSP_SIU_IRQ_MSCAN1		= BSP_PER_IRQ_LOWEST_OFFSET + 17,
+  BSP_SIU_IRQ_MSCAN2		= BSP_PER_IRQ_LOWEST_OFFSET + 18,
+  BSP_SIU_IRQ_IR_RX		= BSP_PER_IRQ_LOWEST_OFFSET + 19,
+  BSP_SIU_IRQ_IR_TX		= BSP_PER_IRQ_LOWEST_OFFSET + 20,
+  BSP_SIU_IRQ_XLB_ARB		= BSP_PER_IRQ_LOWEST_OFFSET + 21,
+
+  /* SL_TIMER1 -- handler entry only used in case of SMI */
+  BSP_SIU_IRQ_SL_TIMER1	        = BSP_MAIN_IRQ_LOWEST_OFFSET + 0,
+  BSP_SIU_IRQ_IRQ1		= BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
+  BSP_SIU_IRQ_IRQ2		= BSP_MAIN_IRQ_LOWEST_OFFSET + 2,
+  BSP_SIU_IRQ_IRQ3		= BSP_MAIN_IRQ_LOWEST_OFFSET + 3,
+  /* LO_INT --  handler entry never used (only placeholder) */
+  BSP_SIU_IRQ_LO_INT		= BSP_MAIN_IRQ_LOWEST_OFFSET + 4,
+  BSP_SIU_IRQ_RTC_PER		= BSP_MAIN_IRQ_LOWEST_OFFSET + 5,
+  BSP_SIU_IRQ_RTC_STW		= BSP_MAIN_IRQ_LOWEST_OFFSET + 6,
+  BSP_SIU_IRQ_GPIO_STD		= BSP_MAIN_IRQ_LOWEST_OFFSET + 7,
+  BSP_SIU_IRQ_GPIO_WKUP		= BSP_MAIN_IRQ_LOWEST_OFFSET + 8,
+  BSP_SIU_IRQ_TMR0		= BSP_MAIN_IRQ_LOWEST_OFFSET + 9,
+  BSP_SIU_IRQ_TMR1		= BSP_MAIN_IRQ_LOWEST_OFFSET + 10,
+  BSP_SIU_IRQ_TMR2		= BSP_MAIN_IRQ_LOWEST_OFFSET + 1,
+  BSP_SIU_IRQ_TMR3		= BSP_MAIN_IRQ_LOWEST_OFFSET + 12,
+  BSP_SIU_IRQ_TMR4		= BSP_MAIN_IRQ_LOWEST_OFFSET + 13,
+  BSP_SIU_IRQ_TMR5		= BSP_MAIN_IRQ_LOWEST_OFFSET + 14,
+  BSP_SIU_IRQ_TMR6		= BSP_MAIN_IRQ_LOWEST_OFFSET + 15,
+  BSP_SIU_IRQ_TMR7		= BSP_MAIN_IRQ_LOWEST_OFFSET + 16,
+
+  BSP_SIU_IRQ_IRQ0		= BSP_CRIT_IRQ_LOWEST_OFFSET + 0,
+  BSP_SIU_IRQ_SL_TIMER0		= BSP_CRIT_IRQ_LOWEST_OFFSET + 1,
+  /* HI_INT -- handler entry never used (only placeholder) */
+  BSP_SIU_IRQ_HI_INT		= BSP_CRIT_IRQ_LOWEST_OFFSET + 2,
+  BSP_SIU_IRQ_CSS_WKUP		= BSP_CRIT_IRQ_LOWEST_OFFSET + 3,
+
+  BSP_DECREMENTER		= BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 0,
+  BSP_SYSMGMT			= BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 1,
+  BSP_EXT                 	= BSP_PROCESSOR_IRQ_LOWEST_OFFSET + 2
+} rtems_irq_symbolic_name;
+
+#define BSP_CRIT_IRQ_PRIO_LEVELS	  		  4
+#define BSP_PERIODIC_TIMER                    BSP_SIU_IRQ_TMR6
+
+#define BSP_INTERRUPT_VECTOR_MIN BSP_LOWEST_OFFSET
+
+#define BSP_INTERRUPT_VECTOR_MAX BSP_MAX_OFFSET
+
+#endif
+
+#endif /* LIBBSP_POWERPC_GEN5200_IRQ_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/mpc5200.h b/bsps/powerpc/gen5200/include/bsp/mpc5200.h
new file mode 100644
index 0000000000..263e66fb9e
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/mpc5200.h
@@ -0,0 +1,1369 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC5200 BSP                              |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below.   |
+| Adaptions, modifications, enhancements and any recent parts of  |
+| the code are:                                                   |
+|                    Copyright (c) 2005                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains definitions for the mpc5200 hw registers     |
+\*===============================================================*/
+
+#ifndef __MPC5200_h__
+#define __MPC5200_h__
+
+/* Additional Harpo Core SPR definitions (603le only) */
+#define CSRR0    58   /* Critical Interrupt SRR0 */
+#define CSRR1    59   /* Critical Interrupt SRR1 */
+#define DABR2  1000   /* Data Address Breakpoint #2 */
+#define DBCR   1001   /* Data Address Breakpoint Control */
+#define IBCR   1002   /* Instruction Breakpoint Control */
+#define IABR2  1018   /* Instruction Breakpoint #2 */
+
+/*
+ * Initial post-reset location of MGT5100 module base address register (MBAR)
+ */
+#define MBAR_RESET      0x80000000
+
+/*
+ * Location and size of onchip SRAM (relative to MBAR)
+ */
+#define ONCHIP_SRAM_OFFSET  0x8000
+#define ONCHIP_SRAM_SIZE    0x4000
+
+#ifndef ASM
+#include <rtems.h>
+
+#include <bsp/utility.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MPC5200_CAN_NO         2
+#define MPC5200_PSC_NO         6
+  /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap
+  *      from PSC5, therefore we instantiate seven(!) PSC register sets
+ */
+#define MPC5200_PSC_REG_SETS   7
+
+#define MPC5200_GPT_NO         8
+#define MPC5200_SLT_NO         2
+
+/*
+ * Bit fields for FEC interrupts, ievent and imask above.
+ */
+#define FEC_INTR_HBERR     0x80000000  /* heartbeat error */
+#define FEC_INTR_BABR      0x40000000  /* babbling receive error */
+#define FEC_INTR_BABT      0x20000000  /* babbling transmit error */
+#define FEC_INTR_GRA       0x10000000  /* graceful stop complete */
+#define FEC_INTR_TFINT     0x08000000  /* transmit frame interrupt */
+/*                         0x04000000    reserved */
+/*                         0x02000000    reserved */
+/*                         0x01000000    reserved */
+#define FEC_INTR_MII       0x00800000  /* MII interrupt */
+/*                         0x00400000      reserved */
+#define FEC_INTR_LATE_COL  0x00200000  /* late collision */
+#define FEC_INTR_COL_RETRY 0x00100000  /* collision retry limit */
+#define FEC_INTR_XFIFO_UN  0x00080000  /* transmit FIFO error */
+#define FEC_INTR_XFIFO_ERR 0x00040000  /* transmit FIFO error */
+#define FEC_INTR_RFIFO_ERR 0x00020000  /* receive FIFO error */
+/*                         0x00010000     reserved */
+/*                         0x0000ffff     reserved */
+#define FEC_INTR_HBEEN     FEC_INTR_HBERR
+#define FEC_INTR_BREN      FEC_INTR_BABR
+#define FEC_INTR_BTEN      FEC_INTR_BABT
+#define FEC_INTR_GRAEN     FEC_INTR_GRA
+#define FEC_INTR_TFINTEN   FEC_INTR_TFINT
+#define FEC_INTR_MIIEN     FEC_INTR_MII
+#define FEC_INTR_LCEN      FEC_INTR_LATE_COL
+#define FEC_INTR_CRLEN     FEC_INTR_COL_RETRY
+#define FEC_INTR_XFUNEN    FEC_INTR_XFIFO_UN
+#define FEC_INTR_XFERREN   FEC_INTR_XFIFO_ERR
+#define FEC_INTR_RFERREN   FEC_INTR_RFIFO_ERR
+#define FEC_INTR_CLEAR_ALL 0xffffffff /* clear all interrupt events */
+#define FEC_INTR_MASK_ALL  0x00000000 /* mask all interrupt events */
+
+/*
+ * Bit fields for FEC ethernet control, ecntrl above.
+ */
+#define FEC_ECNTRL_TAG    0xf0000000  /* TBUS tag bits */
+/*                        0x08000000     reserved */
+#define FEC_ECNTRL_TESTMD 0x04000000  /* test mode */
+/*                        0x03fffff8     reserved */
+#define FEC_ECNTRL_OE     0x00000004  /* FEC output enable */
+#define FEC_ECNTRL_EN     0x00000002  /* ethernet enable */
+#define FEC_ECNTRL_RESET  0x00000001  /* ethernet controller reset */
+
+/*
+ * Bit fields for FEC receive control, r_cntrl above.
+ */
+/*                          0xf1000000    reserved */
+#define FEC_RCNTRL_MAX_FL   0x07ff0000 /* maximum frame length */
+#define FEC_RCNTRL_MAX_FL_SHIFT 16
+/*                          0x0000ffc0    reserved */
+#define FEC_RCNTRL_FCE      0x00000020 /* flow control enable */
+#define FEC_RCNTRL_BC_REJ   0x00000010 /* broadcast frame reject */
+#define FEC_RCNTRL_PROM     0x00000008 /* promiscuous mode */
+#define FEC_RCNTRL_MII_MODE 0x00000004 /* select 18-wire (MII) mode */
+#define FEC_RCNTRL_DRT      0x00000002 /* disable receive on transmit */
+#define FEC_RCNTRL_LOOP     0x00000001 /* internal loopback */
+
+/*
+ * Bit fields for FEC transmit control, x_cntrl above.
+ */
+/*                          0xffffffe0    reserved */
+#define FEC_XCNTRL_RFC_PAUS 0x00000010 /* FDX flow control pause rx */
+#define FEC_XCNTRL_TFC_PAUS 0x00000008 /* assert a PAUSE frame  */
+#define FEC_XCNTRL_FDEN     0x00000004 /* full duplex enable  */
+#define FEC_XCNTRL_HBC      0x00000002 /* heartbeat control  */
+#define FEC_XCNTRL_GTS      0x00000001 /* graceful transmit stop */
+
+/*
+ * Bit fields for FEC transmit status, x_status above.
+ */
+/*                     0xfc000000     reserved */
+#define FEC_XSTAT_DEF  0x02000000 /* defer */
+#define FEC_XSTAT_HB   0x01000000 /* heartbeat error */
+#define FEC_XSTAT_LC   0x00800000 /* late collision */
+#define FEC_XSTAT_RL   0x00400000 /* retry limit  */
+#define FEC_XSTAT_RC   0x003c0000 /* retry count  */
+#define FEC_XSTAT_UN   0x00020000 /* underrun */
+#define FEX_XSTAT_CSL  0x00010000 /* carrier sense lost  */
+/*       0x0000ffff reserved */
+
+/*
+ * Bit fields for FEC transmit FIFO watermark, x_wmrk above.
+ */
+#define FEC_XWMRK_64    0x00000000  /*   64 bytes written to TxFIFO */
+#define FEC_XWMRK_128   0x00000001  /*  128 bytes written to TxFIFO */
+#define FEC_XWMRK_192   0x00000002  /*  192 bytes written to TxFIFO */
+#define FEC_XWMRK_256   0x00000003  /*  256 bytes written to TxFIFO */
+#define FEC_XWMRK_320   0x00000004  /*  320 bytes written to TxFIFO */
+#define FEC_XWMRK_384   0x00000005  /*  384 bytes written to TxFIFO */
+#define FEC_XWMRK_448   0x00000006  /*  448 bytes written to TxFIFO */
+#define FEC_XWMRK_512   0x00000007  /*  512 bytes written to TxFIFO */
+#define FEC_XWMRK_576   0x00000008  /*  576 bytes written to TxFIFO */
+#define FEC_XWMRK_640   0x00000009  /*  640 bytes written to TxFIFO */
+#define FEC_XWMRK_704   0x0000000a  /*  704 bytes written to TxFIFO */
+#define FEC_XWMRK_768   0x0000000b  /*  768 bytes written to TxFIFO */
+#define FEC_XWMRK_832   0x0000000c  /*  832 bytes written to TxFIFO */
+#define FEC_XWMRK_896   0x0000000d  /*  896 bytes written to TxFIFO */
+#define FEC_XWMRK_960   0x0000000e  /*  960 bytes written to TxFIFO */
+#define FEC_XWMRK_1024  0x0000000f  /* 1024 bytes written to TxFIFO */
+
+/*
+ * Bit fields for FEC transmit finite state machine.
+ */
+/*                      0xfc000000    reserved */
+#define FEC_FSM_CRC     0x02000000 /* append CRC (typical use) */
+#define FEC_FSM_ENFSM   0x01000000 /* enable CRC FSM (typical use) */
+/*                      0x00ffffff reserved */
+
+/*
+ * Bit fields for FEC FIFOs, rfifo_status, rfifo_cntrl, tfifo_status
+ * and tfifo_cntrl.
+ */
+#define FEC_FIFO_STAT_IP    0x80000000 /* illegal pointer, sticky */
+/*                          0x70000000    reserved */
+#define FEC_FIFO_STAT_FRAME 0x0f000000 /* frame indicator */
+#define FEC_FIFO_STAT_FAE   0x00800000 /* frame accept error  */
+#define FEC_FIFO_STAT_RXW   0x00400000 /* receive wait condition */
+#define FEC_FIFO_STAT_UF    0x00200000 /* underflow  */
+#define FEC_FIFO_STAT_OF    0x00100000 /* overflow */
+#define FEC_FIFO_STAT_FR    0x00080000 /* frame ready, read-only */
+#define FEC_FIFO_STAT_FULL  0x00040000 /* full alarm, read-only */
+#define FEC_FIFO_STAT_ALARM 0x00020000 /* fifo alarm  */
+#define FEC_FIFO_STAT_EMPTY 0x00010000 /* empty, read-only */
+/*                          0x0000ffff    reserved */
+#define FEC_FIFO_STAT_ERROR ( FEC_FIFO_STAT_IP  \
+              | FEC_FIFO_STAT_FAE \
+              | FEC_FIFO_STAT_RXW \
+              | FEC_FIFO_STAT_UF  \
+              | FEC_FIFO_STAT_OF  \
+              )
+
+/*                              0x80000000    reserved */
+#define FEC_FIFO_CNTRL_WCTL     0x40000000 /* write control */
+#define FEC_FIFO_CNTRL_WFR      0x20000000 /* write frame  */
+/*                              0x10000000    reserved */
+#define FEC_FIFO_CNTRL_FRAME    0x08000000 /* frame mode enable */
+#define FEC_FIFO_CNTRL_GR       0x07000000 /* last transfer granularity */
+#define FEC_FIFO_CNTRL_GR_SHIFT 24
+#define FEC_FIFO_CNTRL_IP_MASK  0x00800000 /* illegal pointer mask  */
+#define FEC_FIFO_CNTRL_FAE_MASK 0x00400000 /* frame accept mask  */
+#define FEC_FIFO_CNTRL_RXW_MASK 0x00200000 /* receive wait mask  */
+#define FEC_FIFO_CNTRL_UF_MASK  0x00100000 /* underflow mask */
+#define FEC_FIFO_CNTRL_OF_MASK  0x00080000 /* overflow mask */
+/*                              0x0007ffff    reserved */
+
+#define SDMA_TCR_EN BSP_BBIT16(0)
+#define SDMA_TCR_VAL BSP_BBIT16(1)
+#define SDMA_TCR_ALW_INIT BSP_BBIT16(2)
+#define SDMA_TCR_IN(val) BSP_BFLD16(val, 3, 7)
+#define SDMA_TCR_AUTO_START BSP_BBIT16(8)
+#define SDMA_TCR_HIGH_EN BSP_BBIT16(9)
+#define SDMA_TCR_HOLD BSP_BBIT16(10)
+#define SDMA_TCR_AS(val) BSP_BFLD16(val, 12, 15)
+
+#define SDMA_IPR_HOLD BSP_BBIT8(0)
+#define SDMA_IPR_PRIOR(val) BSP_BFLD8(val, 5, 7)
+
+#define SDMA_REQMUX_SET_31(reg, val) BSP_BFLD32SET(reg, val, 0, 1)
+#define SDMA_REQMUX_SET_30(reg, val) BSP_BFLD32SET(reg, val, 2, 3)
+#define SDMA_REQMUX_SET_29(reg, val) BSP_BFLD32SET(reg, val, 4, 5)
+#define SDMA_REQMUX_SET_28(reg, val) BSP_BFLD32SET(reg, val, 6, 7)
+#define SDMA_REQMUX_SET_27(reg, val) BSP_BFLD32SET(reg, val, 8, 9)
+#define SDMA_REQMUX_SET_26(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
+#define SDMA_REQMUX_SET_25(reg, val) BSP_BFLD32SET(reg, val, 12, 13)
+#define SDMA_REQMUX_SET_24(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
+#define SDMA_REQMUX_SET_23(reg, val) BSP_BFLD32SET(reg, val, 16, 17)
+#define SDMA_REQMUX_SET_22(reg, val) BSP_BFLD32SET(reg, val, 18, 19)
+#define SDMA_REQMUX_SET_21(reg, val) BSP_BFLD32SET(reg, val, 20, 21)
+#define SDMA_REQMUX_SET_20(reg, val) BSP_BFLD32SET(reg, val, 22, 23)
+#define SDMA_REQMUX_SET_19(reg, val) BSP_BFLD32SET(reg, val, 24, 25)
+#define SDMA_REQMUX_SET_18(reg, val) BSP_BFLD32SET(reg, val, 26, 27)
+#define SDMA_REQMUX_SET_17(reg, val) BSP_BFLD32SET(reg, val, 28, 29)
+#define SDMA_REQMUX_SET_16(reg, val) BSP_BFLD32SET(reg, val, 30, 31)
+
+/* SDMA / BestComm */
+typedef struct {
+  uint32_t taskBar;
+  uint32_t currentPointer;
+  uint32_t endPointer;
+  uint32_t variablePointer;
+  uint8_t IntVect1;
+  uint8_t IntVect2;
+  uint16_t PtdCntrl;
+  uint32_t IntPend;
+  uint32_t IntMask;
+  uint16_t tcr [16];
+  uint8_t ipr [32];
+  uint32_t cReqSelect;
+  uint32_t task_size0;
+  uint32_t task_size1;
+  uint32_t reserved_0;
+  uint32_t reserved_1;
+  uint32_t Value1;
+  uint32_t Value2;
+  uint32_t Control;
+  uint32_t Status;
+} mpc5200_sdma;
+
+typedef struct {
+#define CSC_CFG_WAITP(val) BSP_BFLD32(val, 0, 7)
+#define CSC_CFG_WAITX(val) BSP_BFLD32(val, 8, 15)
+#define CSC_CFG_MX BSP_BBIT32(16)
+#define CSC_CFG_AA BSP_BBIT32(18)
+#define CSC_CFG_CE BSP_BBIT32(19)
+#define CSC_CFG_AS(val) BSP_BFLD32(val, 20, 21)
+#define CSC_CFG_DS(val) BSP_BFLD32(val, 22, 23)
+#define CSC_CFG_BANK(val) BSP_BFLD32(val, 24, 25)
+#define CSC_CFG_WTYP(val) BSP_BFLD32(val, 26, 27)
+#define CSC_CFG_WS BSP_BBIT32(28)
+#define CSC_CFG_RS BSP_BBIT32(29)
+#define CSC_CFG_WO BSP_BBIT32(30)
+#define CSC_CFG_RO BSP_BBIT32(31)
+  uint32_t config_0;
+  uint32_t config_1;
+  uint32_t config_2;
+  uint32_t config_3;
+  uint32_t config_4;
+  uint32_t config_5;
+
+#define CSC_CTRL_ME BSP_BBIT32(7)
+  uint32_t control;
+
+#define CSC_STAT_WOERR BSP_BBIT32(2)
+#define CSC_STAT_ROERR BSP_BBIT32(3)
+#define CSC_STAT_GET_CSXERR(reg) BSP_BFLD32GET(reg, 5, 7)
+  uint32_t status;
+
+  uint32_t config_6;
+  uint32_t config_7;
+
+#define CSC_BST_CTRL_CW7 BSP_BBIT32(0)
+#define CSC_BST_CTRL_SLB7 BSP_BBIT32(1)
+#define CSC_BST_CTRL_BRE7 BSP_BBIT32(3)
+#define CSC_BST_CTRL_CW6 BSP_BBIT32(4)
+#define CSC_BST_CTRL_SLB6 BSP_BBIT32(5)
+#define CSC_BST_CTRL_BRE6 BSP_BBIT32(7)
+#define CSC_BST_CTRL_CW5 BSP_BBIT32(8)
+#define CSC_BST_CTRL_SLB5 BSP_BBIT32(9)
+#define CSC_BST_CTRL_BRE5 BSP_BBIT32(11)
+#define CSC_BST_CTRL_CW4 BSP_BBIT32(12)
+#define CSC_BST_CTRL_SLB4 BSP_BBIT32(13)
+#define CSC_BST_CTRL_BRE4 BSP_BBIT32(15)
+#define CSC_BST_CTRL_CW3 BSP_BBIT32(16)
+#define CSC_BST_CTRL_SLB3 BSP_BBIT32(17)
+#define CSC_BST_CTRL_BRE3 BSP_BBIT32(19)
+#define CSC_BST_CTRL_CW2 BSP_BBIT32(20)
+#define CSC_BST_CTRL_SLB2 BSP_BBIT32(21)
+#define CSC_BST_CTRL_BRE2 BSP_BBIT32(23)
+#define CSC_BST_CTRL_CW1 BSP_BBIT32(24)
+#define CSC_BST_CTRL_SLB1 BSP_BBIT32(25)
+#define CSC_BST_CTRL_BRE1 BSP_BBIT32(27)
+#define CSC_BST_CTRL_CW0 BSP_BBIT32(28)
+#define CSC_BST_CTRL_SLB0 BSP_BBIT32(29)
+#define CSC_BST_CTRL_BRE0 BSP_BBIT32(31)
+  uint32_t burst_control;
+
+#define CSC_DCYC_CTRL_DC7(val) BSP_BFLD32(val, 2, 3)
+#define CSC_DCYC_CTRL_SET_DC7(reg, val) BSP_BFLD32SET(reg, val, 2, 3)
+#define CSC_DCYC_CTRL_DC6(val) BSP_BFLD32(val, 6, 7)
+#define CSC_DCYC_CTRL_SET_DC6(reg, val) BSP_BFLD32SET(reg, val, 6, 7)
+#define CSC_DCYC_CTRL_DC5(val) BSP_BFLD32(val, 10, 11)
+#define CSC_DCYC_CTRL_SET_DC5(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
+#define CSC_DCYC_CTRL_DC4(val) BSP_BFLD32(val, 14, 15)
+#define CSC_DCYC_CTRL_SET_DC4(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
+#define CSC_DCYC_CTRL_DC3(val) BSP_BFLD32(val, 18, 19)
+#define CSC_DCYC_CTRL_SET_DC3(reg, val) BSP_BFLD32SET(reg, val, 18, 19)
+#define CSC_DCYC_CTRL_DC2(val) BSP_BFLD32(val, 22, 23)
+#define CSC_DCYC_CTRL_SET_DC2(reg, val) BSP_BFLD32SET(reg, val, 22, 23)
+#define CSC_DCYC_CTRL_DC1(val) BSP_BFLD32(val, 26, 27)
+#define CSC_DCYC_CTRL_SET_DC1(reg, val) BSP_BFLD32SET(reg, val, 26, 27)
+#define CSC_DCYC_CTRL_DC0(val) BSP_BFLD32(val, 30, 31)
+#define CSC_DCYC_CTRL_SET_DC0(reg, val) BSP_BFLD32SET(reg, val, 30, 31)
+  uint32_t deadcycle_control;
+
+  uint8_t reserved [208];
+} mpc5200_csc;
+
+typedef struct {
+  uint32_t memory_address_base;
+  uint32_t cs0_start_address;
+  uint32_t cs0_stop_address;
+  uint32_t cs1_start_address;
+  uint32_t cs1_stop_address;
+  uint32_t cs2_start_address;
+  uint32_t cs2_stop_address;
+  uint32_t cs3_start_address;
+  uint32_t cs3_stop_address;
+  uint32_t cs4_start_address;
+  uint32_t cs4_stop_address;
+  uint32_t cs5_start_address;
+  uint32_t cs5_stop_address;
+  uint32_t sdram_chip_select_0;
+  uint32_t sdram_chip_select_1;
+  uint8_t reserved_0 [16];
+  uint32_t boot_start_address;
+  uint32_t boot_stop_address;
+
+#define MM_IPBI_CTRL_CS7ENA BSP_BBIT16(4)
+#define MM_IPBI_CTRL_CS6ENA BSP_BBIT16(5)
+#define MM_IPBI_CTRL_BOOTENA BSP_BBIT16(6)
+#define MM_IPBI_CTRL_CS5ENA BSP_BBIT16(10)
+#define MM_IPBI_CTRL_CS4ENA BSP_BBIT16(11)
+#define MM_IPBI_CTRL_CS3ENA BSP_BBIT16(12)
+#define MM_IPBI_CTRL_CS2ENA BSP_BBIT16(13)
+#define MM_IPBI_CTRL_CS1ENA BSP_BBIT16(14)
+#define MM_IPBI_CTRL_CS0ENA BSP_BBIT16(15)
+  uint16_t ipbi_control;
+
+  uint16_t wait_state_enable;
+  uint32_t cs6_start_address;
+  uint32_t cs6_stop_address;
+  uint32_t cs7_start_address;
+  uint32_t cs7_stop_address;
+  uint8_t reserved_1 [152];
+} mpc5200_mm;
+
+/*
+*************************************************************************
+*                 MPC5x00 internal register memory map                  *
+*************************************************************************
+*/
+typedef struct mpc5200_ {
+  /*
+   * memory map registers (MBAR + 0)
+   */
+  volatile mpc5200_mm mm;
+
+  /*
+   * SDRAM memory controller registers (MBAR + 0x100)
+   */
+  volatile uint8_t    mc[0x100];
+
+  /*
+   * clock distribution module registers (MBAR + 0x200)
+   */
+  volatile uint8_t    cdm[0x100];
+
+  /*
+   * chip selct controller registers(MBAR + 0x300)
+   */
+  volatile mpc5200_csc csc;
+
+  /*
+   * SmartComm timer registers (MBAR + 0x400)
+   */
+  volatile uint8_t    sct[0x100];
+
+  /*
+   * interrupt controller registers (MBAR + 0x500)
+   */
+  volatile uint32_t    per_mask;          /* + 0x00 */
+  volatile uint32_t    per_pri_1;         /* + 0x04 */
+  volatile uint32_t    per_pri_2;         /* + 0x08 */
+  volatile uint32_t    per_pri_3;         /* + 0x0C */
+
+#define ICTL_EET_ECLR0 BSP_BBIT32(4)
+#define ICTL_EET_ECLR1 BSP_BBIT32(5)
+#define ICTL_EET_ECLR2 BSP_BBIT32(6)
+#define ICTL_EET_ECLR3 BSP_BBIT32(7)
+#define ICTL_EET_ETYPE0(val) BSP_BFLD32(val, 8, 9)
+#define ICTL_EET_ETYPE1(val) BSP_BFLD32(val, 10, 11)
+#define ICTL_EET_ETYPE2(val) BSP_BFLD32(val, 12, 13)
+#define ICTL_EET_ETYPE3(val) BSP_BFLD32(val, 14, 15)
+#define ICTL_EET_SET_ETYPE0(reg, val) BSP_BFLD32SET(reg, val, 8, 9)
+#define ICTL_EET_SET_ETYPE1(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
+#define ICTL_EET_SET_ETYPE2(reg, val) BSP_BFLD32SET(reg, val, 12, 13)
+#define ICTL_EET_SET_ETYPE3(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
+#define ICTL_EET_MEE BSP_BBIT32(19)
+#define ICTL_EET_EENA0 BSP_BBIT32(20)
+#define ICTL_EET_EENA1 BSP_BBIT32(21)
+#define ICTL_EET_EENA2 BSP_BBIT32(22)
+#define ICTL_EET_EENA3 BSP_BBIT32(23)
+#define ICTL_EET_CEB BSP_BBIT32(31)
+
+  volatile uint32_t    ext_en_type;       /* + 0x10 */
+  volatile uint32_t    crit_pri_main_mask;/* + 0x14 */
+  volatile uint32_t    main_pri_1;        /* + 0x18 */
+  volatile uint32_t    main_pri_2;        /* + 0x1C */
+  volatile uint32_t    res1;              /* + 0x20 */
+  volatile uint32_t    pmce;              /* + 0x24 */
+  volatile uint32_t    csa;               /* + 0x28 */
+  volatile uint32_t    msa;               /* + 0x2C */
+  volatile uint32_t    psa;               /* + 0x30 */
+  volatile uint32_t    res2;              /* + 0x34 */
+  volatile uint32_t    psa_be;            /* + 0x38 */
+  volatile uint8_t     res3[0xC4];        /* + 0x3C */
+
+  /*
+    * general pupose timer registers (MBAR + 0x600/+ 0x610/+ 0x620/+ 0x630/+ 0x640/+ 0x650/+ 0x660/+ 0x670)
+   */
+  struct mpc5200_gpt {
+    volatile uint32_t    emsel;     /* + 0x00 */
+    volatile uint32_t    count_in;  /* + 0x04 */
+    volatile uint32_t    pwm_conf;  /* + 0x08 */
+    volatile uint32_t    status;    /* + 0x0C */
+  } gpt[MPC5200_GPT_NO];
+
+#define GPT_STATUS_RESET           0x0000000F
+#define GPT_STATUS_TEXP            (1 << 3)
+#define GPT_STATUS_PIN             (1 << 8)
+#define GPT_EMSEL_GPIO_DIR         (2 << 4)
+#define GPT_EMSEL_GPIO_OUT         (1 << 4)
+#define GPT_EMSEL_GPIO_OUT_HIGH    (3 << 4)
+#define GPT_EMSEL_TIMER_MS_GPIO    (4 << 0)
+#define GPT_EMSEL_GPIO_IN          (0 << 0)
+#define GPT_EMSEL_CE               (1 << 12)
+#define GPT_EMSEL_ST_CONT          (1 << 10)
+#define GPT_EMSEL_INTEN            (1 << 8)
+#define GPT_EMSEL_WDEN          (1 << 15)
+
+#define GPT0                       0
+#define GPT1                       1
+#define GPT2                       2
+#define GPT3                       3
+#define GPT4                       4
+#define GPT5                       5
+#define GPT6                       6
+#define GPT7                       7
+
+  volatile uint8_t   gpt_res[0x80];
+
+   /*
+    * slice time registers (MBAR + 0x700/+ 0x710)
+ */
+  struct mpc5200_slt {
+    volatile uint32_t  tcr;       /* + 0x00 */
+    volatile uint32_t  cntrl;     /* + 0x04 */
+    volatile uint32_t  cvr;       /* + 0x08 */
+    volatile uint32_t  tsr;       /* + 0x0C */
+  } slt[MPC5200_SLT_NO];
+
+    volatile uint8_t   slt_res[0xE0];
+
+  /*
+   * real time clock registers (MBAR + 0x800)
+   */
+  volatile uint8_t    rtc[0x100];
+
+
+  /*
+   * MSCAN registers (MBAR + 0x900 /+ 0x980)
+   */
+  struct mpc5200_mscan {
+    volatile uint8_t    ctl0;   /* + 0x0 */
+    volatile uint8_t    ctl1;   /* + 0x1 */
+    volatile uint8_t    res1;   /* + 0x2 */
+    volatile uint8_t    res2;   /* + 0x3 */
+    volatile uint8_t    btr0;   /* + 0x4 */
+    volatile uint8_t    btr1;   /* + 0x5 */
+    volatile uint8_t    res3;   /* + 0x6 */
+    volatile uint8_t    res4;   /* + 0x7 */
+    volatile uint8_t    rflg;   /* + 0x8 */
+    volatile uint8_t    rier;   /* + 0x9 */
+    volatile uint8_t    res5;   /* + 0xA */
+    volatile uint8_t    res6;   /* + 0xB */
+    volatile uint8_t    tflg;   /* + 0xC */
+    volatile uint8_t    tier;   /* + 0xD */
+    volatile uint8_t    res7;   /* + 0xE */
+    volatile uint8_t    res8;   /* + 0xF */
+    volatile uint8_t    tarq;   /* + 0x10 */
+    volatile uint8_t    taak;   /* + 0x11 */
+    volatile uint8_t    res9;   /* + 0x12 */
+    volatile uint8_t    res10;  /* + 0x13 */
+    volatile uint8_t    bsel;   /* + 0x14 */
+    volatile uint8_t    idac;   /* + 0x15 */
+    volatile uint8_t    res11;  /* + 0x16 */
+    volatile uint8_t    res12;  /* + 0x17 */
+    volatile uint8_t    res13;  /* + 0x18 */
+    volatile uint8_t    res14;  /* + 0x19 */
+    volatile uint8_t    res15;  /* + 0x1A */
+    volatile uint8_t    res16;  /* + 0x1B */
+    volatile uint8_t    rxerr;  /* + 0x1C */
+    volatile uint8_t    txerr;  /* + 0x1D */
+    volatile uint8_t    res17;  /* + 0x1E */
+    volatile uint8_t    res18;  /* + 0x1F */
+    volatile uint8_t    idar0;  /* + 0x20 */
+    volatile uint8_t    idar1;  /* + 0x21 */
+    volatile uint8_t    res19;  /* + 0x22 */
+    volatile uint8_t    res20;  /* + 0x23 */
+    volatile uint8_t    idar2;  /* + 0x24 */
+    volatile uint8_t    idar3;  /* + 0x25 */
+    volatile uint8_t    res21;  /* + 0x26 */
+    volatile uint8_t    res22;  /* + 0x27 */
+    volatile uint8_t    idmr0;  /* + 0x28 */
+    volatile uint8_t    idmr1;  /* + 0x29 */
+    volatile uint8_t    res23;  /* + 0x2A */
+    volatile uint8_t    res24;  /* + 0x2B */
+    volatile uint8_t    idmr2;  /* + 0x2C */
+    volatile uint8_t    idmr3;  /* + 0x2D */
+    volatile uint8_t    res25;  /* + 0x2E */
+    volatile uint8_t    res26;  /* + 0x2F */
+    volatile uint8_t    idar4;  /* + 0x30 */
+    volatile uint8_t    idar5;  /* + 0x31 */
+    volatile uint8_t    res27;  /* + 0x32 */
+    volatile uint8_t    res28;  /* + 0x33 */
+    volatile uint8_t    idar6;  /* + 0x34 */
+    volatile uint8_t    idar7;  /* + 0x35 */
+    volatile uint8_t    res29;  /* + 0x36 */
+    volatile uint8_t    res30;  /* + 0x37 */
+    volatile uint8_t    idmr4;  /* + 0x38 */
+    volatile uint8_t    idmr5;  /* + 0x39 */
+    volatile uint8_t    res31;  /* + 0x3A */
+    volatile uint8_t    res32;  /* + 0x3B */
+    volatile uint8_t    idmr6;  /* + 0x3C */
+    volatile uint8_t    idmr7;  /* + 0x3D */
+    volatile uint8_t    res33;  /* + 0x3E */
+    volatile uint8_t    res34;  /* + 0x3F */
+    volatile uint8_t    rxidr0; /* + 0x40 */
+    volatile uint8_t    rxidr1; /* + 0x41 */
+    volatile uint8_t    res35;  /* + 0x42 */
+    volatile uint8_t    res36;  /* + 0x43 */
+    volatile uint8_t    rxidr2; /* + 0x44 */
+    volatile uint8_t    rxidr3; /* + 0x45 */
+    volatile uint8_t    res37;  /* + 0x46 */
+    volatile uint8_t    res38;  /* + 0x47 */
+    volatile uint8_t    rxdsr0; /* + 0x48 */
+    volatile uint8_t    rxdsr1; /* + 0x49 */
+    volatile uint8_t    res39;  /* + 0x4A */
+    volatile uint8_t    res40;  /* + 0x4B */
+    volatile uint8_t    rxdsr2; /* + 0x4C */
+    volatile uint8_t    rxdsr3; /* + 0x4D */
+    volatile uint8_t    res41;  /* + 0x4E */
+    volatile uint8_t    res42;  /* + 0x4F */
+    volatile uint8_t    rxdsr4; /* + 0x50 */
+    volatile uint8_t    rxdsr5; /* + 0x51 */
+    volatile uint8_t    res43;  /* + 0x52 */
+    volatile uint8_t    res44;  /* + 0x53 */
+    volatile uint8_t    rxdsr6; /* + 0x54 */
+    volatile uint8_t    rxdsr7; /* + 0x55 */
+    volatile uint8_t    res45;  /* + 0x56 */
+    volatile uint8_t    res46;  /* + 0x57 */
+    volatile uint8_t    rxdlr;  /* + 0x58 */
+    volatile uint8_t    res47;  /* + 0x59 */
+    volatile uint8_t    res48;  /* + 0x5A */
+    volatile uint8_t    res49;  /* + 0x5B */
+    volatile uint8_t    rxtimh; /* + 0x5C */
+    volatile uint8_t    rxtiml; /* + 0x5D */
+    volatile uint8_t    res50;  /* + 0x5E */
+    volatile uint8_t    res51;  /* + 0x5F */
+    volatile uint8_t    txidr0; /* + 0x60 */
+    volatile uint8_t    txidr1; /* + 0x61 */
+    volatile uint8_t    res52;  /* + 0x62 */
+    volatile uint8_t    res53;  /* + 0x63 */
+    volatile uint8_t    txidr2; /* + 0x64 */
+    volatile uint8_t    txidr3; /* + 0x65 */
+    volatile uint8_t    res54;  /* + 0x66 */
+    volatile uint8_t    res55;  /* + 0x67 */
+    volatile uint8_t    txdsr0; /* + 0x68 */
+    volatile uint8_t    txdsr1; /* + 0x69 */
+    volatile uint8_t    res56;  /* + 0x6A */
+    volatile uint8_t    res57;  /* + 0x6B */
+    volatile uint8_t    txdsr2; /* + 0x6C */
+    volatile uint8_t    txdsr3; /* + 0x6D */
+    volatile uint8_t    res58;  /* + 0x6E */
+    volatile uint8_t    res59;  /* + 0x6F */
+    volatile uint8_t    txdsr4; /* + 0x70 */
+    volatile uint8_t    txdsr5; /* + 0x71 */
+    volatile uint8_t    res60;  /* + 0x72 */
+    volatile uint8_t    res61;  /* + 0x73 */
+    volatile uint8_t    txdsr6; /* + 0x74 */
+    volatile uint8_t    txdsr7; /* + 0x75 */
+    volatile uint8_t    res62;  /* + 0x76 */
+    volatile uint8_t    res63;  /* + 0x77 */
+    volatile uint8_t    txdlr;  /* + 0x78 */
+    volatile uint8_t    txtbpr; /* + 0x79 */
+    volatile uint8_t    res64;  /* + 0x7A */
+    volatile uint8_t    res65;  /* + 0x7B */
+    volatile uint8_t    txtimh; /* + 0x7C */
+    volatile uint8_t    txtiml; /* + 0x7D */
+    volatile uint8_t    res66;  /* + 0x7E */
+    volatile uint8_t    res67;  /* + 0x7F */
+  } mscan[MPC5200_CAN_NO];
+
+  volatile uint8_t    res[0x100];
+
+  /*
+   * GPIO standard registers (MBAR + 0xB00)
+   */
+  volatile uint32_t gpiopcr;      /* + 0x00 */
+  #define GPIO_PCR_CHIP_SELECT_1          0x80000000
+  #define GPIO_PCR_CHIP_ALTS              0x30000000
+  #define GPIO_PCR_CHIP_ALTS_NONE         0x00000000
+  #define GPIO_PCR_CHIP_ALTS_CAN          0x10000000
+  #define GPIO_PCR_CHIP_ALTS_SPI          0x20000000
+  #define GPIO_PCR_CHIP_ALTS_BOTH         0x30000000
+  #define GPIO_PCR_CHIP_SELECT_7          0x08000000
+  #define GPIO_PCR_CHIP_SELECT_6          0x04000000
+  #define GPIO_PCR_CHIP_SELECT_ATA        0x03000000
+  #define GPIO_PCR_CHIP_SELECT_IR_USB_CLK 0x00800000
+  #define GPIO_PCR_IRDA                   0x00700000
+  #define GPIO_PCR_ETHERNET               0x000F0000
+  #define GPIO_PCR_PCI_DIS                0x00008000
+  #define GPIO_PCR_USB_SE                 0x00004000
+  #define GPIO_PCR_USB_GPIO               0x00003000
+  #define GPIO_PCR_PSC3                   0x00000F00
+  #define GPIO_PCR_PSC2                   0x00000070
+  #define GPIO_PCR_PSC1                   0x00000007
+
+  #define GPIO_S_PIN_IR_USB_CLK BSP_BBIT32(2)
+  #define GPIO_S_PIN_IRDA_TX BSP_BBIT32(3)
+  #define GPIO_S_PIN_ETH_11 BSP_BBIT32(4)
+  #define GPIO_S_PIN_ETH_10 BSP_BBIT32(5)
+  #define GPIO_S_PIN_ETH_9 BSP_BBIT32(6)
+  #define GPIO_S_PIN_ETH_8 BSP_BBIT32(7)
+  #define GPIO_S_PIN_USB1_8 BSP_BBIT32(12)
+  #define GPIO_S_PIN_USB1_7 BSP_BBIT32(13)
+  #define GPIO_S_PIN_USB1_6 BSP_BBIT32(14)
+  #define GPIO_S_PIN_USB1_0 BSP_BBIT32(15)
+  #define GPIO_S_PIN_PSC3_7 BSP_BBIT32(18)
+  #define GPIO_S_PIN_PSC3_6 BSP_BBIT32(19)
+  #define GPIO_S_PIN_PSC3_3 BSP_BBIT32(20)
+  #define GPIO_S_PIN_PSC3_2 BSP_BBIT32(21)
+  #define GPIO_S_PIN_PSC3_1 BSP_BBIT32(22)
+  #define GPIO_S_PIN_PSC3_0 BSP_BBIT32(23)
+  #define GPIO_S_PIN_PSC2_3 BSP_BBIT32(24)
+  #define GPIO_S_PIN_PSC2_2 BSP_BBIT32(25)
+  #define GPIO_S_PIN_PSC2_1 BSP_BBIT32(26)
+  #define GPIO_S_PIN_PSC2_0 BSP_BBIT32(27)
+  #define GPIO_S_PIN_PSC1_3 BSP_BBIT32(28)
+  #define GPIO_S_PIN_PSC1_2 BSP_BBIT32(29)
+  #define GPIO_S_PIN_PSC1_1 BSP_BBIT32(30)
+  #define GPIO_S_PIN_PSC1_0 BSP_BBIT32(31)
+
+  volatile uint32_t gpiosen;      /* + 0x04 */
+  volatile uint32_t gpiosod;      /* + 0x08 */
+  volatile uint32_t gpiosdd;      /* + 0x0C */
+  volatile uint32_t gpiosdo;      /* + 0x10 */
+  volatile uint32_t gpiosdi;      /* + 0x14 */
+
+  #define GPIO_O_PIN_ETH_7 BSP_BBIT32(0)
+  #define GPIO_O_PIN_ETH_6 BSP_BBIT32(1)
+  #define GPIO_O_PIN_ETH_5 BSP_BBIT32(2)
+  #define GPIO_O_PIN_ETH_4 BSP_BBIT32(3)
+  #define GPIO_O_PIN_ETH_3 BSP_BBIT32(4)
+  #define GPIO_O_PIN_ETH_2 BSP_BBIT32(5)
+  #define GPIO_O_PIN_ETH_1 BSP_BBIT32(6)
+  #define GPIO_O_PIN_ETH_0 BSP_BBIT32(7)
+  #define GPIO_O_PIN_I2C_3 BSP_BBIT32(13)
+  #define GPIO_O_PIN_I2C_0 BSP_BBIT32(14)
+  #define GPIO_O_PIN_I2C_1 BSP_BBIT32(15)
+
+  volatile uint32_t gpiooe;     /* + 0x18 */
+  volatile uint32_t gpioodo;      /* + 0x1C */
+
+  #define GPIO_I_PIN_ETH_16 BSP_BBIT32(0)
+  #define GPIO_I_PIN_ETH_15 BSP_BBIT32(1)
+  #define GPIO_I_PIN_ETH_14 BSP_BBIT32(2)
+  #define GPIO_I_PIN_ETH_13 BSP_BBIT32(3)
+  #define GPIO_I_PIN_USB1_9 BSP_BBIT32(4)
+  #define GPIO_I_PIN_PSC3_8 BSP_BBIT32(5)
+  #define GPIO_I_PIN_PSC3_5 BSP_BBIT32(6)
+  #define GPIO_I_PIN_PSC3_4 BSP_BBIT32(7)
+
+  volatile uint32_t gpiosie;      /* + 0x20 */
+  #define GPIO_SIE_SINT_7_ETH_16_PIN 0x80000000
+  #define GPIO_SIE_SINT_6_ETH_15_PIN 0x40000000
+  #define GPIO_SIE_SINT_5_ETH_14_PIN 0x20000000
+  #define GPIO_SIE_SINT_4_ETH_13_PIN 0x10000000
+  #define GPIO_SIE_SINT_3_USB1_9_PIN 0x08000000
+  #define GPIO_SIE_SINT_2_PSC3_8_PIN 0x04000000
+  #define GPIO_SIE_SINT_1_PSC3_5_PIN 0x02000000
+  #define GPIO_SIE_SINT_0_PSC3_4_PIN 0x01000000
+
+  volatile uint32_t gpiosiod;     /* + 0x24 */
+
+  volatile uint32_t gpiosidd;     /* + 0x28 */
+  #define GPIO_SIDD_SINT_7_ETH_16_PIN 0x80000000
+  #define GPIO_SIDD_SINT_6_ETH_15_PIN 0x40000000
+  #define GPIO_SIDD_SINT_5_ETH_14_PIN 0x20000000
+  #define GPIO_SIDD_SINT_4_ETH_13_PIN 0x10000000
+  #define GPIO_SIDD_SINT_3_USB1_9_PIN 0x08000000
+  #define GPIO_SIDD_SINT_2_PSC3_8_PIN 0x04000000
+  #define GPIO_SIDD_SINT_1_PSC3_5_PIN 0x02000000
+  #define GPIO_SIDD_SINT_0_PSC3_4_PIN 0x01000000
+
+  volatile uint32_t gpiosido;     /* + 0x2C */
+
+  volatile uint32_t gpiosiie;     /* + 0x30 */
+  #define GPIO_SIIE_SINT_7_ETH_16_PIN 0x80000000
+  #define GPIO_SIIE_SINT_6_ETH_15_PIN 0x40000000
+  #define GPIO_SIIE_SINT_5_ETH_14_PIN 0x20000000
+  #define GPIO_SIIE_SINT_4_ETH_13_PIN 0x10000000
+  #define GPIO_SIIE_SINT_3_USB1_9_PIN 0x08000000
+  #define GPIO_SIIE_SINT_2_PSC3_8_PIN 0x04000000
+  #define GPIO_SIIE_SINT_1_PSC3_5_PIN 0x02000000
+  #define GPIO_SIIE_SINT_0_PSC3_4_PIN 0x01000000
+
+  volatile uint32_t gpiosiit;     /* + 0x34 */
+  #define GPIO_SIIT_SET_ETH_16_PIN(reg, val) BSP_BFLD32SET(reg, val, 0, 1)
+  #define GPIO_SIIT_SET_ETH_15_PIN(reg, val) BSP_BFLD32SET(reg, val, 2, 3)
+  #define GPIO_SIIT_SET_ETH_14_PIN(reg, val) BSP_BFLD32SET(reg, val, 4, 5)
+  #define GPIO_SIIT_SET_ETH_13_PIN(reg, val) BSP_BFLD32SET(reg, val, 6, 7)
+  #define GPIO_SIIT_SET_USB1_9_PIN(reg, val) BSP_BFLD32SET(reg, val, 8, 9)
+  #define GPIO_SIIT_SET_PSC3_8_PIN(reg, val) BSP_BFLD32SET(reg, val, 10, 11)
+  #define GPIO_SIIT_SET_PSC3_5_PIN(reg, val) BSP_BFLD32SET(reg, val, 12, 13)
+  #define GPIO_SIIT_SET_PSC3_4_PIN(reg, val) BSP_BFLD32SET(reg, val, 14, 15)
+
+  #define GPIO_SIIT_SINT_7_ETH_16_PIN_MASK 0xc0000000
+  #define GPIO_SIIT_SINT_6_ETH_15_PIN_MASK 0x30000000
+  #define GPIO_SIIT_SINT_5_ETH_14_PIN_MASK 0x0c000000
+  #define GPIO_SIIT_SINT_4_ETH_13_PIN_MASK 0x03000000
+  #define GPIO_SIIT_SINT_3_USB1_9_PIN_MASK 0x00c00000
+  #define GPIO_SIIT_SINT_2_PSC3_8_PIN_MASK 0x00300000
+  #define GPIO_SIIT_SINT_1_PSC3_5_PIN_MASK 0x000c0000
+  #define GPIO_SIIT_SINT_0_PSC3_4_PIN_MASK 0x00030000
+
+  #define GPIO_SIIT_ON_ANY_TRANSITION      0x00000000
+  #define GPIO_SIIT_ON_RISING_EDGE         0x00000001
+  #define GPIO_SIIT_ON_FALLING_EDGE        0x00000002
+  #define GPIO_SIIT_ON_PULSE               0x00000003
+
+  #define GPIO_SIIT_SINT_7_ETH_16_PIN_SHIFT 16
+  #define GPIO_SIIT_SINT_6_ETH_15_PIN_SHIFT 18
+  #define GPIO_SIIT_SINT_5_ETH_14_PIN_SHIFT 20
+  #define GPIO_SIIT_SINT_4_ETH_13_PIN_SHIFT 22
+  #define GPIO_SIIT_SINT_3_USB1_9_PIN_SHIFT 24
+  #define GPIO_SIIT_SINT_2_PSC3_8_PIN_SHIFT 26
+  #define GPIO_SIIT_SINT_1_PSC3_5_PIN_SHIFT 28
+  #define GPIO_SIIT_SINT_0_PSC3_4_PIN_SHIFT 30
+
+  volatile uint32_t gpiosime;     /* + 0x38 */
+  #define GPIO_SIME_MASTER_ENABLE    0x10000000
+
+  volatile uint32_t gpiosist;     /* + 0x3C */
+  #define GPIO_SIST_SINT_7_ETH_16_PIN_STATUS 0x80000000
+  #define GPIO_SIST_SINT_6_ETH_15_PIN_STATUS 0x40000000
+  #define GPIO_SIST_SINT_5_ETH_14_PIN_STATUS 0x20000000
+  #define GPIO_SIST_SINT_4_ETH_13_PIN_STATUS 0x10000000
+  #define GPIO_SIST_SINT_3_USB1_9_PIN_STATUS 0x08000000
+  #define GPIO_SIST_SINT_2_PSC3_8_PIN_STATUS 0x04000000
+  #define GPIO_SIST_SINT_1_PSC3_5_PIN_STATUS 0x02000000
+  #define GPIO_SIST_SINT_0_PSC3_4_PIN_STATUS 0x01000000
+  #define GPIO_SIST_SINT_7_ETH_16_PIN_VALUE  0x00800000
+  #define GPIO_SIST_SINT_6_ETH_15_PIN_VALUE  0x00400000
+  #define GPIO_SIST_SINT_5_ETH_14_PIN_VALUE  0x00200000
+  #define GPIO_SIST_SINT_4_ETH_13_PIN_VALUE  0x00100000
+  #define GPIO_SIST_SINT_3_USB1_9_PIN_VALUE  0x00080000
+  #define GPIO_SIST_SINT_2_PSC3_8_PIN_VALUE  0x00040000
+  #define GPIO_SIST_SINT_1_PSC3_5_PIN_VALUE  0x00020000
+  #define GPIO_SIST_SINT_0_PSC3_4_PIN_VALUE  0x00010000
+
+  #define GPIO_SIST_SINT_CLEAR_ALL           0xff000000
+
+  volatile uint8_t  res4[0xC0];
+
+  /*
+   * GPIO wakeup registers (MBAR + 0xC00)
+   */
+
+  #define GPIO_W_PIN_GPIO_WKUP_7 BSP_BBIT32(0)
+  #define GPIO_W_PIN_GPIO_WKUP_6 BSP_BBIT32(1)
+  #define GPIO_W_PIN_PSC6_1 BSP_BBIT32(2)
+  #define GPIO_W_PIN_PSC6_0 BSP_BBIT32(3)
+  #define GPIO_W_PIN_ETH_17 BSP_BBIT32(4)
+  #define GPIO_W_PIN_PSC3_9 BSP_BBIT32(5)
+  #define GPIO_W_PIN_PSC2_4 BSP_BBIT32(6)
+  #define GPIO_W_PIN_PSC1_4 BSP_BBIT32(7)
+
+  volatile uint32_t gpiowe;     /* + 0x00 */
+  volatile uint32_t gpiowod;    /* + 0x04 */
+  volatile uint32_t gpiowdd;    /* + 0x08 */
+  volatile uint32_t gpiowdo;    /* + 0x0C */
+  volatile uint32_t gpiowue;    /* + 0x10 */
+  volatile uint32_t gpiowsie;   /* + 0x14 */
+  volatile uint32_t gpiowt;     /* + 0x18 */
+  volatile uint32_t gpiowme;    /* + 0x1C */
+  volatile uint32_t gpiowi;     /* + 0x20 */
+  volatile uint32_t gpiows;     /* + 0x24 */
+  volatile uint8_t  gpiow_res[0xD8];
+
+  /*
+   * PPC PCI registers (MBAR + 0xD00)
+   */
+  volatile uint8_t    ppci[0x100];
+
+  /*
+   * consumer infrared registers (MBAR + 0xE00)
+   */
+  volatile uint8_t    ir[0x100];
+
+  /*
+   * serial peripheral interface registers (MBAR + 0xF00)
+   */
+  volatile uint8_t    spi[0x100];
+
+  /*
+   * universal serial bus registers (MBAR + 0x1000)
+   */
+  volatile uint8_t    usb[0x200];
+
+  /*
+   * SmartComm DMA registers (MBAR + 0x1200)
+   */
+  volatile mpc5200_sdma sdma;
+
+  volatile uint32_t EU00;       /* + 0x80 sdMac macer reg */
+  volatile uint32_t EU01;       /* + 0x84 sdMac macemr reg */
+  volatile uint32_t EU02;       /* + 0x88 unused */
+  volatile uint32_t EU03;       /* + 0x8c unused */
+  volatile uint32_t EU04;       /* + 0x90 unused */
+  volatile uint32_t EU05;       /* + 0x94 unused */
+  volatile uint32_t EU06;       /* + 0x98 unused */
+  volatile uint32_t EU07;       /* + 0x9c unused */
+  volatile uint32_t EU10;       /* + 0xa0 unused */
+  volatile uint32_t EU11;       /* + 0xa4 unused */
+  volatile uint32_t EU12;       /* + 0xa8 unused */
+  volatile uint32_t EU13;       /* + 0xac unused */
+  volatile uint32_t EU14;       /* + 0xb0 unused */
+  volatile uint32_t EU15;       /* + 0xb4 unused */
+  volatile uint32_t EU16;       /* + 0xb8 unused */
+  volatile uint32_t EU17;       /* + 0xbc unused */
+  volatile uint32_t EU20;       /* + 0xc0 unused */
+  volatile uint32_t EU21;       /* + 0xc4 unused */
+  volatile uint32_t EU22;       /* + 0xc8 unused */
+  volatile uint32_t EU23;       /* + 0xcc unused */
+  volatile uint32_t EU24;       /* + 0xd0 unused */
+  volatile uint32_t EU25;       /* + 0xd4 unused */
+  volatile uint32_t EU26;       /* + 0xd8 unused */
+  volatile uint32_t EU27;       /* + 0xdc unused */
+  volatile uint32_t EU30;       /* + 0xe0 unused */
+  volatile uint32_t EU31;       /* + 0xe4 unused */
+  volatile uint32_t EU32;       /* + 0xe8 unused */
+  volatile uint32_t EU33;       /* + 0xec unused */
+  volatile uint32_t EU34;       /* + 0xf0 unused */
+  volatile uint32_t EU35;       /* + 0xf4 unused */
+  volatile uint32_t EU36;       /* + 0xf8 unused */
+  volatile uint32_t EU37;       /* + 0xfc unused */
+#if 0
+  volatile uint32_t res8[0x340];
+#else
+  volatile uint8_t res_1300[0xc00];
+
+  volatile uint32_t reserved0;        /* MBAR_XLB_ARB + 0x0000 reserved */
+  volatile uint32_t reserved1;        /* MBAR_XLB_ARB + 0x0004 reserved */
+  volatile uint32_t reserved2;        /* MBAR_XLB_ARB + 0x0008 reserved */
+  volatile uint32_t reserved3;        /* MBAR_XLB_ARB + 0x000c reserved */
+  volatile uint32_t reserved4;        /* MBAR_XLB_ARB + 0x0010 reserved */
+  volatile uint32_t reserved5;        /* MBAR_XLB_ARB + 0x0014 reserved */
+  volatile uint32_t reserved6;        /* MBAR_XLB_ARB + 0x0018 reserved */
+  volatile uint32_t reserved7;        /* MBAR_XLB_ARB + 0x001c reserved */
+  volatile uint32_t reserved8;        /* MBAR_XLB_ARB + 0x0020 reserved */
+  volatile uint32_t reserved9;        /* MBAR_XLB_ARB + 0x0024 reserved */
+  volatile uint32_t reserved10;       /* MBAR_XLB_ARB + 0x0028 reserved */
+  volatile uint32_t reserved11;       /* MBAR_XLB_ARB + 0x002c reserved */
+  volatile uint32_t reserved12;       /* MBAR_XLB_ARB + 0x0030 reserved */
+  volatile uint32_t reserved13;       /* MBAR_XLB_ARB + 0x0034 reserved */
+  volatile uint32_t reserved14;       /* MBAR_XLB_ARB + 0x0038 reserved */
+  volatile uint32_t reserved15;       /* MBAR_XLB_ARB + 0x003c reserved */
+
+#define XLB_CFG_PLDIS BSP_BBIT32(0)
+#define XLB_CFG_BSDIS BSP_BBIT32(15)
+#define XLB_CFG_SE BSP_BBIT32(16)
+#define XLB_CFG_USE_WWF BSP_BBIT32(17)
+#define XLB_CFG_TBEN BSP_BBIT32(18)
+#define XLB_CFG_WS BSP_BBIT32(20)
+#define XLB_CFG_SP(val) BSP_BFLD32(val, 21, 23)
+#define XLB_CFG_SET_SP(reg, val) BSP_BFLD32SET(reg, val, 21, 23)
+#define XLB_CFG_PM(val) BSP_BFLD32(val, 25, 26)
+#define XLB_CFG_SET_PM(reg, val) BSP_BFLD32SET(reg, val, 25, 26)
+#define XLB_CFG_BA BSP_BBIT32(28)
+#define XLB_CFG_DT BSP_BBIT32(29)
+#define XLB_CFG_AT BSP_BBIT32(30)
+
+  volatile uint32_t config;           /* MBAR_XLB_ARB + 0x0040 */
+  volatile uint32_t version;          /* MBAR_XLB_ARB + 0x0044 */
+
+#define XLB_ST_SEA BSP_BBIT32(23)
+#define XLB_ST_MM BSP_BBIT32(24)
+#define XLB_ST_TTA BSP_BBIT32(25)
+#define XLB_ST_TTR BSP_BBIT32(26)
+#define XLB_ST_ECW BSP_BBIT32(27)
+#define XLB_ST_TTM BSP_BBIT32(28)
+#define XLB_ST_BA BSP_BBIT32(29)
+#define XLB_ST_DT BSP_BBIT32(30)
+#define XLB_ST_AT BSP_BBIT32(31)
+                                      /*             read only = 0x0001 */
+  volatile uint32_t xlb_status;       /* MBAR_XLB_ARB + 0x0048 */
+  volatile uint32_t int_enable;       /* MBAR_XLB_ARB + 0x004c */
+  volatile uint32_t add_capture;      /* MBAR_XLB_ARB + 0x0050 read only */
+  volatile uint32_t bus_sig_capture;  /* MBAR_XLB_ARB + 0x0054 read only */
+  volatile uint32_t add_time_out;     /* MBAR_XLB_ARB + 0x0058 */
+  volatile uint32_t data_time_out;    /* MBAR_XLB_ARB + 0x005c */
+  volatile uint32_t bus_time_out;     /* MBAR_XLB_ARB + 0x0060 */
+  volatile uint32_t priority_enable;  /* MBAR_XLB_ARB + 0x0064 */
+  volatile uint32_t priority;         /* MBAR_XLB_ARB + 0x0068 */
+  volatile uint32_t arb_base_addr2;   /* MBAR_XLB_ARB + 0x006c */
+  volatile uint32_t snoop_window;     /* MBAR_XLB_ARB + 0x0070 */
+
+  volatile uint32_t reserved16;       /* MBAR_XLB_ARB + 0x0074 reserved */
+  volatile uint32_t reserved17;       /* MBAR_XLB_ARB + 0x0078 reserved */
+  volatile uint32_t reserved18;       /* MBAR_XLB_ARB + 0x007c reserved */
+
+  volatile uint32_t control;          /* MBAR_XLB_ARB + 0x0080 */
+  volatile uint32_t init_total_count; /* MBAR_XLB_ARB + 0x0084 */
+  volatile uint32_t int_total_count;  /* MBAR_XLB_ARB + 0x0088 */
+
+  volatile uint32_t reserved19;       /* MBAR_XLB_ARB + 0x008c reserved */
+
+  volatile uint32_t lower_address;    /* MBAR_XLB_ARB + 0x0090 */
+  volatile uint32_t higher_address;   /* MBAR_XLB_ARB + 0x0094 */
+  volatile uint32_t int_window_count; /* MBAR_XLB_ARB + 0x0098 */
+  volatile uint32_t window_ter_count; /* MBAR_XLB_ARB + 0x009c */
+    volatile uint8_t  res_0x1fa0[0x60];
+
+
+#endif
+  /*
+  * programmable serial controller 1 (MBAR + 0x2000)
+  */
+
+  struct mpc5200_psc {
+    volatile uint8_t  mr;            /* + 0x00 */
+    volatile uint8_t  res1[3];
+    volatile uint16_t sr_csr;        /* + 0x04 */
+    volatile uint16_t res2[1];
+    volatile uint16_t cr;            /* + 0x08 */
+    volatile uint16_t res3[1];
+    volatile uint32_t rb_tb;         /* + 0x0c */
+    volatile uint16_t ipcr_acr;      /* + 0x10 */
+    volatile uint16_t res4[1];
+    volatile uint16_t isr_imr;       /* + 0x14 */
+#define ISR_TX_RDY      (1 << 8)
+#define ISR_RX_RDY_FULL (1 << 9)
+#define ISR_RB      (1 << 15)
+#define ISR_FE          (1 << 14)
+#define ISR_PE          (1 << 13)
+#define ISR_OE          (1 << 12)
+#define ISR_ERROR       (ISR_FE | ISR_PE | ISR_OE)
+
+#define IMR_TX_RDY      (1 << 8)
+#define IMR_RX_RDY_FULL (1 << 9)
+    volatile uint16_t res5[1];
+    volatile uint8_t  ctur;          /* + 0x18 */
+    volatile uint8_t  res6[3];
+    volatile uint8_t  ctlr;          /* + 0x1C */
+    volatile uint8_t  res7[0x13];
+    volatile uint8_t  ivr;           /* + 0x30 */
+    volatile uint8_t  res8[3];
+    volatile uint8_t  ip;            /* + 0x34 */
+    volatile uint8_t  res9[3];
+    volatile uint8_t  op1;           /* + 0x38 */
+    volatile uint8_t  res10[3];
+    volatile uint8_t  op0;           /* + 0x3C */
+    volatile uint8_t  res11[3];
+    volatile uint8_t  sicr;          /* + 0x40 */
+    volatile uint8_t  res12[0x17];
+    volatile uint16_t rfnum;         /* + 0x58 */
+    volatile uint16_t res13[1];
+    volatile uint16_t tfnum;         /* + 0x5C */
+    volatile uint16_t res14[1];
+    volatile uint16_t rfdata;        /* + 0x60 */
+    volatile uint16_t res15[1];
+    volatile uint16_t rfstat;        /* + 0x64 */
+    volatile uint16_t res16[1];
+    volatile uint8_t  rfcntl;        /* + 0x68 */
+    volatile uint8_t  res17[5];
+    volatile uint16_t rfalarm;       /* + 0x6E */
+    volatile uint8_t  res18[2];
+    volatile uint16_t rfrptr;        /* + 0x72 */
+    volatile uint16_t res19[1];
+    volatile uint16_t rfwptr;        /* + 0x76 */
+    volatile uint16_t res20[1];
+    volatile uint16_t rflrfptr;      /* + 0x7A */
+    volatile uint16_t rflwfptr;      /* + 0x7C */
+    volatile uint16_t res21[1];
+    volatile uint16_t tfdata;        /* + 0x80 */
+    volatile uint16_t res22[1];
+    volatile uint16_t tfstat;        /* + 0x84 */
+    volatile uint16_t res23[1];
+    volatile uint8_t  tfcntl;        /* + 0x88 */
+    volatile uint8_t  res24[5];
+    volatile uint16_t tfalarm;       /* + 0x8E */
+    volatile uint8_t  res25[2];
+    volatile uint16_t tfrptr;        /* + 0x92 */
+    volatile uint16_t res26[1];
+    volatile uint16_t tfwptr;        /* + 0x96 */
+    volatile uint16_t res27[1];
+    volatile uint16_t tflrfptr;      /* + 0x96 */
+    volatile uint16_t tflwfptr;      /* + 0x9C */
+    volatile uint16_t res28[1];      /* end at offset 0x9F */
+    volatile uint8_t  res29[0x160];
+  } psc[MPC5200_PSC_REG_SETS];
+  /* XXX: there are only 6 PSCs, but PSC6 has an extra register gap
+   *      from PSC5, therefore we instantiate seven(!) PSC register sets
+   */
+
+#define TX_FIFO_SIZE    256
+#define RX_FIFO_SIZE    512
+
+
+  volatile uint8_t   irda[0x200];
+
+  /*
+   * ethernet registers (MBAR + 0x3000)
+   */
+
+  /*  Control and status Registers (offset 000-1FF) */
+
+  volatile uint32_t fec_id;          /* + 0x000 */
+  volatile uint32_t ievent;          /* + 0x004 */
+  volatile uint32_t imask;           /* + 0x008 */
+
+  volatile uint32_t res9[1];         /* + 0x00C */
+  volatile uint32_t r_des_active;    /* + 0x010 */
+  volatile uint32_t x_des_active;    /* + 0x014 */
+  volatile uint32_t r_des_active_cl; /* + 0x018 */
+  volatile uint32_t x_des_active_cl; /* + 0x01C */
+  volatile uint32_t ivent_set;       /* + 0x020 */
+  volatile uint32_t ecntrl;          /* + 0x024 */
+
+  volatile uint32_t res10[6];        /* + 0x028-03C */
+  volatile uint32_t mii_data;        /* + 0x040 */
+  volatile uint32_t mii_speed;       /* + 0x044 */
+  volatile uint32_t mii_status;      /* + 0x048 */
+
+  volatile uint32_t res11[5];        /* + 0x04C-05C */
+  volatile uint32_t mib_data;        /* + 0x060 */
+  volatile uint32_t mib_control;     /* + 0x064 */
+
+  volatile uint32_t res12[6];        /* + 0x068-7C */
+  volatile uint32_t r_activate;      /* + 0x080 */
+  volatile uint32_t r_cntrl;         /* + 0x084 */
+  volatile uint32_t r_hash;          /* + 0x088 */
+  volatile uint32_t r_data;          /* + 0x08C */
+  volatile uint32_t ar_done;         /* + 0x090 */
+  volatile uint32_t r_test;          /* + 0x094 */
+  volatile uint32_t r_mib;           /* + 0x098 */
+  volatile uint32_t r_da_low;        /* + 0x09C */
+  volatile uint32_t r_da_high;       /* + 0x0A0 */
+
+  volatile uint32_t res13[7];        /* + 0x0A4-0BC */
+  volatile uint32_t x_activate;      /* + 0x0C0 */
+  volatile uint32_t x_cntrl;         /* + 0x0C4 */
+  volatile uint32_t backoff;         /* + 0x0C8 */
+  volatile uint32_t x_data;          /* + 0x0CC */
+  volatile uint32_t x_status;        /* + 0x0D0 */
+  volatile uint32_t x_mib;           /* + 0x0D4 */
+  volatile uint32_t x_test;          /* + 0x0D8 */
+  volatile uint32_t fdxfc_da1;       /* + 0x0DC */
+  volatile uint32_t fdxfc_da2;       /* + 0x0E0 */
+  volatile uint32_t paddr1;          /* + 0x0E4 */
+  volatile uint32_t paddr2;          /* + 0x0E8 */
+  volatile uint32_t op_pause;        /* + 0x0EC */
+
+  volatile uint32_t res14[4];        /* + 0x0F0-0FC */
+  volatile uint32_t instr_reg;       /* + 0x100 */
+  volatile uint32_t context_reg;     /* + 0x104 */
+  volatile uint32_t test_cntrl;      /* + 0x108 */
+  volatile uint32_t acc_reg;         /* + 0x10C */
+  volatile uint32_t ones;            /* + 0x110 */
+  volatile uint32_t zeros;           /* + 0x114 */
+  volatile uint32_t iaddr1;          /* + 0x118 */
+  volatile uint32_t iaddr2;          /* + 0x11C */
+  volatile uint32_t gaddr1;          /* + 0x120 */
+  volatile uint32_t gaddr2;          /* + 0x124 */
+  volatile uint32_t random;          /* + 0x128 */
+  volatile uint32_t rand1;           /* + 0x12C */
+  volatile uint32_t tmp;             /* + 0x130 */
+
+  volatile uint32_t res15[3];        /* + 0x134-13C */
+  volatile uint32_t fifo_id;         /* + 0x140 */
+  volatile uint32_t x_wmrk;          /* + 0x144 */
+  volatile uint32_t fcntrl;          /* + 0x148 */
+  volatile uint32_t r_bound;         /* + 0x14C */
+  volatile uint32_t r_fstart;        /* + 0x150 */
+  volatile uint32_t r_count;         /* + 0x154 */
+  volatile uint32_t r_lag;           /* + 0x158 */
+  volatile uint32_t r_read;          /* + 0x15C */
+  volatile uint32_t r_write;         /* + 0x160 */
+  volatile uint32_t x_count;         /* + 0x164 */
+  volatile uint32_t x_lag;           /* + 0x168 */
+  volatile uint32_t x_retry;         /* + 0x16C */
+  volatile uint32_t x_write;         /* + 0x170 */
+  volatile uint32_t x_read;          /* + 0x174 */
+
+  volatile uint32_t res16[2];        /* + 0x178-17C */
+  volatile uint32_t fm_cntrl;        /* + 0x180 */
+  volatile uint32_t rfifo_data;      /* + 0x184 */
+  volatile uint32_t rfifo_status;    /* + 0x188 */
+  volatile uint32_t rfifo_cntrl;     /* + 0x18C */
+  volatile uint32_t rfifo_lrf_ptr;   /* + 0x190 */
+  volatile uint32_t rfifo_lwf_ptr;   /* + 0x194 */
+  volatile uint32_t rfifo_alarm;     /* + 0x198 */
+  volatile uint32_t rfifo_rdptr;     /* + 0x19C */
+  volatile uint32_t rfifo_wrptr;     /* + 0x1A0 */
+  volatile uint32_t tfifo_data;      /* + 0x1A4 */
+  volatile uint32_t tfifo_status;    /* + 0x1A8 */
+  volatile uint32_t tfifo_cntrl;     /* + 0x1AC */
+  volatile uint32_t tfifo_lrf_ptr;   /* + 0x1B0 */
+  volatile uint32_t tfifo_lwf_ptr;   /* + 0x1B4 */
+  volatile uint32_t tfifo_alarm;     /* + 0x1B8 */
+  volatile uint32_t tfifo_rdptr;     /* + 0x1BC */
+  volatile uint32_t tfifo_wrptr;     /* + 0x1C0 */
+
+  volatile uint32_t reset_cntrl;     /* + 0x1C4 */
+  volatile uint32_t xmit_fsm;        /* + 0x1C8 */
+
+  volatile uint32_t res17[3];        /* + 0x1CC-1D4 */
+  volatile uint32_t rdes_data0;      /* + 0x1D8 */
+  volatile uint32_t rdes_data1;      /* + 0x1DC */
+  volatile uint32_t r_length;        /* + 0x1E0 */
+  volatile uint32_t x_length;        /* + 0x1E4 */
+  volatile uint32_t x_addr;          /* + 0x1E8 */
+  volatile uint32_t cdes_data;       /* + 0x1EC */
+  volatile uint32_t status;          /* + 0x1F0 */
+  volatile uint32_t dma_control;     /* + 0x1F4 */
+  volatile uint32_t des_cmnd;        /* + 0x1F8 */
+  volatile uint32_t data;            /* + 0x1FC */
+
+  volatile uint8_t  RES[0x600];
+
+
+#if 0
+  /* MIB COUNTERS (Offset 200-2FF) */
+
+  volatile uint32_t rmon_t_drop;        /* + 0x200 */
+  volatile uint32_t rmon_t_packets;     /* + 0x204 */
+  volatile uint32_t rmon_t_bc_pkt;      /* + 0x208 */
+  volatile uint32_t rmon_t_mc_pkt;      /* + 0x20C */
+  volatile uint32_t rmon_t_crc_align;   /* + 0x210 */
+  volatile uint32_t rmon_t_undersize;   /* + 0x214 */
+  volatile uint32_t rmon_t_oversize;    /* + 0x218 */
+  volatile uint32_t rmon_t_frag;        /* + 0x21C */
+  volatile uint32_t rmon_t_jab;         /* + 0x220 */
+  volatile uint32_t rmon_t_col;         /* + 0x224 */
+  volatile uint32_t rmon_t_p64;         /* + 0x228 */
+  volatile uint32_t rmon_t_p65to127;    /* + 0x22C */
+  volatile uint32_t rmon_t_p128to255;   /* + 0x230 */
+  volatile uint32_t rmon_t_p256to511;   /* + 0x234 */
+  volatile uint32_t rmon_t_p512to1023;  /* + 0x238 */
+  volatile uint32_t rmon_t_p1024to2047; /* + 0x23C */
+  volatile uint32_t rmon_t_p_gte2048;   /* + 0x240 */
+  volatile uint32_t rmon_t_octets;      /* + 0x244 */
+  volatile uint32_t ieee_t_drop;        /* + 0x248 */
+  volatile uint32_t ieee_t_frame_ok;    /* + 0x24C */
+  volatile uint32_t ieee_t_1col;        /* + 0x250 */
+  volatile uint32_t ieee_t_mcol;        /* + 0x254 */
+  volatile uint32_t ieee_t_def;         /* + 0x258 */
+  volatile uint32_t ieee_t_lcol;        /* + 0x25C */
+  volatile uint32_t ieee_t_excol;       /* + 0x260 */
+  volatile uint32_t ieee_t_macerr;      /* + 0x264 */
+  volatile uint32_t ieee_t_cserr;       /* + 0x268 */
+  volatile uint32_t ieee_t_sqe;         /* + 0x26C */
+  volatile uint32_t t_fdxfc;            /* + 0x270 */
+  volatile uint32_t ieee_t_octets_ok;   /* + 0x274 */
+
+  volatile uint32_t res18[2];           /* + 0x278-27C */
+  volatile uint32_t rmon_r_drop;        /* + 0x280 */
+  volatile uint32_t rmon_r_packets;     /* + 0x284 */
+  volatile uint32_t rmon_r_bc_pkt;      /* + 0x288 */
+  volatile uint32_t rmon_r_mc_pkt;      /* + 0x28C */
+  volatile uint32_t rmon_r_crc_align;   /* + 0x290 */
+  volatile uint32_t rmon_r_undersize;   /* + 0x294 */
+  volatile uint32_t rmon_r_oversize;    /* + 0x298 */
+  volatile uint32_t rmon_r_frag;        /* + 0x29C */
+  volatile uint32_t rmon_r_jab;         /* + 0x2A0 */
+
+  volatile uint32_t rmon_r_resvd_0;     /* + 0x2A4 */
+
+  volatile uint32_t rmon_r_p64;         /* + 0x2A8 */
+  volatile uint32_t rmon_r_p65to127;    /* + 0x2AC */
+  volatile uint32_t rmon_r_p128to255;   /* + 0x2B0 */
+  volatile uint32_t rmon_r_p256to511;   /* + 0x2B4 */
+  volatile uint32_t rmon_r_p512to1023;  /* + 0x2B8 */
+  volatile uint32_t rmon_r_p1024to2047; /* + 0x2BC */
+  volatile uint32_t rmon_r_p_gte2048;   /* + 0x2C0 */
+  volatile uint32_t rmon_r_octets;      /* + 0x2C4 */
+  volatile uint32_t ieee_r_drop;        /* + 0x2C8 */
+  volatile uint32_t ieee_r_frame_ok;    /* + 0x2CC */
+  volatile uint32_t ieee_r_crc;         /* + 0x2D0 */
+  volatile uint32_t ieee_r_align;       /* + 0x2D4 */
+  volatile uint32_t r_macerr;           /* + 0x2D8 */
+  volatile uint32_t r_fdxfc;            /* + 0x2DC */
+  volatile uint32_t ieee_r_octets_ok;   /* + 0x2E0 */
+
+  volatile uint32_t res19[6];           /* + 0x2E4-2FC */
+
+  volatile uint32_t res20[64];          /* + 0x300-3FF */
+
+  volatile uint32_t res21[256];         /* + 0x400-800 */
+#endif
+
+  /*
+   * SmartComm DMA PCI registers (MBAR + 0x3800)
+   */
+  volatile uint8_t    pci[0x200];
+
+  /*
+   * advanced technology attachment registers (MBAR + 0x3A00)
+   */
+
+  /* ATA host registers (offset 0x00-0x28) */
+  volatile uint32_t ata_hcfg;     /* + 0x00 */
+  volatile uint32_t ata_hsr;      /* + 0x04 */
+  volatile uint32_t ata_pio1;     /* + 0x08 */
+  volatile uint32_t ata_pio2;     /* + 0x0C */
+  volatile uint32_t ata_dma1;     /* + 0x10 */
+  volatile uint32_t ata_dma2;     /* + 0x14 */
+  volatile uint32_t ata_udma1;    /* + 0x18 */
+  volatile uint32_t ata_udma2;    /* + 0x1C */
+  volatile uint32_t ata_udma3;    /* + 0x20 */
+  volatile uint32_t ata_udma4;    /* + 0x24 */
+  volatile uint32_t ata_udma5;    /* + 0x28 */
+  volatile uint32_t ata_res1[4];  /* + 0x2C-0x3C */
+
+  /* ATA FIFO registers (offset 0x3C-0x50) */
+  volatile uint32_t ata_rtfdwr;   /* + 0x3C */
+
+#define ATA_RTFSR_ERR BSP_BBIT32(9)
+#define ATA_RTFSR_UF BSP_BBIT32(10)
+#define ATA_RTFSR_OF BSP_BBIT32(11)
+#define ATA_RTFSR_FULL BSP_BBIT32(12)
+#define ATA_RTFSR_HI BSP_BBIT32(13)
+#define ATA_RTFSR_LO BSP_BBIT32(14)
+#define ATA_RTFSR_EMPTY BSP_BBIT32(15)
+
+  volatile uint32_t ata_rtfsr;    /* + 0x40 */
+
+#define ATA_RTFCR_WFR BSP_BBIT32(2)
+#define ATA_RTFCR_GR(val) BSP_BFLD32(val, 5, 7)
+
+  volatile uint32_t ata_rtfcr;    /* + 0x44 */
+  volatile uint32_t ata_rtfar;    /* + 0x48 */
+  volatile uint32_t ata_rtfrpr;   /* + 0x4C */
+  volatile uint32_t ata_rtfwpr;   /* + 0x50 */
+  volatile uint32_t ata_res2[2];  /* + 0x54-0x5C */
+
+  /* ATA drive registers (offset 0x5C-0x80) */
+  volatile uint32_t ata_dctr_dasr;  /* + 0x5C */
+  volatile uint32_t ata_ddr;        /* + 0x60 */
+  volatile uint32_t ata_dfr_der;    /* + 0x64 */
+  volatile uint32_t ata_dscr;       /* + 0x68 */
+  volatile uint32_t ata_dsnr;       /* + 0x6C */
+  volatile uint32_t ata_dclr;       /* + 0x70 */
+  volatile uint32_t ata_dchr;       /* + 0x74 */
+  volatile uint32_t ata_ddhr;       /* + 0x78 */
+  volatile uint32_t ata_dcr_dsr;    /* + 0x7C */
+  volatile uint32_t ata_res3[0xA0]; /* + 0x80-0x200 */
+
+  /*
+   * inter-integrated circuit registers (MBAR + 0x3D00)
+   */
+  struct mpc5200_i2c_regs_s {
+    volatile uint8_t  madr;   /* i2c address reg.       + 0x00 */
+    volatile uint8_t  res_1[3];
+    volatile uint8_t  mfdr;   /* i2c freq. divider reg. + 0x04 */
+    volatile uint8_t  res_5[3];
+    volatile uint8_t  mcr;    /* i2c control reg.       + 0x08 */
+    volatile uint8_t  res_9[3];
+
+#define MPC5200_I2C_MCR_MEN    (1 << (7-0))
+#define MPC5200_I2C_MCR_MIEN   (1 << (7-1))
+#define MPC5200_I2C_MCR_MSTA   (1 << (7-2))
+#define MPC5200_I2C_MCR_MTX    (1 << (7-3))
+#define MPC5200_I2C_MCR_TXAK   (1 << (7-4))
+#define MPC5200_I2C_MCR_RSTA   (1 << (7-5))
+
+      volatile uint8_t  msr;    /* i2c status reg.        + 0x0C */
+      volatile uint8_t  res_d[3];
+#define MPC5200_I2C_MSR_CF    (1 << (7-0))
+#define MPC5200_I2C_MSR_MAAS  (1 << (7-1))
+#define MPC5200_I2C_MSR_BB    (1 << (7-2))
+#define MPC5200_I2C_MSR_MAL   (1 << (7-3))
+#define MPC5200_I2C_MSR_SRW   (1 << (7-5))
+#define MPC5200_I2C_MSR_MIF   (1 << (7-6))
+#define MPC5200_I2C_MSR_RXAK  (1 << (7-7))
+      volatile uint8_t  mdr;    /* i2c data I/O reg.      + 0x10 */
+      volatile uint8_t  res_11[3];
+      volatile uint8_t  res_14[12];  /* reserved          + 0x14 */
+      volatile uint8_t  icr;   /* i2c irq ctrl reg.      + 0x20 */
+#define MPC5200_I2C_ICR_BNBE2  (1 << (7-0))
+#define MPC5200_I2C_ICR_TE2    (1 << (7-1))
+#define MPC5200_I2C_ICR_RE2    (1 << (7-2))
+#define MPC5200_I2C_ICR_IE2    (1 << (7-3))
+#define MPC5200_I2C_ICR_MASK2  (MPC5200_I2C_ICR_BNBE2|MPC5200_I2C_ICR_TE2\
+                               |MPC5200_I2C_ICR_RE2|MPC5200_I2C_ICR_IE2)
+#define MPC5200_I2C_ICR_BNBE1  (1 << (7-4))
+#define MPC5200_I2C_ICR_TE1    (1 << (7-5))
+#define MPC5200_I2C_ICR_RE1    (1 << (7-6))
+#define MPC5200_I2C_ICR_IE1    (1 << (7-7))
+#define MPC5200_I2C_ICR_MASK1  (MPC5200_I2C_ICR_BNBE1|MPC5200_I2C_ICR_TE1\
+                               |MPC5200_I2C_ICR_RE1|MPC5200_I2C_ICR_IE1)
+      volatile uint8_t  res_21[3];
+      volatile uint32_t res_24[7];   /* reserved          + 0x24 */
+    } i2c_regs[2];
+    volatile uint8_t    res_3d80[0x280];
+
+  /*
+   * on-chip static RAM memory locations (MBAR + 0x4000)
+   */
+  volatile uint8_t    sram_res0x4000[0x4000];
+  volatile uint8_t    sram[0x4000];
+
+} mpc5200_t;
+
+extern volatile mpc5200_t mpc5200;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /*ASM*/
+
+#endif /* __MPC5200_h__ */
diff --git a/bsps/powerpc/gen5200/include/bsp/mscan-base.h b/bsps/powerpc/gen5200/include/bsp/mscan-base.h
new file mode 100644
index 0000000000..a2b8737d8e
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/mscan-base.h
@@ -0,0 +1,284 @@
+/**
+ * @file
+ *
+ * @ingroup m
+ *
+ * @brief MSCAN register definitions and support functions.
+ */
+
+/*
+ * Copyright (c) 2008
+ * Embedded Brains GmbH
+ * Obere Lagerstr. 30
+ * D-82178 Puchheim
+ * Germany
+ * rtems@embedded-brains.de
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_MSCAN_BASE_H
+#define LIBBSP_MSCAN_BASE_H
+
+#include <stdbool.h>
+
+#include <bsp/mpc5200.h>
+
+/**
+ * @defgroup m MSCAN
+ *
+ * @{
+ */
+
+#define MSCAN_BIT_RATE_MIN 10000
+
+#define MSCAN_BIT_RATE_MAX 1000000
+
+#define MSCAN_BIT_RATE_DEFAULT 125000
+
+#define MSCAN_FILTER_NUMBER_MIN 0
+
+#define MSCAN_FILTER_NUMBER_2 2
+
+#define MSCAN_FILTER_NUMBER_4 4
+
+#define MSCAN_FILTER_NUMBER_MAX 8
+
+#define MSCAN_FILTER_ID_DEFAULT 0U
+
+#define MSCAN_FILTER_MASK_DEFAULT 0xffffffffU
+
+#define MSCAN_TRANSMIT_BUFFER_NUMBER 3
+
+/**
+ * @name MSCAN Control Register 0 (CANCTL0)
+ *
+ * @{
+ */
+
+#define CTL0_RXFRM               (1 << 7)
+#define CTL0_RXACT               (1 << 6)
+#define CTL0_CSWAI               (1 << 5)
+#define CTL0_SYNCH               (1 << 4)
+#define CTL0_TIME                (1 << 3)
+#define CTL0_WUPE                (1 << 2)
+#define CTL0_SLPRQ               (1 << 1)
+#define CTL0_INITRQ              (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Control Register 1 (CANCTL1)
+ *
+ * @{
+ */
+
+#define CTL1_CANE                (1 << 7)
+#define CTL1_CLKSRC              (1 << 6)
+#define CTL1_LOOPB               (1 << 5)
+#define CTL1_LISTEN              (1 << 4)
+#define CTL1_WUPM                (1 << 2)
+#define CTL1_SLPAK               (1 << 1)
+#define CTL1_INITAK              (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Bus Timing Register 0 (CANBTR0)
+ *
+ * @{
+ */
+
+#define BTR0_SJW_MASK            0xc0
+#define BTR0_BRP_MASK            0x3f
+
+#define BTR0_SJW( btr0)          ((btr0) << 6)
+#define BTR0_BRP( btr0)          ((btr0) << 0)
+
+#define BTR0_GET_SJW( btr0)      (((btr0) & BTR0_SJW_MASK) >> 6)
+#define BTR0_GET_BRP( btr0)      (((btr0) & BTR0_BRP_MASK) >> 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Bus Timing Register 1 (CANBTR1)
+ *
+ * @{
+ */
+
+#define BTR1_SAMP_MASK           0x80
+#define BTR1_TSEG1_MASK          0x0f
+#define BTR1_TSEG2_MASK          0x70
+
+#define BTR1_SAMP                (1 << 7)
+#define BTR1_TSEG1( btr1)        ((btr1) << 0)
+#define BTR1_TSEG2( btr1)        ((btr1) << 4)
+
+#define BTR1_GET_TSEG1( btr0)    (((btr0) & BTR1_TSEG1_MASK) >> 0)
+#define BTR1_GET_TSEG2( btr0)    (((btr0) & BTR1_TSEG2_MASK) >> 4)
+
+/** @} */
+
+/**
+ * @name MSCAN Receiver Flag Register (CANRFLG)
+ *
+ * @{
+ */
+
+#define RFLG_WUPIF               (1 << 7)
+#define RFLG_CSCIF               (1 << 6)
+#define RFLG_RSTAT_MASK          (3 << 4)
+#define RFLG_RSTAT_OK            (0 << 4)
+#define RFLG_RSTAT_WRN           (1 << 4)
+#define RFLG_RSTAT_ERR           (2 << 4)
+#define RFLG_RSTAT_OFF           (3 << 4)
+#define RFLG_TSTAT_MASK          (3 << 2)
+#define RFLG_TSTAT_OK            (0 << 2)
+#define RFLG_TSTAT_WRN           (1 << 2)
+#define RFLG_TSTAT_ERR           (2 << 2)
+#define RFLG_TSTAT_OFF           (3 << 2)
+#define RFLG_OVRIF               (1 << 1)
+#define RFLG_RXF                 (1 << 0)
+#define RFLG_GET_RX_STATE(rflg)  (((rflg) >> 4) & 0x03)
+#define RFLG_GET_TX_STATE(rflg)  (((rflg) >> 2) & 0x03)
+
+/** @} */
+
+/**
+ * @name MSCAN Receiver Interrupt Enable Register (CANRIER)
+ *
+ * @{
+ */
+
+#define RIER_WUPIE               (1 << 7)
+#define RIER_CSCIE               (1 << 6)
+#define RIER_RSTAT(rier)         ((rier) << 4)
+#define RIER_TSTAT(rier)         ((rier) << 2)
+#define RIER_OVRIE               (1 << 1)
+#define RIER_RXFIE               (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Transmitter Flag Register (CANTFLG)
+ *
+ * @{
+ */
+
+#define TFLG_TXE2                (1 << 2)
+#define TFLG_TXE1                (1 << 1)
+#define TFLG_TXE0                (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Transmitter Interrupt Enable Register (CANTIER)
+ *
+ * @{
+ */
+
+#define TIER_TXEI2               (1 << 2)
+#define TIER_TXEI1               (1 << 1)
+#define TIER_TXEI0               (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Transmitter Message Abort Request (CANTARQ)
+ *
+ * @{
+ */
+
+#define TARQ_ABTRQ2              (1 << 2)
+#define TARQ_ABTRQ1              (1 << 1)
+#define TARQ_ABTRQ0              (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Transmitter Message Abort Acknoledge (CANTAAK)
+ *
+ * @{
+ */
+
+#define TAAK_ABTRQ2              (1 << 2)
+#define TAAK_ABTRQ1              (1 << 1)
+#define TAAK_ABTRQ0              (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN Transmit Buffer Selection (CANBSEL)
+ *
+ * @{
+ */
+
+#define BSEL_TX2                 (1 << 2)
+#define BSEL_TX1                 (1 << 1)
+#define BSEL_TX0                 (1 << 0)
+
+/** @} */
+
+/**
+ * @name MSCAN ID Acceptance Control Register (CANIDAC)
+ *
+ * @{
+ */
+
+#define IDAC_IDAM1               (1 << 5)
+#define IDAC_IDAM0               (1 << 4)
+#define IDAC_IDAM                (IDAC_IDAM1 | IDAC_IDAM0)
+#define IDAC_IDHIT( idac)        ((idac) & 0x7)
+
+/** @} */
+
+/**
+ * @brief MSCAN registers.
+ */
+typedef struct mpc5200_mscan mscan;
+
+/**
+ * @brief MSCAN context that has to be saved throughout the initialization
+ * mode.
+ */
+typedef struct {
+  uint8_t ctl0;
+  uint8_t rier;
+  uint8_t tier;
+} mscan_context;
+
+bool mscan_enable( volatile mscan *m, unsigned bit_rate);
+
+void mscan_disable( volatile mscan *m);
+
+void mscan_interrupts_disable( volatile mscan *m);
+
+bool mscan_set_bit_rate( volatile mscan *m, unsigned bit_rate);
+
+void mscan_initialization_mode_enter( volatile mscan *m, mscan_context *context);
+
+void mscan_initialization_mode_leave( volatile mscan *m, const mscan_context *context);
+
+void mscan_sleep_mode_enter( volatile mscan *m);
+
+void mscan_sleep_mode_leave( volatile mscan *m);
+
+volatile uint8_t *mscan_id_acceptance_register( volatile mscan *m, unsigned i);
+
+volatile uint8_t *mscan_id_mask_register( volatile mscan *m, unsigned i);
+
+unsigned mscan_filter_number( volatile mscan *m);
+
+bool mscan_set_filter_number( volatile mscan *m, unsigned number);
+
+bool mscan_filter_operation( volatile mscan *m, bool set, unsigned index, uint32_t *id, uint32_t *mask);
+
+void mscan_filter_clear( volatile mscan *m);
+
+void mscan_get_error_counters( volatile mscan *m, unsigned *rec, unsigned *tec);
+
+/** @} */
+
+#endif /* LIBBSP_MSCAN_BASE_H */
diff --git a/bsps/powerpc/gen5200/include/bsp/mscan.h b/bsps/powerpc/gen5200/include/bsp/mscan.h
new file mode 100644
index 0000000000..9cb7fd44e7
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/mscan.h
@@ -0,0 +1,127 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC5200 BSP                              |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below.   |
+| Adaptions, modifications, enhancements and any recent parts of  |
+| the code are:                                                   |
+|                    Copyright (c) 2005                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file has to be included by application when using mscan    |
+\*===============================================================*/
+#ifndef __MSCAN_H__
+#define __MSCAN_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define MSCAN_A_DEV_NAME         "/dev/mscana"
+#define MSCAN_B_DEV_NAME         "/dev/mscanb"
+#define MSCAN_0_DEV_NAME         "/dev/mscan0"
+#define MSCAN_1_DEV_NAME         "/dev/mscan1"
+#define MSCAN_A                  0
+#define MSCAN_B                  1
+
+#define MSCAN_MAX_DATA_BYTES     8
+
+#define MSCAN_MESS_ID_RTR        (1 << 15)
+#define MSCAN_MESS_ID_RTR_MASK   (1 << 15)
+#define MSCAN_MESS_ID_ID_MASK    ((1 << 11)-1)
+#define MSCAN_MESS_ID_HAS_RTR(id) (((id)&MSCAN_MESS_ID_RTR_MASK)==MSCAN_MESS_ID_RTR)
+
+#define MSCAN_SET_RX_ID          1
+#define MSCAN_GET_RX_ID          2
+#define MSCAN_SET_RX_ID_MASK     3
+#define MSCAN_GET_RX_ID_MASK     4
+#define MSCAN_SET_TX_ID          5
+#define MSCAN_GET_TX_ID          6
+#define TOUCAN_MSCAN_INIT        7
+#define MSCAN_SET_BAUDRATE       8
+#define SET_TX_BUF_NO            9
+
+struct can_message
+  {
+    /* uint16_t mess_len; */
+  uint16_t mess_id;
+  uint16_t mess_time_stamp;
+  uint8_t  mess_data[MSCAN_MAX_DATA_BYTES];
+  uint8_t  mess_len;
+  uint8_t  mess_rtr;
+  uint32_t toucan_tx_idx;
+  };
+
+struct mscan_rx_parms
+  {
+  struct can_message *rx_mess;
+  uint32_t rx_timeout;
+  uint8_t  rx_flags;
+  };
+
+struct mscan_tx_parms
+  {
+  struct can_message *tx_mess;
+  uint32_t tx_idx;
+  };
+
+struct mscan_ctrl_parms
+  {
+    uint32_t ctrl_id;
+    uint32_t ctrl_id_mask;
+    uint8_t  ctrl_reg_no;
+    uint8_t  ctrl_tx_buf_no;
+    uint32_t ctrl_can_bitrate;
+    void (*toucan_cb_fnc)(int16_t);
+  };
+
+
+rtems_device_driver mscan_initialize( rtems_device_major_number,
+				                      rtems_device_minor_number,
+				                      void *
+				                    );
+
+rtems_device_driver mscan_open( rtems_device_major_number,
+				                rtems_device_minor_number,
+				                void *
+				              );
+
+rtems_device_driver mscan_close( rtems_device_major_number,
+				                 rtems_device_minor_number,
+                				 void *
+                			   );
+
+rtems_device_driver mscan_read( rtems_device_major_number,
+				                rtems_device_minor_number,
+				                void *
+				              );
+
+rtems_device_driver mscan_write( rtems_device_major_number,
+				                 rtems_device_minor_number,
+				                 void *
+				               );
+
+rtems_device_driver mscan_control( rtems_device_major_number,
+				                   rtems_device_minor_number,
+				                   void *
+				                 );
+
+
+#define MSCAN_DRIVER_TABLE_ENTRY \
+  { mscan_initialize, mscan_open, mscan_close, \
+    mscan_read, mscan_write, mscan_control }
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MSCAN_H__ */
diff --git a/bsps/powerpc/gen5200/include/bsp/nvram.h b/bsps/powerpc/gen5200/include/bsp/nvram.h
new file mode 100644
index 0000000000..b05c35986f
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/nvram.h
@@ -0,0 +1,141 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC5200 BSP                              |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below.   |
+| Adaptions, modifications, enhancements and any recent parts of  |
+| the code are:                                                   |
+|                    Copyright (c) 2005                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file contains the nvram declarations                       |
+\*===============================================================*/
+/***********************************************************************/
+/*                                                                     */
+/*   Module:       nvram.h                                             */
+/*   Date:         07/17/2003                                          */
+/*   Purpose:      RTEMS M93C64-based header file                      */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Description:  M93C46 is a serial microwire EEPROM which contains  */
+/*                 1Kbit (128 bytes/64 words) of non-volatile memory.  */
+/*                 The device can be configured for byte- or word-     */
+/*                 access. The driver provides a file-like interface   */
+/*                 to this memory.                                     */
+/*                                                                     */
+/*                 MPC5x00 PIN settings:                               */
+/*                                                                     */
+/*                 PSC3_6 (output) -> MC93C46 serial data in    (D)    */
+/*                 PSC3_7 (input)  -> MC93C46 serial data out   (Q)    */
+/*                 PSC3_8 (output) -> MC93C46 chip select input (S)    */
+/*                 PSC3_9 (output) -> MC93C46 serial clock      (C)    */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Code                                                              */
+/*   References:   DS1307-based Non-Volatile memory device driver      */
+/*   Module:       nvram.h                                             */
+/*   Project:      RTEMS 4.6.0pre1 / MCF5206Elite BSP                  */
+/*   Version       1.1                                                 */
+/*   Date:         10/26/2001                                          */
+/*   Author:       Victor V. Vengerov                                  */
+/*   Copyright:    Copyright (C) 2000 OKTET Ltd.,St.-Petersburg,Russia */
+/*                                                                     */
+/*   The license and distribution terms for this file may be           */
+/*   found in the file LICENSE in this distribution or at              */
+/*   http://www.rtems.org/license/LICENSE.                        */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Partially based on the code references which are named above.     */
+/*   Adaptions, modifications, enhancements and any recent parts of    */
+/*   the code are under the right of                                   */
+/*                                                                     */
+/*         IPR Engineering, Dachauer Straße 38, D-80335 München        */
+/*                        Copyright(C) 2003                            */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   IPR Engineering makes no representation or warranties with        */
+/*   respect to the performance of this computer program, and          */
+/*   specifically disclaims any responsibility for any damages,        */
+/*   special or consequential, connected with the use of this program. */
+/*                                                                     */
+/*---------------------------------------------------------------------*/
+/*                                                                     */
+/*   Version history:  1.0                                             */
+/*                                                                     */
+/***********************************************************************/
+
+#ifndef __NVRAM_H__
+#define __NVRAM_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* include <bsp.h> */
+#include <bsp.h>
+
+/* Macros for TBL read access */
+#define TBL_READ(count)    __asm__ volatile ("mftb %0\n" : "=r" (count) : "0" (count))
+#define TMBASE_CLOCK       (G2_CLOCK/4)
+
+/* Simple usec delay function prototype */
+void wait_usec(unsigned long);
+
+/* nvram_driver_initialize --
+ *     Non-volatile memory device driver initialization.
+ */
+rtems_device_driver
+nvram_driver_initialize(rtems_device_major_number major,
+                        rtems_device_minor_number minor,
+                        void *arg);
+
+/* nvram_driver_open --
+ *     Non-volatile memory device driver open primitive.
+ */
+rtems_device_driver
+nvram_driver_open(rtems_device_major_number major,
+                  rtems_device_minor_number minor,
+                  void *arg);
+
+/* nvram_driver_close --
+ *     Non-volatile memory device driver close primitive.
+ */
+rtems_device_driver
+nvram_driver_close(rtems_device_major_number major,
+                   rtems_device_minor_number minor,
+                   void *arg);
+
+/* nvram_driver_read --
+ *     Non-volatile memory device driver read primitive.
+ */
+rtems_device_driver
+nvram_driver_read(rtems_device_major_number major,
+                  rtems_device_minor_number minor,
+                  void *arg);
+
+/* nvram_driver_write --
+ *     Non-volatile memory device driver write primitive.
+ */
+rtems_device_driver
+nvram_driver_write(rtems_device_major_number major,
+                   rtems_device_minor_number minor,
+                   void *arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __NVRAM_H__ */
diff --git a/bsps/powerpc/gen5200/include/bsp/slicetimer.h b/bsps/powerpc/gen5200/include/bsp/slicetimer.h
new file mode 100644
index 0000000000..e089dbc8ad
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/slicetimer.h
@@ -0,0 +1,69 @@
+/*===============================================================*\
+| Project: RTEMS generic MPC5200 BSP                              |
++-----------------------------------------------------------------+
+| Partially based on the code references which are named below.   |
+| Adaptions, modifications, enhancements and any recent parts of  |
+| the code are:                                                   |
+|                    Copyright (c) 2005                           |
+|                    Embedded Brains GmbH                         |
+|                    Obere Lagerstr. 30                           |
+|                    D-82178 Puchheim                             |
+|                    Germany                                      |
+|                    rtems@embedded-brains.de                     |
++-----------------------------------------------------------------+
+| The license and distribution terms for this file may be         |
+| found in the file LICENSE in this distribution or at            |
+|                                                                 |
+| http://www.rtems.org/license/LICENSE.                           |
+|                                                                 |
++-----------------------------------------------------------------+
+| this file declares functions to use the slice timer module
+\*===============================================================*/
+#ifndef __SLICETIMER_H__
+#define __SLICETIMER_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define SLT0                          0
+#define SLT1                          1
+
+#define SLT0_INT_FREQUENCY            10000
+#define SLT1_INT_FREQUENCY            0
+
+#define SLT_CNTRL_RW                  (1 << 26)
+#define SLT_CNTRL_INTEN               (1 << 25)
+#define SLT_CNTRL_TIMEN               (1 << 24)
+
+#define SLT_TSR_ST                    (1 << 24)
+
+#define SLT_TSR_COUNT(freq)           ((freq) ? ((IPB_CLOCK)/(freq)) : (0xFFFFFF))
+
+rtems_device_driver slt_initialize( rtems_device_major_number,
+				                      rtems_device_minor_number,
+				                      void *
+				                    );
+
+#define SLTIME_DRIVER_TABLE_ENTRY \
+  { slt_initialize, NULL, NULL, \
+    NULL, NULL, NULL }
+
+void mpc5200_slt_isr(uint32_t);
+rtems_isr mpc5200_slt0_isr(rtems_irq_hdl_param);
+rtems_isr mpc5200_slt1_isr(rtems_irq_hdl_param);
+void mpc5200_init_slt(uint32_t);
+void mpc5200_set_slt_count(uint32_t);
+void mpc5200_enable_slt_int(uint32_t);
+void mpc5200_disable_slt_int(uint32_t);
+uint32_t mpc5200_check_slt_status(uint32_t);
+/*void sltOn(const rtems_irq_connect_data *);
+void sltOff(const rtems_irq_connect_data *);
+int sltIsOn(const rtems_irq_connect_data *);*/
+void Install_slt(rtems_device_minor_number);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SLICETIMER_H__ */
diff --git a/bsps/powerpc/gen5200/include/bsp/u-boot-config.h b/bsps/powerpc/gen5200/include/bsp/u-boot-config.h
new file mode 100644
index 0000000000..2fee83bce9
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/bsp/u-boot-config.h
@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H
+#define LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H
+
+#define CONFIG_MPC5xxx
+
+#endif /* LIBBSP_POWERPC_GEN52XX_U_BOOT_CONFIG_H */
diff --git a/bsps/powerpc/gen5200/include/tm27.h b/bsps/powerpc/gen5200/include/tm27.h
new file mode 100644
index 0000000000..ff43cc9ab6
--- /dev/null
+++ b/bsps/powerpc/gen5200/include/tm27.h
@@ -0,0 +1,66 @@
+/*
+ * @file
+ * @ingroup powerpc_gen5200
+ * @brief Implementations for interrupt mechanisms for Time Test 27
+ */
+
+/*
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef _RTEMS_TMTEST27
+#error "This is an RTEMS internal file you must not include directly."
+#endif
+
+#ifndef __tm27_h
+#define __tm27_h
+
+#include <bsp/fatal.h>
+#include <bsp/irq.h>
+
+/*
+ *  Stuff for Time Test 27
+ */
+
+#define MUST_WAIT_FOR_INTERRUPT 1
+
+void nullFunc() {}
+
+static rtems_irq_connect_data clockIrqData = {BSP_DECREMENTER,
+                                              0,
+                                              (rtems_irq_enable)nullFunc,
+                                              (rtems_irq_disable)nullFunc,
+                                              (rtems_irq_is_enabled) nullFunc};
+void Install_tm27_vector(void (*_handler)())
+{
+  clockIrqData.hdl = _handler;
+  if (!BSP_install_rtems_irq_handler (&clockIrqData)) {
+        printk("Error installing clock interrupt handler!\n");
+        bsp_fatal(MPC5200_FATAL_TM27_IRQ_INSTALL);
+  }
+}
+
+#define Cause_tm27_intr()  \
+  do { \
+    uint32_t   _clicks = 8; \
+    __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
+  } while (0)
+
+#define Clear_tm27_intr() \
+  do { \
+    uint32_t   _clicks = 0xffffffff; \
+    __asm__ volatile( "mtdec %0" : "=r" ((_clicks)) : "r" ((_clicks)) ); \
+  } while (0)
+
+#define Lower_tm27_intr() \
+  do { \
+    uint32_t   _msr = 0; \
+    _ISR_Set_level( 0 ); \
+    __asm__ volatile( "mfmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
+    _msr |=  0x8002; \
+    __asm__ volatile( "mtmsr %0 ;" : "=r" (_msr) : "r" (_msr) ); \
+  } while (0)
+
+#endif