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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-21 10:22:08 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-23 15:18:42 +0200 |
commit | adb85dd473af5c9a72e9da9b7fe013d1b216abc3 (patch) | |
tree | ed54d2ce2354cf2b75995d1e1f2bc685436bc4ca /bsps/mips | |
parent | bsps: Remove AC_CONFIG_SRCDIR() (diff) | |
download | rtems-adb85dd473af5c9a72e9da9b7fe013d1b216abc3.tar.bz2 |
bsps: Move make/custom/* files to bsps
Adjust various build files. Remove automatic generation of the
c/src/lib/libbsp/*/acinclude.m4 files from bootstrap script.
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'bsps/mips')
-rw-r--r-- | bsps/mips/csb350/config/csb350.cfg | 19 | ||||
-rw-r--r-- | bsps/mips/hurricane/config/hurricane-testsuite.tcfg | 5 | ||||
-rw-r--r-- | bsps/mips/hurricane/config/hurricane.cfg | 22 | ||||
-rw-r--r-- | bsps/mips/jmr3904/config/jmr3904-testsuite.tcfg | 9 | ||||
-rw-r--r-- | bsps/mips/jmr3904/config/jmr3904.cfg | 16 | ||||
-rw-r--r-- | bsps/mips/malta/config/malta.cfg | 17 | ||||
-rw-r--r-- | bsps/mips/rbtx4925/config/rbtx4925-testsuite.tcfg | 5 | ||||
-rw-r--r-- | bsps/mips/rbtx4925/config/rbtx4925.cfg | 22 | ||||
-rw-r--r-- | bsps/mips/rbtx4938/config/rbtx4938-testsuite.tcfg | 5 | ||||
-rw-r--r-- | bsps/mips/rbtx4938/config/rbtx4938.cfg | 20 |
10 files changed, 140 insertions, 0 deletions
diff --git a/bsps/mips/csb350/config/csb350.cfg b/bsps/mips/csb350/config/csb350.cfg new file mode 100644 index 0000000000..f6d50662b0 --- /dev/null +++ b/bsps/mips/csb350/config/csb350.cfg @@ -0,0 +1,19 @@ +# +# Config file for the Cogent CSB350 board +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU=mips + +# This contains the compiler options necessary to select the CPU model +# and (hopefully) optimize for it. +# +# gcc 3.1 and newer +CPU_CFLAGS = -mips32 -G0 -msoft-float + +# optimize flag: typically -O2 +CFLAGS_OPTIMIZE_V = -O2 -g +CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections + +LDFLAGS = -Wl,--gc-sections diff --git a/bsps/mips/hurricane/config/hurricane-testsuite.tcfg b/bsps/mips/hurricane/config/hurricane-testsuite.tcfg new file mode 100644 index 0000000000..fb84b55762 --- /dev/null +++ b/bsps/mips/hurricane/config/hurricane-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# This is the set of tests which are known to not link on this BSP +# + +include: testdata/dltests-broken-on-this-bsp.tcfg diff --git a/bsps/mips/hurricane/config/hurricane.cfg b/bsps/mips/hurricane/config/hurricane.cfg new file mode 100644 index 0000000000..b1c050b966 --- /dev/null +++ b/bsps/mips/hurricane/config/hurricane.cfg @@ -0,0 +1,22 @@ +# +# Config file for the Quick Logic Hurricane evaluation board with PMC-Sierra RM5231 cpu +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +# This contains the compiler options necessary to select the CPU model +# and (hopefully) optimize for it. +CPU_CFLAGS = -mips3 -G0 -EL + +# optimize flag: typically -O2 +CFLAGS_OPTIMIZE_V = -O2 -g -fomit-frame-pointer +CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections + +LDFLAGS = -Wl,--gc-sections + +define bsp-post-link + $(OBJCOPY) -O srec $@ $(basename $@).srec1 + $(PACKHEX) < $(basename $@).srec1 > $(basename $@)$(DOWNEXT) + $(RM) $(basename $@).srec1 + $(default-bsp-post-link) +endef diff --git a/bsps/mips/jmr3904/config/jmr3904-testsuite.tcfg b/bsps/mips/jmr3904/config/jmr3904-testsuite.tcfg new file mode 100644 index 0000000000..a8d24a09a9 --- /dev/null +++ b/bsps/mips/jmr3904/config/jmr3904-testsuite.tcfg @@ -0,0 +1,9 @@ +# +# The GDB MIPS JMR3904 simulator in GDB +# + +include: testdata/disable-intrcritical-tests.tcfg + +# The simulator catches the data access fault and exits before the +# simulated MIPS handler can run. +exclude: spfatal26 diff --git a/bsps/mips/jmr3904/config/jmr3904.cfg b/bsps/mips/jmr3904/config/jmr3904.cfg new file mode 100644 index 0000000000..ed4e6b3be0 --- /dev/null +++ b/bsps/mips/jmr3904/config/jmr3904.cfg @@ -0,0 +1,16 @@ +# +# Config file for the jmr3904 board which has a simulator in gdb +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU=mips + +CPU_CFLAGS = -march=r3900 -Wa,-xgot -G0 + +CFLAGS_OPTIMIZE_V = -O2 -g + +# arguments to compile and link with per-element sections +CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections +LDFLAGS = -Wl,--gc-sections + diff --git a/bsps/mips/malta/config/malta.cfg b/bsps/mips/malta/config/malta.cfg new file mode 100644 index 0000000000..a25abcc911 --- /dev/null +++ b/bsps/mips/malta/config/malta.cfg @@ -0,0 +1,17 @@ +# +# Config file for the MIPS Malta board with 24kf CPU +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +RTEMS_CPU=mips + +# This contains the compiler options necessary to select the CPU model +# and (hopefully) optimize for it. +CPU_CFLAGS = -march=24kf1_1 -Wa,-xgot -G0 + +# optimize flag: typically -O2 +CFLAGS_OPTIMIZE_V = -O0 -g +CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections + +LDFLAGS = -Wl,--gc-sections diff --git a/bsps/mips/rbtx4925/config/rbtx4925-testsuite.tcfg b/bsps/mips/rbtx4925/config/rbtx4925-testsuite.tcfg new file mode 100644 index 0000000000..fb84b55762 --- /dev/null +++ b/bsps/mips/rbtx4925/config/rbtx4925-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# This is the set of tests which are known to not link on this BSP +# + +include: testdata/dltests-broken-on-this-bsp.tcfg diff --git a/bsps/mips/rbtx4925/config/rbtx4925.cfg b/bsps/mips/rbtx4925/config/rbtx4925.cfg new file mode 100644 index 0000000000..744fdb4240 --- /dev/null +++ b/bsps/mips/rbtx4925/config/rbtx4925.cfg @@ -0,0 +1,22 @@ +# +# Config file for the Toshiba RBTX4925 evaluation board with TX4925 cpu +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +# This contains the compiler options necessary to select the CPU model +# and (hopefully) optimize for it. +CPU_CFLAGS = -mips3 -G0 -EL + +# optimize flag: typically -O2 +CFLAGS_OPTIMIZE_V = -O2 -g -fomit-frame-pointer +CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections + +LDFLAGS = -Wl,--gc-sections + +define bsp-post-link + $(OBJCOPY) -O srec $@ $(basename $@).srec1 + $(PACKHEX) < $(basename $@).srec1 > $(basename $@)$(DOWNEXT) + $(RM) $(basename $@).srec1 + $(default-bsp-post-link) +endef diff --git a/bsps/mips/rbtx4938/config/rbtx4938-testsuite.tcfg b/bsps/mips/rbtx4938/config/rbtx4938-testsuite.tcfg new file mode 100644 index 0000000000..fb84b55762 --- /dev/null +++ b/bsps/mips/rbtx4938/config/rbtx4938-testsuite.tcfg @@ -0,0 +1,5 @@ +# +# This is the set of tests which are known to not link on this BSP +# + +include: testdata/dltests-broken-on-this-bsp.tcfg diff --git a/bsps/mips/rbtx4938/config/rbtx4938.cfg b/bsps/mips/rbtx4938/config/rbtx4938.cfg new file mode 100644 index 0000000000..42cdf17a04 --- /dev/null +++ b/bsps/mips/rbtx4938/config/rbtx4938.cfg @@ -0,0 +1,20 @@ +# +# Config file for the Toshiba RBTX4938 evaluation board with TX4938 cpu +# + +include $(RTEMS_ROOT)/make/custom/default.cfg + +# This contains the compiler options necessary to select the CPU model +# and (hopefully) optimize for it. +CPU_CFLAGS = -mips3 -G0 -EL + +# optimize flag: typically -O2 +CFLAGS_OPTIMIZE_V = -O2 -g -fomit-frame-pointer +CFLAGS_OPTIMIZE_V += -ffunction-sections -fdata-sections + +LDFLAGS = -Wl,--gc-sections + +define bsp-post-link + $(OBJCOPY) --srec-len=30 -O srec $@ $(basename $@)$(DOWNEXT) + $(default-bsp-post-link) +endef |