bsps: Move interrupt controller support to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

2 files changed, 126 insertions, 0 deletions

diff --git a/bsps/mips/malta/irq/interruptmask.c b/bsps/mips/malta/irq/interruptmask.c
new file mode 100644
index 0000000000..d639ab17a9
--- /dev/null
+++ b/bsps/mips/malta/irq/interruptmask.c
@@ -0,0 +1,36 @@
+/**
+ *  @file
+ *
+ *  This file contains the implementation of the MIPS port
+ *  support routine which provides the BSP specific default
+ *  interrupt mask.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+
+/*
+ *  This function returns a mask value which is used to select the bits
+ *  in the processor status register that can be set to enable interrupts.
+ *  The mask value should not include the 2 software interrupt enable bits.
+ */
+
+uint32_t mips_interrupt_mask( void )
+{
+  uint32_t interrupt_mask;
+
+  /*
+   * This has only been tested with qemu for the mips malta and
+   * may not be correct for the 24k on real hardware.
+   */
+  interrupt_mask = 0x0000ff00;
+  return(interrupt_mask);
+}
diff --git a/bsps/mips/malta/irq/vectorisrs.c b/bsps/mips/malta/irq/vectorisrs.c
new file mode 100644
index 0000000000..a2b9288646
--- /dev/null
+++ b/bsps/mips/malta/irq/vectorisrs.c
@@ -0,0 +1,90 @@
+/**
+ *  @file
+ *
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <bsp/irq-generic.h>
+#include <bsp/pci.h>
+#include <bsp/i8259.h>
+#include <bsp.h>
+#include <libcpu/isr_entries.h>
+
+void mips_default_isr( int vector );
+
+#include <rtems/bspIo.h>  /* for printk */
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+  unsigned int pending;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  pending = (cause & sr & 0xff00) >> CAUSE_IPSHIFT;
+
+  /* SW Bits */
+  if ( pending & 0x01) {
+    printk("Pending IRQ Q 0x%x\n", pending );
+  }
+
+  if ( pending & 0x02) {
+    printk("Pending IRQ Q 0x%x\n", pending );
+  }
+
+  /* South Bridge Interrupt */
+  if ( pending & 0x04) {
+     BSP_i8259s_int_process();
+  }
+
+  /* South Bridge SMI */
+  if (pending & 0x08){
+    printk( "Pending IRQ 0x%x\n", pending );
+  }
+
+  /* TTY 2 */
+  if (pending & 0x10) {
+    printk( "Pending IRQ 0x%x\n", pending );
+  }
+  /* Core HI */
+  if (pending & 0x20) {
+    printk( "Pending IRQ 0x%x\n", pending );
+  }
+   /* Core LO */
+  if (pending & 0x40) {
+    printk( "Pending IRQ 0x%x\n", pending );
+  }
+
+  if ( pending & 0x80 ) {
+    bsp_interrupt_handler_dispatch( MALTA_INT_TICKER );
+  }
+}
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+
+  while(1);      /* Lock it up */
+
+  rtems_fatal_error_occurred(1);
+}
+