bsps: Move interrupt controller support to bsps

This patch is a part of the BSP source reorganization.

Update #3285.

13 files changed, 1760 insertions, 0 deletions

diff --git a/bsps/mips/csb350/irq/vectorisrs.c b/bsps/mips/csb350/irq/vectorisrs.c
new file mode 100644
index 0000000000..d8e071281e
--- /dev/null
+++ b/bsps/mips/csb350/irq/vectorisrs.c
@@ -0,0 +1,168 @@
+/**
+ *  @file
+ *  
+ *  Au1x00 Interrupt Vectoring
+ */
+
+/*
+ *  Copyright (c) 2005 by Cogent Computer Systems
+ *  Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <libcpu/au1x00.h>
+#include <libcpu/isr_entries.h>
+#include <rtems/irq.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+
+static void call_vectored_isr(CPU_Interrupt_frame *, uint32_t , void *);
+
+#include <rtems/bspIo.h>  /* for printk */
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  cause &= (sr & SR_IMASK);
+  cause >>= CAUSE_IPSHIFT;
+
+  /* count/compare interrupt */
+  if ( cause & 0x80 ) {
+      unsigned long zero = 0;
+      /*
+       * I don't see a good way to disable the compare
+       * interrupt, so let's just ignore it.
+       */
+      __asm__ volatile ("mtc0 %0, $11\n" :: "r" (zero));
+  }
+
+  /* Performance counter */
+  if ( cause & 0x40 ) {
+      bsp_interrupt_handler_dispatch(AU1X00_IRQ_PERF);
+  }
+
+  /* Interrupt controller 0 */
+  if ( cause & 0x0c ) {
+      call_vectored_isr(frame, cause, (void *)AU1X00_IC0_ADDR);
+  }
+
+  /* Interrupt controller 1 */
+  if ( cause & 0x30 ) {
+      call_vectored_isr(frame, cause, (void *)AU1X00_IC1_ADDR);
+  }
+
+  /* SW[0] */
+  if ( cause & 0x01 )
+      bsp_interrupt_handler_dispatch( AU1X00_IRQ_SW0 );
+
+  /* SW[1] */
+  if ( cause & 0x02 )
+      bsp_interrupt_handler_dispatch( AU1X00_IRQ_SW1 );
+}
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+  rtems_fatal_error_occurred(1);
+}
+
+static void call_vectored_isr(
+    CPU_Interrupt_frame *frame,
+    uint32_t cause,
+    void *ctrlr
+    )
+{
+    uint32_t src;
+    uint32_t mask;
+    int index;
+
+    /* get mask register */
+    mask = AU1X00_IC_MASKRD(ctrlr);
+
+    /* check request 0 */
+    src = AU1X00_IC_REQ0INT(ctrlr);
+    src = src & mask;
+    index = 0;
+    while (src) {
+        /* check LSB */
+        if (src & 1) {
+            /* clear rising/falling edge detects */
+            AU1X00_IC_RISINGCLR(ctrlr) = (1 << index);
+            AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index);
+            au_sync();
+            bsp_interrupt_handler_dispatch(AU1X00_IRQ_IC0_BASE + index);
+        }
+        index ++;
+
+        /* shift, and make sure MSB is clear */
+        src = (src >> 1) & 0x7fffffff;
+    }
+
+    /* check request 1 */
+    src = AU1X00_IC_REQ1INT(ctrlr);
+    src = src & mask;
+    index = 0;
+    while (src) {
+        /* check LSB */
+        if (src & 1) {
+            /* clear rising/falling edge detects */
+            AU1X00_IC_RISINGCLR(ctrlr) = (1 << index);
+            AU1X00_IC_FALLINGCLR(ctrlr) = (1 << index);
+            au_sync();
+            bsp_interrupt_handler_dispatch(AU1X00_IRQ_IC0_BASE + index);
+        }
+        index ++;
+
+        /* shift, and make sure MSB is clear */
+        src = (src >> 1) & 0x7fffffff;
+    }
+}
+
+/* Generate a software interrupt */
+int assert_sw_irq(uint32_t irqnum)
+{
+    uint32_t cause;
+
+    if (irqnum <= 1) {
+        mips_get_cause(cause);
+        cause = cause | ((irqnum + 1) << CAUSE_IPSHIFT);
+        mips_set_cause(cause);
+
+        return irqnum;
+    } else {
+        return -1;
+    }
+}
+
+/* Clear a software interrupt */
+int negate_sw_irq(uint32_t irqnum)
+{
+    uint32_t cause;
+
+    if (irqnum <= 1) {
+        mips_get_cause(cause);
+        cause = cause & ~((irqnum + 1) << CAUSE_IPSHIFT);
+        mips_set_cause(cause);
+
+        return irqnum;
+    } else {
+        return -1;
+    }
+}
diff --git a/bsps/mips/hurricane/irq/vectorisrs.c b/bsps/mips/hurricane/irq/vectorisrs.c
new file mode 100644
index 0000000000..e55566697d
--- /dev/null
+++ b/bsps/mips/hurricane/irq/vectorisrs.c
@@ -0,0 +1,58 @@
+/**
+ *  @file
+ *
+ *  RM5231 Interrupt Vectoring  
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <libcpu/isr_entries.h>
+#include <libcpu/rm5231.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+
+#include <rtems/bspIo.h>  /* for printk */
+
+void mips_default_isr( int vector );
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+  unsigned int i;
+  unsigned int mask;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  cause &= (sr & SR_IMASK);
+  cause >>= CAUSE_IPSHIFT;
+
+  for ( i=1, mask=0x80 ; i<=8 ; i++, mask >>= 1 ) {
+    if ( cause & mask )
+      bsp_interrupt_handler_dispatch( MIPS_INTERRUPT_BASE + 8 - i );
+  }
+}
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+  rtems_fatal_error_occurred(1);
+}
+
diff --git a/bsps/mips/jmr3904/irq/vectorisrs.c b/bsps/mips/jmr3904/irq/vectorisrs.c
new file mode 100644
index 0000000000..629c4c45f8
--- /dev/null
+++ b/bsps/mips/jmr3904/irq/vectorisrs.c
@@ -0,0 +1,47 @@
+/**
+ *  @file
+ *  
+ *  TX3904 Interrupt Vectoring
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <bsp/irq.h>
+#include <rtems/bspIo.h>  /* for printk */
+#include <bsp/irq-generic.h>
+#include <libcpu/isr_entries.h>
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  cause &= (sr & SR_IMASK);
+  cause >>= CAUSE_IPSHIFT;
+
+  if ( cause & 0x80 )       /* IP[5] ==> INT0 */
+    bsp_interrupt_handler_dispatch( TX3904_IRQ_INT0 );
+
+  if ( cause & 0x40 ) {     /* (IP[4] == 1) ==> IP[0-3] are valid */
+    unsigned int v = (cause >> 2) & 0x0f;
+    bsp_interrupt_handler_dispatch( MIPS_INTERRUPT_BASE + v );
+  }
+
+  if ( cause & 0x02 )       /* SW[0] */
+    bsp_interrupt_handler_dispatch( TX3904_IRQ_SOFTWARE_1 );
+
+  if ( cause & 0x01 )       /* IP[1] */
+    bsp_interrupt_handler_dispatch( TX3904_IRQ_SOFTWARE_2 );
+}
diff --git a/bsps/mips/malta/irq/interruptmask.c b/bsps/mips/malta/irq/interruptmask.c
new file mode 100644
index 0000000000..d639ab17a9
--- /dev/null
+++ b/bsps/mips/malta/irq/interruptmask.c
@@ -0,0 +1,36 @@
+/**
+ *  @file
+ *
+ *  This file contains the implementation of the MIPS port
+ *  support routine which provides the BSP specific default
+ *  interrupt mask.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+
+/*
+ *  This function returns a mask value which is used to select the bits
+ *  in the processor status register that can be set to enable interrupts.
+ *  The mask value should not include the 2 software interrupt enable bits.
+ */
+
+uint32_t mips_interrupt_mask( void )
+{
+  uint32_t interrupt_mask;
+
+  /*
+   * This has only been tested with qemu for the mips malta and
+   * may not be correct for the 24k on real hardware.
+   */
+  interrupt_mask = 0x0000ff00;
+  return(interrupt_mask);
+}
diff --git a/bsps/mips/malta/irq/vectorisrs.c b/bsps/mips/malta/irq/vectorisrs.c
new file mode 100644
index 0000000000..a2b9288646
--- /dev/null
+++ b/bsps/mips/malta/irq/vectorisrs.c
@@ -0,0 +1,90 @@
+/**
+ *  @file
+ *
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <bsp/irq-generic.h>
+#include <bsp/pci.h>
+#include <bsp/i8259.h>
+#include <bsp.h>
+#include <libcpu/isr_entries.h>
+
+void mips_default_isr( int vector );
+
+#include <rtems/bspIo.h>  /* for printk */
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+  unsigned int pending;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  pending = (cause & sr & 0xff00) >> CAUSE_IPSHIFT;
+
+  /* SW Bits */
+  if ( pending & 0x01) {
+    printk("Pending IRQ Q 0x%x\n", pending );
+  }
+
+  if ( pending & 0x02) {
+    printk("Pending IRQ Q 0x%x\n", pending );
+  }
+
+  /* South Bridge Interrupt */
+  if ( pending & 0x04) {
+     BSP_i8259s_int_process();
+  }
+
+  /* South Bridge SMI */
+  if (pending & 0x08){
+    printk( "Pending IRQ 0x%x\n", pending );
+  }
+
+  /* TTY 2 */
+  if (pending & 0x10) {
+    printk( "Pending IRQ 0x%x\n", pending );
+  }
+  /* Core HI */
+  if (pending & 0x20) {
+    printk( "Pending IRQ 0x%x\n", pending );
+  }
+   /* Core LO */
+  if (pending & 0x40) {
+    printk( "Pending IRQ 0x%x\n", pending );
+  }
+
+  if ( pending & 0x80 ) {
+    bsp_interrupt_handler_dispatch( MALTA_INT_TICKER );
+  }
+}
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+
+  while(1);      /* Lock it up */
+
+  rtems_fatal_error_occurred(1);
+}
+
diff --git a/bsps/mips/rbtx4925/irq/vectorisrs.c b/bsps/mips/rbtx4925/irq/vectorisrs.c
new file mode 100644
index 0000000000..09020c5020
--- /dev/null
+++ b/bsps/mips/rbtx4925/irq/vectorisrs.c
@@ -0,0 +1,64 @@
+/**
+ *  @file
+ *  
+ *  TX4925 Interrupt Vectoring
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <libcpu/isr_entries.h>
+#include <libcpu/tx4925.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <rtems/bspIo.h>  /* for printk */
+
+void mips_default_isr( int vector );
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+  unsigned int pending;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  pending = (cause & sr & 0x700) >> CAUSE_IPSHIFT;
+
+  if ( pending & 0x4 ) {     /* (IP[2] == 1) ==> IP[3-7] are valid */
+    unsigned int v = (cause >> (CAUSE_IPSHIFT + 3)) & 0x1f;
+    bsp_interrupt_handler_dispatch( MIPS_INTERRUPT_BASE + v );
+  }
+
+  if ( pending & 0x01 )       /* IP[0] */
+    bsp_interrupt_handler_dispatch( TX4925_IRQ_SOFTWARE_1 );
+
+  if ( pending & 0x02 )       /* IP[1] */
+    bsp_interrupt_handler_dispatch( TX4925_IRQ_SOFTWARE_2 );
+}
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+
+  while(1);	/* Lock it up */
+
+  rtems_fatal_error_occurred(1);
+}
+
diff --git a/bsps/mips/rbtx4938/irq/vectorisrs.c b/bsps/mips/rbtx4938/irq/vectorisrs.c
new file mode 100644
index 0000000000..d38e4f81c2
--- /dev/null
+++ b/bsps/mips/rbtx4938/irq/vectorisrs.c
@@ -0,0 +1,64 @@
+/**
+ *  @file
+ *  
+ *  TX4925 Interrupt Vectoring
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <stdlib.h>
+#include <libcpu/isr_entries.h>
+#include <libcpu/tx4938.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <rtems/bspIo.h>  /* for printk */
+
+void mips_default_isr( int vector );
+
+void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
+{
+  unsigned int sr;
+  unsigned int cause;
+  unsigned int pending;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  pending = (cause & sr & 0x700) >> CAUSE_IPSHIFT;
+
+  if ( pending & 0x4 ) {     /* (IP[2] == 1) ==> IP[3-7] are valid */
+    unsigned int v = (cause >> (CAUSE_IPSHIFT + 3)) & 0x1f;
+    bsp_interrupt_handler_dispatch( MIPS_INTERRUPT_BASE + v );
+  }
+
+  if ( pending & 0x01 )       /* IP[0] */
+    bsp_interrupt_handler_dispatch( TX4938_IRQ_SOFTWARE_1 );
+
+  if ( pending & 0x02 )       /* IP[1] */
+    bsp_interrupt_handler_dispatch( TX4938_IRQ_SOFTWARE_2 );
+}
+
+void mips_default_isr( int vector )
+{
+  unsigned int sr;
+  unsigned int cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
+      vector, cause, sr );
+
+  while(1);	/* Lock it up */
+
+  rtems_fatal_error_occurred(1);
+}
+
diff --git a/bsps/mips/shared/irq/exception.S b/bsps/mips/shared/irq/exception.S
new file mode 100644
index 0000000000..e916ae55fe
--- /dev/null
+++ b/bsps/mips/shared/irq/exception.S
@@ -0,0 +1,661 @@
+/*
+ *  This file contains a customized MIPS exception handler.
+ *  It hooks into the exception handler present in the resident
+ *  PMON debug monitor.
+ */
+
+/*
+ *  Author: Bruce Robinson
+ *
+ *  This code was derived from cpu_asm.S with the following copyright:
+ *
+ *  COPYRIGHT (c) 1996 by Transition Networks Inc.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of Transition Networks not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      Transition Networks makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/exec/score/cpu/no_cpu/cpu_asm.s:
+ *
+ *  COPYRIGHT (c) 1989-2010.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <bspopts.h>
+#include <rtems/asm.h>
+#include <rtems/score/percpu.h>
+#include <rtems/mips/iregdef.h>
+#include <rtems/mips/idtcpu.h>
+#if BSP_HAS_USC320
+  #include <usc.h>
+#endif
+
+#if __mips == 3
+/* 64 bit register operations */
+#define NOP	nop
+#define ADD	dadd
+#define STREG	sd
+#define LDREG	ld
+#define ADDU	addu
+#define ADDIU	addiu
+#define STREGC1	sdc1
+#define LDREGC1	ldc1
+#define R_SZ	8
+#define F_SZ	8
+#define SZ_INT	8
+#define SZ_INT_POW2 3
+
+/* XXX if we don't always want 64 bit register ops, then another ifdef */
+
+#elif __mips == 1
+/* 32 bit register operations*/
+#define NOP	nop
+#define ADD	add
+#define STREG	sw
+#define LDREG	lw
+#define ADDU	add
+#define ADDIU	addi
+#define STREGC1	swc1
+#define LDREGC1	lwc1
+#define R_SZ	4
+#define F_SZ	4
+#define SZ_INT	4
+#define SZ_INT_POW2 2
+#else
+#error "mips assembly: what size registers do I deal with?"
+#endif
+
+
+#define ISR_VEC_SIZE	4
+#define EXCP_STACK_SIZE (NREGS*R_SZ)
+
+.extern _Thread_Dispatch
+
+/*  void __ISR_Handler()
+ *
+ *  This routine provides the RTEMS interrupt management.
+ *
+ */
+
+#if 0
+void _ISR_Handler()
+{
+   /*
+    *  This discussion ignores a lot of the ugly details in a real
+    *  implementation such as saving enough registers/state to be
+    *  able to do something real.  Keep in mind that the goal is
+    *  to invoke a user's ISR handler which is written in C and
+    *  uses a certain set of registers.
+    *
+    *  Also note that the exact order is to a large extent flexible.
+    *  Hardware will dictate a sequence for a certain subset of
+    *  _ISR_Handler while requirements for setting
+    */
+
+  /*
+   *  At entry to "common" _ISR_Handler, the vector number must be
+   *  available.  On some CPUs the hardware puts either the vector
+   *  number or the offset into the vector table for this ISR in a
+   *  known place.  If the hardware does not give us this information,
+   *  then the assembly portion of RTEMS for this port will contain
+   *  a set of distinct interrupt entry points which somehow place
+   *  the vector number in a known place (which is safe if another
+   *  interrupt nests this one) and branches to _ISR_Handler.
+   *
+   */
+#endif
+FRAME(bsp_ISR_Handler,sp,0,ra)
+	.set noreorder
+
+#if 0
+/* Activate TX49xx PIO19 signal for diagnostics */
+	lui	k0,0xff1f
+	ori	k0,k0,0xf500
+	lw	k0,(k0)
+	lui	k1,0x8
+	or	k1,k1,k0
+	lui	k0,0xff1f
+	ori	k0,k0,0xf500
+	sw	k1,(k0)
+#endif
+	mfc0 k0,C0_CAUSE	/* Determine if an interrupt generated this exception */
+	nop
+	and k1,k0,CAUSE_EXCMASK
+	beq k1,zero,_chk_int	/* If so, branch to service here */
+	nop
+	la  k0,_int_esr_link	/* Otherwise, jump to next exception handler in PMON exception chain */
+	lw  k0,(k0)
+	lw  k0,4(k0)
+	j   k0
+	nop
+_chk_int:
+	mfc0 k1,C0_SR
+	nop
+	and k0,k1
+#if HAS_RM52xx
+	and k0,CAUSE_IPMASK
+#elif HAS_TX49xx
+	and k0,(SR_IBIT1 | SR_IBIT2 | SR_IBIT3)
+#endif
+	/* external interrupt not enabled, ignore */
+	beq k0,zero,_ISR_Handler_quick_exit
+	nop
+
+/* For debugging interrupts, clear EXL to allow breakpoints */
+#if 0
+        MFC0    k0, C0_SR
+#if __mips == 3
+	li	k1,SR_EXL	/* Clear EXL and Set IE to enable interrupts */
+	not	k1
+	and	k0,k1
+	li	k1,SR_IE
+#elif __mips == 1
+	li	k1,SR_IEC
+#endif
+	or	k0, k1
+        mtc0    k0, C0_SR
+	NOP
+#endif
+
+
+  /*
+   *  save some or all context on stack
+   *  may need to save some special interrupt information for exit
+   */
+
+        /* Q: _ISR_Handler, not using IDT/SIM ...save extra regs? */
+
+        /* wastes a lot of stack space for context?? */
+	ADDIU    sp,sp,-EXCP_STACK_SIZE
+
+        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */
+        STREG v0, R_V0*R_SZ(sp)
+        STREG v1, R_V1*R_SZ(sp)
+        STREG a0, R_A0*R_SZ(sp)
+        STREG a1, R_A1*R_SZ(sp)
+        STREG a2, R_A2*R_SZ(sp)
+        STREG a3, R_A3*R_SZ(sp)
+        STREG t0, R_T0*R_SZ(sp)
+        STREG t1, R_T1*R_SZ(sp)
+        STREG t2, R_T2*R_SZ(sp)
+        STREG t3, R_T3*R_SZ(sp)
+        STREG t4, R_T4*R_SZ(sp)
+        STREG t5, R_T5*R_SZ(sp)
+        STREG t6, R_T6*R_SZ(sp)
+        STREG t7, R_T7*R_SZ(sp)
+        mflo  t0
+        STREG t8, R_T8*R_SZ(sp)
+        STREG t0, R_MDLO*R_SZ(sp)
+        STREG t9, R_T9*R_SZ(sp)
+        mfhi  t0
+        STREG gp, R_GP*R_SZ(sp)
+        STREG t0, R_MDHI*R_SZ(sp)
+        STREG fp, R_FP*R_SZ(sp)
+
+        .set noat
+        STREG AT, R_AT*R_SZ(sp)
+        .set at
+
+        mfc0     t0,C0_SR
+	dmfc0    t1,C0_EPC
+        STREG    t0,R_SR*R_SZ(sp)
+        STREG    t1,R_EPC*R_SZ(sp)
+
+  /*
+   *
+   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+   *    if ( _ISR_Nest_level == 0 )
+   *      switch to software interrupt stack
+   *  #endif
+   */
+
+  /*
+   *  _ISR_Nest_level++;
+   */
+        lw	t0,ISR_NEST_LEVEL
+	NOP
+        add	t0,t0,1
+        sw	t0,ISR_NEST_LEVEL
+  /*
+   *  _Thread_Dispatch_disable_level++;
+   */
+        lw	t1,THREAD_DISPATCH_DISABLE_LEVEL
+	NOP
+        add	t1,t1,1
+        sw	t1,THREAD_DISPATCH_DISABLE_LEVEL
+
+	/* DEBUG - Add the following code to disable interrupts and clear
+	 *	   EXL in status register, this will allow memory
+	 *         exceptions to occur while servicing the current interrupt
+	 */
+#if 0
+	/* Disable interrupts from internal interrupt controller */
+	li t0,~CAUSE_IP2_MASK
+	mfc0 t1,C0_SR
+	nop
+	and t1,t0
+	mtc0 t1,C0_SR
+	nop
+	/* Clear EXL in status register to allow memory exceptions to occur */
+	li t0,~SR_EXL
+	mfc0 t1,C0_SR
+	nop
+	and t1,t0
+	mtc0 t1,C0_SR
+	nop
+#endif
+
+  /*
+   *  Call the CPU model or BSP specific routine to decode the
+   *  interrupt source and actually vector to device ISR handlers.
+   */
+	move	 a0,sp
+        jal      mips_vector_isr_handlers
+        NOP
+
+	/* Add the following code to disable interrupts (see DEBUG above) */
+#if 0
+	li t0,SR_EXL		/* Set EXL to hold off interrupts */
+	mfc0 t1,C0_SR
+	nop
+	or t1,t0
+	mtc0 t1,C0_SR
+	nop
+	/* Enable interrupts from internal interrupt controller */
+	li t0,CAUSE_IP2_MASK
+	mfc0 t1,C0_SR
+	nop
+	or t1,t0
+	mtc0 t1,C0_SR
+	nop
+#endif
+
+_ISR_Handler_cleanup:
+
+  /*
+   *  --_ISR_Nest_level;
+   */
+        lw	t2,ISR_NEST_LEVEL
+	NOP
+        add	t2,t2,-1
+        sw	t2,ISR_NEST_LEVEL
+  /*
+   *  --_Thread_Dispatch_disable_level;
+   */
+        lw	t1,THREAD_DISPATCH_DISABLE_LEVEL
+	NOP
+        add	t1,t1,-1
+        sw	t1,THREAD_DISPATCH_DISABLE_LEVEL
+  /*
+   *  if ( _Thread_Dispatch_disable_level || _ISR_Nest_level )
+   *    goto the label "exit interrupt (simple case)"
+   */
+        or  t0,t2,t1
+        bne t0,zero,_ISR_Handler_exit
+        NOP
+
+
+  /*
+   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
+   *    restore stack
+   *  #endif
+   *
+   *  if ( !_Thread_Dispatch_necessary )
+   *    goto the label "exit interrupt (simple case)"
+   */
+        lb	t0,DISPATCH_NEEDED
+	NOP
+        or 	t0,t0,t0
+        beq	t0,zero,_ISR_Handler_exit
+        NOP
+
+/*
+** Turn on interrupts before entering Thread_Dispatch which
+** will run for a while, thus allowing new interrupts to
+** be serviced.  Observe the Thread_Dispatch_disable_level interlock
+** that prevents recursive entry into Thread_Dispatch.
+*/
+
+        mfc0    t0, C0_SR
+#if __mips == 3
+	li	t1,SR_EXL	/* Clear EXL and Set IE to enable interrupts */
+	not	t1
+	and	t0,t1
+	li	t1,SR_IE
+#elif __mips == 1
+	li	t1,SR_IEC
+#endif
+	or	t0, t1
+        mtc0    t0, C0_SR
+	NOP
+
+	/* save off our stack frame so the context switcher can get to it */
+	la	t0,__exceptionStackFrame
+	STREG	sp,(t0)
+
+        jal     _Thread_Dispatch
+        NOP
+
+	/* and make sure its clear in case we didn't dispatch.  if we did, its
+	** already cleared */
+	la	t0,__exceptionStackFrame
+	STREG	zero,(t0)
+	NOP
+
+/*
+** turn interrupts back off while we restore context so
+** a badly timed interrupt won't accidentally mess things up
+*/
+        mfc0    t0, C0_SR
+#if __mips == 3
+	li	t1,SR_IE		/* Clear IE first (recommended) */
+	not	t1
+	and	t0,t1
+        mtc0    t0, C0_SR
+	li	t1,SR_EXL | SR_IE	/* Set EXL and IE, this puts status register bits back to interrupted state */
+	or	t0,t1
+#elif __mips == 1
+	/* ints off, current & prev kernel mode on (kernel mode enabled is bit clear..argh!) */
+	li	t1,SR_IEC | SR_KUP | SR_KUC
+	not	t1
+	and	t0, t1
+#endif
+	mtc0    t0, C0_SR
+	NOP
+
+  /*
+   *  prepare to get out of interrupt
+   *  return from interrupt  (maybe to _ISR_Dispatch)
+   *
+   *  LABEL "exit interrupt (simple case):"
+   *  prepare to get out of interrupt
+   *  return from interrupt
+   */
+
+_ISR_Handler_exit:
+
+/* restore interrupt context from stack */
+        LDREG t8, R_MDLO*R_SZ(sp)
+        LDREG t0, R_T0*R_SZ(sp)
+        mtlo  t8
+        LDREG t8, R_MDHI*R_SZ(sp)
+        LDREG t1, R_T1*R_SZ(sp)
+        mthi  t8
+        LDREG t2, R_T2*R_SZ(sp)
+        LDREG t3, R_T3*R_SZ(sp)
+        LDREG t4, R_T4*R_SZ(sp)
+        LDREG t5, R_T5*R_SZ(sp)
+        LDREG t6, R_T6*R_SZ(sp)
+        LDREG t7, R_T7*R_SZ(sp)
+        LDREG t8, R_T8*R_SZ(sp)
+        LDREG t9, R_T9*R_SZ(sp)
+        LDREG gp, R_GP*R_SZ(sp)
+        LDREG fp, R_FP*R_SZ(sp)
+        LDREG ra, R_RA*R_SZ(sp)
+        LDREG a0, R_A0*R_SZ(sp)
+        LDREG a1, R_A1*R_SZ(sp)
+        LDREG a2, R_A2*R_SZ(sp)
+        LDREG a3, R_A3*R_SZ(sp)
+        LDREG v1, R_V1*R_SZ(sp)
+        LDREG v0, R_V0*R_SZ(sp)
+
+        LDREG k1, R_EPC*R_SZ(sp)
+	mtc0  k1,C0_EPC
+
+	.set noat
+        LDREG     AT, R_AT*R_SZ(sp)
+        .set at
+
+        ADDIU     sp,sp,EXCP_STACK_SIZE
+
+_ISR_Handler_quick_exit:
+	eret
+	nop
+
+
+#if BSP_HAS_USC320
+	/* Interrupts from USC320 are serviced here */
+	.global	USC_isr
+	.extern	Clock_isr
+USC_isr:
+	/* check if it's a USC320 heartbeat interrupt */
+        la      k0,INT_STAT	/* read INT_STAT register */
+        lw      k0,(k0)
+        nop			/* reading from external device	*/
+        sll     k0,(31-21)	/* test bit 21 (HBI) */
+
+        bgez	k0,USC_isr2	/* branch if not a heartbeat interrupt */
+	NOP
+
+	/* clear the heartbeat interrupt */
+	la      k0,INT_STAT
+	li      t0,HBI_MASK
+	sw      t0,(k0)
+	/* wait for interrupt to clear */
+USC_isr1:
+	la      k0,INT_STAT	/* read INT_STAT register */
+	lw      k0,(k0)
+	nop			/* reading from external device */
+        sll     k0,(31-21)	/* test bit 21 (HBI) */
+        bltz    k0,USC_isr1   	/* branch if bit set */
+        nop
+	j	Clock_isr	/* Jump to clock isr */
+	nop
+USC_isr2:
+	j	ra		/* no serviceable interrupt, return without doing anything */
+	nop
+#endif
+
+#if 0
+	.global	int7_isr
+	.extern	Interrupt_7_isr
+int7_isr:
+	/* Verify interrupt is from Timer */
+        la      k0,IRCS		/* read Interrupt Current Status register */
+        lw      k0,(k0)
+        nop			/* reading from external device	*/
+	li	k1,IRCS_CAUSE_MASK
+        and     k0,k0,k1	/* isolate interrupt cause  */
+
+	li	k1,INT7INT	/* test for interrupt 7 */
+        subu	k1,k0,k1
+        beq	k1,zero,int7_isr1
+        nop
+        j	ra		/* interrupt 7 no longer valid, return without doing anything */
+        nop
+int7_isr1:
+	j	Interrupt_7_isr	/* Jump to Interrupt 7 isr */
+	nop
+#endif
+
+       .set    reorder
+
+ENDFRAME(bsp_ISR_Handler)
+
+
+FRAME(_BRK_Handler,sp,0,ra)
+	.set noreorder
+
+#if BSP_HAS_USC320
+	la	k0,INT_CFG3	/* Disable heartbeat interrupt in USC320, it interferes with PMON exception handler */
+	lw	k1,(k0)
+	li	k0,~HBI_MASK
+	and	k1,k1,k0
+	la	k0,INT_CFG3
+	sw	k1,(k0)
+#endif
+
+	la  k0,_brk_esr_link	/* Jump to next exception handler in PMON exception chain */
+	lw  k0,(k0)
+	lw  k0,4(k0)
+	j   k0
+	nop
+
+	.set reorder
+ENDFRAME(_BRK_Handler)
+
+
+/**************************************************************************
+**
+**	init_exc_vecs() - moves the exception code into the addresses
+**			  reserved for exception vectors
+**
+**	UTLB Miss exception vector at address 0x80000000
+**
+**	General exception vector at address 0x80000080
+**
+**	RESET exception vector is at address 0xbfc00000
+**
+***************************************************************************/
+
+FRAME(init_exc_vecs,sp,0,ra)
+	.set noreorder
+
+	.extern mon_onintr
+
+/* Install interrupt handler in PMON exception handling chain */
+
+	addiu	sp,sp,-8
+	sw	ra,(sp)			/* Save ra contents on stack */
+	move	a0,zero
+	la	a1,_int_esr_link
+	jal	mon_onintr		/* Make PMON system call to install interrupt exception handler */
+	nop
+	li	a0,9
+	la	a1,_brk_esr_link
+	jal	mon_onintr		/* Make PMON system call to install break exception handler */
+	nop
+	lw	ra,(sp)
+	addiu	sp,sp,8			/* Restore ra contents from stack */
+	j	ra
+	nop
+
+	.set reorder
+ENDFRAME(init_exc_vecs)
+
+
+#if 0		/* Unused code below */
+
+/*************************************************************
+*  enable_int7(ints)
+*	Enable interrupt 7
+*/
+FRAME(enable_int7,sp,0,ra)
+	.set noreorder
+
+	la	t0,IRDM1	# Set interrupt controller detection mode (bits 2-3 = 0 for int 7 active low)
+	li	t1,0x0
+	sw	t1,(t0)
+
+	la	t0,IRLVL4	# Set interrupt controller level (bit 8-10 = 2 for int 7 at level 2)
+	li	t1,0x200
+	sw	t1,(t0)
+
+	la	t0,IRMSK	# Set interrupt controller mask
+	li	t1,0x0
+	sw	t1,(t0)
+
+	la	t0,IRDEN	# Enable interrupts from controller
+	li	t1,0x1
+	sw	t1,(t0)
+
+	j	ra
+	nop
+	.set reorder
+ENDFRAME(enable_int7)
+
+/*************************************************************
+*  disable_int7(ints)
+*	Disable interrupt 7
+*/
+FRAME(disable_int7,sp,0,ra)
+	.set noreorder
+
+	la	t0,IRLVL4	# Set interrupt controller level (bit 8-10 = 0 to diasble int 7)
+	li	t1,0x200
+	sw	t1,(t0)
+
+	j	ra
+	nop
+	.set reorder
+ENDFRAME(disable_int7)
+#endif
+
+/*************************************************************
+*  exception:
+*       Diagnostic code that can be hooked to PMON interrupt handler.
+*       Generates pulse on PIO22 pin.
+*	Called from _exception code in PMON (see mips.s of PMON).
+*	Return address is located in k1.
+*/
+FRAME(tx49xxexception,sp,0,ra)
+	.set noreorder
+	la	k0,k1tmp
+	sw	k1,(k0)
+
+/* Activate TX49xx PIO22 signal for diagnostics */
+	lui	k0,0xff1f
+	ori	k0,k0,0xf500
+	lw	k0,(k0)
+	lui	k1,0x40
+	or	k1,k1,k0
+	lui	k0,0xff1f
+	ori	k0,k0,0xf500
+	sw	k1,(k0)
+	nop
+
+/* De-activate TX49xx PIO22 signal for diagnostics */
+	lui	k0,0xff1f
+	ori	k0,k0,0xf500
+	lw	k0,(k0)
+	lui	k1,0x40
+	not	k1
+	and	k1,k1,k0
+	lui	k0,0xff1f
+	ori	k0,k0,0xf500
+	sw	k1,(k0)
+	nop
+
+	la	k0,k1tmp
+	lw	k1,(k0)
+	j	k1
+	.set reorder
+ENDFRAME(tx49xxexception)
+
+
+
+
+	.data
+
+k1tmp:	.word	0	/* Temporary strage for K1 during interrupt service */
+
+/*************************************************************
+*
+* Exception handler links, used in PMON exception handler chains
+*/
+	/* Interrupt exception service routine link */
+	.global	_int_esr_link
+_int_esr_link:
+	.word	0
+	.word	bsp_ISR_Handler
+
+	/* Break exception service routine link */
+	.global	_brk_esr_link
+_brk_esr_link:
+	.word	0
+	.word	_BRK_Handler
+
+
+
+
diff --git a/bsps/mips/shared/irq/i8259.c b/bsps/mips/shared/irq/i8259.c
new file mode 100644
index 0000000000..d92b5400a9
--- /dev/null
+++ b/bsps/mips/shared/irq/i8259.c
@@ -0,0 +1,332 @@
+/**
+ *  @file
+ *  
+ *  This file was based upon the powerpc and the i386.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+/*
+ *  Copyright (C) 1998, 1999 valette@crf.canon.fr
+ */
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/i8259.h>
+#include <bsp/pci.h>
+#include <bsp/irq-generic.h>
+#include <rtems/bspIo.h>
+
+
+#define DEBUG_8259      1
+
+#define ValidateIrqLine( _irq ) \
+   if ( ((int)_irq < 0) ||((int)_irq > 16)) return 1;
+
+/*-------------------------------------------------------------------------+
+| Cache for 1st and 2nd PIC IRQ line's status (enabled or disabled) register.
++--------------------------------------------------------------------------*/
+/*
+ * lower byte is interrupt mask on the master PIC.
+ * while upper bits are interrupt on the slave PIC.
+ */
+volatile rtems_i8259_masks i8259s_cache = 0xfffb;
+
+/*-------------------------------------------------------------------------+
+|         Function:  BSP_irq_disable_at_i8259s
+|      Description: Mask IRQ line in appropriate PIC chip.
+| Global Variables: i8259s_cache
+|        Arguments: vector_offset - number of IRQ line to mask.
+|          Returns: original state or -1 on error.
++--------------------------------------------------------------------------*/
+int BSP_irq_disable_at_i8259s    (const rtems_irq_number irqLine)
+{
+  unsigned short        mask;
+  rtems_interrupt_level level;
+  int                   rval;
+
+  ValidateIrqLine(irqLine);
+
+  rtems_interrupt_disable(level);
+
+  /* Recalculate the value */
+  mask = 1 << irqLine;
+  rval = i8259s_cache & mask ? 0 : 1;
+  i8259s_cache |= mask;
+
+  /* Determine which chip and write the value. */
+  if (irqLine < 8) {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_IMR_IO_PORT, 
+      i8259s_cache & 0xff
+    );
+  } else {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_SLAVE_IMR_IO_PORT, 
+      ((i8259s_cache & 0xff00) >> 8)
+    );
+  }
+
+  rtems_interrupt_enable(level);
+
+  return rval;
+}
+
+/*-------------------------------------------------------------------------+
+|         Function:  BSP_irq_enable_at_i8259s
+|      Description: Unmask IRQ line in appropriate PIC chip.
+| Global Variables: i8259s_cache
+|        Arguments: irqLine - number of IRQ line to mask.
+|          Returns: Nothing.
++--------------------------------------------------------------------------*/
+int BSP_irq_enable_at_i8259s    (const rtems_irq_number irqLine)
+{
+  unsigned short        mask;
+  rtems_interrupt_level level;
+  
+  ValidateIrqLine( irqLine );
+
+  rtems_interrupt_disable(level);
+
+  /* Calculate the value */
+  mask = ~(1 << irqLine);
+  i8259s_cache &= mask;
+
+  /* Determine which chip and write the value */
+  if (irqLine < 8) {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_IMR_IO_PORT, 
+      i8259s_cache & 0xff
+    );
+  } else {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_SLAVE_IMR_IO_PORT, 
+      ((i8259s_cache & 0xff00) >> 8)
+    );
+  }
+
+  rtems_interrupt_enable(level);
+
+  return 0;
+} /* mask_irq */
+
+
+int BSP_irq_enabled_at_i8259s(const rtems_irq_number irqLine)
+{
+  unsigned short mask;
+
+  ValidateIrqLine( irqLine );
+
+  mask = (1 << irqLine);
+
+  return  (~(i8259s_cache & mask));
+}
+
+/*-------------------------------------------------------------------------+
+|         Function: BSP_irq_ack_at_i8259s
+|      Description: Signal generic End Of Interrupt (EOI) to appropriate PIC.
+| Global Variables: None.
+|        Arguments: irqLine - number of IRQ line to acknowledge.
+|          Returns: Nothing.
++--------------------------------------------------------------------------*/
+int BSP_irq_ack_at_i8259s (const rtems_irq_number irqLine)
+{
+  if (irqLine >= 8) {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_COMMAND_IO_PORT, 
+      SLAVE_PIC_EOSI
+    );
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_SLAVE_COMMAND_IO_PORT, 
+      (PIC_EOSI | (irqLine - 8))
+    );
+  }else {
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_COMMAND_IO_PORT, 
+      (PIC_EOSI | irqLine)
+    );
+  }
+
+  return 0;
+
+} /* ackIRQ */
+
+void BSP_i8259s_init(void)
+{
+  volatile uint32_t i;
+
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_IMR_IO_PORT, 0xff );
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT,  0xff );
+  
+
+  /*
+   * init master 8259 interrupt controller
+   */
+
+  /* Start init sequence */
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_MASTER_COMMAND_IO_PORT, 
+    0x11
+  );
+  /* Vector base  = 0 */
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_MASTER_IMR_IO_PORT, 
+    0x00
+  );
+
+  /* edge tiggered, Cascade (slave) on IRQ2 */
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_MASTER_IMR_IO_PORT, 
+    0x04
+  );
+
+  /* Select 8086 mode */
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_MASTER_IMR_IO_PORT, 
+    0x01
+  );
+
+  /*
+   * init slave  interrupt controller
+   */
+
+  /* Start init sequence */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_COMMAND_IO_PORT, 0x11); 
+
+  /* Vector base  = 8 */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0x08);
+
+  /* edge triggered, Cascade (slave) on IRQ2 */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0x02);
+
+  /* Select 8086 mode */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0x01); 
+
+  /* Mask all except cascade */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_IMR_IO_PORT, 0xFB); 
+
+  /* Mask all */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0xFF); 
+
+  /*
+   * Enable all interrupts in debug mode.
+   */
+
+  if ( DEBUG_8259 ) {
+     i8259s_cache = 0x0101;
+  }
+
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_MASTER_IMR_IO_PORT, 
+    i8259s_cache & 0xff
+  );
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_SLAVE_IMR_IO_PORT, 
+    ((i8259s_cache & 0xff00) >> 8)
+  );
+
+  for (i=0; i<10000; i++);
+}
+
+#define PCI__GEN(bus, off, num)		(((off)^((bus) << 7))+((num) << 4))
+#define PCI_INTR_ACK(bus)		PCI__GEN(bus, 0x0c34, 0)
+
+volatile uint8_t  master;
+volatile uint8_t  slave;
+volatile uint8_t  temp;
+
+void bsp_show_interrupt_regs(void);
+void bsp_show_interrupt_regs() {
+  unsigned int sr;
+  unsigned int cause;
+  unsigned int pending;
+
+  mips_get_sr( sr ); 
+  mips_get_cause( cause );
+  pending = (cause & sr & 0xff00) >> CAUSE_IPSHIFT;
+
+  master = simple_in_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_COMMAND_IO_PORT);
+  slave  = simple_in_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_COMMAND_IO_PORT);
+
+  printk("sr: 0x%x cause: 0x%x pending: 0x%x  master: 0x%x slave: 0x%x\n", 
+    sr, cause, pending, master, slave 
+  );
+}
+
+int BSP_i8259s_int_process()
+{
+  uint8_t           irq;
+  volatile uint32_t temp;
+
+  /* Get the Interrupt */
+  irq = simple_in_le32(BSP_PCI_BASE_ADDRESS, PCI_INTR_ACK(0) );
+
+  /*
+   *  Mask interrupts
+   *   + Mask all except cascade on master
+   *   + Mask all on slave
+   */
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_IMR_IO_PORT, 0xFB);
+  simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0xFF);
+
+  /* Call the Handler */
+  temp = irq + MALTA_SB_IRQ_0;
+  bsp_interrupt_handler_dispatch( temp );
+
+  /* Reset the interrupt on the 8259 either the master or the slave chip */
+  if (irq & 8) {
+    temp = simple_in_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT);
+
+    /* Mask all */
+    simple_out_8(BSP_8259_BASE_ADDRESS, PIC_SLAVE_IMR_IO_PORT, 0xFF); 
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_SLAVE_COMMAND_IO_PORT, 
+      (PIC_EOSI + (irq&7))
+    );
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_COMMAND_IO_PORT, 
+      SLAVE_PIC_EOSI 
+    );
+  } else {
+    temp = simple_in_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_IMR_IO_PORT);
+    /* Mask all except cascade */
+    simple_out_8(BSP_8259_BASE_ADDRESS, PIC_MASTER_IMR_IO_PORT, 0xFB);
+    simple_out_8(
+      BSP_8259_BASE_ADDRESS, 
+      PIC_MASTER_COMMAND_IO_PORT, 
+      (PIC_EOSI+irq)
+    );
+  }
+
+  /* Restore the interrupts */
+  simple_out_8(BSP_8259_BASE_ADDRESS,PIC_MASTER_IMR_IO_PORT,i8259s_cache&0xff);
+  simple_out_8(
+    BSP_8259_BASE_ADDRESS, 
+    PIC_SLAVE_IMR_IO_PORT, 
+    ((i8259s_cache & 0xff00) >> 8)
+  );
+
+  return 0;
+}
diff --git a/bsps/mips/shared/irq/interruptmask.c b/bsps/mips/shared/irq/interruptmask.c
new file mode 100644
index 0000000000..c63421e569
--- /dev/null
+++ b/bsps/mips/shared/irq/interruptmask.c
@@ -0,0 +1,29 @@
+/**
+ *  @file
+ *  
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+
+/*
+ *  This function returns a mask value which is used to select the bits
+ *  in the processor status register that can be set to enable interrupts.
+ *  The mask value should not include the 2 software interrupt enable bits.
+ */
+
+uint32_t mips_interrupt_mask( void )
+{
+  uint32_t interrupt_mask;
+
+  interrupt_mask = 0x0000fc00;
+  return(interrupt_mask);
+}
diff --git a/bsps/mips/shared/irq/interruptmask_TX49.c b/bsps/mips/shared/irq/interruptmask_TX49.c
new file mode 100644
index 0000000000..5b1daa57c3
--- /dev/null
+++ b/bsps/mips/shared/irq/interruptmask_TX49.c
@@ -0,0 +1,29 @@
+/**
+ *  @file
+ *  
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+
+/*
+ *  This function returns a mask value which is used to select the bits
+ *  in the processor status register that can be set to enable interrupts.
+ *  The mask value should not include the 2 software interrupt enable bits.
+ */
+
+uint32_t mips_interrupt_mask( void )
+{
+  uint32_t interrupt_mask;
+
+  interrupt_mask = 0x00000400;			/* Toshiba TX49 processors have a non-standard interrupt mask */
+  return(interrupt_mask);
+}
diff --git a/bsps/mips/shared/irq/irq.c b/bsps/mips/shared/irq/irq.c
new file mode 100644
index 0000000000..1c2d3b8c5b
--- /dev/null
+++ b/bsps/mips/shared/irq/irq.c
@@ -0,0 +1,101 @@
+/**
+ * @file
+ *
+ * @ingroup bsp_interrupt
+ *
+ * @brief Interrupt support.
+ */
+
+/*
+ *  Copyright (c) 2005 by Cogent Computer Systems
+ *  Written by Jay Monkman <jtm@lopingdog.com>
+ *
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+
+#include <inttypes.h>
+
+#include <bsp.h>
+#include <bsp/irq.h>
+#include <bsp/irq-generic.h>
+#include <libcpu/isr_entries.h>
+#include <rtems/bspIo.h>
+
+static const char *const cause_strings[32] = {
+  /*  0 */ "Int",
+  /*  1 */ "TLB Mods",
+  /*  2 */ "TLB Load",
+  /*  3 */ "TLB Store",
+  /*  4 */ "Address Load",
+  /*  5 */ "Address Store",
+  /*  6 */ "Instruction Bus Error",
+  /*  7 */ "Data Bus Error",
+  /*  8 */ "Syscall",
+  /*  9 */ "Breakpoint",
+  /* 10 */ "Reserved Instruction",
+  /* 11 */ "Coprocessor Unuseable",
+  /* 12 */ "Overflow",
+  /* 13 */ "Trap",
+  /* 14 */ "Instruction Virtual Coherency Error",
+  /* 15 */ "FP Exception",
+  /* 16 */ "Reserved 16",
+  /* 17 */ "Reserved 17",
+  /* 18 */ "Reserved 18",
+  /* 19 */ "Reserved 19",
+  /* 20 */ "Reserved 20",
+  /* 21 */ "Reserved 21",
+  /* 22 */ "Reserved 22",
+  /* 23 */ "Watch",
+  /* 24 */ "Reserved 24",
+  /* 25 */ "Reserved 25",
+  /* 26 */ "Reserved 26",
+  /* 27 */ "Reserved 27",
+  /* 28 */ "Reserved 28",
+  /* 29 */ "Reserved 29",
+  /* 30 */ "Reserved 30",
+  /* 31 */ "Data Virtual Coherency Error"
+};
+
+static inline bool bsp_irq_is_valid(rtems_vector_number vector)
+{
+  return vector <= BSP_INTERRUPT_VECTOR_MAX;
+}
+
+void bsp_interrupt_vector_enable(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+}
+
+void bsp_interrupt_vector_disable(rtems_vector_number vector)
+{
+  bsp_interrupt_assert(bsp_interrupt_is_valid_vector(vector));
+}
+
+rtems_status_code bsp_interrupt_facility_initialize(void)
+{
+  mips_install_isr_entries();
+  return RTEMS_SUCCESSFUL;
+}
+
+void bsp_interrupt_handler_default(rtems_vector_number vector)
+{
+  uint32_t sr;
+  uint32_t cause;
+
+  mips_get_sr( sr );
+  mips_get_cause( cause );
+
+  printk( "Unhandled exception %" PRId32 "\n", vector );
+  printk( "sr: 0x%08" PRIu32 "  cause: 0x%08" PRIu32 " --> %s\n", sr, cause,
+     cause_strings[(cause >> 2) &0x1f] );
+  #if 0
+    mips_dump_exception_frame( frame );
+  #endif
+  rtems_fatal_error_occurred(1);
+}
diff --git a/bsps/mips/shared/irq/vectorexceptions.c b/bsps/mips/shared/irq/vectorexceptions.c
new file mode 100644
index 0000000000..cdfd94c136
--- /dev/null
+++ b/bsps/mips/shared/irq/vectorexceptions.c
@@ -0,0 +1,81 @@
+/**
+ *  @file
+ *  
+ *  Common Code for Vectoring MIPS Exceptions
+ *
+ *  The actual decoding of the cause register and vector number assignment
+ *  is CPU model specific.
+ */
+
+/*
+ *  COPYRIGHT (c) 1989-2012.
+ *  On-Line Applications Research Corporation (OAR).
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.rtems.org/license/LICENSE.
+ */
+
+#include <rtems.h>
+#include <inttypes.h>
+#include <stdlib.h>
+#include <string.h>
+#include <rtems/mips/iregdef.h>
+#include <rtems/mips/idtcpu.h>
+#include <rtems/bspIo.h>
+#include <bsp/irq-generic.h>
+
+struct regdef
+{
+  int  offset;
+  char *name;
+};
+
+static const struct regdef dumpregs[]= {
+  { R_RA, "R_RA" }, { R_V0, "R_V0" },     { R_V1, "R_V1" },
+  { R_A0, "R_A0" }, { R_A1, "R_A1" },     { R_A2, "R_A2" },
+  { R_A3, "R_A3" }, { R_T0, "R_T0" },     { R_T1, "R_T1" },
+  { R_T2, "R_T2" }, { R_T3, "R_T3" },     { R_T4, "R_T4" },
+  { R_T5, "R_T5" }, { R_T6, "R_T6" },     { R_T7, "R_T7" },
+  { R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" },
+  { R_GP, "R_GP" }, { R_FP, "R_FP" },     { R_AT, "R_AT" },
+  { R_EPC,"R_EPC"}, { -1, NULL }
+};
+
+void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
+{
+  uint32_t *frame_u32;
+  int   i, j;
+
+  frame_u32 = (uint32_t *)frame;
+  for(i=0; dumpregs[i].offset > -1; i++)
+  {
+     printk("   %s", dumpregs[i].name);
+     for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" ");
+#if (__mips == 1 ) || (__mips == 32)
+     printk("  %08" PRIu32 "%c",
+            frame_u32[dumpregs[i].offset], (i%3) ? '\t' : '\n' );
+#elif __mips == 3
+     printk("  %08" PRIu32 "", frame_u32[2 * dumpregs[i].offset + 1] );
+     printk("%08" PRIu32 "%c",
+            frame_u32[2 * dumpregs[i].offset], (i%2) ? '\t' : '\n' );
+#endif
+  }
+  printk( "\n" );
+}
+
+/*
+ *  There are constants defined for these but they should basically
+ *  all be close to the same set.
+ */
+
+void mips_vector_exceptions( CPU_Interrupt_frame *frame )
+{
+  uint32_t   cause;
+  uint32_t   exc;
+
+  mips_get_cause( cause );
+  exc = (cause >> 2) & 0x1f;
+
+  bsp_interrupt_handler_dispatch( exc );
+}