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author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-19 06:35:52 +0200 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-04-20 09:57:01 +0200 |
commit | 7632906fc290b652416ab59eb5fb49356c064ed6 (patch) | |
tree | ac036b1f95637e044e10138ceea8d2b56d80ec97 /bsps/mips/csb350 | |
parent | bsps: Move bspsmpgetcurrentprocessor.c to bsps (diff) | |
download | rtems-7632906fc290b652416ab59eb5fb49356c064ed6.tar.bz2 |
bsps: Move clock drivers to bsps
This patch is a part of the BSP source reorganization.
Update #3285.
Diffstat (limited to 'bsps/mips/csb350')
-rw-r--r-- | bsps/mips/csb350/clock/clockdrv.c | 90 |
1 files changed, 90 insertions, 0 deletions
diff --git a/bsps/mips/csb350/clock/clockdrv.c b/bsps/mips/csb350/clock/clockdrv.c new file mode 100644 index 0000000000..e42261e529 --- /dev/null +++ b/bsps/mips/csb350/clock/clockdrv.c @@ -0,0 +1,90 @@ +/** + * @file + * + * Instantiate the clock driver shell. + * + * This uses the TOY (Time of Year) timer to implement the clock. + */ + +/* + * Copyright (c) 2005 by Cogent Computer Systems + * Written by Jay Monkman <jtm@lopingdog.com> + * + * The license and distribution terms for this file may be + * found in the file LICENSE in this distribution or at + * http://www.rtems.org/license/LICENSE. + */ + +#include <rtems.h> +#include <bsp.h> +#include <bsp/irq.h> +#include <rtems/bspIo.h> + +uint32_t tick_interval; +uint32_t last_match; + +void au1x00_clock_init(void); + +#define CLOCK_VECTOR AU1X00_IRQ_TOY_MATCH2 + +#define Clock_driver_support_at_tick() \ + do { \ + while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0); \ + last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR); \ + AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + tick_interval; \ + au_sync(); \ + } while(0) + +/* Set for rising edge interrupt */ +#define Clock_driver_support_install_isr( _new ) \ + do { \ + rtems_interrupt_handler_install( \ + CLOCK_VECTOR, \ + "clock", \ + 0, \ + _new, \ + NULL \ + ); \ + AU1X00_IC_MASKCLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ + AU1X00_IC_SRCSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ + AU1X00_IC_CFG0SET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ + AU1X00_IC_CFG1CLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ + AU1X00_IC_CFG2CLR(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ + AU1X00_IC_ASSIGNSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; \ + } while(0) + +void au1x00_clock_init(void) +{ + uint32_t wakemask; + /* Clear the trim register */ + AU1X00_SYS_TOYTRIM(AU1X00_SYS_ADDR) = 0; + + /* Clear the TOY counter */ + while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS); + AU1X00_SYS_TOYWRITE(AU1X00_SYS_ADDR) = 0; + while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TS); + + wakemask = AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR); + wakemask |= AU1X00_SYS_WAKEMSK_M20; + AU1X00_SYS_WAKEMSK(AU1X00_SYS_ADDR) = wakemask; + AU1X00_IC_WAKESET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; + + tick_interval = 32768 * rtems_configuration_get_microseconds_per_tick(); + tick_interval = tick_interval / 1000000; + + last_match = AU1X00_SYS_TOYREAD(AU1X00_SYS_ADDR); + AU1X00_SYS_TOYMATCH2(AU1X00_SYS_ADDR) = last_match + (50*tick_interval); + AU1X00_IC_MASKSET(AU1X00_IC0_ADDR) = AU1X00_IC_IRQ_TOY_MATCH2; + while (AU1X00_SYS_CNTCTRL(AU1X00_SYS_ADDR) & AU1X00_SYS_CNTCTRL_TM0); +} + +#define Clock_driver_support_initialize_hardware() \ + do { \ + au1x00_clock_init(); \ + } while(0) + +#define Clock_driver_support_shutdown_hardware() + +#define CLOCK_DRIVER_USE_DUMMY_TIMECOUNTER + +#include "../../../shared/dev/clock/clockimpl.h" |