diff options
| author | Karel Gardas <karel@functional.vision> | 2022-04-01 18:14:17 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2022-04-05 09:56:06 +0200 |
| commit | b50f3e88c25f4b1789e8eb3b2119aad089de03bb (patch) | |
| tree | 6279b3a24ef10486d843ac96673e78bcb385a296 /bsps/arm | |
| parent | bsp/stm32h7: disable ethernet for STM32H7B3I-DK BSP variant (diff) | |
| download | rtems-b50f3e88c25f4b1789e8eb3b2119aad089de03bb.tar.bz2 | |
bsp/stm32h7: configure AHB clock divider for STM32H7B3xxQ (e.g. STM32H7B3I-DK BSP)
Diffstat (limited to 'bsps/arm')
| -rw-r--r-- | bsps/arm/stm32h7/start/stm32h7-config-clk.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/bsps/arm/stm32h7/start/stm32h7-config-clk.c b/bsps/arm/stm32h7/start/stm32h7-config-clk.c index 3e7c930201..4c25241b99 100644 --- a/bsps/arm/stm32h7/start/stm32h7-config-clk.c +++ b/bsps/arm/stm32h7/start/stm32h7-config-clk.c @@ -37,7 +37,11 @@ const RCC_ClkInitTypeDef stm32h7_config_clocks = { | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1, .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK, .SYSCLKDivider = RCC_SYSCLK_DIV1, +#ifdef STM32H7B3xxQ + .AHBCLKDivider = RCC_HCLK_DIV1, +#else .AHBCLKDivider = RCC_HCLK_DIV2, +#endif .APB3CLKDivider = RCC_APB3_DIV2, .APB1CLKDivider = RCC_APB1_DIV2, .APB2CLKDivider = RCC_APB2_DIV2, |