From b50f3e88c25f4b1789e8eb3b2119aad089de03bb Mon Sep 17 00:00:00 2001 From: Karel Gardas Date: Fri, 1 Apr 2022 18:14:17 +0200 Subject: bsp/stm32h7: configure AHB clock divider for STM32H7B3xxQ (e.g. STM32H7B3I-DK BSP) --- bsps/arm/stm32h7/start/stm32h7-config-clk.c | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'bsps/arm') diff --git a/bsps/arm/stm32h7/start/stm32h7-config-clk.c b/bsps/arm/stm32h7/start/stm32h7-config-clk.c index 3e7c930201..4c25241b99 100644 --- a/bsps/arm/stm32h7/start/stm32h7-config-clk.c +++ b/bsps/arm/stm32h7/start/stm32h7-config-clk.c @@ -37,7 +37,11 @@ const RCC_ClkInitTypeDef stm32h7_config_clocks = { | RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1, .SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK, .SYSCLKDivider = RCC_SYSCLK_DIV1, +#ifdef STM32H7B3xxQ + .AHBCLKDivider = RCC_HCLK_DIV1, +#else .AHBCLKDivider = RCC_HCLK_DIV2, +#endif .APB3CLKDivider = RCC_APB3_DIV2, .APB1CLKDivider = RCC_APB1_DIV2, .APB2CLKDivider = RCC_APB2_DIV2, -- cgit v1.2.3