Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

1 files changed, 115 insertions, 0 deletions

diff --git a/bsps/arm/xilinx-zynq/include/bsp/irq.h b/bsps/arm/xilinx-zynq/include/bsp/irq.h
new file mode 100644
index 0000000000..e8288938fe
--- /dev/null
+++ b/bsps/arm/xilinx-zynq/include/bsp/irq.h
@@ -0,0 +1,115 @@
+/**
+ * @file
+ * @ingroup zynq_interrupt
+ * @brief Interrupt definitions.
+ */
+
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
+#define LIBBSP_ARM_XILINX_ZYNQ_IRQ_H
+
+#ifndef ASM
+
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#include <bsp/arm-a9mpcore-irq.h>
+#include <bsp/arm-gic-irq.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/**
+ * @defgroup zynq_interrupt Interrupt Support
+ * @ingroup arm_zynq
+ * @brief Interrupt Support
+ * @{
+ */
+
+#define ZYNQ_IRQ_CPU_0 32
+#define ZYNQ_IRQ_CPU_1 33
+#define ZYNQ_IRQ_L2_CACHE 34
+#define ZYNQ_IRQ_OCM 35
+#define ZYNQ_IRQ_PMU_0 37
+#define ZYNQ_IRQ_PMU_1 38
+#define ZYNQ_IRQ_XADC 39
+#define ZYNQ_IRQ_DVI 40
+#define ZYNQ_IRQ_SWDT 41
+#define ZYNQ_IRQ_TTC_0_0 42
+#define ZYNQ_IRQ_TTC_1_0 43
+#define ZYNQ_IRQ_TTC_2_0 44
+#define ZYNQ_IRQ_DMAC_ABORT 45
+#define ZYNQ_IRQ_DMAC_0 46
+#define ZYNQ_IRQ_DMAC_1 47
+#define ZYNQ_IRQ_DMAC_2 48
+#define ZYNQ_IRQ_DMAC_3 49
+#define ZYNQ_IRQ_SMC 50
+#define ZYNQ_IRQ_QUAD_SPI 51
+#define ZYNQ_IRQ_GPIO 52
+#define ZYNQ_IRQ_USB_0 53
+#define ZYNQ_IRQ_ETHERNET_0 54
+#define ZYNQ_IRQ_ETHERNET_0_WAKEUP 55
+#define ZYNQ_IRQ_SDIO_0 56
+#define ZYNQ_IRQ_I2C_0 57
+#define ZYNQ_IRQ_SPI_0 58
+#define ZYNQ_IRQ_UART_0 59
+#define ZYNQ_IRQ_CAN_0 60
+#define ZYNQ_IRQ_FPGA_0 61
+#define ZYNQ_IRQ_FPGA_1 62
+#define ZYNQ_IRQ_FPGA_2 63
+#define ZYNQ_IRQ_FPGA_3 64
+#define ZYNQ_IRQ_FPGA_4 65
+#define ZYNQ_IRQ_FPGA_5 66
+#define ZYNQ_IRQ_FPGA_6 67
+#define ZYNQ_IRQ_FPGA_7 68
+#define ZYNQ_IRQ_TTC_0_1 69
+#define ZYNQ_IRQ_TTC_1_1 70
+#define ZYNQ_IRQ_TTC_2_1 71
+#define ZYNQ_IRQ_DMAC_4 72
+#define ZYNQ_IRQ_DMAC_5 73
+#define ZYNQ_IRQ_DMAC_6 74
+#define ZYNQ_IRQ_DMAC_7 75
+#define ZYNQ_IRQ_USB_1 76
+#define ZYNQ_IRQ_ETHERNET_1 77
+#define ZYNQ_IRQ_ETHERNET_1_WAKEUP 78
+#define ZYNQ_IRQ_SDIO_1 79
+#define ZYNQ_IRQ_I2C_1 80
+#define ZYNQ_IRQ_SPI_1 81
+#define ZYNQ_IRQ_UART_1 82
+#define ZYNQ_IRQ_CAN_1 83
+#define ZYNQ_IRQ_FPGA_8 84
+#define ZYNQ_IRQ_FPGA_9 85
+#define ZYNQ_IRQ_FPGA_10 86
+#define ZYNQ_IRQ_FPGA_11 87
+#define ZYNQ_IRQ_FPGA_12 88
+#define ZYNQ_IRQ_FPGA_13 89
+#define ZYNQ_IRQ_FPGA_14 90
+#define ZYNQ_IRQ_FPGA_15 91
+#define ZYNQ_IRQ_PARITY 92
+
+#define BSP_INTERRUPT_VECTOR_MIN 0
+#define BSP_INTERRUPT_VECTOR_MAX 92
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_XILINX_ZYNQ_IRQ_H */