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authorChris Johns <chrisj@rtems.org>2017-12-23 18:18:56 +1100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-01-25 08:45:26 +0100
commit2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 (patch)
tree44759efe9374f13200a97e96d91bd9a2b7e5ce2a /bsps/arm
parentMAINTAINERS: Add myself to Write After Approval. (diff)
downloadrtems-2afb22b7e1ebcbe40373ff7e0efae7d207c655a9.tar.bz2
Remove make preinstall
A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
Diffstat (limited to 'bsps/arm')
-rw-r--r--bsps/arm/altera-cyclone-v/headers.am45
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp.h50
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h1555
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h825
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h964
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h114
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h1434
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h1007
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h162
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h951
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h1254
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h56
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h2024
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h533
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h156
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h167
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h291
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/hwlib.h189
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h76
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/irq.h41
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h3569
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h6464
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h144
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h144
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h1991
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h5940
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h6299
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h5951
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h52
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h3382
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h4149
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h24810
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h5158
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h8026
-rw-r--r--bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h259
-rw-r--r--bsps/arm/altera-cyclone-v/include/tm27.h24
-rw-r--r--bsps/arm/atsam/headers.am269
-rw-r--r--bsps/arm/atsam/include/bsp.h102
-rw-r--r--bsps/arm/atsam/include/bsp/atsam-clock-config.h62
-rw-r--r--bsps/arm/atsam/include/bsp/atsam-i2c.h74
-rw-r--r--bsps/arm/atsam/include/bsp/atsam-spi.h36
-rw-r--r--bsps/arm/atsam/include/bsp/i2c.h36
-rw-r--r--bsps/arm/atsam/include/bsp/irq.h30
-rw-r--r--bsps/arm/atsam/include/bsp/pin-config.h36
-rw-r--r--bsps/arm/atsam/include/bsp/power.h245
-rw-r--r--bsps/arm/atsam/include/bsp/sc16is752.h68
-rw-r--r--bsps/arm/atsam/include/bsp/spi.h36
-rw-r--r--bsps/arm/atsam/include/libchip/chip.h124
-rw-r--r--bsps/arm/atsam/include/libchip/compiler.h476
-rw-r--r--bsps/arm/atsam/include/libchip/include/acc.h152
-rw-r--r--bsps/arm/atsam/include/libchip/include/adc.h179
-rw-r--r--bsps/arm/atsam/include/libchip/include/aes.h68
-rw-r--r--bsps/arm/atsam/include/libchip/include/afe_dma.h116
-rw-r--r--bsps/arm/atsam/include/libchip/include/afec.h190
-rw-r--r--bsps/arm/atsam/include/libchip/include/chip.h1
-rw-r--r--bsps/arm/atsam/include/libchip/include/dac_dma.h150
-rw-r--r--bsps/arm/atsam/include/libchip/include/efc.h128
-rw-r--r--bsps/arm/atsam/include/libchip/include/exceptions.h52
-rw-r--r--bsps/arm/atsam/include/libchip/include/flashd.h91
-rw-r--r--bsps/arm/atsam/include/libchip/include/gmac.h349
-rw-r--r--bsps/arm/atsam/include/libchip/include/gmacd.h283
-rw-r--r--bsps/arm/atsam/include/libchip/include/hsmci.h155
-rw-r--r--bsps/arm/atsam/include/libchip/include/icm.h112
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-rw-r--r--bsps/arm/atsam/include/libchip/include/iso7816_4.h110
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-rw-r--r--bsps/arm/atsam/include/libchip/include/mcid.h170
-rw-r--r--bsps/arm/atsam/include/libchip/include/mediaLB.h45
-rw-r--r--bsps/arm/atsam/include/libchip/include/mpu.h222
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-rw-r--r--bsps/arm/atsam/include/libchip/include/pio_capture.h79
-rw-r--r--bsps/arm/atsam/include/libchip/include/pio_it.h117
-rw-r--r--bsps/arm/atsam/include/libchip/include/pmc.h101
-rw-r--r--bsps/arm/atsam/include/libchip/include/pwmc.h137
-rw-r--r--bsps/arm/atsam/include/libchip/include/qspi.h236
-rw-r--r--bsps/arm/atsam/include/libchip/include/qspi_dma.h115
-rw-r--r--bsps/arm/atsam/include/libchip/include/rstc.h64
-rw-r--r--bsps/arm/atsam/include/libchip/include/rtc.h102
-rw-r--r--bsps/arm/atsam/include/libchip/include/rtt.h82
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_acc.h128
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_aes.h191
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_afec.h483
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_chipid.h123
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_dacc.h184
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_efc.h111
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_gmac.h1240
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_gpbr.h53
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_hsmci.h335
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_icm.h192
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_isi.h280
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_matrix.h301
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_mcan.h845
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_pio.h1711
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_pmc.h723
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_pwm.h644
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_qspi.h216
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_rstc.h79
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_rswdt.h72
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_rtc.h234
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_rtt.h71
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_sdramc.h173
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_smc.h144
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_spi.h161
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_ssc.h280
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_supc.h295
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_tc.h346
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_trng.h73
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_twihs.h250
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_uart.h151
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_usart.h478
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_usbhs.h909
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_utmi.h63
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_wdt.h72
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/component/component_xdmac.h616
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70j19.h431
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-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70n19.h495
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-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q19.h668
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q20.h668
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/pio/pio_same70q21.h668
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/same70.h55
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/same70j19.h623
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/same70j20.h630
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/same70j21.h630
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/same70n19.h636
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-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/same70n21.h636
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/same70q19.h684
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-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/same70q21.h689
-rw-r--r--bsps/arm/atsam/include/libchip/include/same70/system_same70.h80
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_acc.h128
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_aes.h191
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_afec.h483
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_chipid.h123
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_dacc.h184
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_efc.h111
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_gpbr.h53
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_hsmci.h335
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_icm.h192
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_isi.h280
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_matrix.h461
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_pio.h1711
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_pmc.h786
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_pwm.h667
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_qspi.h216
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_rstc.h79
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_rswdt.h72
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_rtc.h234
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_rtt.h71
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_sdramc.h173
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_smc.h144
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_spi.h161
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_ssc.h280
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_supc.h295
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_tc.h346
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_trng.h73
-rw-r--r--bsps/arm/atsam/include/libchip/include/sams70/component/component_twihs.h250
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-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_dma.h711
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_dmm.h557
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_efuse.h126
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_emacc.h285
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_emacm.h898
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_emif.h468
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_esm.h170
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_flash.h675
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_flex_ray.h618
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_gio.h324
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_htu.h333
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_i2c.h363
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_iomm.h235
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_lin.h594
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_mdio.h230
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_n2het.h332
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_pbist.h195
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_pcr.h120
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_pll.h298
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_pmm.h258
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_pom.h309
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_rti.h359
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_rtp.h227
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_sci.h450
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_spi.h918
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_stc.h158
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_sys.h695
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_sys2.h170
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_tcr.h84
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_tcram.h170
-rw-r--r--bsps/arm/tms570/include/bsp/ti_herc/reg_vim.h190
-rw-r--r--bsps/arm/tms570/include/bsp/tms570-pinmux.h137
-rw-r--r--bsps/arm/tms570/include/bsp/tms570-pins.h10
-rw-r--r--bsps/arm/tms570/include/bsp/tms570-pom.h60
-rw-r--r--bsps/arm/tms570/include/bsp/tms570-rti.h46
-rw-r--r--bsps/arm/tms570/include/bsp/tms570-sci-driver.h65
-rw-r--r--bsps/arm/tms570/include/bsp/tms570-sci.h45
-rw-r--r--bsps/arm/tms570/include/bsp/tms570-vim.h48
-rw-r--r--bsps/arm/tms570/include/bsp/tms570.h137
-rw-r--r--bsps/arm/tms570/include/bsp/tms570_hwinit.h31
-rw-r--r--bsps/arm/tms570/include/bsp/tms570_selftest.h214
-rw-r--r--bsps/arm/tms570/include/bsp/tms570_selftest_parity.h110
-rw-r--r--bsps/arm/tms570/include/bsp/tms570lc4357-pins.h1114
-rw-r--r--bsps/arm/tms570/include/bsp/tms570ls3137zwt-pins.h690
-rw-r--r--bsps/arm/tms570/include/tm27.h1
-rw-r--r--bsps/arm/xilinx-zynq/headers.am15
-rw-r--r--bsps/arm/xilinx-zynq/include/bsp.h80
-rw-r--r--bsps/arm/xilinx-zynq/include/bsp/cadence-i2c-regs.h73
-rw-r--r--bsps/arm/xilinx-zynq/include/bsp/cadence-i2c.h35
-rw-r--r--bsps/arm/xilinx-zynq/include/bsp/i2c.h50
-rw-r--r--bsps/arm/xilinx-zynq/include/bsp/irq.h115
-rw-r--r--bsps/arm/xilinx-zynq/include/bsp/zynq-uart-regs.h150
-rw-r--r--bsps/arm/xilinx-zynq/include/bsp/zynq-uart.h67
-rw-r--r--bsps/arm/xilinx-zynq/include/tm27.h36
538 files changed, 221145 insertions, 0 deletions
diff --git a/bsps/arm/altera-cyclone-v/headers.am b/bsps/arm/altera-cyclone-v/headers.am
new file mode 100644
index 0000000000..f63ee38854
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/headers.am
@@ -0,0 +1,45 @@
+## This file was generated by "./boostrap -H".
+
+include_HEADERS =
+include_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp.h
+include_HEADERS += include/bspopts.h
+include_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/tm27.h
+
+include_bspdir = $(includedir)/bsp
+include_bsp_HEADERS =
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/hwlib.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h
+include_bsp_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/irq.h
+
+include_bsp_socaldir = $(includedir)/bsp/socal
+include_bsp_socal_HEADERS =
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_clkmgr.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmanonsecure.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_dmasecure.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_gpio.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_i2c.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_l3.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspi.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_qspidata.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_rstmgr.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sdr.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_sysmgr.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/alt_uart.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/hps.h
+include_bsp_socal_HEADERS += ../../../../../../bsps/arm/altera-cyclone-v/include/bsp/socal/socal.h
diff --git a/bsps/arm/altera-cyclone-v/include/bsp.h b/bsps/arm/altera-cyclone-v/include/bsp.h
new file mode 100644
index 0000000000..4118823958
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp.h
@@ -0,0 +1,50 @@
+/*
+ * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ * <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H
+#define LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H
+
+#include <bspopts.h>
+
+#define BSP_FEATURE_IRQ_EXTENSION
+
+#ifndef ASM
+
+#include <rtems.h>
+
+#include <bsp/default-initial-extension.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define BSP_ARM_A9MPCORE_SCU_BASE 0xFFFEC000
+
+#define BSP_ARM_GIC_CPUIF_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000100 )
+
+#define BSP_ARM_A9MPCORE_GT_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00000200 )
+
+#define BSP_ARM_GIC_DIST_BASE ( BSP_ARM_A9MPCORE_SCU_BASE + 0x00001000 )
+
+#define BSP_ARM_L2C_310_BASE 0xfffef000
+
+#define BSP_ARM_L2C_310_ID 0x410000c9
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h
new file mode 100644
index 0000000000..bca6f63e00
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_16550_uart.h
@@ -0,0 +1,1555 @@
+/*
+ * Altera - SoC UART Manager
+ */
+
+/*****************************************************************************
+ *
+ * Copyright 2013 Altera Corporation. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
+ * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
+ * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+ * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
+ * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+ * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ *****************************************************************************/
+
+#ifndef __ALT_16550_UART_H__
+#define __ALT_16550_UART_H__
+
+#include "hwlib.h"
+#include "alt_clock_manager.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+ * \addtogroup UART UART Driver API
+ *
+ * This module defines the Universal Asynchronous Receiver/Transmitter (UART)
+ * API for accessing and using the UART resources. The API allows for general
+ * control of a 16550 compatible UART controller.
+ *
+ * This implementation can control the following UARTs:
+ * * SoCFPGA On-board UARTs
+ * * Altera 16550 Compatible Soft IP UART
+ *
+ * The following reference materials were used in the design of this API:
+ * * Synopsys&reg; DesignWare DW_apb_uart Databook v3.10a
+ *
+ * @{
+ */
+
+/*!
+ * \addtogroup UART_BASIC UART Basic
+ *
+ * This group of APIs provides basic access to the UART to initialize,
+ * uninitialize, read, write, and reset the UART.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the list of UARTs available on the system.
+ */
+typedef enum ALT_16550_DEVICE_e
+{
+ /*!
+ * This option selects UART0 in the SoC FPGA.
+ */
+ ALT_16550_DEVICE_SOCFPGA_UART0 = 0,
+
+ /*!
+ * This option selects UART1 in the SoC FPGA.
+ */
+ ALT_16550_DEVICE_SOCFPGA_UART1 = 1,
+
+ /*!
+ * This option selects an Altera 16550 Compatible soft IP UART. The memory
+ * location of the device must be provided as part of the initialization.
+ */
+ ALT_16550_DEVICE_ALTERA_16550_UART = 0x100
+}
+ALT_16550_DEVICE_t;
+
+/*!
+ * This structure is used to represent a handle to a specific UART on the
+ * system. The internal members are undocumented and should be not altered
+ * outside of this API.
+ */
+typedef struct ALT_16550_HANDLE_s
+{
+ ALT_16550_DEVICE_t device;
+ void * location;
+ alt_freq_t clock_freq;
+ uint32_t data;
+ uint32_t fcr;
+}
+ALT_16550_HANDLE_t;
+
+/*!
+ * Performs the initialization steps needed by the UART. This should be the
+ * first API call made when accessing a particular UART
+ *
+ * The default UART setting is 8 databits, no parity, 1 stopbit, and 57600
+ * baud.
+ *
+ * For the SoCFPGA UARTs, The ALT_CLK_L4_SP clock needs to be setup before
+ * initialization.
+ *
+ * \param device
+ * The UART device identifier.
+ *
+ * \param location
+ * The memory of the location for the given UART. For SoCFPGA
+ * UARTs, this parameter is ignored.
+ *
+ * \param clock_freq
+ * The clock frequency of the serial clock for the given UART.
+ * For SoCFPGA UARTs, this paramter is ignored.
+ *
+ * \param handle
+ * [out] A pointer to a handle that will represent the UART. This
+ * handle should subsequently be used when calling other UART
+ * APIs.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device identifier is invalid.
+ * \retval ALT_E_BAD_CLK The required clock is not yet setup.
+ */
+ALT_STATUS_CODE alt_16550_init(ALT_16550_DEVICE_t device,
+ void * location,
+ alt_freq_t clock_freq,
+ ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Performs the uninitialization steps for the UART. This should be the last
+ * API call made to cleanup the UART.
+ *
+ * After calling this function, the handle will need to be initialized again
+ * before being used by calling alt_16550_init().
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_uninit(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Resets the UART to the default configuration. The UART will be reset and
+ * reinitialized.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_reset(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Starts the UART after all configuration has been completed.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_enable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Stops the UART. While UART configuration can be done while enabled, it is
+ * not recommended.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_disable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Reads a single character from the UART receiver buffer. This API should
+ * only be used when FIFOs are disabled.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param item
+ * [out] Pointer to an output parameter that contains the in
+ * receiver buffer of the UART.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_read(ALT_16550_HANDLE_t * handle,
+ char * item);
+
+/*!
+ * Writes a single character to the UART transmitter buffer. This API should
+ * only be used when FIFOs are disabled.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param item
+ * The character to write to the transmitter buffer of the UART.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_write(ALT_16550_HANDLE_t * handle,
+ char item);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup UART_FIFO UART FIFO Interface
+ *
+ * This group of APIs provides access, configuration, and control of the UART
+ * FIFO. The FIFO allows the UART to buffer received data and data to be
+ * transmitted.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the receiver FIFO level conditions that
+ * will trigger the receiver FIFO to issue a receiver FIFO full event.
+ */
+typedef enum ALT_16550_FIFO_TRIGGER_RX_e
+{
+ /*!
+ * 1 or more character(s) in the receiver FIFO will trigger an event.
+ */
+ ALT_16550_FIFO_TRIGGER_RX_ANY = 0,
+
+ /*!
+ * 25% or higher capacity usage in the receiver FIFO will trigger an
+ * event.
+ */
+ ALT_16550_FIFO_TRIGGER_RX_QUARTER_FULL = 1,
+
+ /*!
+ * 50% or higher capacity usage in the receiver FIFO will trigger an
+ * event.
+ */
+ ALT_16550_FIFO_TRIGGER_RX_HALF_FULL = 2,
+
+ /*!
+ * 2 characters less than the receiver FIFO capacity will trigger an
+ * event.
+ */
+ ALT_16550_FIFO_TRIGGER_RX_ALMOST_FULL = 3
+}
+ALT_16550_FIFO_TRIGGER_RX_t;
+
+/*!
+ * This type definition enumerates the transmitter FIFO level conditions that
+ * will trigger the transmitter FIFO to issue a transmitter FIFO empty event.
+ */
+typedef enum ALT_16550_FIFO_TRIGGER_TX_e
+{
+ /*!
+ * Transmitter FIFO being completely empty will trigger an event.
+ */
+ ALT_16550_FIFO_TRIGGER_TX_EMPTY = 0,
+
+ /*!
+ * 2 or less character(s) in the transmitter FIFO will trigger an event.
+ */
+ ALT_16550_FIFO_TRIGGER_TX_ALMOST_EMPTY = 1,
+
+ /*!
+ * 25% or less capacity usage in the transmitter FIFO will trigger an
+ * event.
+ */
+ ALT_16550_FIFO_TRIGGER_TX_QUARTER_FULL = 2,
+
+ /*!
+ * 50% or less capacity usage in the transmitter FIFO will trigger an
+ * event.
+ */
+ ALT_16550_FIFO_TRIGGER_TX_HALF_FULL = 3
+}
+ALT_16550_FIFO_TRIGGER_TX_t;
+
+/*!
+ * Enables FIFO on the UART. This will enable both the receiver FIFO and
+ * transmitter FIFO. Both FIFOs will be cleared.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_enable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables FIFOs on the UART. This will disable both the receiver FIFO and
+ * transmitter FIFO. Any data left in the FIFOs will be lost.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_disable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Reads the given buffer from the receiver FIFO in the UART.
+ *
+ * The available characters in the FIFO can be determined by a few ways. Users
+ * can determine the number of items by calling alt_16550_fifo_level_get_rx().
+ *
+ * Another way is by using the RX trigger and RX interrupt. First determine the
+ * RX FIFO size by calling alt_16550_fifo_size_get_rx(). Then set the desired
+ * trigger level by calling alt_16550_fifo_trigger_set_rx(). Calculate the
+ * triggering point by applying trigger description on the FIFO size. Enable RX
+ * interrupts by calling alt_16550_int_enable_rx(). When the RX interrupt fires
+ * due to the ALT_16550_INT_STATUS_RX_DATA condition, the calculated triggering
+ * point value can be used to determine the RX FIFO level. If the interrupt
+ * fires due to the ALT_16550_INT_STATUS_RX_TIMEOUT, the RX FIFO can be
+ * completely emptied by repeatedly polling the Line Status
+ * ALT_16550_LINE_STATUS_DR condition by calling alt_16550_line_status_get().
+ * These steps are necessary if the UART does not implement FIFO level query
+ * functionality. As of 13.0sp1, this applies to the Altera 16550 Compatible
+ * Soft UART.
+ *
+ * Reading more data than that which is available can result in invalid data
+ * appearing like valid data.
+ *
+ * The FIFO must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param buffer
+ * [out] Pointer to a buffer where the specified count of
+ * characters from the receiver FIFO will be copied to.
+ *
+ * \param count
+ * The count of characters from the receiver FIFO to be copied.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_read(ALT_16550_HANDLE_t * handle,
+ char * buffer,
+ size_t count);
+
+/*!
+ * Writes the given buffer to the transmitter FIFO in the UART.
+ *
+ * The available space in the FIFO can be determined by a few ways. Users can
+ * determine the number of items by calculating the FIFO capacity minus the
+ * FIFO level. This can be done by calling alt_16550_fifo_size_get_tx() and
+ * alt_16550_fifo_level_get_tx() respectively.
+ *
+ * Another way is by using the TX trigger and TX interrupt. First determine the
+ * TX FIFO size by calling alt_16550_fifo_size_get_tx(). The set the desired
+ * trigger level by calling alt_16550_fifo_trigger_set_tx(). Calculate the
+ * triggering point by applying the trigger description on the FIFO size.
+ * Enable TX interrupts by calling alt_16550_int_enable_tx(). When the TX
+ * interrupt fires, calculate the empty entries in the FIFO by subtracting the
+ * TX FIFO size and the calculated value. These steps are necessary if the UART
+ * does not implement FIFO level query functionality. As of 13.0sp1, this
+ * applies to the Altera 16550 Compatible Soft UART.
+ *
+ * Writing more data that there is space can result in data lost due to
+ * overflowing.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param buffer
+ * Pointer to a buffer from where the specified count of
+ * characters will be copied to the transmitter FIFO.
+ *
+ * \param count
+ * The count of characters from the given buffer to be copied.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_write(ALT_16550_HANDLE_t * handle,
+ const char * buffer,
+ size_t count);
+
+/*!
+ * Clears the contents of the receiver FIFO. Any characters which were
+ * previously contained in that FIFO will be discarded.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_clear_rx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Clears the contents of the transmitter FIFO. Any characters which were
+ * previously contained in that FIFO will be discarded.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_clear_tx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Clears the contents of the receiver and transmitter FIFO. Any characters
+ * which were previously contained on those FIFOs will be discarded.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_clear_all(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Queries the size of the receiver FIFO.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param size
+ * [out] Pointer to an output parameter that contains the size of
+ * the receiver FIFO.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_size_get_rx(ALT_16550_HANDLE_t * handle,
+ uint32_t * size);
+
+/*!
+ * Queries the size of the transmitter FIFO.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param size
+ * [out] Pointer to an output parameter that contains the size of
+ * the transmitter FIFO.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_size_get_tx(ALT_16550_HANDLE_t * handle,
+ uint32_t * size);
+
+/*!
+ * Queries the current level of the receiver FIFO.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * For the Altera 16550 Compatible UART, it may not be possible to read the
+ * FIFO level and this function may always report 0. For more information on
+ * interacting with the FIFO in this situation, see documentation for
+ * alt_16550_fifo_read().
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param level
+ * [out] Pointer to an output parameter that contains the level
+ * or number of characters in the receiver FIFO.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_level_get_rx(ALT_16550_HANDLE_t * handle,
+ uint32_t * level);
+
+/*!
+ * Queries the current level of the transmitter FIFO.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * For the Altera 16550 Compatible UART, it may not be possible to read the
+ * FIFO level and this function may always report 0. For more information on
+ * interacting with the FIFO in this situation, see documentation for
+ * alt_16550_fifo_write().
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param level
+ * [out] Pointer to an output parameter that contains the level
+ * or number of characters in the transmitter FIFO.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_level_get_tx(ALT_16550_HANDLE_t * handle,
+ uint32_t * level);
+
+/*!
+ * Sets the receiver FIFO level which will trigger the receiver FIFO to issue
+ * receiver FIFO full event. For the list of available receiver FIFO trigger
+ * levels, see the documentation for ALT_16550_FIFO_TRIGGER_RX_t.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param trigger
+ * The level of the receiver FIFO which is needed to trigger a
+ * receiver FIFO full event.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_trigger_set_rx(ALT_16550_HANDLE_t * handle,
+ ALT_16550_FIFO_TRIGGER_RX_t trigger);
+
+/*!
+ * Sets the transmitter FIFO level which will trigger the transmitter FIFO to
+ * transmitter FIFO empty event. For the list of available transmitter FIFO
+ * trigger levels, see the documentation for ALT_16550_FIFO_TRIGGER_TX_t.
+ *
+ * The FIFOs must first be enabled before calling this function by calling
+ * alt_16550_fifo_enable().
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param trigger
+ * The level of the transmitter FIFO which is needed to trigger a
+ * transmitter FIFO empty event.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_fifo_trigger_set_tx(ALT_16550_HANDLE_t * handle,
+ ALT_16550_FIFO_TRIGGER_TX_t trigger);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup UART_BAUD UART Baudrate Interface
+ *
+ * This group of APIs allows for the configuration of the UART's baudrate
+ * generation related functions.
+ *
+ * The UART baudrate is determined by dividing the ALT_CLK_L4_SP clock with
+ * the configured divisor.
+ *
+ * @{
+ */
+
+/*!
+ * This enumeration lists out the common baudrates used with modem and serial
+ * ports. Not every baudrate is available for the UART due to the limits of
+ * the serial clock frequency and divisor value.
+ */
+typedef enum ALT_16550_BAUDRATE_e
+{
+ ALT_16550_BAUDRATE_50 = 50, /*!< 50 bps baudrate. */
+ ALT_16550_BAUDRATE_75 = 75, /*!< 75 bps baudrate. */
+ ALT_16550_BAUDRATE_150 = 150, /*!< 150 bps baudrate. */
+ ALT_16550_BAUDRATE_300 = 300, /*!< 300 bps baudrate. */
+ ALT_16550_BAUDRATE_600 = 600, /*!< 600 bps baudrate. */
+ ALT_16550_BAUDRATE_900 = 900, /*!< 900 bps baudrate. */
+ ALT_16550_BAUDRATE_1200 = 1200, /*!< 1200 bps baudrate. */
+ ALT_16550_BAUDRATE_1800 = 1800, /*!< 1800 bps baudrate. */
+ ALT_16550_BAUDRATE_2400 = 2400, /*!< 2400 bps baudrate. */
+ ALT_16550_BAUDRATE_3600 = 3600, /*!< 3600 bps baudrate. */
+ ALT_16550_BAUDRATE_4800 = 4800, /*!< 4800 bps baudrate. */
+ ALT_16550_BAUDRATE_7200 = 7200, /*!< 7200 bps baudrate. */
+ ALT_16550_BAUDRATE_9600 = 9600, /*!< 9600 bps baudrate. */
+ ALT_16550_BAUDRATE_14400 = 14400, /*!< 14400 bps baudrate. */
+ ALT_16550_BAUDRATE_19200 = 19200, /*!< 19200 bps baudrate. */
+ ALT_16550_BAUDRATE_28800 = 28800, /*!< 28800 bps baudrate. */
+ ALT_16550_BAUDRATE_38400 = 38400, /*!< 38400 bps baudrate. */
+ ALT_16550_BAUDRATE_57600 = 57600, /*!< 57600 bps baudrate. */
+ ALT_16550_BAUDRATE_115200 = 115200 /*!< 115200 bps baudrate. */
+}
+ALT_16550_BAUDRATE_t;
+
+/*!
+ * Gets the baudrate for the UART.
+ *
+ * This is done by calculating the baudrate from the divisor and the serial
+ * clock. The reported baudrate may not correspond exactly to the request
+ * baudrate.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param baudrate
+ * [out] Pointer to an output paramter that contains the current
+ * baudrate of the UART.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_baudrate_get(ALT_16550_HANDLE_t * handle,
+ uint32_t * baudrate);
+
+/*!
+ * Sets the baudrate for the UART. This change will take effect when the UART
+ * moves from disabled to enabled.
+ *
+ * This is done by calculating the correct divisor using the request baudrate
+ * and the known serial clock.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param baudrate
+ * The requested baudrate for the UART.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ * \retval ALT_E_ARG_RANGE The given baudrate is not possible due to
+ * limitations of the baudrate divisor and/or
+ * serial clock.
+ */
+ALT_STATUS_CODE alt_16550_baudrate_set(ALT_16550_HANDLE_t * handle,
+ uint32_t baudrate);
+
+/*!
+ * Gets the baudrate divisor for the UART.
+ *
+ * The baudrate is determined by the following formula:
+ * * Baudrate = (serial clock frequency) / (16 * divisor)
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param divisor
+ * [out] Pointer to an output parameter that contains the current
+ * divisor used for baudrate generation.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_divisor_get(ALT_16550_HANDLE_t * handle,
+ uint32_t * divisor);
+
+/*!
+ * Sets the baudrate divisor for the UART. This change will take effect when
+ * the UART moves from disabled to enabled.
+ *
+ * The baudrate is determined by the following formula:
+ * * Baudrate = (serial clock frequency) / (16 * divisor)
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param divisor
+ * The specified divisor value to use for baudrate generation.
+ * Valid values are 1 - 65535.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART identifier is invalid or the
+ * specified divisor is not supported by the
+ * UART.
+ */
+ALT_STATUS_CODE alt_16550_divisor_set(ALT_16550_HANDLE_t * handle,
+ uint32_t divisor);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup UART_INT UART Interrupt Interface
+ *
+ * This group of APIs provides access, configuration, and control of the
+ * UART interrupts.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the different interrupt conditions that can
+ * be generated by the UART controller.
+ *
+ * Interrupts are listed in highest to lowest priority order.
+ */
+typedef enum ALT_16550_INT_STATUS_e
+{
+ /*!
+ * This interrupt signals that a overrun, parity, or framing error
+ * occurred, or a break event occured. The interrupt is cleared by reading
+ * the line status by calling alt_16550_line_status_get() or by disabling
+ * line status interrupts by calling alt_16550_int_disable_line().
+ */
+ ALT_16550_INT_STATUS_LINE = 0x6,
+
+ /*!
+ * This interrupt signals that some data is available to be read from the
+ * UART. The definition of some depends on whether FIFOs are enabled or
+ * not.
+ *
+ * If FIFOs are disabled, this interrupt signals that the receiver
+ * contains data. In this case, the interrupt is cleared by reading the
+ * data from the UART by calling alt_16550_read().
+ *
+ * If FIFOs are enabled, this interrupt signals that the receiver FIFO
+ * level is above the receiver trigger level specified. In this case, the
+ * interrupt is cleared by reading a sufficiently large buffer from the
+ * receiver FIFO such that the FIFO is filled below the receiver trigger
+ * level specified by calling alt_16550_fifo_read() or by adjusting the
+ * receiver trigger level appropriately by calling
+ * alt_16550_fifo_trigger_set_rx().
+ *
+ * In either case, this interrupt can also be cleared by disabling
+ * receiver interrupts by calling alt_16550_int_disable_rx().
+ */
+ ALT_16550_INT_STATUS_RX_DATA = 0x4,
+
+ /*!
+ * This interrupt signals that data is available in the receiver FIFO and
+ * that there has been no activity with the receiver FIFO for the last 4
+ * character frames. In essence, the receiver FIFO has temporarily settled
+ * thus it may be a good time to empty the receiver FIFO. This interrupt
+ * is only available if FIFOs are enabled. The interrupt is cleared by
+ * reading from the receiver FIFO by calling alt_16550_fifo_read() or by
+ * disabling receiver interrupts by calling alt_16550_int_disable_rx().
+ */
+ ALT_16550_INT_STATUS_RX_TIMEOUT = 0xC,
+
+ /*!
+ * This interrupt signals that the transmitter is idling. The definition
+ * of idling depends on whether FIFOs are enabled or not.
+ *
+ * If FIFOs are disabled, this interrupt signals that the transmitter
+ * shift register is empty. In this case, the interrupt is cleared by
+ * writing data to the UART by calling alt_16550_write().
+ *
+ * If FIFO are enabled, this interrupt signals that the transmitter FIFO
+ * level is below the transmitter trigger level specified. In this case,
+ * the interrupt is cleared by writing a sufficiently large buffer to the
+ * transmitter FIFO such that the FIFO is filled above the transmitter
+ * trigger level specified by calling alt_16550_fifo_write() or by
+ * adjusting the transmitter trigger level appropriately by calling
+ * alt_16550_fifo_trigger_set_tx().
+ *
+ * In either case, this interrupt can also be cleared by disabling
+ * transmitter interrupts by calling alt_16550_int_disable_tx().
+ */
+ ALT_16550_INT_STATUS_TX_IDLE = 0x2,
+
+ /*!
+ * Modem status interrupt pending. The interrupt is cleared by reading the
+ * modem status by calling alt_16550_modem_status_get() or by disabling
+ * modem status interrupts by calling alt_16550_int_disable_modem().
+ */
+ ALT_16550_INT_STATUS_MODEM = 0x0,
+
+ /*!
+ * No interrupts pending.
+ */
+ ALT_16550_INT_STATUS_NONE = 0x1
+}
+ALT_16550_INT_STATUS_t;
+
+/*!
+ * Enables the receiver FIFO to generate interrupts. Enabling this interrupt
+ * allows for the following interrupt signal(s):
+ * * ALT_16550_INT_STATUS_RX_DATA
+ * * ALT_16550_INT_STATUS_RX_TIMEOUT
+ *
+ * This interrupt is disabled by default.
+ *
+ * The FIFOs must also be enabled for this interrupt to actually be generated.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_enable_rx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables the receiver FIFO from generating interrupts.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_disable_rx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Enables the transmitter FIFO to generate interrupts. Enabling this
+ * interrupt allows for the following interrupt signal(s):
+ * * ALT_16550_INT_STATUS_TX_IDLE
+ *
+ * This interrupt is disabled by default.
+ *
+ * The FIFOs must also be enabled for this interrupt to actually be generated.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_enable_tx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables the transmitter FIFO from generating interrupts.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_disable_tx(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Enables the receiver to generate line status interrupts. Enabling this
+ * interrupt allows for the following interrupt signal(s):
+ * * ALT_16550_INT_STATUS_LINE
+ *
+ * This interrupt is disabled by default.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_enable_line(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables the receiver from generating line status interrupts.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_disable_line(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Enables the UART to generate modem status interrupts. Enabling this
+ * interrupt allows for the following interrupt signal(s):
+ * * ALT_16550_INT_STATUS_MODEM
+ *
+ * This interrupt is disabled by default.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_enable_modem(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables the UART from generate modem status interrupts.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_disable_modem(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables all interrupts on the UART.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_disable_all(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Queries the interrupt status of the UART. This returns the highest priority
+ * interrupt pending. The appropriate interrupts must be enabled for them be
+ * generated in the UART.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param status
+ * [out] Pointer to an output parameter that contains the current
+ * interrupt status of the UART.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_int_status_get(ALT_16550_HANDLE_t * handle,
+ ALT_16550_INT_STATUS_t * status);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup UART_MODEM UART Modem Interface
+ *
+ * This group of APIs provides access, configuration, and control of the UART
+ * Modem interface.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the set of UART modem status conditions as
+ * register mask values.
+ */
+typedef enum ALT_16550_MODEM_STATUS_e
+{
+ /*!
+ * Data Carrier Detect. This status indicates that the carrier has been
+ * detected by the modem. It corresponds to an inverted dcd_n input. DCD
+ * is unasserted when dcd_n is logic 1 and asserted when dcd_n is logic 0.
+ */
+ ALT_16550_MODEM_STATUS_DCD = 1 << 7,
+
+ /*!
+ * Ring Indicator. This status indicates that the telephone ringing signal
+ * has been redeived by the modem. It corresponds to an inverted ri_n
+ * input. RI is unasserted when ri_n is logic 1 and asserted when ri_n is
+ * logic 0.
+ */
+ ALT_16550_MODEM_STATUS_RI = 1 << 6,
+
+ /*!
+ * Data Set Ready. This status indicates that the modem is ready to
+ * establish communications with the UART. It corresponds to an inverted
+ * dsr_n input. DSR is unasserted when dsr_n is logic 1 and asserted when
+ * dsr_n is logic 0.
+ */
+ ALT_16550_MODEM_STATUS_DSR = 1 << 5,
+
+ /*!
+ * Clear To Send. This status indicates the current state of the modem
+ * cts_n line. It corresponds to an inverted cts_n input. CTS is
+ * unasserted when cts_n is logic 1 and asserted when cts_n is logic 0.
+ */
+ ALT_16550_MODEM_STATUS_CTS = 1 << 4,
+
+ /*!
+ * Delta Data Carrier Detect. This status condition indicates that the
+ * Data Carrier Detect has changed since the last time the modem status
+ * was read. Reading the modem status clears this status. For more
+ * information about the Data Carrier Detect status, see
+ * ALT_16550_MODEM_STATUS_DCD.
+ */
+ ALT_16550_MODEM_STATUS_DDCD = 1 << 3,
+
+ /*!
+ * Trailing Edge of Ring Indicator. This status indicates that the Ring
+ * Indicator has changed from asserted to unasserted. Reading the modem
+ * status will clear this status. For more information about the Ring
+ * Indicator status, reference ALT_16550_MODEM_STATUS_RI.
+ */
+ ALT_16550_MODEM_STATUS_TERI = 1 << 2,
+
+ /*!
+ * Delta Data Set Ready. This status condition indicates that the Data Set
+ * Ready has changed since the last time the modem status was read.
+ * Reading the modem status will clear this status. For more information
+ * about the Data Set Ready status, see ALT_16550_MODEM_STATUS_DSR.
+ */
+ ALT_16550_MODEM_STATUS_DDSR = 1 << 1,
+
+ /*!
+ * Delta Clear To Send. This status condition indicates that the Clear To
+ * Send has changed since the last time the modem status was read. Reading
+ * the modem status will clear this status. For more information about the
+ * Clear To Send status, see ALT_16550_MODEM_STATUS_CTS.
+ */
+ ALT_16550_MODEM_STATUS_DCTS = 1 << 0
+}
+ALT_16550_MODEM_STATUS_t;
+
+/*!
+ * Enables automatic flow control in the UART modem. When in this mode, the
+ * rts_n is gated with the threshold trigger condition of the receiver FIFO.
+ *
+ * The Altera 16550 Compatible Soft IP UART may not have this option enabled.
+ *
+ * The FIFOs must be enabled for flow control to be used.
+ *
+ * The recommended bring up for flow control is as follows:
+ * * Enable automatic flow control by calling alt_16550_flowcontrol_enable().
+ * This will allow both the receiver FIFO and user RTS to control the rts_n
+ * output. Because the user RTS is not enabled, the rts_n will be inactive
+ * high.
+ * * Enable RTS by calling alt_16550_modem_enable_rts(). This will give the
+ * receiver FIFO to have full control of the rts_n output.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_flowcontrol_enable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Disables automatic flow control in the UART modem.
+ *
+ * The recommended bring down for flow control is as follows:
+ * * Disable RTS by calling alt_16550_modem_disable_rts(). This will disable
+ * generation of the rts_n ouput.
+ * * Disable automatic flow control by calling
+ * alt_16550_flowcontrol_disable().
+ *
+ * The receiver FIFO will still be active after these steps.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_flowcontrol_disable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Puts the UART in loopback mode. This is used for diagnostic and test
+ * purposes.
+ *
+ * The SoCFPGA UARTs does not support automatic flow control when in loopback
+ * mode.
+ *
+ * The Altera 16550 Compatible Soft IP UART implements this in 13.0sp1 and
+ * later. Setting this has no effect with 13.0.
+ *
+ * When in this mode, the modem control inputs (dsr_n, cts_n, ri_n, dcd_n) are
+ * disconnected and the modem control outputs (dtr_n, rts_n, out1_n, out2_n)
+ * are held inactive high externally and internally looped back to the inputs.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_loopback_enable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Takes the UART out of loopback mode.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_loopback_disable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Asserts the OUT1 output. OUT1 is inverted then driven out to out1_n.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_enable_out1(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Unasserts the OUT1 output. OUT1 is inverted then driven out to out1_n.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_disable_out1(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Asserts the OUT2 output. OUT2 is inverted then driven out to out2_n.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_enable_out2(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Unasserts the OUT2 output. OUT2 is inverted then driven out to out2_n.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_disable_out2(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Asserts the RTS (Request To Send) output. RTS is inverted then driven out
+ * to rts_n. RTS is used to inform the modem that the UART is ready to receive
+ * data.
+ *
+ * There are special considerations when the UART is in automatic flow control
+ * mode. See alt_16550_flowcontrol_enable() for more information.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_enable_rts(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Deaserts the RTS (Request To Send) output. RTS is inverted then driven out
+ * to rts_n.
+ *
+ * There are special considerations when the UART is in automatic flow control
+ * mode. See alt_16550_flowcontrol_enable() for more information.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_disable_rts(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Asserts the DTR (Data Terminal Ready) output. DTR is inverted then driven
+ * out to dtr_n. DTR is used to inform the modem that UART is ready to
+ * establish communications.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_enable_dtr(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Deasserts the DTR (Data Terminal Ready) output. DTR is inverted then driven
+ * out to dtr_n.
+ *
+ * There are special considerations when the UART is in loopback mode. See
+ * alt_16550_loopback_enable() for more information.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_disable_dtr(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Reads the modem status from the UART.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param status
+ * [out] Pointer to an output parameter that contains the current
+ * modem status of the UART as a register mask.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_modem_status_get(ALT_16550_HANDLE_t * handle,
+ uint32_t * status);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup UART_LINE UART Line Interface
+ *
+ * This group of APIs provides access, configuration, and control of the UART
+ * Line interface.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the supported databits per frame.
+ */
+typedef enum ALT_16550_DATABITS_e
+{
+ /*!
+ * This option selects 5 databits per frame.
+ */
+ ALT_16550_DATABITS_5 = 0,
+
+ /*!
+ * This option selects 6 databits per frame.
+ */
+ ALT_16550_DATABITS_6 = 1,
+
+ /*!
+ * This option selects 7 databits per frame.
+ */
+ ALT_16550_DATABITS_7 = 2,
+
+ /*!
+ * This option selects 8 databits per frame.
+ */
+ ALT_16550_DATABITS_8 = 3
+}
+ALT_16550_DATABITS_t;
+
+/*!
+ * This type definition enumerates the supported stopbits per frame.
+ */
+typedef enum ALT_16550_STOPBITS_e
+{
+ /*!
+ * This options specifies 1 stopbit per frame.
+ */
+ ALT_16550_STOPBITS_1 = 0,
+
+ /*!
+ * This options specifies 2 stopbits per frame. If the frame is
+ * configured with 5 databits, 1.5 stopbits is used instead.
+ */
+ ALT_16550_STOPBITS_2 = 1
+}
+ALT_16550_STOPBITS_t;
+
+/*!
+ * This type definition enumerates the possible parity to use per frame.
+ */
+typedef enum ALT_16550_PARITY_e
+{
+ /*!
+ * This option disables the parity error detection bit in the data frame.
+ */
+ ALT_16550_PARITY_DISABLE = 0,
+
+ /*!
+ * This option enables the odd parity error detection bit in the data
+ * frame.
+ */
+ ALT_16550_PARITY_ODD = 1,
+
+ /*!
+ * This option enables the even parity error detection bit in the data
+ * frame.
+ */
+ ALT_16550_PARITY_EVEN = 2
+}
+ALT_16550_PARITY_t;
+
+/*!
+ * This type definition enumerates the set of UART line status conditions as
+ * register mask values.
+ */
+typedef enum ALT_16550_LINE_STATUS_e
+{
+ /*!
+ * Receiver FIFO Error. This status indicates that one or more parity
+ * error, framing error, or break indication exists in the receiver FIFO.
+ * It is only set when FIFO is enabled. This status cleared when line
+ * status is read, the character with the issue is at the top of the FIFO,
+ * and when no other issues exist in the FIFO.
+ */
+ ALT_16550_LINE_STATUS_RFE = 1 << 7,
+
+ /*!
+ * Transmitter EMpTy (Empty). This status indicates that transmitter shift
+ * register is empty. If FIFOs are enabled, the status is set when the
+ * transmitter FIFO is also empty. This status is cleared when the
+ * transmitter shift registers is loaded by writing to the UART
+ * transmitter buffer or transmitter FIFO if FIFOs are enabled. This is
+ * done by calling alt_16550_write() and alt_16550_fifo_write()
+ * respectively.
+ */
+ ALT_16550_LINE_STATUS_TEMT = 1 << 6,
+
+ /*!
+ * Transmitter Holding Register Empty. This status indicates that the
+ * transmitter will run out of data soon. The definition of soon depends
+ * on whether the FIFOs are enabled.
+ *
+ * If FIFOs are disabled, this status indicates that the transmitter will
+ * run out of data to send after the current transmit shift register
+ * completes. In this case, this status is cleared when the data is
+ * written to the UART. This can be done by calling alt_16550_write().
+ *
+ * If FIFOs are enabled, this status indicates that the transmitter FIFO
+ * level is below the transmitter trigger level specified. In this case,
+ * this status is cleared by writing a sufficiently large buffer to the
+ * transmitter FIFO such that the FIFO is filled above the transmitter
+ * trigger level specified by calling alt_16550_fifo_write() or by
+ * adjusting the transmitter trigger level appropriately by calling
+ * alt_16550_fifo_trigger_set_tx().
+ *
+ * \internal
+ * The implementation of the UART driver always ensures that IER[7] is
+ * set. This means that the UART always has Programmable THRE (Transmitter
+ * Holding Register Empty) Interrupt Mode Enable (PTIME) enabled.
+ * \endinternal
+ */
+ ALT_16550_LINE_STATUS_THRE = 1 << 5,
+
+ /*!
+ * Break Interrupt. This status indicates that a break interrupt sequence
+ * is detected in the incoming serial data. This happens when the the data
+ * is 0 for longer than a frame would normally be transmitted. The break
+ * interrupt status is cleared by reading the line status by calling
+ * alt_16550_line_status_get().
+ *
+ * If FIFOs are enabled, this status will be set when the character with
+ * the break interrupt status is at the top of the receiver FIFO.
+ */
+ ALT_16550_LINE_STATUS_BI = 1 << 4,
+
+ /*!
+ * Framing Error. This status indicates that a framing error occurred in
+ * the receiver. This happens when the receiver detects a missing or
+ * incorrect number of stopbit(s).
+ *
+ * If FIFOs are enabled, this status will be set when the character with
+ * the framing error is at the top of the FIFO. When a framing error
+ * occurs, the UART attempts to resynchronize with the transmitting UART.
+ * This status is also set if break interrupt occurred.
+ */
+ ALT_16550_LINE_STATUS_FE = 1 << 3,
+
+ /*!
+ * Parity Error. This status indicates that a parity error occurred in the
+ * receiver.
+ *
+ * If FIFOs are enabled, this status will be set when the character with
+ * the parity error is at the top of the receiver FIFO. This status is
+ * also set if a break interrupt occurred.
+ */
+ ALT_16550_LINE_STATUS_PE = 1 << 2,
+
+ /*!
+ * Overrun Error. This status indicates that an overrun occurred in the
+ * receiver.
+ *
+ * If FIFOs are disabled, the arriving character will overwrite the
+ * existing character in the receiver. Any previously existing
+ * character(s) will be lost.
+ *
+ * If FIFOs are disabled, the arriving character will be discarded. The
+ * buffer will continue to contain the preexisting characters.
+ */
+ ALT_16550_LINE_STATUS_OE = 1 << 1,
+
+ /*!
+ * Data Ready. This status indicates that the receiver or receiver FIFO
+ * contains at least one character.
+ */
+ ALT_16550_LINE_STATUS_DR = 1 << 0
+}
+ALT_16550_LINE_STATUS_t;
+
+/*!
+ * Sets the configuration for a given character frame.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param databits
+ * The number of databits for each character frame.
+ *
+ * \param parity
+ * The parity to use for each character frame.
+ *
+ * \param stopbits
+ * The number of stopbits for each character frame.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_line_config_set(ALT_16550_HANDLE_t * handle,
+ ALT_16550_DATABITS_t databits,
+ ALT_16550_PARITY_t parity,
+ ALT_16550_STOPBITS_t stopbits);
+
+/*!
+ * Starts transmitting a break condition by transmitting a logic 0 state
+ * longer than a frame would normally be transmitted.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_line_break_enable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Stops transmitting a break condition.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_line_break_disable(ALT_16550_HANDLE_t * handle);
+
+/*!
+ * Reads the line status from the UART.
+ *
+ * \param handle
+ * The UART device handle.
+ *
+ * \param status
+ * [out] Pointer to an output parameter that contains the current
+ * line status of the UART.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given UART device handle is invalid.
+ */
+ALT_STATUS_CODE alt_16550_line_status_get(ALT_16550_HANDLE_t * handle,
+ uint32_t * status);
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_16550_UART_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h
new file mode 100644
index 0000000000..781cc49aa3
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_address_space.h
@@ -0,0 +1,825 @@
+/*! \file
+ * Altera - SoC FPGA Address Space Manager
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __ALT_ADDRESS_SPACE_H__
+#define __ALT_ADDRESS_SPACE_H__
+
+#include <stdbool.h>
+#include "hwlib.h"
+#include "socal/hps.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/******************************************************************************/
+// ARM Level 2 Cache Controller L2C-310 Register Interface
+
+// Address Filtering Start Register
+// The Address Filtering Start Register is a read and write register.
+// Bits Field Description
+// :-------|:--------------------------|:-----------------------------------------
+// [31:20] | address_filtering_start | Address filtering start address for
+// | | bits [31:20] of the filtering address.
+// [19:1] | Reserved | SBZ/RAZ
+// [0] | address_filtering_enable | 0 - address filtering disabled
+// | | 1 - address filtering enabled.
+
+// Address Filtering Start Register Address
+#define L2_CACHE_ADDR_FILTERING_START_OFST 0xC00
+#define L2_CACHE_ADDR_FILTERING_START_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_START_OFST)
+// Address Filtering Start Register - Start Value Mask
+#define L2_CACHE_ADDR_FILTERING_START_ADDR_MASK 0xFFF00000
+// Address Filtering Start Register - Reset Start Address Value (1 MB)
+#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
+// Address Filtering Start Register - Enable Flag Mask
+#define L2_CACHE_ADDR_FILTERING_ENABLE_MASK 0x00000001
+// Address Filtering Start Register - Reset Enable Flag Value (Enabled)
+#define L2_CACHE_ADDR_FILTERING_ENABLE_RESET 0x1
+
+// Address Filtering End Register
+// The Address Filtering End Register is a read and write register.
+// Bits Field Description
+// :-------|:--------------------------|:-----------------------------------------
+// [31:20] | address_filtering_end | Address filtering end address for bits
+// | | [31:20] of the filtering address.
+// [19:0] | Reserved | SBZ/RAZ
+
+// Address Filtering End Register Address
+#define L2_CACHE_ADDR_FILTERING_END_OFST 0xC04
+#define L2_CACHE_ADDR_FILTERING_END_ADDR (ALT_MPUL2_OFST + L2_CACHE_ADDR_FILTERING_END_OFST)
+// Address Filtering End Register - End Value Mask
+#define L2_CACHE_ADDR_FILTERING_END_ADDR_MASK 0xFFF00000
+// Address Filtering End Register - Reset End Address Value (3 GiB)
+#define L2_CACHE_ADDR_FILTERING_END_RESET 0xC0000000
+
+#ifndef __ASSEMBLY__
+
+/******************************************************************************/
+/*! \addtogroup ADDR_SPACE_MGR The Address Space Manager
+ *
+ * This module contains group APIs for managing the HPS address space. This
+ * module contains group APIs to manage:
+ * * Memory Map Control
+ * * Memory Coherence
+ * * Cache Managment
+ * * MMU Managment
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*! \addtogroup ADDR_SPACE_MGR_REMAP Address Space Mapping Control
+ *
+ * This group API provides functions to map and remap selected address ranges
+ * into the accessible (visible) views of the MPU and non MPU address spaces.
+ *
+ * \b Caveats
+ *
+ * \b NOTE: Caution should be observed when remapping address 0 to different
+ * memory. The code performing the remapping operation should not be executing
+ * in the address range being remapped to different memory.
+ *
+ * For example, if address 0 is presently mapped to OCRAM and the code is
+ * preparing to remap address 0 to SDRAM, then the code must not be executing in
+ * the range 0 to 64 KB as this address space is about to be remapped to
+ * different memory. If the code performing the remap operation is executing
+ * from OCRAM then it needs to be executing from its permanently mapped OCRAM
+ * address range in upper memory (i.e. ALT_OCRAM_LB_ADDR to ALT_OCRAM_UB_ADDR).
+ *
+ * \b NOTE: The MPU address space view is controlled by two disparate hardware
+ * control interfaces: the L3 remap register and the L2 cache address filtering
+ * registers. To complicate matters, the L3 remap register is write-only which
+ * means not only that current remap register state cannot be read but also that
+ * a read-modify-write operation cannot be performed on the register.
+ *
+ * This should not present a problem in most use case scenarios except for the
+ * case where a current MPU address space mapping of 0 to SDRAM is being changed
+ * to to a mapping of 0 to Boot ROM or OCRAM.
+ *
+ * In this case, a two step process whereby the L3 remap register is first set
+ * to the new desired MPU address 0 mapping and then the L2 cache address
+ * filtering registers have their address ranges adjusted accordingly must be
+ * followed. An example follows:
+\verbatim
+// 1 MB reset default value for address filtering start
+#define L2_CACHE_ADDR_FILTERING_START_RESET 0x100000
+uint32_t addr_filt_start;
+uint32_t addr_filt_end;
+
+// Perform L3 remap register programming first by setting the desired new MPU
+// address space 0 mapping. Assume OCRAM for the example.
+alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM, ...);
+
+// Next, adjust the L2 cache address filtering range. Set the start address to
+// the default reset value and retain the existing end address configuration.
+alt_l2_addr_filter_cfg_get(&addr_filt_start, &addr_filt_end);
+if (addr_filt_start != L2_CACHE_ADDR_FILTERING_START_RESET)
+{
+ alt_l2_addr_filter_cfg_set(L2_CACHE_ADDR_FILTERING_START_RESET, addr_filt_end);
+}
+\endverbatim
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the MPU address space attributes.
+ *
+ * The MPU address space consists of the ARM Cortex A9 processors and associated
+ * processor peripherals (cache, MMU).
+ */
+typedef enum ALT_ADDR_SPACE_MPU_ATTR_e
+{
+ ALT_ADDR_SPACE_MPU_ZERO_AT_BOOTROM, /*!< Maps the Boot ROM to address
+ * 0x0 for the MPU L3 master. Note
+ * that the Boot ROM is also
+ * always mapped to address
+ * 0xfffd_0000 for the MPU L3
+ * master independent of
+ * attribute.
+ */
+
+ ALT_ADDR_SPACE_MPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address
+ * 0x0 for the MPU L3 master. Note
+ * that the On-chip RAM is also
+ * always mapped to address
+ * 0xffff_0000 for the MPU L3
+ * master independent of this
+ * attribute.
+ */
+} ALT_ADDR_SPACE_MPU_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the non-MPU address space attributes.
+ *
+ * The non-MPU address space consists of the non-MPU L3 masters including the
+ * DMA controllers (standalone and those built into peripherals), the F2H AXI
+ * Bridge, and the DAP.
+ */
+typedef enum ALT_ADDR_SPACE_NONMPU_ATTR_e
+{
+ ALT_ADDR_SPACE_NONMPU_ZERO_AT_SDRAM, /*!< Maps the SDRAM to address 0x0
+ * for the non-MPU L3 masters.
+ */
+ ALT_ADDR_SPACE_NONMPU_ZERO_AT_OCRAM /*!< Maps the On-chip RAM to address
+ * 0x0 for the non-MPU L3
+ * masters. Note that the On-chip
+ * RAM is also always mapped to
+ * address 0xffff_0000 for the
+ * non-MPU L3 masters independent
+ * of this attribute.
+ */
+} ALT_ADDR_SPACE_NONMPU_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the HPS to FPGA bridge accessiblity
+ * attributes.
+ */
+typedef enum ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_e
+{
+ ALT_ADDR_SPACE_H2F_INACCESSIBLE, /*!< The H2F AXI Bridge is not
+ * visible to L3 masters. Accesses
+ * to the associated address range
+ * return an AXI decode error to
+ * the master.
+ */
+ ALT_ADDR_SPACE_H2F_ACCESSIBLE /*!< The H2F AXI Bridge is visible
+ * to L3 masters.
+ */
+} ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the Lightweight HPS to FPGA bridge
+ * accessiblity attributes.
+ */
+typedef enum ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_e
+{
+ ALT_ADDR_SPACE_LWH2F_INACCESSIBLE, /*!< The LWH2F AXI Bridge is not
+ * visible to L3 masters. Accesses
+ * to the associated address range
+ * return an AXI decode error to
+ * the master.
+ */
+ ALT_ADDR_SPACE_LWH2F_ACCESSIBLE /*!< The LWH2F AXI Bridge is visible
+ * to L3 masters.
+ */
+} ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t;
+
+/******************************************************************************/
+/*!
+ * Configures the mapped and accessible (visible) address ranges for the HPS
+ * MPU, non-MPU, and Bridge address spaces.
+ *
+ * \param mpu_attr
+ * The MPU address space configuration attributes.
+ *
+ * \param nonmpu_attr
+ * The non-MPU address space configuration attributes.
+ *
+ * \param h2f_attr
+ * The H2F Bridge attribute mapping and accessibility attributes.
+ *
+ * \param lwh2f_attr
+ * The Lightweight H2F Bridge attribute mapping and accessibility
+ * attributes.
+ *
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_INV_OPTION One or more invalid attribute options were
+ * specified.
+ */
+ALT_STATUS_CODE alt_addr_space_remap(ALT_ADDR_SPACE_MPU_ATTR_t mpu_attr,
+ ALT_ADDR_SPACE_NONMPU_ATTR_t nonmpu_attr,
+ ALT_ADDR_SPACE_H2F_BRIDGE_ATTR_t h2f_attr,
+ ALT_ADDR_SPACE_LWH2F_BRIDGE_ATTR_t lwh2f_attr);
+
+/******************************************************************************/
+/*!
+ * Maps SDRAM to address 0x0 for the MPU address space view.
+ *
+ * When address 0x0 is mapped to the Boot ROM or on-chip RAM, only the lowest
+ * 64KB of the boot region are accessible because the size of the Boot ROM and
+ * on-chip RAM are only 64KB. Addresses in the range 0x100000 (1MiB) to
+ * 0xC0000000 (3GiB) access SDRAM and addresses in the range 0xC0000000 (3GiB) to
+ * 0xFFFFFFFF access the L3 interconnect. Thus, the lowest 1MiB of SDRAM is not
+ * accessible to the MPU unless address 0 is remapped to SDRAM after reset.
+ *
+ * This function remaps the addresses between 0x0 to 0x100000 (1MiB) to access
+ * SDRAM.
+ *
+ * \internal
+ * The remap to address 0x0 is achieved by configuring the L2 cache Address
+ * Filtering Registers to redirect address 0x0 to \e sdram_end_addr to the SDRAM
+ * AXI (M1) master port by calling:
+ *
+ * alt_l2_addr_filter_cfg_set(0x0, <current_addr_filt_end_value>);
+ *
+ * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
+ * Reference Manual, Section 3.3.12 Address Filtering </em>.
+ * \endinternal
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_mpu_addr_space_remap_0_to_sdram(void);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup L2_ADDR_FLTR L2 Cache Address Filter
+ *
+ * The L2 cache address filter controls where physical addresses within certain
+ * ranges of the MPU address space are directed.
+ *
+ * The L2 cache has master port connections to the L3 interconnect and the SDRAM
+ * controller. A programmable address filter controls which portions of the
+ * 32-bit physical address space use each master.
+ *
+ * When l2 address filtering is configured and enabled, a physical address will
+ * be redirected to one master or the other based upon the address filter
+ * configuration.
+ *
+ * If \b address_filter_start <= \e physical_address < \b address_filter_end:
+ * * then redirect \e physical_address to AXI Master Port M1 (SDRAM controller)
+ * * else redirect \e physical_address to AXI Master Port M0 (L3 interconnect)
+ *
+ * See: <em>ARM DDI 0246F, CoreLink Level 2 Cache Controller L2C-310 Technical
+ * Reference Manual, Section 3.3.12 Address Filtering </em> for more information.
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Get the L2 cache address filtering configuration settings.
+ *
+ * \param addr_filt_start
+ * [out] An output parameter variable for the address filtering
+ * start address for the range of physical addresses redirected to
+ * the SDRAM AXI master port. The value returned is always a 1 MiB
+ * aligned address.
+ *
+ * \param addr_filt_end
+ * [out] An output parameter variable for the address filtering
+ * end address for the range of physical addresses redirected to
+ * the SDRAM AXI master port. The value returned is always a 1 MiB
+ * aligned address.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG An bad argument was passed. Either \e addr_filt_start
+ * or \e addr_filt_end or both are invalid addresses.
+ */
+ALT_STATUS_CODE alt_l2_addr_filter_cfg_get(uint32_t* addr_filt_start,
+ uint32_t* addr_filt_end);
+
+/******************************************************************************/
+/*!
+ * Set the L2 cache address filtering configuration settings.
+ *
+ * Address filtering start and end values must be 1 MiB aligned.
+ *
+ * \param addr_filt_start
+ * The address filtering start address for the range of physical
+ * addresses redirected to the SDRAM AXI master port. Only bits
+ * [31:20] of the address are valid. Any bits outside the range
+ * [31:20] are invalid and will cause an error status to be
+ * returned.
+ *
+ * \param addr_filt_end
+ * The address filtering end address for the range of physical
+ * addresses redirected to the SDRAM AXI master port. Only bits
+ * [31:20] of the address are valid. Any bits outside the range
+ * [31:20] are invalid and will cause an error status to be
+ * returned.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
+ * more address arguments do not satisfy the argument
+ * constraints.
+ */
+ALT_STATUS_CODE alt_l2_addr_filter_cfg_set(uint32_t addr_filt_start,
+ uint32_t addr_filt_end);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ADDR_SPACE_MGR_MEM_COHERENCE ACP Memory Coherence and ID Mapping
+ *
+ * This API provides management of the ACP ID Mapper that enables data coherent
+ * access to the MPU address space by external masters. The set of external
+ * masters include L3 master peripherals and FPGA soft IP.
+ *
+ * The Accelerator Coherency Port (ACP) allows peripherals - including FPGA
+ * based soft IP - to maintain data coherency with the Cortex-A9 MPCore
+ * processors and the Snoop Control Unit (SCU).
+ *
+ * The ACP supports up to six masters. However, soft IP implemented in the FPGA
+ * fabric can have a larger number of masters that need to access the ACP. The
+ * ACP ID Mapper expands the number of masters able to access the ACP. The ACP
+ * ID Mapper is situated between the interconnect and the ACP of the MPU
+ * subsystem. It has the following characteristics:
+ * * Support for up to six concurrent ID mappings.
+ * * 1 GiB coherent window into 4 GiB MPU address space
+ * * Remaps the 5-bit user sideband signals used by the Snoop Control Unit (SCU)
+ * and L2 cache.
+ *
+ * The function of the ACP ID Mapper is to map 12-bit Advanced Microcontroller
+ * Bus Architecture (AMBA) Advanced eXtensible Interface (AXI) IDs (input
+ * identifiers) from the Level 3 (L3) interconnect to 3-bit AXI IDs (output
+ * identifiers) required by the ACP slave port.
+ *
+ * The ACP ID Mapper supports the two ID mapping modes:
+ * * Dynamic Mapping - In this mode an input ID is automatically mapped to an
+ * available output ID. The dynamic mode is more flexible because the hardware
+ * handles the mapping. The hardware mapping allows an output ID to be used
+ * for more than one input ID. Output IDs are assigned to input IDs on a
+ * first-come, first-served basis.
+ * * Fixed Mapping - In this mode there is a one-to-one mapping from input IDs
+ * to output IDs.
+ *
+ * Out of the total of eight ACP output ID values, only six are available to the
+ * ACP ID Mapper for remapping. The first two output IDs (0 and 1) are
+ * dedicated to the Cortex-A9 processor cores in the MPU subsystem, leaving the
+ * last six output IDs (2-7) available to the ACP ID mapper. Output IDs 2-6
+ * support fixed and dynamic modes of operation while output ID 7 supports
+ * dynamic mode only.
+ *
+ * The following table summarizes the usage of the 3-bit ouput ID values by the
+ * ACP ID Mapper and their settings at reset.
+ *
+ * Output ID | Usage | Reset State
+ * :-----------|:--------------------------------------------------|:------------
+ * 0 | Reserved for Cortex-A9 cores. | -
+ * 1 | Reserved for Cortex-A9 cores. | -
+ * 2 | Assigned to Debug Access Port (DAP) input ID at | Fixed
+ * : | reset. After reset, can be reconfigured to either | DAP Master
+ * : | fixed or dynamic. |:
+ * 3 | Configurable fixed or dynamic mode. | Dynamic
+ * 4 | Configurable fixed or dynamic mode. | Dynamic
+ * 5 | Configurable fixed or dynamic mode. | Dynamic
+ * 6 | Configurable fixed or dynamic mode. | Dynamic
+ * 7 | Dynamic mode only. | Dynamic
+ *
+ * Where <em>Output ID</em> is the ACP ID Mapper output value that goes to the ACP.
+ *
+ * Additionally, for masters unable to drive the AXI user sideband signals of
+ * incoming transactions, the ACP ID Mapper allows control of the AXI user
+ * sideband signal values. Not all masters drive these signals, so the ACP ID
+ * Mapper makes it possible to drive the 5-bit user sideband signal with either
+ * a default value (in dynamic mode) or specific values (in fixed mode).
+ *
+ * The ACP ID Mapper can also control which 1 GiB coherent window into memory is
+ * accessed by masters of the L3 interconnect. Each fixed mapping can be
+ * assigned a different user sideband signal and memory window to allow specific
+ * settings for different masters. All dynamic mappings share a common user
+ * sideband signal and memory window setting. One important exception, however,
+ * is that the ACP ID mapper always allows user sideband signals from the
+ * FPGA-to-HPS bridge to pass through to the ACP regardless of the configured
+ * user sideband value associated with the ID.
+ *
+ * The ACP ID Mapper has a 1 GiB address window into the MPU address space, which
+ * is by default a view into the bottom 1 GiB of SDRAM. The ACP ID Mapper allows
+ * transactions to be routed to different 1 GiB-sized memory views, called pages,
+ * in both dynamic and fixed modes.
+ *
+ * See: <em>Chapter 6: Cortex-A9 Microprocessor Unit Subsystem</em> in
+ * <em>Volume 3: Hard Processor System Technical Reference Manual</em> of the
+ * <em>Arria V or Cyclone V Device Handbook</em> for a complete discussion of
+ * the operation and restrictions on the ACP and the ACP ID Mapper.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * \name External Master ID Macros
+ *
+ * These macros define the HPS external master identifiers that are 12-bit input
+ * IDs to the ACP ID Mapper. Some of the masters have a range of identifier
+ * values assigned to them and are distinguished by taking a <em>(var)\</em>
+ * argument.
+ * @{
+ */
+
+/*! Bit mask for the relevant 12 bits of an external master ID */
+#define ALT_ACP_ID_MAP_MASTER_ID_MASK 0xfff
+
+/*! Master ID for L2M0 */
+#define ALT_ACP_ID_MAP_MASTER_ID_L2M0(var) (0x00000002 | (0x000007f8 & (var)))
+/*! Master ID for DMA */
+#define ALT_ACP_ID_MAP_MASTER_ID_DMA(var) (0x00000001 | (0x00000078 & (var)))
+/*! Master ID for EMAC0 */
+#define ALT_ACP_ID_MAP_MASTER_ID_EMAC0(var) (0x00000801 | (0x00000878 & (var)))
+/*! Master ID for EMAC1 */
+#define ALT_ACP_ID_MAP_MASTER_ID_EMAC1(var) (0x00000802 | (0x00000878 & (var)))
+/*! Master ID for USB0 */
+#define ALT_ACP_ID_MAP_MASTER_ID_USB0 0x00000803
+/*! Master ID for USB1 */
+#define ALT_ACP_ID_MAP_MASTER_ID_USB1 0x00000806
+/*! Master ID for NAND controller */
+#define ALT_ACP_ID_MAP_MASTER_ID_NAND(var) (0x00000804 | (0x00000ff8 & (var)))
+/*! Master ID for Embedded Trace Router (ETR) */
+#define ALT_ACP_ID_MAP_MASTER_ID_TMC 0x00000800
+/*! Master ID for Debug Access Port (DAP) */
+#define ALT_ACP_ID_MAP_MASTER_ID_DAP 0x00000004
+/*! Master ID for SD/MMC controller */
+#define ALT_ACP_ID_MAP_MASTER_ID_SDMMC 0x00000805
+/*! Master ID for FPGA to HPS (F2H) bridge - conduit for soft IP masters in FPGA fabric */
+#define ALT_ACP_ID_MAP_MASTER_ID_F2H(var) (0x00000000 | (0x000007f8 & (var)))
+/*! @} */
+
+/******************************************************************************/
+/*!
+ * This type defines the enumerations 3-bit output ids to ACP ID mapper.
+ */
+typedef enum ALT_ACP_ID_OUTPUT_ID_e
+{
+ ALT_ACP_ID_OUT_FIXED_ID_2 = 2, /*!< Assigned to the input ID of the DAP at reset.
+ * After reset, can be either fixed or dynamic,
+ * programmed by software.
+ */
+ ALT_ACP_ID_OUT_DYNAM_ID_3 = 3, /*!< Fixed or dynamic, programmed by software output id */
+ ALT_ACP_ID_OUT_DYNAM_ID_4 = 4, /*!< Fixed or dynamic, programmed by software output id */
+ ALT_ACP_ID_OUT_DYNAM_ID_5 = 5, /*!< Fixed or dynamic, programmed by software output id */
+ ALT_ACP_ID_OUT_DYNAM_ID_6 = 6, /*!< Fixed or dynamic, programmed by software output id */
+ ALT_ACP_ID_OUT_DYNAM_ID_7 = 7 /*!< Dynamic mapping only */
+} ALT_ACP_ID_OUTPUT_ID_t;
+
+/*!
+ * This type defines the enumerations used to specify the 1 GiB page view of the
+ * MPU address space used by an ACP ID mapping configuration.
+ */
+typedef enum ALT_ACP_ID_MAP_PAGE_e
+{
+ ALT_ACP_ID_MAP_PAGE_0 = 0, /*!< Page 0 - MPU address range 0x00000000 - 0x3FFFFFFF */
+ ALT_ACP_ID_MAP_PAGE_1 = 1, /*!< Page 1 - MPU address range 0x40000000 - 0x7FFFFFFF */
+ ALT_ACP_ID_MAP_PAGE_2 = 2, /*!< Page 2 - MPU address range 0x80000000 - 0xBFFFFFFF */
+ ALT_ACP_ID_MAP_PAGE_3 = 3 /*!< Page 3 - MPU address range 0xC0000000 - 0xFFFFFFFF */
+} ALT_ACP_ID_MAP_PAGE_t;
+
+/******************************************************************************/
+/*!
+ * Configure a fixed ACP ID mapping for read transactions originating from
+ * external masters identified by \e input_id. The \e input_id value is
+ * translated to the specified 3-bit \e output_id required by the ACP slave
+ * port.
+ *
+ * \param input_id
+ * The 12 bit external master ID originating read transactions
+ * targeted for ID translation. Valid argument range must be 0 <=
+ * \e output_id <= 4095.
+ *
+ * \param output_id
+ * The 3-bit output ID value the ACP ID Mapper translates read
+ * transactions identified by \e input_id to. This is the value
+ * propogated to the ACP slave port. Valid argument values must be
+ * 0 <= \e output_id <= 7.
+ *
+ * \param page
+ * The MPU address space page view to use for the ACP window used
+ * by the ID tranlation mapping.
+ *
+ * \param aruser
+ * The 5-bit AXI ARUSER read user sideband signal value to use for
+ * masters unable to drive the AXI user sideband signals. Valid
+ * argument range is 0 <= \e aruser <= 31.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_RESERVED The argument value is reserved or unavailable.
+ * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
+ * more of the \e input_id, and/or \e output_id
+ * arguments violates its range constraint.
+ * \retval ALT_E_BAD_ARG The \e page argument is invalid.
+ */
+ALT_STATUS_CODE alt_acp_id_map_fixed_read_set(const uint32_t input_id,
+ const uint32_t output_id,
+ const ALT_ACP_ID_MAP_PAGE_t page,
+ const uint32_t aruser);
+
+/******************************************************************************/
+/*!
+ * Configure a fixed ACP ID mapping for write transactions originating from
+ * external masters identified by \e input_id. The \e input_id value is
+ * translated to the specified 3-bit \e output_id required by the ACP slave
+ * port.
+ *
+ * \param input_id
+ * The 12 bit external master ID originating write transactions
+ * targeted for ID translation. Valid argument range must be 0 <=
+ * \e output_id <= 4095.
+ *
+ * \param output_id
+ * The 3-bit output ID value the ACP ID Mapper translates write
+ * transactions identified by \e input_id to. This is the value
+ * propogated to the ACP slave port. Valid argument values must be
+ * 0 <= \e output_id <= 7.
+ *
+ * \param page
+ * The MPU address space page view to use for the ACP window used
+ * by the ID tranlation mapping.
+ *
+ * \param awuser
+ * The 5-bit AXI AWUSER write user sideband signal value to use for
+ * masters unable to drive the AXI user sideband signals. Valid
+ * argument range is 0 <= \e awuser <= 31.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_RESERVED The argument value is reserved or unavailable.
+ * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
+ * more of the \e input_id, and/or \e output_id
+ * arguments violates its range constraint.
+ * \retval ALT_E_BAD_ARG The \e page argument is invalid.
+ */
+ALT_STATUS_CODE alt_acp_id_map_fixed_write_set(const uint32_t input_id,
+ const uint32_t output_id,
+ const ALT_ACP_ID_MAP_PAGE_t page,
+ const uint32_t awuser);
+
+/******************************************************************************/
+/*!
+ * Configure the designated 3-bit output ID as an available identifier resource
+ * for use by the dynamic ID mapping function of the ACP ID Mapper for read
+ * transactions. The \e output_id value is available for dynamic assignment to
+ * external master read transaction IDs that do not have an explicit fixed ID
+ * mapping.
+ *
+ * \param output_id
+ * The 3-bit output ID value designated as an available ID for use
+ * by the dynamic mapping function of the ACP ID Mapper. The \e
+ * ouput_id value is used exclusively for dynamic ID mapping until
+ * reconfigured as a fixed ID mapping by a call to
+ * alt_acp_id_map_fixed_read_set(). Valid argument values must be
+ * 0 <= \e output_id <= 7.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_RESERVED The argument value is reserved or unavailable.
+ * \retval ALT_E_ARG_RANGE An argument violates a range constraint.
+ */
+ALT_STATUS_CODE alt_acp_id_map_dynamic_read_set(const uint32_t output_id);
+
+/******************************************************************************/
+/*!
+ * Configure the designated 3-bit output ID as an available identifier resource
+ * for use by the dynamic ID mapping function of the ACP ID Mapper for write
+ * transactions. The \e output_id value is available for dynamic assignment to
+ * external master write transaction IDs that do not have an explicit fixed ID
+ * mapping.
+ *
+ * \param output_id
+ * The 3-bit output ID value designated as an available ID for use
+ * by the dynamic mapping function of the ACP ID Mapper. The \e
+ * ouput_id value is used exclusively for dynamic ID mapping until
+ * reconfigured as a fixed ID mapping by a call to
+ * alt_acp_id_map_fixed_write_set(). Valid argument values must be
+ * 0 <= \e output_id <= 7.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_RESERVED The argument value is reserved or unavailable.
+ * \retval ALT_E_ARG_RANGE An argument violates a range constraint.
+ */
+ALT_STATUS_CODE alt_acp_id_map_dynamic_write_set(const uint32_t output_id);
+
+/******************************************************************************/
+/*!
+ * Configure the page and user read sideband signal options that are applied to
+ * all read transactions that have their input IDs dynamically mapped.
+ *
+ * \param page
+ * The MPU address space page view to use for the ACP window used
+ * by the dynamic ID tranlation mapping.
+ *
+ * \param aruser
+ * The 5-bit AXI ARUSER read user sideband signal value to use for
+ * masters unable to drive the AXI user sideband signals. Valid
+ * argument range is 0 <= \e aruser <= 31.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_RESERVED The argument value is reserved or unavailable.
+ * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
+ * more of the \e page and/or \e aruser
+ * arguments violates its range constraint.
+ * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master
+ * identifier.
+ */
+ALT_STATUS_CODE alt_acp_id_map_dynamic_read_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
+ const uint32_t aruser);
+
+/******************************************************************************/
+/*!
+ * Configure the page and user write sideband signal options that are applied to
+ * all write transactions that have their input IDs dynamically mapped.
+ *
+ * \param page
+ * The MPU address space page view to use for the ACP window used
+ * by the dynamic ID tranlation mapping.
+ *
+ * \param awuser
+ * The 5-bit AXI AWUSER write user sideband signal value to use for
+ * masters unable to drive the AXI user sideband signals. Valid
+ * argument range is 0 <= \e aruser <= 31.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_RESERVED The argument value is reserved or unavailable.
+ * \retval ALT_E_ARG_RANGE An argument violates a range constraint. One or
+ * more of the \e page and/or \e awuser
+ * arguments violates its range constraint.
+ * \retval ALT_E_BAD_ARG The \e mid argument is not a valid master
+ * identifier.
+ */
+ALT_STATUS_CODE alt_acp_id_map_dynamic_write_options_set(const ALT_ACP_ID_MAP_PAGE_t page,
+ const uint32_t awuser);
+
+/******************************************************************************/
+/*!
+ * Return the current read transaction mapping configuration used by the ACP ID
+ * Mapper for the specified output ID.
+ *
+ * If \e output_id is configured as a fixed mapping then \b true is returned in
+ * the \e fixed output parameter and the translation mapping options configured
+ * for that \e output_id are returned in the other output parameters.
+ *
+ * If \e output_id is configured as a dynamic mapping then \b false is returned
+ * in the \e fixed output parameter and the translation mapping options
+ * configured for all dynamically remapped output IDs are returned in the other
+ * output parameters.
+ *
+ * \param output_id
+ * The output ID to return the mapping configuration for. 0 <= \e
+ * output_id <= 7.
+ *
+ * \param fixed
+ * [out] Set to \b true if the specified \e output_id is a fixed ID
+ * mapping configuration. Set to \b false if the mapping
+ * configuration is dynamic.
+ *
+ * \param input_id
+ * [out] The input ID of the external master that a fixed ID
+ * mapping is applied to for the \e output_id. If \e fixed is \b
+ * false then this output parameter is set to 0 and its value
+ * should be considered as not applicable.
+ *
+ * \param page
+ * [out] The MPU address space page view used by the mapping
+ * configuration.
+ *
+ * \param aruser
+ * [out] The 5-bit AXI ARUSER read user sideband signal value used
+ * by the mapping configuration when masters are unable to drive
+ * the AXI user sideband signals.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_RESERVED The argument value is reserved or unavailable.
+ * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e
+ * output_id argument violates its range constraint.
+ */
+ALT_STATUS_CODE alt_acp_id_map_read_options_get(const uint32_t output_id,
+ bool* fixed,
+ uint32_t* input_id,
+ ALT_ACP_ID_MAP_PAGE_t* page,
+ uint32_t* aruser);
+
+/******************************************************************************/
+/*!
+ * Return the current write transaction mapping configuration used by the ACP ID
+ * Mapper for the specified output ID.
+ *
+ * If \e output_id is configured as a fixed mapping then \b true is returned in
+ * the \e fixed output parameter and the translation mapping options configured
+ * for that \e output_id are returned in the other output parameters.
+ *
+ * If \e output_id is configured as a dynamic mapping then \b false is returned
+ * in the \e fixed output parameter and the translation mapping options
+ * configured for all dynamically remapped output IDs are returned in the other
+ * output parameters.
+ *
+ * \param output_id
+ * The output ID to return the mapping configuration for. 0 <= \e
+ * output_id <= 7.
+ *
+ * \param fixed
+ * [out] Set to \b true if the specified \e output_id is a fixed ID
+ * mapping configuration. Set to \b false if the mapping
+ * configuration is dynamic.
+ *
+ * \param input_id
+ * [out] The input ID of the external master that a fixed ID
+ * mapping is applied to for the \e output_id. If \e fixed is \b
+ * false then this output parameter is set to 0 and its value
+ * should be considered as not applicable.
+ *
+ * \param page
+ * [out] The MPU address space page view used by the mapping
+ * configuration.
+ *
+ * \param awuser
+ * [out] The 5-bit AXI AWUSER write user sideband signal value used
+ * by the mapping configuration when masters are unable to drive
+ * the AXI user sideband signals.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_RESERVED The argument value is reserved or unavailable.
+ * \retval ALT_E_ARG_RANGE An argument violates a range constraint. The \e
+ * output_id argument violates its range constraint.
+ */
+ALT_STATUS_CODE alt_acp_id_map_write_options_get(const uint32_t output_id,
+ bool* fixed,
+ uint32_t* input_id,
+ ALT_ACP_ID_MAP_PAGE_t* page,
+ uint32_t* awuser);
+
+/*! @} */
+
+/*! @} */
+
+#endif /* __ASSEMBLY__ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __ALT_ADDRESS_SPACE_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h
new file mode 100644
index 0000000000..8d088ab744
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_cache.h
@@ -0,0 +1,964 @@
+/******************************************************************************
+ *
+ * Copyright 2013 Altera Corporation. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+#ifndef __ALT_CACHE_H__
+#define __ALT_CACHE_H__
+
+#include "hwlib.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+ * \addtogroup CACHE_MGR Cache Management API
+ *
+ * This module defines the cache management API for enabling and disabling L1
+ * data cache, L1 instruction cache, L1 dynamic branch prediction caches, L1
+ * TLB cache, and L2 cache in the SoC. As well, many it allows users to perform
+ * cache maintenance operations on these caches. This includes the following
+ * operations:
+ * * Invalidate: Marks the cache line as being invalid, freeing up the space
+ * to cache other data. All APIs which enable caches invalidates the memory
+ * before being enabling the cache.
+ * * Clean: If the cache line is dirty, it synchronizes the cache line data
+ * with the upper level memory system and marks that line as clean. All APIs
+ * which disable caches cleans the memory before disabling the cache.
+ * * Purge: A term used in this API as a short form for clean and invalidate.
+ * This operation cleans and invalidates a cache line in that order, as a
+ * single command to the cache controller.
+ *
+ * The following reference materials were used in the design of this API:
+ * * ARM&reg; Architecture Reference Manual, ARMv7-A and ARMv7-R edition
+ * * Cortex&trade;-A9 Technical Reference Manual
+ * * Cortex&trade;-A9 MPCore Technical Reference Manual
+ * * CoreLink&trade; Level 2 Cache Controller L2C-310 Technical Reference
+ * Manual
+ *
+ * @{
+ */
+
+/*!
+ * \addtogroup CACHE_SYS System Level Cache Management API
+ *
+ * This API group provides cache maintenance operations which affects multiple
+ * cache levels.
+ *
+ * The enable and disable functions enables and disables all caches in the
+ * system respectively. For caches shared by the CPU core(s), particularly the
+ * L2 cache, once that cache is enabled or disabled it will not be invalidated
+ * or cleaned again respectively. This allows the safe system-wide enable and
+ * disable to be used in single-core and multi-core scenarios.
+ *
+ * For cache maintenance operations, this API implements the procedures
+ * outlined in the L2C-310 Technical Reference Manual, section 3.3.10,
+ * subsection "System cache maintenance considerations". This allows for a
+ * convenient way to invalidate, clean, or clean and invalidate cache data from
+ * the L1 to L2 to L3 while avoiding any potential race conditions in
+ * mutli-core or multi-master scenarios. It assumes that the L1 and L2 cache is
+ * set in "non-exclusive" mode. This means a segment of data can reside in both
+ * the L1 and L2 simultaneously. This is the default mode for caches in the
+ * system.
+ *
+ * The current implementation of the system cache APIs assumes that the MMU is
+ * configured with a flat memory mapping or that every virtual address matches
+ * perfectly with the physical address. This restriction may be lifted in a
+ * future release of the cache API implementation.
+ *
+ * @{
+ */
+
+/*!
+ * Enables support for a non-flat virtual memory. A flat virtual memory is
+ * where every virtual address matches exactly to the physical address, making
+ * the virtual to physical translation trivial. Adding support for non-flat
+ * adds some overhead for the VA to PA translation and error detection.
+ *
+ * To enable non-flat virtual memory support, defined
+ * ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY=1 in your Makefile when compiling
+ * HWLibs.
+ */
+#ifndef ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY
+#define ALT_CACHE_SUPPORT_NON_FLAT_VIRTUAL_MEMORY (0)
+#endif
+
+/*!
+ * This is the system wide cache line size, given in bytes.
+ */
+#define ALT_CACHE_LINE_SIZE 32
+
+/*!
+ * Enables all caches and features which improve reliability and speed on all
+ * cache controllers visible to the current CPU core. This includes parity
+ * error detection. Cache controllers visible to multiple CPU cores, for
+ * example the L2, will first be checked to be disabled before being enabled.
+ * All necessary cache maintenance operations will be done automatically.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_system_enable(void);
+
+/*!
+ * Disables all cache controllers visible to the current CPU core. Cache
+ * controllers visible to multiple CPU cores, for example the L2, will first
+ * be checked to be enabled before being disabled. All necessary cache
+ * maintenance operations will be done automatically.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_system_disable(void);
+
+/*!
+ * Invalidates the specified contents of all cache levels visible to the
+ * current CPU core for the given memory segment.
+ *
+ * The memory segment address and length specified must align to the
+ * characteristics of the cache line. This means the address and length must be
+ * multiples of the cache line size. To determine the cache line size, use the
+ * \b ALT_CACHE_LINE_SIZE macro.
+ *
+ * The following pseudocode outlines the operations carried out by this
+ * function:
+ * -# L2 invalidate address(es)
+ * -# L2 cache sync
+ * -# L1 invalidate address(es)
+ * -# DSB instruction
+ *
+ * The current implementation of the system cache APIs assumes that the MMU is
+ * configured with a flat memory mapping or that every virtual address matches
+ * perfectly with the physical address. This restriction may be lifted in a
+ * future release of the cache API implementation.
+ *
+ * \param vaddress
+ * The virtual address of the memory segment to be invalidated.
+ *
+ * \param length
+ * The length of the memory segment to be invalidated.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The memory segment is invalid.
+ * \retval ALT_E_TMO The memory operation timed out.
+ */
+ALT_STATUS_CODE alt_cache_system_invalidate(void * vaddress, size_t length);
+
+/*!
+ * Cleans the specified contents of all cache levels visible to the current
+ * CPU core for the given memory segment.
+ *
+ * The memory segment address and length specified must align to the
+ * characteristics of the cache line. This means the address and length must be
+ * multiples of the cache line size. To determine the cache line size, use the
+ * \b ALT_CACHE_LINE_SIZE macro.
+ *
+ * The following pseudocode outlines the operations carried out by this
+ * function:
+ * -# L1 clean address(es)
+ * -# DSB instruction
+ * -# L2 clean address(es)
+ * -# L2 cache sync
+ *
+ * The current implementation of the system cache APIs assumes that the MMU is
+ * configured with a flat memory mapping or that every virtual address matches
+ * perfectly with the physical address. This restriction may be lifted in a
+ * future release of the cache API implementation.
+ *
+ * \param vaddress
+ * The virtual address of the memory segment to be cleaned.
+ *
+ * \param length
+ * The length of the memory segment to be cleaned.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The memory segment is invalid.
+ * \retval ALT_E_TMO The memory operation timed out.
+ */
+ALT_STATUS_CODE alt_cache_system_clean(void * vaddress, size_t length);
+
+/*!
+ * Cleans and invalidates the specified contents of all cache levels visible
+ * to the current CPU core for the given memory segment.
+ *
+ * The memory segment address and length specified must align to the
+ * characteristics of the cache line. This means the address and length must be
+ * multiples of the cache line size. To determine the cache line size, use the
+ * \b ALT_CACHE_LINE_SIZE macro.
+ *
+ * The following pseudocode outlines the operations carried out by this
+ * function:
+ * -# L1 clean address(es)
+ * -# DSB instruction
+ * -# L2 clean and invalidate address(es)
+ * -# L2 cache sync
+ * -# L1 invalidate address(es)
+ * -# DSB instruction
+ *
+ * The current implementation of the system cache APIs assumes that the MMU is
+ * configured with a flat memory mapping or that every virtual address matches
+ * perfectly with the physical address. This restriction may be lifted in a
+ * future release of the cache API implementation.
+ *
+ * \param vaddress
+ * The virtual address of the memory segment to be purged.
+ *
+ * \param length
+ * The length of the memory segment to be purged.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The memory segment is invalid.
+ * \retval ALT_E_TMO The memory operation timed out.
+ */
+ALT_STATUS_CODE alt_cache_system_purge(void * vaddress, size_t length);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup CACHE_L1 L1 Cache Management API
+ *
+ * This API group provides functions to interact with various components of the
+ * L1 cache on the SoCFPGA. This includes the following cache components:
+ * * Instruction Cache
+ * * Data Cache
+ * * Parity error detection
+ * * Dynamic branch prediction
+ * * Data prefetching
+ *
+ * The API within this group only affects the L1 cache on the current CPU. To
+ * interact the L1 cache on another CPU, the API must be called from that other
+ * CPU.
+ *
+ * With respect to bring-up, the L1 and L2 cache controller setups are fully
+ * independent. The L2 can be setup at any time, before or after the L1 is setup.
+ * \internal
+ * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up".
+ * \endinternal
+ *
+ * @{
+ */
+
+/*!
+ * Enables all L1 caches and features on the current CPU core. This includes
+ * the instruction cache, data cache, parity error detection, branch target
+ * address cache, global history buffer, and data prefetching. All necessary
+ * maintenance tasks will be taken care of.
+ *
+ * This function should not be mixed with other L1 cache related functions
+ * which enable or disable caches individually.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_enable_all(void);
+
+/*!
+ * Disables all L1 caches and features on the current CPU core. This includes
+ * the instruction cache, data cache, parity error detection, branch target
+ * address cache, global history buffer, and data prefetching. All necessary
+ * maintenance tasks will be taken care of.
+ *
+ * This function should not be mixed with other L1 cache related functions
+ * which enable or disable caches individually.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_disable_all(void);
+
+/*!
+ * Enables the L1 instruction cache on the current CPU core. If the cache is
+ * already enabled, nothing is done. Otherwise the instruction cache is first
+ * invalidated before being enabled.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_instruction_enable(void);
+
+/*!
+ * Disables the L1 instruction cache on the current CPU core.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_instruction_disable(void);
+
+/*!
+ * Returns \b true when the L1 instruction cache is enabled and \b false when
+ * it is disabled on the current CPU core.
+ *
+ * \retval true The L1 instruction cache is enabled.
+ * \retval false The L1 instruction cache is disabled.
+ */
+bool alt_cache_l1_instruction_is_enabled(void);
+
+/*!
+ * Invalidates the contents of the L1 instruction cache on the current CPU
+ * core.
+ *
+ * Normally this is done automatically as part of
+ * alt_cache_l1_instruction_enable(), but in certain circumstances it may be
+ * necessary to invalidate it manually. An example of this situation is when
+ * the address space is remapped and the processor executes instructions from
+ * the new memory area.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_instruction_invalidate(void);
+
+/*!
+ * Enables the L1 data cache on the current CPU core.
+ *
+ * If the cache is already enabled nothing is done. Otherwise the data cache is
+ * first invalidated before being enabled.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_data_enable(void);
+
+/*!
+ * Disables the L1 data cache on the current CPU core.
+ *
+ * If the cache is already disabled nothing is done. Otherwise the data cache
+ * is first cleaned before being disabled.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_data_disable(void);
+
+/*!
+ * Returns \b true when the L1 data cache is enabled and \b false when it is
+ * disabled on the current CPU core.
+ *
+ * \retval true The L1 data cache is enabled.
+ * \retval false The L1 data cache is disabled.
+ */
+bool alt_cache_l1_data_is_enabled(void);
+
+/*!
+ * Invalidates the specified contents of the L1 data cache on the current CPU
+ * core for the given memory segment.
+ *
+ * The memory segment address and length specified must align to the
+ * characteristics of the cache line. This means the address and length must be
+ * multiples of the cache line size. To determine the cache line size, use the
+ * \b ALT_CACHE_LINE_SIZE macro.
+ *
+ * \param vaddress
+ * The virtual address of the memory segment to be invalidated.
+ *
+ * \param length
+ * The length of the memory segment to be invalidated.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The memory segment is invalid.
+ */
+ALT_STATUS_CODE alt_cache_l1_data_invalidate(void * vaddress, size_t length);
+
+/*!
+ * Invalidates the entire contents of the L1 data cache on the current CPU
+ * core.
+ *
+ * Normally this is done automatically as part of alt_cache_l1_data_enable(),
+ * but in certain circumstances it may be necessary to invalidate it manually.
+ * An example of this situation is when the address space is remapped and the
+ * processor accesses memory from the new memory area.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_data_invalidate_all(void);
+
+/*!
+ * Cleans the specified contents of the L1 data cache on the current CPU core
+ * for the given memory segment.
+ *
+ * The memory segment address and length specified must align to the
+ * characteristics of the cache line. This means the address and length must be
+ * multiples of the cache line size. To determine the cache line size, use the
+ * \b ALT_CACHE_LINE_SIZE macro.
+ *
+ * \param vaddress
+ * The virtual address of the memory segment to be cleaned.
+ *
+ * \param length
+ * The length of the memory segment to be cleaned.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The memory segment is invalid.
+ */
+ALT_STATUS_CODE alt_cache_l1_data_clean(void * vaddress, size_t length);
+
+/*!
+ * Cleans the entire L1 data cache for the current CPU core.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_data_clean_all(void);
+
+/*!
+ * Cleans and invalidates the specified contents of the L1 data cache on the
+ * current CPU core for the given memory segment.
+ *
+ * The memory segment address and length specified must align to the
+ * characteristics of the cache line. This means the address and length must be
+ * multiples of the cache line size. To determine the cache line size, use the
+ * \b ALT_CACHE_LINE_SIZE macro.
+ *
+ * Normally this is done automatically as part of alt_cache_l1_data_disable(),
+ * but in certain circumstances it may be necessary to purged it manually.
+ * An example of this situation is when the address space is remapped and the
+ * processor accesses memory from the new memory area.
+ *
+ * \param vaddress
+ * The virtual address of the memory segment to be purged.
+ *
+ * \param length
+ * The length of the memory segment to be purged.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The memory segment is invalid.
+ */
+ALT_STATUS_CODE alt_cache_l1_data_purge(void * vaddress, size_t length);
+
+/*!
+ * Cleans and invalidates the entire L1 data cache for the current CPU core.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_data_purge_all(void);
+
+/*!
+ * Enables the parity error detection feature in the L1 caches on the current
+ * CPU core.
+ *
+ * Ideally parity should be enabled before any L1 caches are enabled. If the
+ * instruction, data, and / or dynamic branch predictor caches are already
+ * enabled, they will first be cleaned (if needed) and disabled before parity
+ * is enabled in hardware. Afterwards, the affected caches will be invalidated
+ * and enabled.
+ *
+ * Parity and TLB interaction deserves special attention. The TLB is considered
+ * to be a L1 cache but is enabled when the MMU, which is grouped in another
+ * API, is enabled. Due to the system-wide influence of the MMU, it cannot be
+ * disabled and enabled with impunity as the other L1 caches, which are
+ * designed to operate as transparently as possible. Thus parity error
+ * detection must be enabled before the L1 TLB cache, and by extension the MMU,
+ * is enabled.
+ *
+ * For a parity error to be reported, the appropriate CPU PARITYFAIL interrupt
+ * for the current CPU core must be enabled using the interrupt controller API.
+ * For CPU0, ALT_INT_INTERRUPT_CPU0_PARITYFAIL is asserted if any parity error
+ * is detected while the other PARITYFAIL interrupts are for parity errors in a
+ * specific memory. Refer to the interrupt controller API for more details
+ * about programming the interrupt controller.
+ *
+ * In the event of a parity error is detected, the appropriate CPU parity
+ * interrupt will be raised. CPU parity interrupts are all edge triggered and
+ * are cleared by acknowledging them in the interrupt controller API.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_parity_enable(void);
+
+/*!
+ * Disables parity error detection in the L1 caches.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_parity_disable(void);
+
+/*!
+ * Returns \b true when parity error detection is enabled and \b false when it
+ * is disabled on the current CPU core.
+ *
+ * \retval true Parity error detection for L1 caches is
+ * enabled.
+ * \retval false Parity error detection for L1 caches is
+ * disabled.
+ */
+bool alt_cache_l1_parity_is_enabled(void);
+
+/*!
+ * Enables the dynamic branch predictor features on the current CPU core.
+ *
+ * This operation enables both the Branch Target Address Cache (BTAC) and
+ * the Global History Buffer (GHB). Affected caches are automatically
+ * invalidated before use.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_branch_enable(void);
+
+/*!
+ * Disables the dynamic branch predictor features on the current CPU core.
+ *
+ * This operation disables both the Branch Target Address Cache (BTAC) and
+ * the Global History Buffer (GHB).
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_branch_disable(void);
+
+/*!
+ * Returns \b true when both the dynamic predictor features are enabled and
+ * \b false when they are disabled on the current CPU core.
+ *
+ * \retval true The L1 branch predictor caches are all enabled.
+ * \retval false Some or all L1 branch predictor caches are
+ * disabled.
+ */
+bool alt_cache_l1_branch_is_enabled(void);
+
+/*!
+ * Invalidates the dynamic branch predictor feature caches on the current CPU
+ * core.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_branch_invalidate(void);
+
+/*!
+ * Enables the L1 cache data prefetch feature on the current CPU core.
+ *
+ * This allows data to be prefetched into the data cache before it is to be
+ * used. For example in a loop the current iteration may want to preload the
+ * data which will be used in the next teration. This is done by using the PLD
+ * instructions.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_prefetch_enable(void);
+
+/*!
+ * Disables the L1 cache data prefetch feature on the current CPU core.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l1_prefetch_disable(void);
+
+/*!
+ * Returns \b true if the L1 cache data prefetch feature is enabled and
+ * \b false if it is disabled on the current CPU core.
+ *
+ * \retval true The L1 data cache prefetch feature is enabled.
+ * \retval false The L1 data cache prefetch feature is disabled.
+ */
+bool alt_cache_l1_prefetch_is_enabled(void);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup CACHE_L2 L2 Cache Management API
+ *
+ * This API group provides functions to interact with various features of the
+ * L2 cache on the SoCFPGA. This includes the following features:
+ * * L2 cache
+ * * Parity error detection
+ * * Data prefetching
+ * * Interrupt Management
+ *
+ * \internal
+ * Additional features that may be implemented in the future:
+ * * Lockdown
+ * * Event counter
+ * \endinternal
+ *
+ * The API within this group affects the L2 cache which is visible to all CPUs
+ * on the system.
+ *
+ * With respect to bring-up, the L1 and L2 cache controller setups are fully
+ * independent. The L2 can be setup at any time, before or after the L1 is setup.
+ * \internal
+ * Source: Cortex-A9 MPCore TRM, section 5.3.4 "Multiprocessor bring-up".
+ * \endinternal
+ *
+ * @{
+ */
+
+/*!
+ * Initializes the L2 cache controller.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ */
+ALT_STATUS_CODE alt_cache_l2_init(void);
+
+/*!
+ * Uninitializes the L2 cache controller.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ */
+ALT_STATUS_CODE alt_cache_l2_uninit(void);
+
+/*!
+ * Enables the L2 cache features for data and instruction prefetching.
+ *
+ * Prefetching can be enabled or disabled while the L2 cache is enabled.
+ * \internal
+ * Source: Use the Prefetch Control Register.
+ * \endinternal
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l2_prefetch_enable(void);
+
+/*!
+ * Disables the L2 cache features for data and instruction prefetching.
+ *
+ * Prefetching can be enabled or disabled while the L2 cache is enabled.
+ * \internal
+ * Source: Use the Prefetch Control Register.
+ * \endinternal
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l2_prefetch_disable(void);
+
+/*!
+ * Returns \b true if either L2 cache data or instruction prefetch features are
+ * enabled and \b false if no prefetching features are enabled.
+ *
+ * \retval true The L2 data and instruction prefetch features
+ * are enabled.
+ * \retval false Some L2 data and instruction prefetch features
+ * are disabled.
+ */
+bool alt_cache_l2_prefetch_is_enabled(void);
+
+/*!
+ * Enables parity error detection in the L2 cache.
+ *
+ * Ideally parity should be enabled before the L2 cache is enabled. If the
+ * cache is already enabled, it will first be cleaned and disabled before
+ * parity is enabled in hardware. Afterwards, the cache will be invalidated and
+ * enabled.
+ *
+ * For a parity error to be reported, the ALT_CACHE_L2_INTERRUPT_PARRD and / or
+ * ALT_CACHE_L2_INTERRUPT_PARRT interrupt condition(s) must be enabled. This is
+ * done by calling alt_cache_l2_int_enable(). As well, the L2 cache interrupt
+ * must be enabled using the interrupt controller API. Refer to the interrupt
+ * controller API for more details about programming the interrupt controller.
+ *
+ * In the event of a parity error is detected, the appropriate L2 cache parity
+ * interrupt will be raised. To clear the parity interrupt(s), the appropriate
+ * L2 cache parity interrupt must be cleared by calling
+ * alt_cache_l2_int_status_clear().
+ *
+ * For ECC support, refer to the ECC related API documentation for more
+ * information.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l2_parity_enable(void);
+
+/*!
+ * Disables parity error detection in the L2 cache.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l2_parity_disable(void);
+
+/*!
+ * Returns \b true when parity error detection is enabled and \b false when it
+ * is disabled.
+ *
+ * \retval true The L2 cache parity error detection feature is
+ * enabled.
+ * \retval false The L2 cache parity error detection feature is
+ * disabled.
+ */
+bool alt_cache_l2_parity_is_enabled(void);
+
+/*!
+ * Enables the L2 cache.
+ *
+ * If the L2 cache is already enabled, nothing is done. Otherwise the entire
+ * contents of the cache is first invalidated before being enabled.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l2_enable(void);
+
+/*!
+ * Disables the L2 cache.
+ *
+ * If the L2 cache is already disabled, nothing is done. Otherwise the entire
+ * contents of the cache is first cleaned before being disabled.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l2_disable(void);
+
+/*!
+ * Returns \b true when the L2 cache is enabled and \b false when it is
+ * disabled.
+ *
+ * \retval true The L2 cache is enabled.
+ * \retval false The L2 cache is disabled.
+ */
+bool alt_cache_l2_is_enabled(void);
+
+/*!
+ * Flushes the L2 cache controller hardware buffers.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_TMO The memory operation timed out.
+ */
+ALT_STATUS_CODE alt_cache_l2_sync(void);
+
+/*!
+ * Invalidates the specified contents of the L2 cache for the given memory
+ * segment.
+ *
+ * The memory segment address and length specified must align to the
+ * characteristics of the cache line. This means the address and length must be
+ * multiples of the cache line size. To determine the cache line size, use the
+ * \b ALT_CACHE_LINE_SIZE macro.
+ *
+ * \param paddress
+ * The physical address of the memory segment to be invalidated.
+ *
+ * \param length
+ * The length of the memory segment to be invalidated.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The memory segment is invalid.
+ * \retval ALT_E_TMO The memory operation timed out.
+ */
+ALT_STATUS_CODE alt_cache_l2_invalidate(void * paddress, size_t length);
+
+/*!
+ * Invalidates th entire contents of the L2 cache.
+ *
+ * Normally this is done automatically as part of alt_cache_l2_enable(), but
+ * in certain circumstances it may be necessary to invalidate it manually. An
+ * example of this situation is when the address space is remapped and the
+ * processor accesses memory from the new memory area.
+
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_TMO The memory operation timed out.
+ */
+ALT_STATUS_CODE alt_cache_l2_invalidate_all(void);
+
+/*!
+ * Cleans the specified contents of the L2 cache for the given memory segment.
+ *
+ * The memory segment address and length specified must align to the
+ * characteristics of the cache line. This means the address and length must be
+ * multiples of the cache line size. To determine the cache line size, use the
+ * \b ALT_CACHE_LINE_SIZE macro.
+ *
+ * \param paddress
+ * The physical address of the memory segment to be cleaned.
+ *
+ * \param length
+ * The length of the memory segment to be cleaned.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The memory segment is invalid.
+ * \retval ALT_E_TMO The memory operation timed out.
+ */
+ALT_STATUS_CODE alt_cache_l2_clean(void * paddress, size_t length);
+
+/*!
+ * Cleans the entire L2 cache. All L2 cache controller interrupts will be
+ * temporarily disabled while the clean operation is in progress and restored
+ * once the it is finished.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_TMO The memory operation timed out.
+ */
+ALT_STATUS_CODE alt_cache_l2_clean_all(void);
+
+/*!
+ * Cleans and invalidates the specified contents of the L2 cache for the
+ * given memory segment.
+ *
+ * The memory segment address and length specified must align to the
+ * characteristics of the cache line. This means the address and length must be
+ * multiples of the cache line size. To determine the cache line size, use the
+ * \b ALT_CACHE_LINE_SIZE macro.
+ *
+ * \param paddress
+ * The physical address of the memory segment to be purged.
+ *
+ * \param length
+ * The length of the memory segment to be purged.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The memory segment is invalid.
+ */
+ALT_STATUS_CODE alt_cache_l2_purge(void * paddress, size_t length);
+
+/*!
+ * Cleans and invalidates the entire L2 cache. All L2 cache controller
+ * interrupts will be temporarily disabled while the clean and invalidate
+ * operation is in progress and restored once the it is finished.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_TMO The memory operation timed out.
+ */
+ALT_STATUS_CODE alt_cache_l2_purge_all(void);
+
+/*!
+ * This type definition enumerates all the interrupt conditions that can be
+ * generated by the L2 cache controller as register mask values.
+ */
+enum ALT_CACHE_L2_INTERRUPT_e
+{
+ /*! Decode error received on the master ports from L3. */
+ ALT_CACHE_L2_INTERRUPT_DECERR = 1 << 8,
+
+ /*! Slave error received on the master ports from L3. */
+ ALT_CACHE_L2_INTERRUPT_SLVERR = 1 << 7,
+
+ /*! Error on the L2 data RAM read. */
+ ALT_CACHE_L2_INTERRUPT_ERRRD = 1 << 6,
+
+ /*! Error on the L2 tag RAM read. */
+ ALT_CACHE_L2_INTERRUPT_ERRRT = 1 << 5,
+
+ /*! Error on the L2 data RAM write. */
+ ALT_CACHE_L2_INTERRUPT_ERRWD = 1 << 4,
+
+ /*! Error on the L2 tag RAM write. */
+ ALT_CACHE_L2_INTERRUPT_ERRWT = 1 << 3,
+
+ /*! Parity error on the L2 data RAM read. */
+ ALT_CACHE_L2_INTERRUPT_PARRD = 1 << 2,
+
+ /*! Parity error on the L2 tag RAM read. */
+ ALT_CACHE_L2_INTERRUPT_PARRT = 1 << 1,
+
+ /*! Event counter overflow or increment. */
+ ALT_CACHE_L2_INTERRUPT_ECNTR = 1 << 0
+};
+typedef enum ALT_CACHE_L2_INTERRUPT_e ALT_CACHE_L2_INTERRUPT_t;
+
+/*!
+ * Enables the L2 cache controller interrupts for the specified set of
+ * condition(s).
+ *
+ * \param interrupt
+ * A register mask of the selected L2 cache controller
+ * interrupting conditions.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l2_int_enable(uint32_t interrupt);
+
+/*!
+ * Disables the L2 cache controller interrupts for the specified set of
+ * condition(s).
+ *
+ * \param interrupt
+ * A register mask of the selected L2 cache controller
+ * interrupting conditions.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l2_int_disable(uint32_t interrupt);
+
+/*!
+ * Gets the condition(s) causing the L2 cache controller to interrupt as a
+ * register mask.
+ *
+ * \returns A register mask of the currently asserted and enabled
+ * conditions resulting in an interrupt being generated.
+ */
+uint32_t alt_cache_l2_int_status_get(void);
+
+/*!
+ * Clears the specified conditon(s) causing the L2 cache controller to
+ * interrupt as a mask. Condition(s) specified which are not causing an
+ * interrupt or condition(s) specified which are not enabled are ignored.
+ *
+ * \param interrupt
+ * A register mask of the selected L2 cache controller
+ * interrupting conditions.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_cache_l2_int_status_clear(uint32_t interrupt);
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_CACHE_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h
new file mode 100644
index 0000000000..a43608e9f3
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h
@@ -0,0 +1,114 @@
+/******************************************************************************
+ *
+ * Copyright 2013 Altera Corporation. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+/*!
+ * \file
+ *
+ * Contains the definition of an opaque data structure that contains raw
+ * configuration information for a clock group.
+ */
+
+#ifndef __ALT_CLK_GRP_H__
+#define __ALT_CLK_GRP_H__
+
+#include "hwlib.h"
+#include "socal/alt_clkmgr.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*!
+ * This type definition enumerates the clock groups
+ */
+typedef enum ALT_CLK_GRP_e
+{
+ ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */
+
+ ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */
+
+ ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */
+
+} ALT_CLK_GRP_t;
+
+/*!
+ * This type definition defines an opaque data structure for holding the
+ * configuration settings for a complete clock group.
+ */
+typedef struct ALT_CLK_GROUP_RAW_CFG_s
+{
+ uint32_t verid; /*!< SoC FPGA version identifier. This field
+ * encapsulates the silicon identifier and
+ * version information associated with this
+ * clock group configuration. It is used to
+ * assert that this clock group configuration
+ * is valid for this device. */
+
+ uint32_t siliid2; /*!< Reserved register - reserved for future
+ * device IDs or capability flags. */
+
+ ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */
+
+ /*!
+ * This union holds the register values for configuration of the set of
+ * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator
+ * identifies the valid clock group union data member.
+ */
+ union ALT_CLK_GROUP_RAW_CFG_u
+ {
+ /*! Clock group configuration for Main PLL group. */
+ union
+ {
+ ALT_CLKMGR_MAINPLL_t fld; /*!< Field access. */
+ ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */
+ } mainpllgrp;
+
+ /*! Clock group configuration for Peripheral PLL group. */
+ union
+ {
+ ALT_CLKMGR_PERPLL_t fld; /*!< Field access. */
+ ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */
+ } perpllgrp;
+
+ /*! Clock group configuration for SDRAM PLL group. */
+ union
+ {
+ ALT_CLKMGR_SDRPLL_t fld; /*!< Field access. */
+ ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */
+ } sdrpllgrp;
+
+ } clkgrp;
+} ALT_CLK_GROUP_RAW_CFG_t;
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __ALT_CLK_GRP_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h
new file mode 100644
index 0000000000..d6d96544f7
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_manager.h
@@ -0,0 +1,1434 @@
+/*! \file
+ * Contains definitions for the Altera Hardware Libraries Clock Manager
+ * Application Programming Interface
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __ALT_CLK_MGR_H__
+#define __ALT_CLK_MGR_H__
+
+#include "hwlib.h"
+#include "alt_clock_group.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*! \addtogroup CLK_MGR The Clock Manager API
+ *
+ * This module defines the Clock Manager API for accessing, configuring, and
+ * controlling the HPS clock resources.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition is an opaque type definition for clock frequency values
+ * in Hz.
+ */
+typedef uint32_t alt_freq_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the names of the clock and PLL resources
+ * managed by the Clock Manager.
+ */
+typedef enum ALT_CLK_e
+{
+ /* Clock Input Pins */
+ ALT_CLK_IN_PIN_OSC1,
+ /*!< \b OSC_CLK_1_HPS
+ * External oscillator input:
+ * * Input Pin
+ * * Clock source to Main PLL
+ * * Clock source to SDRAM PLL
+ * and Peripheral PLL if selected via
+ * register write
+ * * Clock source for clock in safe mode
+ */
+
+ ALT_CLK_IN_PIN_OSC2,
+ /*!< \b OSC_CLK_2_HPS
+ * External Oscillator input:
+ * * Input Pin
+ * * Optional clock source to SDRAM PLL
+ * and Peripheral PLL if selected
+ * * Typically used for Ethernet
+ * reference clock
+ */
+
+
+ /* FPGA Clock Sources External to HPS */
+ ALT_CLK_F2H_PERIPH_REF,
+ /*<! Alternate clock source from FPGA
+ * for HPS Peripheral PLL. */
+
+ ALT_CLK_F2H_SDRAM_REF,
+ /*<! Alternate clock source from FPGA
+ * for HPS SDRAM PLL. */
+
+
+ /* Other Clock Sources External to HPS */
+ ALT_CLK_IN_PIN_JTAG,
+ /*!< \b JTAG_TCK_HPS
+ * * Input Pin
+ * * External HPS JTAG clock input.
+ */
+
+ ALT_CLK_IN_PIN_ULPI0,
+ /*!< \b ULPI0_CLK
+ * ULPI Clock provided by external USB0
+ * PHY
+ * * Input Pin
+ */
+
+ ALT_CLK_IN_PIN_ULPI1,
+ /*!< \b ULPI1_CLK
+ * ULPI Clock provided by external USB1
+ * PHY
+ * * Input Pin
+ */
+
+ ALT_CLK_IN_PIN_EMAC0_RX,
+ /*!< \b EMAC0:RX_CLK
+ * Rx Reference Clock for EMAC0
+ * * Input Pin
+ */
+
+ ALT_CLK_IN_PIN_EMAC1_RX,
+ /*!< \b EMAC1:RX_CLK
+ * Rx Reference Clock for EMAC1
+ * * Input Pin
+ */
+
+
+ /* PLLs */
+ ALT_CLK_MAIN_PLL,
+ /*!< \b main_pll_ref_clkin
+ * Main PLL input reference clock,
+ * used to designate the Main PLL in
+ * PLL clock selections.
+ */
+
+ ALT_CLK_PERIPHERAL_PLL,
+ /*!< \b periph_pll_ref_clkin
+ * Peripheral PLL input reference
+ * clock, used to designate the
+ * Peripheral PLL in PLL clock
+ * selections.
+ */
+
+ ALT_CLK_SDRAM_PLL,
+ /*!< \b sdram_pll_ref_clkin
+ * SDRAM PLL input reference clock,
+ * used to designate the SDRAM PLL in
+ * PLL clock selections.
+ */
+
+ /* OSC1 Clock Group - The OSC1 clock group contains those clocks which are derived
+ * directly from the osc_clk_1_HPS pin */
+ ALT_CLK_OSC1,
+ /*!< \b osc1_clk
+ * OSC1 Clock Group - The
+ * OSC1 clock group contains
+ * those clocks which are
+ * derived directly from the
+ * osc_clk_1_HPS pin.
+ * * alias for ALT_CLK_IN_PIN_OSC1
+ */
+
+ /* Main Clock Group - The following clocks are derived from the Main PLL. */
+ ALT_CLK_MAIN_PLL_C0,
+ /*!< \b Main PLL C0 Output */
+
+ ALT_CLK_MAIN_PLL_C1,
+ /*!< \b Main PLL C1 Output */
+
+ ALT_CLK_MAIN_PLL_C2,
+ /*!< \b Main PLL C2 Output */
+
+ ALT_CLK_MAIN_PLL_C3,
+ /*!< \b Main PLL C3 Output */
+
+ ALT_CLK_MAIN_PLL_C4,
+ /*!< \b Main PLL C4 Output */
+
+ ALT_CLK_MAIN_PLL_C5,
+ /*!< \b Main PLL C5 Output */
+
+ ALT_CLK_MPU,
+ /*!< \b mpu_clk
+ * Main PLL C0 Output. Clock for MPU
+ * subsystem, including CPU0 and CPU1.
+ * * Alias for \e ALT_CLK_MAIN_PLL_C0
+ */
+
+ ALT_CLK_MPU_L2_RAM,
+ /*!< \b mpu_l2_ram_clk
+ * Clock for MPU level 2 (L2) RAM
+ */
+
+ ALT_CLK_MPU_PERIPH,
+ /*!< \b mpu_periph_clk
+ * Clock for MPU snoop control unit
+ * (SCU) peripherals, such as the
+ * general interrupt controller (GIC)
+ */
+
+ ALT_CLK_L3_MAIN,
+ /*!< \b main_clk
+ * Main PLL C1 Output
+ * * Alias for \e ALT_CLK_MAIN_PLL_C1
+ */
+
+ ALT_CLK_L3_MP,
+ /*!< \b l3_mp_clk
+ * Clock for L3 Master Peripheral Switch
+ */
+
+ ALT_CLK_L3_SP,
+ /*!< \b l3_sp_clk
+ * Clock for L3 Slave Peripheral Switch
+ */
+
+ ALT_CLK_L4_MAIN,
+ /*!< \b l4_main_clk
+ * Clock for L4 main bus
+ * * Clock for DMA
+ * * Clock for SPI masters
+ */
+
+ ALT_CLK_L4_MP,
+ /*!< \b l4_mp_clk
+ * Clock for L4 master peripherals (MP) bus
+ */
+
+ ALT_CLK_L4_SP,
+ /*!< \b l4_sp_clk
+ * Clock for L4 slave peripherals (SP) bus
+ */
+
+ ALT_CLK_DBG_BASE,
+ /*!< \b dbg_base_clk
+ * Main PLL C2 Output
+ * * Alias for \e ALT_CLK_MAIN_PLL_C2
+ */
+
+ ALT_CLK_DBG_AT,
+ /*!< \b dbg_at_clk
+ * Clock for CoreSight debug Advanced
+ * Microcontroller Bus Architecture
+ * (AMBA) Trace Bus (ATB)
+ */
+
+ ALT_CLK_DBG_TRACE,
+ /*!< \b dbg_trace_clk
+ * Clock for CoreSight debug Trace
+ * Port Interface Unit (TPIU)
+ */
+
+ ALT_CLK_DBG_TIMER,
+ /*!< \b dbg_timer_clk
+ * Clock for the trace timestamp
+ * generator
+ */
+
+ ALT_CLK_DBG,
+ /*!< \b dbg_clk
+ * Clock for Debug Access Port (DAP)
+ * and debug Advanced Peripheral Bus
+ * (APB)
+ */
+
+ ALT_CLK_MAIN_QSPI,
+ /*!< \b main_qspi_clk
+ * Main PLL C3 Output. Quad SPI flash
+ * internal logic clock.
+ * * Alias for \e ALT_CLK_MAIN_PLL_C3
+ */
+
+ ALT_CLK_MAIN_NAND_SDMMC,
+ /*!< \b main_nand_sdmmc_clk
+ * Main PLL C4 Output. Input clock to
+ * flash controller clocks block.
+ * * Alias for \e ALT_CLK_MAIN_PLL_C4
+ */
+
+ ALT_CLK_CFG,
+ /*!< \b cfg_clk
+ * FPGA manager configuration clock.
+ */
+
+ ALT_CLK_H2F_USER0,
+ /*!< \b h2f_user0_clock
+ * Clock to FPGA fabric
+ */
+
+
+ /* Peripherals Clock Group - The following clocks are derived from the Peripheral PLL */
+ ALT_CLK_PERIPHERAL_PLL_C0,
+ /*!< \b Peripheral PLL C0 Output */
+
+ ALT_CLK_PERIPHERAL_PLL_C1,
+ /*!< \b Peripheral PLL C1 Output */
+
+ ALT_CLK_PERIPHERAL_PLL_C2,
+ /*!< \b Peripheral PLL C2 Output */
+
+ ALT_CLK_PERIPHERAL_PLL_C3,
+ /*!< \b Peripheral PLL C3 Output */
+
+ ALT_CLK_PERIPHERAL_PLL_C4,
+ /*!< \b Peripheral PLL C4 Output */
+
+ ALT_CLK_PERIPHERAL_PLL_C5,
+ /*!< \b Peripheral PLL C5 Output */
+
+ ALT_CLK_USB_MP,
+ /*!< \b usb_mp_clk
+ * Clock for USB
+ */
+
+ ALT_CLK_SPI_M,
+ /*!< \b spi_m_clk
+ * Clock for L4 SPI master bus
+ */
+
+ ALT_CLK_QSPI,
+ /*!< \b qspi_clk
+ * Clock for Quad SPI
+ */
+
+ ALT_CLK_NAND_X,
+ /*!< \b nand_x_clk
+ * NAND flash controller master and
+ * slave clock
+ */
+
+ ALT_CLK_NAND,
+ /*!< \b nand_clk
+ * Main clock for NAND flash
+ * controller
+ */
+
+ ALT_CLK_SDMMC,
+ /*!< \b sdmmc_clk
+ * Clock for SD/MMC logic input clock
+ */
+
+ ALT_CLK_EMAC0,
+ /*!< \b emac0_clk
+ * EMAC 0 clock - Peripheral PLL C0
+ * Output
+ * * Alias for \e ALT_CLK_PERIPHERAL_PLL_C0
+ */
+
+ ALT_CLK_EMAC1,
+ /*!< \b emac1_clk
+ * EMAC 1 clock - Peripheral PLL C1
+ * Output
+ * * Alias for \e ALT_CLK_PERIPHERAL_PLL_C1
+ */
+
+ ALT_CLK_CAN0,
+ /*!< \b can0_clk
+ * Controller area network (CAN)
+ * controller 0 clock
+ */
+
+ ALT_CLK_CAN1,
+ /*!< \b can1_clk
+ * Controller area network (CAN)
+ * controller 1 clock
+ */
+
+ ALT_CLK_GPIO_DB,
+ /*!< \b gpio_db_clk
+ * Debounce clock for GPIO0, GPIO1,
+ * and GPIO2
+ */
+
+ ALT_CLK_H2F_USER1,
+ /*!< \b h2f_user1_clock
+ * Clock to FPGA fabric - Peripheral
+ * PLL C5 Output
+ * * Alias for \e ALT_CLK_PERIPHERAL_PLL_C5
+ */
+
+
+ /* SDRAM Clock Group - The following clocks are derived from the SDRAM PLL */
+ ALT_CLK_SDRAM_PLL_C0,
+ /*!< \b SDRAM PLL C0 Output */
+
+ ALT_CLK_SDRAM_PLL_C1,
+ /*!< \b SDRAM PLL C1 Output */
+
+ ALT_CLK_SDRAM_PLL_C2,
+ /*!< \b SDRAM PLL C2 Output */
+
+ ALT_CLK_SDRAM_PLL_C3,
+ /*!< \b SDRAM PLL C3 Output */
+
+ ALT_CLK_SDRAM_PLL_C4,
+ /*!< \b SDRAM PLL C4 Output */
+
+ ALT_CLK_SDRAM_PLL_C5,
+ /*!< \b SDRAM PLL C5 Output */
+
+ ALT_CLK_DDR_DQS,
+ /*!< \b ddr_dqs_clk
+ * Clock for MPFE, single-port
+ * controller, CSR access, and PHY -
+ * SDRAM PLL C0 Output
+ * * Alias for \e ALT_CLK_SDRAM_PLL_C0
+ */
+
+ ALT_CLK_DDR_2X_DQS,
+ /*!< \b ddr_2x_dqs_clk
+ * Clock for PHY - SDRAM PLL C1 Output
+ * * Alias for \e ALT_CLK_SDRAM_PLL_C1
+ */
+
+ ALT_CLK_DDR_DQ,
+ /*!< \b ddr_dq_clk
+ * Clock for PHY - SDRAM PLL C2 Output
+ * * Alias for \e ALT_CLK_SDRAM_PLL_C2
+ */
+
+ ALT_CLK_H2F_USER2,
+ /*!< \b h2f_user2_clock
+ * Clock to FPGA fabric - SDRAM PLL C5
+ * Output
+ * * Alias for \e ALT_CLK_SDRAM_PLL_C5
+ */
+
+ /* Clock Output Pins */
+ ALT_CLK_OUT_PIN_EMAC0_TX,
+ /*!< \b EMAC0:TX_CLK
+ * Tx Reference Clock for EMAC0
+ * * Output Pin
+ */
+
+ ALT_CLK_OUT_PIN_EMAC1_TX,
+ /*!< \b EMAC1:TX_CLK
+ * Tx Reference Clock for EMAC1
+ * * Output Pin
+ */
+
+ ALT_CLK_OUT_PIN_SDMMC,
+ /*!< \b SDMMC:CLK
+ * SD/MMC Card Clock
+ * * Output Pin
+ */
+
+ ALT_CLK_OUT_PIN_I2C0_SCL,
+ /*!< \b I2C0:SCL
+ * I2C Clock for I2C0
+ * * Output Pin
+ */
+
+ ALT_CLK_OUT_PIN_I2C1_SCL,
+ /*!< \b I2C1:SCL
+ * I2C Clock for I2C1
+ * * Output Pin
+ */
+
+ ALT_CLK_OUT_PIN_I2C2_SCL,
+ /*!< \b I2C2:SCL
+ * I2C Clock for I2C2/2 wire
+ * * Output Pin
+ */
+
+ ALT_CLK_OUT_PIN_I2C3_SCL,
+ /*!< \b I2C3:SCL
+ * I2C Clock for I2C1/2 wire
+ * * Output Pin
+ */
+
+ ALT_CLK_OUT_PIN_SPIM0,
+ /*!< \b SPIM0:CLK
+ * SPI Clock
+ * * Output Pin
+ */
+
+ ALT_CLK_OUT_PIN_SPIM1,
+ /*!< \b SPIM1:CLK
+ * SPI Clock
+ * * Output Pin
+ */
+
+ ALT_CLK_OUT_PIN_QSPI,
+ /*!< \b QSPI:CLK
+ * QSPI Flash Clock
+ * * Output Pin
+ */
+
+ ALT_CLK_UNKNOWN
+} ALT_CLK_t;
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_STATUS Clock Manager Status
+ *
+ * This functional group provides status information on various aspects and
+ * properties of the Clock Manager state.
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * This type definition defines the lock condition status codes for each of the
+ * PLLs. If the PLL lock status condition is enabled (See: alt_clk_irq_enable())
+ * then it contributes to the overall \b clkmgr_IRQ signal assertion state.
+ */
+typedef enum ALT_CLK_PLL_LOCK_STATUS_e
+{
+ ALT_MAIN_PLL_LOCK_ACHV = 0x00000001, /*!< This condition is set if the Main
+ * PLL has achieved lock at least once
+ * since this condition was last
+ * cleared.
+ */
+ ALT_PERIPH_PLL_LOCK_ACHV = 0x00000002, /*!< This condition is set if the Peripheral
+ * PLL has achieved lock at least once
+ * since this condition was last
+ * cleared.
+ */
+ ALT_SDR_PLL_LOCK_ACHV = 0x00000004, /*!< This condition is set if the SDRAM
+ * PLL has achieved lock at least once
+ * since this condition was last
+ * cleared.
+ */
+ ALT_MAIN_PLL_LOCK_LOST = 0x00000008, /*!< This condition is set if the Main
+ * PLL has lost lock at least once
+ * since this condition was last
+ * cleared.
+ */
+ ALT_PERIPH_PLL_LOCK_LOST = 0x00000010, /*!< This condition is set if the Peripheral
+ * PLL has lost lock at least once
+ * since this condition was last
+ * cleared.
+ */
+ ALT_SDR_PLL_LOCK_LOST = 0x00000020 /*!< This condition is set if the SDRAM
+ * PLL has lost lock at least once
+ * since this condition was last
+ * cleared.
+ */
+} ALT_CLK_PLL_LOCK_STATUS_t;
+
+/******************************************************************************/
+/*!
+ * Clear the selected PLL lock status conditions.
+ *
+ * This function clears assertions of one or more of the PLL lock status
+ * conditions.
+ *
+ * NOTE: This function is used to clear \b clkmgr_IRQ interrupt signal source
+ * assertion conditions.
+ *
+ * \param lock_stat_mask
+ * Specifies the PLL lock status conditions to clear. \e lock_stat_mask
+ * is a mask of logically OR'ed \ref ALT_CLK_PLL_LOCK_STATUS_t
+ * values designating the PLL lock conditions to clear.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an
+ * unknown condition value.
+ */
+ALT_STATUS_CODE alt_clk_lock_status_clear(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
+
+/******************************************************************************/
+/*!
+ * Returns the PLL lock status condition values.
+ *
+ * This function returns the value of the PLL lock status conditions.
+ *
+ * \returns The current values of the PLL lock status conditions as defined by
+ * the \ref ALT_CLK_PLL_LOCK_STATUS_t mask bits. If the corresponding bit is set
+ * then the condition is asserted.
+ */
+uint32_t alt_clk_lock_status_get(void);
+
+/******************************************************************************/
+/*!
+ * Returns ALT_E_TRUE if the designated PLL is currently locked and ALT_E_FALSE
+ * otherwise.
+ *
+ * \param pll
+ * The PLL to return the lock status of.
+ *
+ * \retval ALT_E_TRUE The specified PLL is currently locked.
+ * \retval ALT_E_FALSE The specified PLL is currently not locked.
+ * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock
+ * value.
+ * \internal
+ * NOTE: This function uses the
+ * * \b hps::clkmgr::inter::mainplllocked
+ * * \b hps::clkmgr::inter::perplllocked,
+ * * \b hps::clkmgr::inter::sdrplllocked
+ *
+ * bits to determine if the PLL is locked or not.
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_clk_pll_is_locked(ALT_CLK_t pll);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_SAFE_MODE Safe Mode Options
+ *
+ * When safe mode is enabled, clocks in the HPS are directly generated from the
+ * \b osc1_clk clock. Safe mode is enabled by the assertion of a safe mode
+ * request from the reset manager or by a cold reset. Assertion of the safe mode
+ * request from the reset manager sets the safe mode bit in the clock manager
+ * control register. No other control register bits are affected by the safe
+ * mode request from the reset manager.
+ *
+ * While in safe mode, clock manager register settings which control clock
+ * behavior are not changed. However, the output of the registers which control
+ * the clock manager state are forced to the safe mode values such that the
+ * following conditions occur:
+ * * All PLLs are bypassed to the \b osc1_clk clock, including their counters.
+ * * Clock dividers select their default reset values.
+ * * The flash controllers source clock selections are set to the peripheral
+ * PLL.
+ * * All clocks are enabled.
+ * * Safe mode is optionally applied to debug clocks.
+ *
+ * A write by software is the only way to clear the safe mode bit. All registers
+ * and clocks need to be configured correctly and all software-managed clocks
+ * need to be gated off before clearing safe mode. Software can then gate clocks
+ * on as required.
+ *
+ * On cold reset, all clocks are put in safe mode.
+ *
+ * On warm reset, safe mode is optionally and independently applied to debug
+ * clocks and normal (i.e.non-debug) clocks based on clock manager register
+ * settings. The default response for warm reset is to put all clocks in safe
+ * mode.
+ *
+ * The APIs in this group provide control of the Clock Manager safe mode warm
+ * reset response behavior.
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the safe mode clock domains under control of
+ * the Clock Manager.
+ */
+typedef enum ALT_CLK_SAFE_DOMAIN_e
+{
+ /*!
+ * This enumeration literal specifies the normal safe mode domain. The
+ * normal domain consists of all clocks except debug clocks.
+ */
+ ALT_CLK_DOMAIN_NORMAL,
+ /*!
+ * This enumeration literal specifies the debug safe mode domain. The debug
+ * domain consists of all debug clocks.
+ */
+ ALT_CLK_DOMAIN_DEBUG
+} ALT_CLK_SAFE_DOMAIN_t;
+
+/******************************************************************************/
+/*!
+ * Clear the safe mode status of the Clock Manager following a reset.
+ *
+ * NOTE: Safe mode should only be cleared once clocks have been correctly
+ * configured.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_safe_mode_clear(void);
+
+/******************************************************************************/
+/*!
+ * Return whether the specified safe mode clock domain is in safe mode or not.
+ *
+ * \param clk_domain
+ * The safe mode clock domain to check whether in safe mode or not.
+ *
+ * \retval TRUE The safe mode clock domain is in safe mode.
+ * \retval FALSE The safe mode clock domain is not in safe mode.
+ */
+bool alt_clk_is_in_safe_mode(ALT_CLK_SAFE_DOMAIN_t clk_domain);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_BYPASS PLL Bypass Control
+ *
+ * When a PLL is in bypass, the PLL clock logic is kept in reset. In this
+ * manner, the PLL clock can be free running while it stabilizes and achieves
+ * lock. The bypass logic isolates PLL configuration registers from the clock
+ * while changes are made to the PLL settings.
+ *
+ * The bypass controls are used by software to change the source clock input
+ * reference (for Peripheral and SDRAM PLLs) and is recommended when changing
+ * settings that may affect the ability of the VCO to maintain lock. When a PLL
+ * is taken in or out of bypass the PLL output clocks will pause momentarily
+ * while the clocks are in transition, There will be no glitches or clocks
+ * shorter than the either the old or the new clock period.
+ *
+ * In summary, the PLL bypass controls permit:
+ * * Each PLL to be individually bypassed.
+ * * Bypass of all PLL clock outputs to \b osc1_clk or alternatively the PLLs
+ * reference clock input source reference clock selection.
+ * * Isolation of a the PLL VCO frequency registers (multiplier and divider),
+ phase shift registers (negative phase) , and post scale counters.
+ * * Glitch free clock transitions.
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Disable bypass mode for the specified PLL. This operation takes the PLL out
+ * of bypass mode.
+ *
+ * \param pll
+ * The PLL to take out of bypass mode.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL clock
+ * value.
+ */
+ALT_STATUS_CODE alt_clk_pll_bypass_disable(ALT_CLK_t pll);
+
+/******************************************************************************/
+/*!
+ * Enable bypass mode for the specified PLL.
+ *
+ * \param pll
+ * The PLL to put into bypass mode.
+ *
+ * \param use_input_mux
+ * If TRUE then use the PLLs reference clock input source selection
+ * to directly drive the bypass clock. If FALSE then use bypass
+ * clock directly driven by the \b osc1_clk.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The \e pll argument specified a non PLL
+ * clock value.
+ * \retval ALT_E_INV_OPTION TRUE is an invalid option for
+ * \e use_input_mux with the \e pll selection.
+ */
+ALT_STATUS_CODE alt_clk_pll_bypass_enable(ALT_CLK_t pll,
+ bool use_input_mux);
+
+/******************************************************************************/
+/*!
+ * Return whether the specified PLL is in bypass or not.
+ *
+ * \internal
+ * This function must also test the \b clkmgr.ctrl.safemode bit in
+ * addition to the PLLs bypass bit to tell whether the bypass mode is
+ * effect or not.
+ * \endinternal
+ *
+ * \param pll
+ * The PLL to check whether in bypass mode or not.
+ *
+ * \retval ALT_E_TRUE The PLL is in bypass mode.
+ * \retval ALT_E_FALSE The PLL is not in bypass mode.
+ * \retval ALT_E_BAD_ARG The \e pll argument designates a non PLL clock
+ * value.
+ */
+ALT_STATUS_CODE alt_clk_pll_is_bypassed(ALT_CLK_t pll);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_GATE Clock Gating Control
+ *
+ * This functional group provides gating control of selected clock signals.
+ *
+ * When a clock is enabled, then its clock signal propogates to its respective
+ * clocked IP block(s). When a clock is disabled, then its clock signal is
+ * prevented from propogating to its respective clocked IP block(s).
+ *
+ * The following clocks may be gated:
+ *
+ * * Main PLL Group
+ * - l4_main_clk
+ * - l3_mp_clk
+ * - l4_mp_clk
+ * - l4_sp_clk
+ * - dbg_at_clk
+ * - dbg_clk
+ * - dbg_trace_clk
+ * - dbg_timer_clk
+ * - cfg_clk
+ * - s2f_user0_clk
+ *
+ * * SDRAM PLL Group
+ * - ddr_dqs_clk
+ * - ddr_2x_clk
+ * - ddr_dq_clk
+ * - s2f_user2_clk
+ *
+ * * Peripheral PLL Group
+ * - emac0_clk
+ * - emac1_clk
+ * - usb_mp_clk
+ * - spi_m_clk
+ * - can0_clk
+ * - can1_clk
+ * - gpio_db_clk
+ * - s2f_user1_clk
+ * - sdmmc_clk
+ * - nand_clk
+ * - nand_x_clk
+ * - qspi_clk
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Disable the specified clock. Once the clock is disabled, its clock signal does
+ * not propogate to its clocked elements.
+ *
+ * \param clk
+ * The clock to disable.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock
+ * value.
+ */
+ALT_STATUS_CODE alt_clk_clock_disable(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * Enable the specified clock. Once the clock is enabled, its clock signal
+ * propogates to its elements.
+ *
+ * \param clk
+ * The clock to enable.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock
+ * value.
+ */
+ALT_STATUS_CODE alt_clk_clock_enable(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * Return whether the specified clock is enabled or not.
+ *
+ * \param clk
+ * The clock to check whether enabled or not.
+ *
+ * \retval ALT_E_TRUE The clock is enabled.
+ * \retval ALT_E_FALSE The clock is not enabled.
+ * \retval ALT_E_BAD_ARG The \e clk argument designates a non gated clock
+ * value.
+ */
+ALT_STATUS_CODE alt_clk_is_enabled(ALT_CLK_t clk);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_CLK_SEL Clock Source Selection
+ *
+ * This API group provide access and control to the input reference clock source
+ * selection for a clock or PLL.
+ *
+ * \internal
+ * These are the clocks that have software configurable input reference clock
+ * source selection available. Each clock below is listed with its valid
+ * input reference clock source selections.
+ *
+ * + Valid reference clock input selections for \b sdram_pll_ref_clkin
+ * - osc_clk_1
+ * - osc_clk_2
+ * - f2h_sdram_ref_clk
+ *
+ * + Valid reference clock input selections for \b periph_pll_ref_clkin
+ * - osc_clk_1
+ * - osc_clk_2,
+ * - f2h_periph_ref_clk
+ *
+ * + Valid reference clock input selections for \b l4_mp_clk
+ * - periph_base_clk
+ * - main_clk
+ *
+ * + Valid reference clock input selections for \b l4_sp_clk
+ * - periph_base_clk
+ * - main_clk
+ *
+ * + Valid reference clock input selections for \b sdmmc_clk
+ * - f2h_periph_ref_clk
+ * - main_nand_sdmmc_clk
+ * - periph_nand_sdmmc_clk
+ *
+ * + Valid reference clock input selections for \b nand_clk
+ * - f2h_periph_ref_clk
+ * - main_nand_sdmmc_clk
+ * - periph_nand_sdmmc_clk
+ *
+ * + Valid reference clock input selections for \b qspi_clk
+ * - f2h_periph_ref_clk
+ * - main_qspi_clk
+ * - periph_qspi_clk
+ *
+ * \endinternal
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Get the input reference clock source selection value for the specified clock
+ * or PLL.
+ *
+ * NOTE: This function returns a clock value even though \e clk may specify a
+ * clock that does not have a selectable input reference clock source. In
+ * this case, the clock value returned is the static clock source for the
+ * specified clock. For example calling alt_clk_source_get() with \e clk
+ * set to \ref ALT_CLK_MAIN_PLL will return \ref ALT_CLK_OSC1.
+ *
+ * \param clk
+ * The clock or PLL to retrieve the input reference clock source
+ * selection value for.
+ *
+ * \returns The clock's currently selected input reference clock source.
+ */
+ALT_CLK_t alt_clk_source_get(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * Set the specified clock's input reference clock source selection.
+ *
+ * \param clk
+ * The clock or PLL to set the input reference clock source
+ * selection for.
+ *
+ * \param ref_clk
+ * The input reference clock source selection value.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The \e clk argument designates a clock that
+ * does not have a selectable input reference
+ * clock source.
+ * \retval ALT_E_INV_OPTION The \e ref_clk argument designates a clock that
+ * is an invalid reference clock source for the
+ * specified clock.
+ */
+ALT_STATUS_CODE alt_clk_source_set(ALT_CLK_t clk,
+ ALT_CLK_t ref_clk);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_FREQ Clock Frequency Control
+ *
+ * This API group provides access and control of the output frequency of a clock
+ * or PLL.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Set the external clock frequency value.
+ *
+ * The function is used to specify the frequency of the external clock source as
+ * a measure of Hz. The supplied frequency should be within the Fmin and Fmax
+ * values allowed for the external clock source.
+ *
+ * \param clk
+ * The external clock source. Valid external clocks are
+ * * \e ALT_CLK_OSC1
+ * * \e ALT_CLK_OSC2
+ * * \e ALT_CLK_F2H_PERIPH_REF
+ * * \e ALT_CLK_F2H_SDRAM_REF
+ *
+ * \param freq
+ * The frequency of the external clock in Hz.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG A bad argument value was passed. Either the \e clk
+ * argument is bad or not a valid external clock
+ * source
+ * \retval ALT_E_ARG_RANGE The frequency value violates the range constraints
+ * for the specified clock.
+
+ */
+ALT_STATUS_CODE alt_clk_ext_clk_freq_set(ALT_CLK_t clk,
+ alt_freq_t freq);
+
+/******************************************************************************/
+/*!
+ * Get the external clock frequency value.
+ *
+ * This function returns the frequency of the external clock source as
+ * a measure of Hz.
+ *
+ * \param clk
+ * The external clock source. Valid external clocks are
+ * * \e ALT_CLK_OSC1
+ * * \e ALT_CLK_OSC2
+ * * \e ALT_CLK_F2H_PERIPH_REF
+ * * \e ALT_CLK_F2H_SDRAM_REF
+ *
+ * \retval freq
+ * The frequency of the external clock in Hz.
+ *
+ */
+alt_freq_t alt_clk_ext_clk_freq_get(ALT_CLK_t clk);
+
+/******************************************************************************/
+/*!
+ * This type definition defines a structure to contain the generalized
+ * configuration settings for a PLL.
+ */
+typedef struct ALT_CLK_PLL_CFG_s
+{
+ ALT_CLK_t ref_clk; /*!< PLL Reference Clock Source */
+ uint32_t mult; /*!< VCO Frequency Configuration -
+ * Multiplier (M) value, range 1 to 4096
+ */
+ uint32_t div; /*!< VCO Frequency Configuration -
+ * Divider (N) value, range 1 to 64
+ */
+ uint32_t cntrs[6]; /*!< Post-Scale Counters (C0 - C5) -
+ * range 1 to 512
+ */
+ uint32_t pshift[6]; /*!< Phase Shift - 1/8 (45 degrees) of
+ * negative phase shift per increment,
+ * range 0 to 4096
+ */
+} ALT_CLK_PLL_CFG_t;
+
+/******************************************************************************/
+/*!
+ * Get the current PLL configuration.
+ *
+ * \param pll
+ * The PLL to get the configuration from.
+ *
+ * \param pll_cfg
+ * [out] Pointer to an output parameter variable for the returned
+ * PLL configuration.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_cfg_get(ALT_CLK_t pll,
+ ALT_CLK_PLL_CFG_t* pll_cfg);
+
+/******************************************************************************/
+/*!
+ * Set the PLL configuration using the configuration parameters specified in
+ * \e pll_cfg.
+ *
+ * \param pll
+ * The PLL to set the configuration for.
+ *
+ * \param pll_cfg
+ * Pointer to a ALT_CLK_PLL_CFG_t structure specifying the desired
+ * PLL configuration.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_cfg_set(ALT_CLK_t pll,
+ const ALT_CLK_PLL_CFG_t* pll_cfg);
+
+/******************************************************************************/
+/*!
+ * Get the current PLL VCO frequency configuration.
+ *
+ * \param pll
+ * The PLL to get the VCO frequency configuration for.
+ *
+ * \param mult
+ * [out] Pointer to an output variable for the returned
+ * configured PLL VCO multiplier (M) value.
+ *
+ * \param div
+ * [out] Pointer to an output variable for the returned
+ * configured PLL VCO divider (N) value.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_vco_cfg_get(ALT_CLK_t pll,
+ uint32_t* mult,
+ uint32_t* div);
+
+/******************************************************************************/
+/*!
+ * Set the PLL VCO frequency configuration using the supplied multiplier and
+ * divider arguments.
+ *
+ * \param pll
+ * The PLL to set the VCO frequency configuration for.
+ *
+ * \param mult
+ * The PLL VCO multiplier (M). Expected argument range 1 to 4096.
+ *
+ * \param div
+ * The PLL VCO divider (N). Expected argument range 1 to 64.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_clk_pll_vco_cfg_set(ALT_CLK_t pll,
+ uint32_t mult,
+ uint32_t div);
+
+/******************************************************************************/
+/*!
+ * Get the VCO frequency of the specified PLL.
+ *
+ * \param pll
+ * The PLL to retrieve the VCO frequency from.
+ *
+ * \param freq
+ * [out] Pointer to the an output parameter variable to return the
+ * PLL VCO frequency value. The frequency value is returned as a
+ * measures of Hz.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG A bad argument value was passed. Either
+ * the \e pll argument is invalid or a bad
+ * \e freq pointer value was passed.
+ */
+ALT_STATUS_CODE alt_clk_pll_vco_freq_get(ALT_CLK_t pll,
+ alt_freq_t* freq);
+
+/******************************************************************************/
+/*!
+ * Get the PLL frequency guard band value.
+ *
+ * \param pll
+ * The PLL from which to return the current guard band value.
+ *
+ * \returns The current guard band range in effect for the PLL.
+ */
+uint32_t alt_clk_pll_guard_band_get(ALT_CLK_t pll);
+
+/******************************************************************************/
+/*!
+ * Set the PLL frequency guard band value.
+ *
+ * Once a PLL has achieved lock, any changes to the PLL VCO frequency that are
+ * within a specific guard band range (default value 20%) of the reference
+ * period should not cause the PLL to lose lock.
+ *
+ * Programmatic changes to the PLL frequency within this guard band range are
+ * permitted to be made without the risk of breaking lock during the transition
+ * to the new frequency.
+ *
+ * The clk_mgr_pll_guard_band_set() function changes the guard band from its
+ * current value to permit a more lenient or stringent policy to be in effect in
+ * the implementation of the functions configuring PLL VCO frequency. The
+ * rationale for changing the default guard band value might be to accommodate
+ * unexpected environmental conditions (noise, temperature, and other
+ * instability factors) that may affect the PLLs ability to maintain lock during
+ * a frequency change.
+ *
+ * \param pll
+ * The PLL to set the guard band value for.
+ *
+ * \param guard_band
+ * The guard band value. Value should be 0 <= \e guard_band <= 100.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_ARG_RANGE The guard band value violates its range constraint.
+ */
+ALT_STATUS_CODE alt_clk_pll_guard_band_set(ALT_CLK_t pll,
+ uint32_t guard_band);
+
+/******************************************************************************/
+/*!
+ * Get the configured divider value for the specified clock.
+ *
+ * This function is used to get the configured values of both internal and
+ * external clock dividers. The internal divider (PLL counters C0-C5) values
+ * are retrieved by specifying the clock name that is the divider output
+ * (e.g. ALT_CLK_MPU is used to get the Main PLL C0 counter value). \n
+ * It returns the actual divider value, not the encoded bitfield stored
+ * in the register, due to the variety of different encodings.
+ *
+ * \param clk
+ * The clock divider to get the value from.
+ *
+ * \param div
+ * [out] Pointer to an output variable for the returned clock
+ * divider value.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG An invalid clock argument was specified or a
+ * clock that does not have a divider.
+ */
+ALT_STATUS_CODE alt_clk_divider_get(ALT_CLK_t clk,
+ uint32_t* div);
+
+/******************************************************************************/
+/*!
+ * Set the divider value for the specified clock.
+ *
+ * This function is used to set the values of both internal and external clock
+ * dividers. The internal divider (PLL counters C0-C5) values are set by
+ * specifying the clock name that is the divider output (e.g. ALT_CLK_MPU is
+ * used to set the Main PLL C0 counter value).
+ *
+ * \param clk
+ * The clock divider to set the value for.
+ *
+ * \param div
+ * The clock divider value. NOTE: The valid range of clock divider
+ * values depends on the clock being configured. This is the
+ * real divisor ratio, not how the divisor is coded into the
+ * register, and is always one or greater.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG An invalid clock argument was specified or a
+ * clock that does not have a divider.
+ * \retval ALT_E_ARG_RANGE The divider value violates the range constraints
+ * for the clock divider.
+ */
+ALT_STATUS_CODE alt_clk_divider_set(ALT_CLK_t clk,
+ uint32_t div);
+
+/******************************************************************************/
+/*!
+ * Get the output frequency of the specified clock.
+ *
+ * \param clk
+ * The clock to retrieve the output frequency from.
+ *
+ * \param freq
+ * [out] Pointer to the an output parameter variable to return the
+ * clock output frequency value. The frequency value is returned as
+ * a measures of Hz.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG A bad argument value was passed. Either
+ * the \e clk argument is invalid or a bad
+ * \e freq pointer value was passed.
+ */
+ALT_STATUS_CODE alt_clk_freq_get(ALT_CLK_t clk,
+ alt_freq_t* freq);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_INT Clock Manager Interrupt Management
+ *
+ * The functions in this group provide management of interrupts originating from
+ * the Clock Manager.
+ *
+ * The following interrupt request (IRQ) signals are sourced from the Clock
+ * Manager:
+ *
+ * * \b clkmgr_IRQ - Clock Manager lock status interrupt output. The PLL lock
+ * status interrupt is the logical \e OR of six interrupt
+ * sources defining the loss or achievement of lock status for
+ * each PLL. The six PLL lock status conditions are:
+ * - Main PLL Achieved Lock
+ * - Main PLL Lost Lock
+ * - Peripheral PLL Achieved Lock
+ * - Peripheral PLL Lost Lock
+ * - SDRAM PLL Achieved Lock
+ * - SDRAM PLL Lost Lock
+ *
+ * They are enumeratated by the type \ref ALT_CLK_PLL_LOCK_STATUS_t.
+ *
+ * Each PLL lock condition may be individually disabled/enabled
+ * as a contributor to the determination of the \b clkmgr_IRQ
+ * assertion status.
+ *
+ * The alt_clk_lock_status_clear() function is used to clear
+ * the PLL lock conditions causing the \b clkmgr_IRQ
+ * assertion.
+ *
+ * * \b mpuwakeup_IRQ - MPU wakeup interrupt output. This interrupt notifies the
+ * MPU to "wake up" after a transition of the Main PLL into
+ * or out of bypass mode has been safely achieved. The need
+ * for the "wake up" notification is because the PLL clocks
+ * pause for a short number of clock cycles during bypass
+ * state transition. ARM recommeds that the CPUs are placed
+ * in standby if the clocks are ever paused.
+ *
+ * NOTE: \b mpuwakeup_IRQ appears to be an Altera private interrupt and may not
+ * be part of the public API although clearly it has important utility in
+ * implementing safe changes to PLL settings and transitions into and out
+ * of bypass mode.
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Disable the \b clkmgr_IRQ interrupt signal source lock status condition(s).
+ *
+ * This function disables one or more of the lock status conditions as
+ * contributors to the \b clkmgr_IRQ interrupt signal state.
+ *
+ * NOTE: A set bit for a PLL lock status condition in the mask value does not
+ * have the effect of enabling it as a contributor to the \b clkmgr_IRQ
+ * interrupt signal state. The function alt_clk_irq_enable is used to enable PLL
+ * lock status source condition(s).
+ *
+ * \param lock_stat_mask
+ * Specifies the PLL lock status conditions to disable as interrupt
+ * source contributors. \e lock_stat_mask is a mask of logically
+ * OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock
+ * conditions to disable.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an
+ * unknown condition value.
+ */
+ALT_STATUS_CODE alt_clk_irq_disable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
+
+/******************************************************************************/
+/*!
+ * Enable the \b clkmgr_IRQ interrupt signal source lock status condition(s).
+ *
+ * This function enables one or more of the lock status conditions as
+ * contributors to the \b clkmgr_IRQ interrupt signal state.
+ *
+ * NOTE: A cleared bit for any PLL lock status condition in the mask value does
+ * not have the effect of disabling it as a contributor to the \b clkmgr_IRQ
+ * interrupt signal state. The function alt_clk_irq_disable is used to disable
+ * PLL lock status source condition(s).
+ *
+ * \param lock_stat_mask
+ * Specifies the PLL lock status conditions to enable as interrupt
+ * source contributors. \e lock_stat_mask is a mask of logically
+ * OR'ed ALT_CLK_PLL_LOCK_STATUS_t values that designate the PLL lock
+ * conditions to enable.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_BAD_ARG The \e lock_stat_mask argument contains an
+ * unknown condition value.
+ */
+ALT_STATUS_CODE alt_clk_irq_enable(ALT_CLK_PLL_LOCK_STATUS_t lock_stat_mask);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup CLK_MGR_GROUP_CFG Clock Group Configuration
+ *
+ * This API provides the ability to safely set the configuration of a clock
+ * group with a single function call.
+ *
+ * A clock group is defined as set of clocks and signals generated from a common
+ * PLL VCO. The PLL and its derived clocks are treated as a single clock
+ * group. The clocks sourced directly or indirectly from the PLL may or may not
+ * have these features:
+ * * Clock Gates
+ * * Clock Dividers
+ * * Clock Source Selection Options
+ *
+ * The use case for application of the Clock Group Configuration functions is the
+ * ability to safely configure an entire clock group from a known good clock
+ * group configuration using the run-time function alt_clk_group_cfg_raw_set().
+ *
+ * A known good clock group configuration may be generated by one of the
+ * following methods:
+ *
+ * * As static design information generated by an ACDS clock configuration tool
+ * and passed to embedded software for dynamic loading.
+ *
+ * * By calling alt_clk_group_cfg_raw_get() at run-time from an SoC FPGA that has
+ * programmatically established a known good clock group configuration using
+ * the clock manager API configuration functions.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Get the raw configuration state of the designated clock group.
+ *
+ * This function is used to capture the configuration state of the specified
+ * clock group in a private (raw) data structure. The raw data structure may be
+ * saved and used later to restore the clock group configuration using
+ * alt_clk_group_cfg_raw_get().
+ *
+ * \param clk_group
+ * The clock group configuration to capture.
+ *
+ * \param clk_group_raw_cfg
+ * [out] A pointer to a private (raw) data structure to store the
+ * captured clock group configuration.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ */
+ALT_STATUS_CODE alt_clk_group_cfg_raw_get(ALT_CLK_GRP_t clk_group,
+ ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
+
+/******************************************************************************/
+/*!
+ * Set the clock group configuration.
+ *
+ * This function is used to safely set the configuration state of a clock
+ * group from a raw clock group configuration specification. The raw clock
+ * group configuration specification may be a configuration previously
+ * captured with alt_clk_group_cfg_raw_get() or a group clock configuration
+ * generated by an external utility.
+ *
+ * \param clk_group_raw_cfg
+ * A pointer to the specification to use in the configuration of
+ * the clock group.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ * \retval ALT_E_BAD_VERSION The clock group configuration specification is
+ * invalid for this device.
+ */
+ALT_STATUS_CODE alt_clk_group_cfg_raw_set(const ALT_CLK_GROUP_RAW_CFG_t* clk_group_raw_cfg);
+
+ALT_STATUS_CODE alt_clk_clkmgr_init(void);
+
+/*! @} */
+
+/*! @} */
+#ifdef __cplusplus
+}
+
+#endif /* __cplusplus */
+#endif /* __ALT_CLK_MGR_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h
new file mode 100644
index 0000000000..6be93fbd32
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_dma.h
@@ -0,0 +1,1007 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __ALT_DMA_H__
+#define __ALT_DMA_H__
+
+#include "hwlib.h"
+#include "alt_dma_common.h"
+#include "alt_dma_program.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*!
+ * \addtogroup ALT_DMA DMA Controller API
+ *
+ * This module defines the API for configuration and use of the general purpose
+ * DMA controller for the SoC. The DMA controller is an instance of the ARM
+ * Corelink DMA Controller (DMA-330).
+ *
+ * References:
+ * * ARM DDI 0424C, CoreLink DMA Controller DMA-330 Technical Reference
+ * Manual.
+ * * ARM DAI 0239A, Application Note 239 Example Programs for the CoreLink
+ * DMA Controller DMA-330.
+ * * Altera, Cyclone V Device Handbook Volume 3: Hard Processor System
+ * Technical Reference Manual, DMA Controller.
+ *
+ * @{
+ */
+
+/*!
+ * \addtogroup ALT_DMA_COMPILE DMA API Compile Options
+ *
+ * This API provides control over the compile time inclusion of selected
+ * modules. This can allow for a smaller resulting binary.
+ *
+ * @{
+ */
+
+#ifndef ALT_DMA_PERIPH_PROVISION_16550_SUPPORT
+#define ALT_DMA_PERIPH_PROVISION_16550_SUPPORT (1)
+#endif
+
+#ifndef ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT
+#define ALT_DMA_PERIPH_PROVISION_QSPI_SUPPORT (1)
+#endif
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup ALT_DMA_CSR DMA API for Configuration, Control, and Status
+ *
+ * This API provides functions for configuration, control, and status queries
+ * of the DMA controller.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the operational states that the DMA manager
+ * may have.
+ */
+typedef enum ALT_DMA_MANAGER_STATE_e
+{
+ ALT_DMA_MANAGER_STATE_STOPPED = 0, /*!< Stopped */
+ ALT_DMA_MANAGER_STATE_EXECUTING = 1, /*!< Executing */
+ ALT_DMA_MANAGER_STATE_CACHE_MISS = 2, /*!< Cache Miss */
+ ALT_DMA_MANAGER_STATE_UPDATING_PC = 3, /*!< Updating PC */
+ ALT_DMA_MANAGER_STATE_WFE = 4, /*!< Waiting for Event */
+ ALT_DMA_MANAGER_STATE_FAULTING = 15 /*!< Faulting */
+}
+ALT_DMA_MANAGER_STATE_t;
+
+/*!
+ * This type definition enumerates the operational states that a DMA channel
+ * may have.
+ */
+typedef enum ALT_DMA_CHANNEL_STATE_e
+{
+ ALT_DMA_CHANNEL_STATE_STOPPED = 0, /*!< Stopped */
+ ALT_DMA_CHANNEL_STATE_EXECUTING = 1, /*!< Executing */
+ ALT_DMA_CHANNEL_STATE_CACHE_MISS = 2, /*!< Cache Miss */
+ ALT_DMA_CHANNEL_STATE_UPDATING_PC = 3, /*!< Updating PC */
+ ALT_DMA_CHANNEL_STATE_WFE = 4, /*!< Waiting for Event */
+ ALT_DMA_CHANNEL_STATE_AT_BARRIER = 5, /*!< At Barrier */
+ ALT_DMA_CHANNEL_STATE_WFP = 7, /*!< Waiting for Peripheral */
+ ALT_DMA_CHANNEL_STATE_KILLING = 8, /*!< Killing */
+ ALT_DMA_CHANNEL_STATE_COMPLETING = 9, /*!< Completing */
+ ALT_DMA_CHANNEL_STATE_FAULTING_COMPLETING = 14, /*!< Faulting Completing */
+ ALT_DMA_CHANNEL_STATE_FAULTING = 15 /*!< Faulting */
+}
+ALT_DMA_CHANNEL_STATE_t;
+
+/*!
+ * This type definition enumerates the possible fault status that the DMA
+ * manager can have as a register mask.
+ */
+typedef enum ALT_DMA_MANAGER_FAULT_e
+{
+ /*!
+ * The DMA manager abort occured because of an instruction issued through
+ * the debug interface.
+ */
+ ALT_DMA_MANAGER_FAULT_DBG_INSTR = (int32_t)(1UL << 30),
+
+ /*!
+ * The DMA manager instruction fetch AXI bus response was not OKAY.
+ */
+ ALT_DMA_MANAGER_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16),
+
+ /*!
+ * The DMA manager attempted to execute DMAWFE or DMASEV with
+ * inappropriate security permissions.
+ */
+ ALT_DMA_MANAGER_FAULT_MGR_EVNT_ERR = (int32_t)(1UL << 5),
+
+ /*!
+ * The DMA manager attempted to execute DMAGO with inappropriate security
+ * permissions.
+ */
+ ALT_DMA_MANAGER_FAULT_DMAGO_ERR = (int32_t)(1UL << 4),
+
+ /*!
+ * The DMA manager attempted to execute an instruction operand that was
+ * not valid for the DMA configuration.
+ */
+ ALT_DMA_MANAGER_FAULT_OPERAND_INVALID = (int32_t)(1UL << 1),
+
+ /*!
+ * The DMA manager attempted to execute an undefined instruction.
+ */
+ ALT_DMA_MANAGER_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0)
+}
+ALT_DMA_MANAGER_FAULT_t;
+
+/*!
+ * This type definition enumerates the possible fault status that a channel
+ * may have as a register mask.
+ */
+typedef enum ALT_DMA_CHANNEL_FAULT_e
+{
+ /*!
+ * The DMA channel has locked up due to resource starvation.
+ */
+ ALT_DMA_CHANNEL_FAULT_LOCKUP_ERR = (int32_t)(1UL << 31),
+
+ /*!
+ * The DMA channel abort occured because of an instruction issued through
+ * the debug interface.
+ */
+ ALT_DMA_CHANNEL_FAULT_DBG_INSTR = (int32_t)(1UL << 30),
+
+ /*!
+ * The DMA channel data read AXI bus reponse was not OKAY.
+ */
+ ALT_DMA_CHANNEL_FAULT_DATA_READ_ERR = (int32_t)(1UL << 18),
+
+ /*!
+ * The DMA channel data write AXI bus response was not OKAY.
+ */
+ ALT_DMA_CHANNEL_FAULT_DATA_WRITE_ERR = (int32_t)(1UL << 17),
+
+ /*!
+ * The DMA channel instruction fetch AXI bus response was not OKAY.
+ */
+ ALT_DMA_CHANNEL_FAULT_INSTR_FETCH_ERR = (int32_t)(1UL << 16),
+
+ /*!
+ * The DMA channel MFIFO did not have the data for the DMAST instruction.
+ */
+ ALT_DMA_CHANNEL_FAULT_ST_DATA_UNAVAILABLE = (int32_t)(1UL << 13),
+
+ /*!
+ * The DMA channel MFIFO is too small to hold the DMALD instruction data,
+ * or too small to servic the DMAST instruction request.
+ */
+ ALT_DMA_CHANNEL_FAULT_MFIFO_ERR = (int32_t)(1UL << 12),
+
+ /*!
+ * The DMA channel in non-secure state attempted to perform a secure read
+ * or write.
+ */
+ ALT_DMA_CHANNEL_FAULT_CH_RDWR_ERR = (int32_t)(1UL << 7),
+
+ /*!
+ * The DMA channel in non-secure state attempted to execute the DMAWFP,
+ * DMALDP, DMASTP, or DMAFLUSHP instruction involving a secure peripheral.
+ */
+ ALT_DMA_CHANNEL_FAULT_CH_PERIPH_ERR = (int32_t)(1UL << 6),
+
+ /*!
+ * The DMA channel in non-secure state attempted to execute the DMAWFE or
+ * DMASEV instruction for a secure event or secure interrupt (if
+ * applicable).
+ */
+ ALT_DMA_CHANNEL_FAULT_CH_EVNT_ERR = (int32_t)(1UL << 5),
+
+ /*!
+ * The DMA channel attempted to execute an instruction operand that was
+ * not valid for the DMA configuration.
+ */
+ ALT_DMA_CHANNEL_FAULT_OPERAND_INVALID = (int32_t)(1UL << 1),
+
+ /*!
+ * The DMA channel attempted to execute an undefined instruction.
+ */
+ ALT_DMA_CHANNEL_FAULT_UNDEF_INSTR = (int32_t)(1UL << 0)
+}
+ALT_DMA_CHANNEL_FAULT_t;
+
+/*!
+ * This type definition enumerates the possible DMA event-interrupt behavior
+ * option selections when a DMASEV instruction is executed.
+ */
+typedef enum ALT_DMA_EVENT_SELECT_e
+{
+ /*!
+ * If the DMA controller executes DMASEV for the event-interrupt resource
+ * then the DMA sends the event to all of the channel threads.
+ */
+ ALT_DMA_EVENT_SELECT_SEND_EVT,
+
+ /*!
+ * If the DMA controller executes DMASEV for the event-interrupt resource
+ * then the DMA sets the \b irq[N] HIGH.
+ */
+ ALT_DMA_EVENT_SELECT_SIG_IRQ
+}
+ALT_DMA_EVENT_SELECT_t;
+
+/*!
+ * This type enumerates the DMA peripheral interface MUX selection options
+ * available.
+ */
+typedef enum ALT_DMA_PERIPH_MUX_e
+{
+ /*!
+ * Accept the reset default MUX selection
+ */
+ ALT_DMA_PERIPH_MUX_DEFAULT = 0,
+
+ /*!
+ * Select FPGA as the peripheral interface
+ */
+ ALT_DMA_PERIPH_MUX_FPGA = 1,
+
+ /*!
+ * Select CAN as the peripheral interface
+ */
+ ALT_DMA_PERIPH_MUX_CAN = 2
+}
+ALT_DMA_PERIPH_MUX_t;
+
+/*!
+ * This type defines the structure used to specify the configuration of the
+ * security states and peripheral interface MUX selections for the DMA
+ * controller.
+ */
+typedef struct ALT_DMA_CFG_s
+{
+ /*!
+ * DMA Manager security state configuration.
+ */
+ ALT_DMA_SECURITY_t manager_sec;
+
+ /*!
+ * DMA interrupt output security state configurations. Security state
+ * configurations are 0-based index-aligned with the enumeration values
+ * ALT_DMA_EVENT_0 through ALT_DMA_EVENT_7 of the ALT_DMA_EVENT_t type.
+ */
+ ALT_DMA_SECURITY_t irq_sec[8];
+
+ /*!
+ * Peripheral request interface security state configurations. Security
+ * state configurations are 0-based index-aligned with the enumeration
+ * values of the ALT_DMA_PERIPH_t type.
+ */
+ ALT_DMA_SECURITY_t periph_sec[32];
+
+ /*!
+ * DMA Peripheral Register Interface MUX Selections. MUX selections are
+ * 0-based index-aligned with the enumeration values
+ * ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 through
+ * ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 of the ALT_DMA_PERIPH_t type.
+ */
+ ALT_DMA_PERIPH_MUX_t periph_mux[4];
+}
+ALT_DMA_CFG_t;
+
+/*!
+ * Initialize the DMA controller.
+ *
+ * Initializes the DMA controller by setting the necessary control values to
+ * establish the security state and MUXed peripheral request interface selection
+ * configurations before taking the DMA controller out of reset.
+ *
+ * After the DMA is initialized, the following conditions hold true:
+ * * All DMA channel threads are in the Stopped state.
+ * * All DMA channel threads are available for allocation.
+ * * DMA Manager thread is waiting for an instruction from either APB
+ * interface.
+ * * The security state configurations of the DMA Manager, interrupt outputs,
+ * and peripheral request interfaces are established and immutable until the
+ * DMA is reset.
+ * * The MUXed peripheral request interface selection configurations are
+ * established and immutable until the DMA is reset.
+ *
+ * \param dma_cfg
+ * A pointer to a ALT_DMA_CFG_t structure containing the desired
+ * DMA controller security state and peripheral request interface
+ * MUX selections.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_init(const ALT_DMA_CFG_t * dma_cfg);
+
+/*!
+ * Uninitializes the DMA controller.
+ *
+ * Uninitializes the DMA controller by killing any running channel threads and
+ * putting the DMA controller into reset.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_uninit(void);
+
+/*!
+ * Allocate a DMA channel resource for use.
+ *
+ * \param channel
+ * A DMA controller channel.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_channel_alloc(ALT_DMA_CHANNEL_t channel);
+
+/*!
+ * Allocate a free DMA channel resource for use if there are any.
+ *
+ * \param allocated
+ * [out] A pointer to an output parameter that will contain the
+ * channel allocated.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed. An unallocated channel
+ * may not be available at the time of the API
+ * call.
+ */
+ALT_STATUS_CODE alt_dma_channel_alloc_any(ALT_DMA_CHANNEL_t * allocated);
+
+/*!
+ * Free a DMA channel resource for reuse.
+ *
+ * \param channel
+ * The DMA controller channel resource to free.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed. The channel may not be in
+ * the STOPPED state.
+ */
+ALT_STATUS_CODE alt_dma_channel_free(ALT_DMA_CHANNEL_t channel);
+
+/*!
+ * Start execution of a DMA microcode program on the specified DMA channel
+ * thread resource.
+ *
+ * \param channel
+ * The DMA channel thread used to execute the microcode program.
+ *
+ * \param pgm
+ * The DMA microcode program.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_channel_exec(ALT_DMA_CHANNEL_t channel,
+ ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Kill (abort) execution of any microcode program executing on the specified
+ * DMA channel thread resource.
+ *
+ * Terminates the channel thread of execution by issuing a DMAKILL instruction
+ * using the DMA APB slave interface.
+ *
+ * \param channel
+ * The DMA channel thread to abort any executing microcode program
+ * on.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_TMO Timeout waiting for the channel to change into
+ * KILLING or STOPPED state.
+ */
+ALT_STATUS_CODE alt_dma_channel_kill(ALT_DMA_CHANNEL_t channel);
+
+/*!
+ * Returns the current register value for the given DMA channel.
+ *
+ * \param channel
+ * The DMA channel thread to abort any executing microcode program
+ * on.
+ *
+ * \param reg
+ * Register to get the value for.
+ *
+ * \param val
+ * [out] The current value of the requested register.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The specified channel or register is invalid.
+ */
+ALT_STATUS_CODE alt_dma_channel_reg_get(ALT_DMA_CHANNEL_t channel,
+ ALT_DMA_PROGRAM_REG_t reg, uint32_t * val);
+
+/*!
+ * Signals the occurrence of an event or interrupt, using the specified event
+ * number.
+ *
+ * Causes the CPU to issue a DMASEV instruction using the DMA APB slave
+ * interface.
+ *
+ * The Interrupt Enable Register (INTEN) register is used to control if each
+ * event-interrupt resource is either an event or an interrupt. The INTEN
+ * register sets the event-interrupt resource to function as an:
+ * * Event - The DMAC generates an event for the specified event-interrupt
+ * resource. When the DMAC executes a DMAWFE instruction for the
+ * same event-interrupt resource then it clears the event.
+ * * Interrupt - The DMAC sets the \b IRQ[N] signal high, where
+ * \e evt_num is the number of the specified event
+ * resource. The interrupt must be cleared after being handled.
+ *
+ * When the configured to generate an event, this function may be used to
+ * restart one or more waiting DMA channels (i.e. having executed a DMAWFE
+ * instruction).
+ *
+ * See the following sections from the \e ARM DDI 0424C, CoreLink DMA Controller
+ * DMA-330 Technical Reference Manual for implementation details and use cases:
+ * * 2.5.1, Issuing Instructions to the DMAC using a Slave Interface
+ * * 2.7, Using Events and Interrupts
+ *
+ * \param evt_num
+ * A DMA event-interrupt resource. Allowable event values may be
+ * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 but ALT_DMA_EVENT_ABORT is
+ * not.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given event number is invalid.
+ */
+ALT_STATUS_CODE alt_dma_send_event(ALT_DMA_EVENT_t evt_num);
+
+/*!
+ * Returns the current operational state of the DMA manager thread.
+ *
+ * \param state
+ * [out] Pointer to an output parameter to contain the DMA
+ * channel thread state.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_manager_state_get(ALT_DMA_MANAGER_STATE_t * state);
+
+/*!
+ * Returns the current operational state of the specified DMA channel thread.
+ *
+ * \param channel
+ * The DMA channel thread to return the operational state of.
+ *
+ * \param state
+ * [out] Pointer to an output parameter to contain the DMA
+ * channel thread state.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given channel identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_channel_state_get(ALT_DMA_CHANNEL_t channel,
+ ALT_DMA_CHANNEL_STATE_t * state);
+
+/*!
+ * Return the current fault status of the DMA manager thread.
+ *
+ * \param fault
+ * [out] Pointer to an output parameter to contain the DMA
+ * manager fault status.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_dma_manager_fault_status_get(ALT_DMA_MANAGER_FAULT_t * fault);
+
+/*!
+ * Return the current fault status of the specified DMA channel thread.
+ *
+ * \param channel
+ * The DMA channel thread to return the fault status of.
+ *
+ * \param fault
+ * [out] Pointer to an output parameter to contain the DMA
+ * channel fault status.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given channel identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_channel_fault_status_get(ALT_DMA_CHANNEL_t channel,
+ ALT_DMA_CHANNEL_FAULT_t * fault);
+
+/*!
+ * Select whether the DMA controller sends the specific event to all channel
+ * threads or signals an interrupt using the corressponding \b irq when a DMASEV
+ * instruction is executed for the specified event-interrupt resource number.
+ *
+ * \param evt_num
+ * The event-interrupt resource number. Valid values are
+ * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
+ *
+ * \param opt
+ * The desired behavior selection for \e evt_num when a DMASEV is
+ * executed.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given selection identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_event_int_select(ALT_DMA_EVENT_t evt_num,
+ ALT_DMA_EVENT_SELECT_t opt);
+
+/*!
+ * Returns the status of the specified event-interrupt resource.
+ *
+ * Returns ALT_E_TRUE if event is active or \b irq[N] is HIGH and returns
+ * ALT_E_FALSE if event is inactive or \b irq[N] is LOW.
+ *
+ * \param evt_num
+ * The event-interrupt resource number. Valid values are
+ * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
+ *
+ * \retval ALT_E_TRUE Event is active or \b irq[N] is HIGH.
+ * \retval ALT_E_FALSE Event is inactive or \b irq[N] is LOW.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given event identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_event_int_status_get_raw(ALT_DMA_EVENT_t evt_num);
+
+/*!
+ * Returns the status of the specified interrupt resource.
+ *
+ * Returns ALT_E_TRUE if interrupt is active and therfore \b irq[N] is HIGH and
+ * returns ALT_E_FALSE if interrupt is inactive and therfore \b irq[N] is LOW.
+ *
+ * \param irq_num
+ * The interrupt resource number. Valid values are
+ * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
+ *
+ * \retval ALT_E_TRUE Event is active or \b irq[N] is HIGH.
+ * \retval ALT_E_FALSE Event is inactive or \b irq[N] is LOW.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given event identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_int_status_get(ALT_DMA_EVENT_t irq_num);
+
+/*!
+ * Clear the active (HIGH) status of the specified interrupt resource.
+ *
+ * If the specified interrupt is HIGH, then sets \b irq[N] to LOW if the
+ * event-interrupt resource is configured (see: alt_dma_event_int_enable())
+ * to signal an interrupt. Otherwise, the status of \b irq[N] does not change.
+ *
+ * \param irq_num
+ * The interrupt resource number. Valid values are
+ * ALT_DMA_EVENT_0 .. ALT_DMA_EVENT_7 and ALT_DMA_EVENT_ABORT.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given event identifier is invalid.
+ */
+ALT_STATUS_CODE alt_dma_int_clear(ALT_DMA_EVENT_t irq_num);
+
+/*!
+ * @}
+ */
+
+/*!
+ * \addtogroup ALT_DMA_STD_OPS DMA API for Standard Operations
+ *
+ * The functions in this group provide common DMA operations for common bulk
+ * data transfers between:
+ * * Memory to Memory
+ * * Zero to Memory
+ * * Memory to Peripheral
+ * * Peripheral to Memory
+ *
+ * All DMA operations are asynchronous. The following are the ways to receive
+ * notification of a DMA transfer complete operation:
+ * * Use alt_dma_channel_state_get() and poll for the
+ * ALT_DMA_CHANNEL_STATE_STOPPED status.
+ * * In conjunction with the interrupt API, use DMA events to signal an
+ * interrupt. The event first must be configured to signal an interrupt
+ * using alt_dma_event_int_select(). Configure the DMA program to send an
+ * event.
+ * * Construct a custom program which waits for a particular event number by
+ * assemblying a DMAWFE using alt_dma_program_DMAWFE(). Then run the custom
+ * program on a different channel. The custom program will wait until the
+ * DMA program sends the event. Configure the DMA program to send an event.
+ *
+ * Cache related maintenance on the source and/or destinatino buffer are not
+ * handled the DMA API and are the responsibility of the programmer. This is
+ * because the DMA API does not have visibility into the current configuration
+ * of the MMU or know about any special considerations regarding the source
+ * and/or destination memory. The following are some example scenarios and
+ * cache maintenance related precautions that may need to be taken:
+ * * alt_dma_memory_to_memory(): Source buffer should be cleaned or purged,
+ * destination buffer should be invalidated.
+ * * alt_dma_zero_to_memory(): Destination buffer should be invalidated.
+ * * alt_dma_memory_to_register(): Source buffer should be cleaned or purged.
+ * * alt_dma_register_to_memory(): Destination buffer should be invalidated.
+ * * alt_dma_memory_to_periph(): Source buffer should be cleaned or purged.
+ * * alt_dma_periph_to_memory(): Destination buffer should be invalidated.
+ *
+ * @{
+ */
+
+/*!
+ * Uses the DMA engine to asynchronously copy the specified memory from the
+ * given source address to the given destination address.
+ *
+ * Overlapping memory regions are not supported.
+ *
+ * \param channel
+ * The DMA channel thread to use for the transfer.
+ *
+ * \param program
+ * An allocated DMA program buffer to use for the life of the
+ * transfer.
+ *
+ * \param dest
+ * The destination memory address to copy to.
+ *
+ * \param src
+ * The source memory address to copy from.
+ *
+ * \param size
+ * The size of the transfer in bytes.
+ *
+ * \param send_evt
+ * If set to true, the DMA engine will be instructed to send an
+ * event upon completion or fault.
+ *
+ * \param evt
+ * If send_evt is true, the event specified will be sent.
+ * Otherwise the parameter is ignored.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given channel or event identifier (if
+ * used) is invalid, or the memory regions
+ * specified are overlapping.
+ */
+ALT_STATUS_CODE alt_dma_memory_to_memory(ALT_DMA_CHANNEL_t channel,
+ ALT_DMA_PROGRAM_t * program,
+ void * dest,
+ const void * src,
+ size_t size,
+ bool send_evt,
+ ALT_DMA_EVENT_t evt);
+
+/*!
+ * Uses the DMA engine to asynchronously zero out the specified memory buffer.
+ *
+ * \param channel
+ * The DMA channel thread to use for the transfer.
+ *
+ * \param program
+ * An allocated DMA program buffer to use for the life of the
+ * transfer.
+ *
+ * \param buf
+ * The buffer memory address to zero out.
+ *
+ * \param size
+ * The size of the buffer in bytes.
+ *
+ * \param send_evt
+ * If set to true, the DMA engine will be instructed to send an
+ * event upon completion or fault.
+ *
+ * \param evt
+ * If send_evt is true, the event specified will be sent.
+ * Otherwise the parameter is ignored.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given channel or event identifier (if
+ * used) is invalid.
+ */
+ALT_STATUS_CODE alt_dma_zero_to_memory(ALT_DMA_CHANNEL_t channel,
+ ALT_DMA_PROGRAM_t * program,
+ void * buf,
+ size_t size,
+ bool send_evt,
+ ALT_DMA_EVENT_t evt);
+
+/*!
+ * Uses the DMA engine to asynchronously transfer the contents of a memory
+ * buffer to a keyhole register.
+ *
+ * \param channel
+ * The DMA channel thread to use for the transfer.
+ *
+ * \param program
+ * An allocated DMA program buffer to use for the life of the
+ * transfer.
+ *
+ * \param dst_reg
+ * The address of the register to write buffer to.
+ *
+ * \param src_buf
+ * The address of the memory buffer for the data.
+ *
+ * \param count
+ * The number of transfers to make.
+ *
+ * \param register_width_bits
+ * The width of the register to transfer to in bits. Valid values
+ * are 8, 16, 32, and 64.
+ *
+ * \param send_evt
+ * If set to true, the DMA engine will be instructed to send an
+ * event upon completion or fault.
+ *
+ * \param evt
+ * If send_evt is true, the event specified will be sent.
+ * Otherwise the parameter is ignored.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given channel, event identifier (if used),
+ * or register width are invalid, or if the
+ * destination register or source buffer is
+ * unaligned to the register width.
+ */
+ALT_STATUS_CODE alt_dma_memory_to_register(ALT_DMA_CHANNEL_t channel,
+ ALT_DMA_PROGRAM_t * program,
+ void * dst_reg,
+ const void * src_buf,
+ size_t count,
+ uint32_t register_width_bits,
+ bool send_evt,
+ ALT_DMA_EVENT_t evt);
+
+/*!
+ * Uses the DMA engine to asynchronously transfer the contents of a keyhole
+ * register to a memory buffer.
+ *
+ * \param channel
+ * The DMA channel thread to use for the transfer.
+ *
+ * \param program
+ * An allocated DMA program buffer to use for the life of the
+ * transfer.
+ *
+ * \param dst_buf
+ * The address of the memory buffer to copy to.
+ *
+ * \param src_reg
+ * The address of the keyhole register to read from.
+ *
+ * \param count
+ * The number of transfers to make.
+ *
+ * \param register_width_bits
+ * The width of the register to transfer to in bits. Valid values
+ * are 8, 16, 32, and 64.
+ *
+ * \param send_evt
+ * If set to true, the DMA engine will be instructed to send an
+ * event upon completion or fault.
+ *
+ * \param evt
+ * If send_evt is true, the event specified will be sent.
+ * Otherwise the parameter is ignored.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given channel, event identifier (if used),
+ * or register width are invalid, or if the
+ * destination buffer or source register is
+ * unaligned to the register width.
+ */
+ALT_STATUS_CODE alt_dma_register_to_memory(ALT_DMA_CHANNEL_t channel,
+ ALT_DMA_PROGRAM_t * program,
+ void * dst_buf,
+ const void * src_reg,
+ size_t count,
+ uint32_t register_width_bits,
+ bool send_evt,
+ ALT_DMA_EVENT_t evt);
+
+/*!
+ * Uses the DMA engine to asynchronously copy memory from the given source
+ * address to the specified peripheral. Because different peripheral has
+ * different characteristics, individual peripherals need to be explicitly
+ * supported.
+ *
+ * The following lists the peripheral IDs supported by this API:
+ * * ALT_DMA_PERIPH_QSPI_FLASH_TX
+ * * ALT_DMA_PERIPH_UART0_TX
+ * * ALT_DMA_PERIPH_UART1_TX
+ *
+ * \param channel
+ * The DMA channel thread to use for the transfer.
+ *
+ * \param program
+ * An allocated DMA program buffer to use for the life of the
+ * transfer.
+ *
+ * \param dest
+ * The destination peripheral to copy memory to.
+ *
+ * \param src
+ * The source memory address to copy from.
+ *
+ * \param size
+ * The size of the transfer in bytes.
+ *
+ * \param periph_info
+ * A pointer to a peripheral specific data structure. The
+ * following list shows what data structure should be used for
+ * peripherals:
+ * * ALT_DMA_PERIPH_QSPI_FLASH_TX: This parameter is ignored.
+ * * ALT_DMA_PERIPH_UART0_TX: Use a pointer to the
+ * ALT_16550_HANDLE_t used to interact with that UART.
+ * * ALT_DMA_PERIPH_UART1_TX: Use a pointer to the
+ * ALT_16550_HANDLE_t used to interact with that UART.
+ *
+ * \param send_evt
+ * If set to true, the DMA engine will be instructed to send an
+ * event upon completion or fault.
+ *
+ * \param evt
+ * If send_evt is true, the event specified will be sent.
+ * Otherwise the parameter is ignored.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given channel, peripheral, or event
+ * identifier (if used) is invalid.
+ *
+ * \internal
+ * Priority peripheral IDs to be supported:
+ * * ALT_DMA_PERIPH_FPGA_0
+ * * ALT_DMA_PERIPH_FPGA_1
+ * * ALT_DMA_PERIPH_FPGA_2
+ * * ALT_DMA_PERIPH_FPGA_3
+ * * ALT_DMA_PERIPH_FPGA_4
+ * * ALT_DMA_PERIPH_FPGA_5
+ * * ALT_DMA_PERIPH_FPGA_6
+ * * ALT_DMA_PERIPH_FPGA_7
+ * * ALT_DMA_PERIPH_I2C0_TX
+ * * ALT_DMA_PERIPH_I2C1_TX
+ * * ALT_DMA_PERIPH_I2C2_TX
+ * * ALT_DMA_PERIPH_I2C3_TX
+ * * ALT_DMA_PERIPH_SPI0_MASTER_TX
+ * * ALT_DMA_PERIPH_SPI0_SLAVE_TX
+ * * ALT_DMA_PERIPH_SPI1_MASTER_TX
+ * * ALT_DMA_PERIPH_SPI1_SLAVE_TX
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_dma_memory_to_periph(ALT_DMA_CHANNEL_t channel,
+ ALT_DMA_PROGRAM_t * program,
+ ALT_DMA_PERIPH_t dest,
+ const void * src,
+ size_t size,
+ void * periph_info,
+ bool send_evt,
+ ALT_DMA_EVENT_t evt);
+
+/*!
+ * Uses the DMA engine to copy memory from the specified peripheral to the
+ * given destination address. Because different peripheral has different
+ * characteristics, individual peripherals need to be explicitly supported.
+ *
+ * The following lists the peripheral IDs supported by this API:
+ * * ALT_DMA_PERIPH_QSPI_FLASH_RX
+ * * ALT_DMA_PERIPH_UART0_RX
+ * * ALT_DMA_PERIPH_UART1_RX
+ *
+ * \param channel
+ * The DMA channel thread to use for the transfer.
+ *
+ * \param program
+ * An allocated DMA program buffer to use for the life of the
+ * transfer.
+ *
+ * \param dest
+ * The destination memory address to copy to.
+ *
+ * \param src
+ * The source peripheral to copy memory from.
+ *
+ * \param size
+ * The size of the transfer in bytes.
+ *
+ * \param periph_info
+ * A pointer to a peripheral specific data structure. The
+ * following list shows what data structure should be used for
+ * peripherals:
+ * * ALT_DMA_PERIPH_QSPI_FLASH_RX: This parameter is ignored.
+ * * ALT_DMA_PERIPH_UART0_RX: Use a pointer to the
+ * ALT_16550_HANDLE_t used to interact with that UART.
+ * * ALT_DMA_PERIPH_UART1_RX: Use a pointer to the
+ * ALT_16550_HANDLE_t used to interact with that UART.
+ *
+ * \param send_evt
+ * If set to true, the DMA engine will be instructed to send an
+ * event upon completion or fault.
+ *
+ * \param evt
+ * If send_evt is true, the event specified will be sent.
+ * Otherwise the parameter is ignored.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG The given channel, peripheral, or event
+ * identifier (if used) is invalid.
+*
+ * \internal
+ * Priority peripheral IDs to be supported:
+ * * ALT_DMA_PERIPH_FPGA_0
+ * * ALT_DMA_PERIPH_FPGA_1
+ * * ALT_DMA_PERIPH_FPGA_2
+ * * ALT_DMA_PERIPH_FPGA_3
+ * * ALT_DMA_PERIPH_FPGA_4
+ * * ALT_DMA_PERIPH_FPGA_5
+ * * ALT_DMA_PERIPH_FPGA_6
+ * * ALT_DMA_PERIPH_FPGA_7
+ * * ALT_DMA_PERIPH_I2C0_RX
+ * * ALT_DMA_PERIPH_I2C1_RX
+ * * ALT_DMA_PERIPH_I2C2_RX
+ * * ALT_DMA_PERIPH_I2C3_RX
+ * * ALT_DMA_PERIPH_SPI0_MASTER_RX
+ * * ALT_DMA_PERIPH_SPI0_SLAVE_RX
+ * * ALT_DMA_PERIPH_SPI1_MASTER_RX
+ * * ALT_DMA_PERIPH_SPI1_SLAVE_RX
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_dma_periph_to_memory(ALT_DMA_CHANNEL_t channel,
+ ALT_DMA_PROGRAM_t * program,
+ void * dest,
+ ALT_DMA_PERIPH_t src,
+ size_t size,
+ void * periph_info,
+ bool send_evt,
+ ALT_DMA_EVENT_t evt);
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_DMA_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h
new file mode 100644
index 0000000000..e82bc1ae4d
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_common.h
@@ -0,0 +1,162 @@
+/******************************************************************************
+ *
+ * Copyright 2013 Altera Corporation. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+#ifndef __ALT_DMA_COMMON_H__
+#define __ALT_DMA_COMMON_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*!
+ * \addtogroup ALT_DMA_COMMON DMA Controller Common API Definitions
+ *
+ * This module contains the common definitions for the DMA controller related
+ * APIs.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates the DMA controller channel threads.
+ */
+typedef enum ALT_DMA_CHANNEL_e
+{
+ ALT_DMA_CHANNEL_0 = 0, /*!< DMA Channel Thread 0 */
+ ALT_DMA_CHANNEL_1 = 1, /*!< DMA Channel Thread 1 */
+ ALT_DMA_CHANNEL_2 = 2, /*!< DMA Channel Thread 2 */
+ ALT_DMA_CHANNEL_3 = 3, /*!< DMA Channel Thread 3 */
+ ALT_DMA_CHANNEL_4 = 4, /*!< DMA Channel Thread 4 */
+ ALT_DMA_CHANNEL_5 = 5, /*!< DMA Channel Thread 5 */
+ ALT_DMA_CHANNEL_6 = 6, /*!< DMA Channel Thread 6 */
+ ALT_DMA_CHANNEL_7 = 7 /*!< DMA Channel Thread 7 */
+}
+ALT_DMA_CHANNEL_t;
+
+/*!
+ * This type definition enumerates the SoC system peripherals implementing the
+ * required request interface that enables direct DMA transfers to/from the
+ * device.
+ *
+ * FPGA soft IP interface to the DMA are required to comply with the Synopsys
+ * protocol.
+ *
+ * Request interface numbers 4 through 7 are multiplexed between the CAN
+ * controllers and soft logic implemented in the FPGA fabric. The selection
+ * between the CAN controller and FPGA interfaces is determined at DMA
+ * initialization.
+ */
+typedef enum ALT_DMA_PERIPH_e
+{
+ ALT_DMA_PERIPH_FPGA_0 = 0, /*!< FPGA soft IP interface 0 */
+ ALT_DMA_PERIPH_FPGA_1 = 1, /*!< FPGA soft IP interface 1 */
+ ALT_DMA_PERIPH_FPGA_2 = 2, /*!< FPGA soft IP interface 2 */
+ ALT_DMA_PERIPH_FPGA_3 = 3, /*!< FPGA soft IP interface 3 */
+
+ ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 = 4, /*!< Selectively MUXed FPGA 4 or CAN 0 interface 1 */
+ ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 = 5, /*!< Selectively MUXed FPGA 5 or CAN 0 interface 2 */
+ ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 = 6, /*!< Selectively MUXed FPGA 6 or CAN 1 interface 1 */
+ ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 = 7, /*!< Selectively MUXed FPGA 7 or CAN 1 interface 2 */
+
+ ALT_DMA_PERIPH_FPGA_4 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
+ ALT_DMA_PERIPH_FPGA_5 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
+ ALT_DMA_PERIPH_FPGA_6 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
+ ALT_DMA_PERIPH_FPGA_7 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
+
+ ALT_DMA_PERIPH_CAN0_IF1 = 4, /*!< Alias for ALT_DMA_PERIPH_FPGA_4_OR_CAN0_IF1 */
+ ALT_DMA_PERIPH_CAN0_IF2 = 5, /*!< Alias for ALT_DMA_PERIPH_FPGA_5_OR_CAN0_IF2 */
+ ALT_DMA_PERIPH_CAN1_IF1 = 6, /*!< Alias for ALT_DMA_PERIPH_FPGA_6_OR_CAN1_IF1 */
+ ALT_DMA_PERIPH_CAN1_IF2 = 7, /*!< Alias for ALT_DMA_PERIPH_FPGA_7_OR_CAN1_IF2 */
+
+ ALT_DMA_PERIPH_I2C0_TX = 8, /*!< I<sup>2</sup>C 0 TX */
+ ALT_DMA_PERIPH_I2C0_RX = 9, /*!< I<sup>2</sup>C 0 RX */
+ ALT_DMA_PERIPH_I2C1_TX = 10, /*!< I<sup>2</sup>C 1 TX */
+ ALT_DMA_PERIPH_I2C1_RX = 11, /*!< I<sup>2</sup>C 1 RX */
+ ALT_DMA_PERIPH_I2C2_TX = 12, /*!< I<sup>2</sup>C 2 TX */
+ ALT_DMA_PERIPH_I2C2_RX = 13, /*!< I<sup>2</sup>C 2 RX */
+ ALT_DMA_PERIPH_I2C3_TX = 14, /*!< I<sup>2</sup>C 3 TX */
+ ALT_DMA_PERIPH_I2C3_RX = 15, /*!< I<sup>2</sup>C 3 RX */
+ ALT_DMA_PERIPH_SPI0_MASTER_TX = 16, /*!< SPI 0 Master TX */
+ ALT_DMA_PERIPH_SPI0_MASTER_RX = 17, /*!< SPI 0 Master RX */
+ ALT_DMA_PERIPH_SPI0_SLAVE_TX = 18, /*!< SPI 0 Slave TX */
+ ALT_DMA_PERIPH_SPI0_SLAVE_RX = 19, /*!< SPI 0 Slave RX */
+ ALT_DMA_PERIPH_SPI1_MASTER_TX = 20, /*!< SPI 1 Master TX */
+ ALT_DMA_PERIPH_SPI1_MASTER_RX = 21, /*!< SPI 1 Master RX */
+ ALT_DMA_PERIPH_SPI1_SLAVE_TX = 22, /*!< SPI 1 Slave TX */
+ ALT_DMA_PERIPH_SPI1_SLAVE_RX = 23, /*!< SPI 1 Slave RX */
+ ALT_DMA_PERIPH_QSPI_FLASH_TX = 24, /*!< QSPI Flash TX */
+ ALT_DMA_PERIPH_QSPI_FLASH_RX = 25, /*!< QSPI Flash RX */
+ ALT_DMA_PERIPH_STM = 26, /*!< System Trace Macrocell */
+ ALT_DMA_PERIPH_RESERVED = 27, /*!< Reserved */
+ ALT_DMA_PERIPH_UART0_TX = 28, /*!< UART 0 TX */
+ ALT_DMA_PERIPH_UART0_RX = 29, /*!< UART 0 RX */
+ ALT_DMA_PERIPH_UART1_TX = 30, /*!< UART 1 TX */
+ ALT_DMA_PERIPH_UART1_RX = 31 /*!< UART 1 RX */
+}
+ALT_DMA_PERIPH_t;
+
+/*!
+ * This type enumerates the DMA security state options available.
+ */
+typedef enum ALT_DMA_SECURITY_e
+{
+ ALT_DMA_SECURITY_DEFAULT = 0, /*!< Use the default security value (e.g. reset default) */
+ ALT_DMA_SECURITY_SECURE = 1, /*!< Secure */
+ ALT_DMA_SECURITY_NONSECURE = 2 /*!< Non-secure */
+}
+ALT_DMA_SECURITY_t;
+
+/*!
+ * This type definition enumerates the DMA event-interrupt resources.
+ */
+typedef enum ALT_DMA_EVENT_e
+{
+ ALT_DMA_EVENT_0 = 0, /*!< DMA Event 0 */
+ ALT_DMA_EVENT_1 = 1, /*!< DMA Event 1 */
+ ALT_DMA_EVENT_2 = 2, /*!< DMA Event 2 */
+ ALT_DMA_EVENT_3 = 3, /*!< DMA Event 3 */
+ ALT_DMA_EVENT_4 = 4, /*!< DMA Event 4 */
+ ALT_DMA_EVENT_5 = 5, /*!< DMA Event 5 */
+ ALT_DMA_EVENT_6 = 6, /*!< DMA Event 6 */
+ ALT_DMA_EVENT_7 = 7, /*!< DMA Event 7 */
+ ALT_DMA_EVENT_ABORT = 8 /*!< DMA Abort Event */
+}
+ALT_DMA_EVENT_t;
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_DMA_COMMON_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h
new file mode 100644
index 0000000000..5fa876f237
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_dma_program.h
@@ -0,0 +1,951 @@
+/******************************************************************************
+ *
+ * Copyright 2013 Altera Corporation. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+#ifndef __ALT_DMA_PROGRAM_H__
+#define __ALT_DMA_PROGRAM_H__
+
+#include "hwlib.h"
+#include "alt_dma_common.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*!
+ * \addtogroup ALT_DMA_PRG DMA Controller Programming API
+ *
+ * This API provides functions for dynamically defining and assembling microcode
+ * programs for execution on the DMA controller.
+ *
+ * The microcode program assembly API provides users with the ability to develop
+ * highly optimized and tailored algorithms for data transfer between SoC FPGA
+ * IP blocks and/or system memory.
+ *
+ * The same microcode program assembly facilities are also used to implement the
+ * functions found in the HWLIB Common DMA Operations functional API.
+ *
+ * An ALT_DMA_PROGRAM_t structure is used to contain and assemble a DMA
+ * microcode program. The storage for an ALT_DMA_PROGRAM_t stucture is allocated
+ * from used specified system memory. Once a microcode program has been
+ * assembled in a ALT_DMA_PROGRAM_t it may be excecuted on a designated DMA
+ * channel thread. The microcode program may be rerun on any DMA channel thread
+ * whenever required as long as the integrity of the ALT_DMA_PROGRAM_t
+ * containing the program is maintained.
+ *
+ * @{
+ */
+
+/*!
+ * This preprocessor declares the DMA channel thread microcode instruction
+ * cache line width in bytes. It is recommended that the program buffers be
+ * sized to a multiple of the cache line size. This will allow for the most
+ * efficient microcode speed and space utilization.
+ */
+#define ALT_DMA_PROGRAM_CACHE_LINE_SIZE (32)
+
+/*!
+ * This preprocessor declares the DMA channel thread microcode instruction
+ * cache line count. Thus the total size of the cache is the cache line size
+ * multipled by the cache line count. Programs larger than the cache size risk
+ * having a cache miss while executing.
+ */
+#define ALT_DMA_PROGRAM_CACHE_LINE_COUNT (16)
+
+/*!
+ * This preprocessor definition determines the size of the program buffer
+ * within the ALT_DMA_PROGRAM_t structure. This size should provide adequate
+ * size for most DMA microcode programs. If calls within this API are
+ * reporting out of memory response codes, consider increasing the provisioned
+ * program buffersize.
+ *
+ * To specify another DMA microcode program buffer size, redefine the macro
+ * below by defining ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE to another size in
+ * your Makefile. It is recommended that the size be a multiple of the
+ * microcode engine cache line size. See ALT_DMA_PROGRAM_CACHE_LINE_SIZE for
+ * more information. The largest supported buffer size is 65536 bytes.
+ */
+#ifndef ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE
+#define ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE (ALT_DMA_PROGRAM_CACHE_LINE_SIZE * ALT_DMA_PROGRAM_CACHE_LINE_COUNT)
+#endif
+
+/*!
+ * This type defines the structure used to assemble and contain a microcode
+ * program which can be executed by the DMA controller. The internal members
+ * are undocumented and should not be altered outside of this API.
+ */
+typedef struct ALT_DMA_PROGRAM_s
+{
+ uint32_t flag;
+
+ uint16_t buffer_start;
+ uint16_t code_size;
+
+ uint16_t loop0;
+ uint16_t loop1;
+
+ uint16_t sar;
+ uint16_t dar;
+
+ /*
+ * Add a little extra space so that regardless of where this structure
+ * sits in memory, a suitable start address can be aligned to the cache
+ * line stride while providing the requested buffer space.
+ */
+ uint8_t program[ALT_DMA_PROGRAM_PROVISION_BUFFER_SIZE +
+ ALT_DMA_PROGRAM_CACHE_LINE_SIZE];
+}
+ALT_DMA_PROGRAM_t;
+
+/*!
+ * This type definition enumerates the DMA controller register names for use in
+ * microcode program definition.
+ */
+typedef enum ALT_DMA_PROGRAM_REG_e
+{
+ /*! Source Address Register */
+ ALT_DMA_PROGRAM_REG_SAR = 0x0,
+
+ /*! Destination Address Register */
+ ALT_DMA_PROGRAM_REG_DAR = 0x2,
+
+ /*! Channel Control Register */
+ ALT_DMA_PROGRAM_REG_CCR = 0x1
+}
+ALT_DMA_PROGRAM_REG_t;
+
+/*!
+ * This type definition enumerates the instruction modifier options available
+ * for use with selected DMA microcode instructions.
+ *
+ * The enumerations values are context dependent upon the instruction being
+ * modified.
+ *
+ * For the <b>DMALD[S|B]</b>, <b>DMALDP\<S|B></b>, <b>DMAST[S|B]</b>, and
+ * <b>DMASTP\<S|B></b> microcode instructions, the enumeration
+ * ALT_DMA_PROGRAM_INST_MOD_SINGLE specifies the <b>S</b> option modifier
+ * while the enumeration ALT_DMA_PROGRAM_INST_MOD_BURST specifies the <b>B</b>
+ * option modifier. The enumeration ALT_DMA_PROGRAM_INST_MOD_NONE specifies
+ * that no modifier is present for instructions where use of <b>[S|B]</b> is
+ * optional.
+ *
+ * For the <b>DMAWFP</b> microcode instruction, the enumerations
+ * ALT_DMA_PROGRAM_INST_MOD_SINGLE, ALT_DMA_PROGRAM_INST_MOD_BURST, or
+ * ALT_DMA_PROGRAM_INST_MOD_PERIPH each specify one of the corresponding
+ * options <b>\<single|burst|periph></b>.
+ */
+typedef enum ALT_DMA_PROGRAM_INST_MOD_e
+{
+ /*!
+ * This DMA instruction modifier specifies that no special modifier is
+ * added to the instruction.
+ */
+ ALT_DMA_PROGRAM_INST_MOD_NONE,
+
+ /*!
+ * Depending on the DMA microcode instruction modified, this modifier
+ * specifies <b>S</b> case for a <b>[S|B]</b> or a <b>\<single></b> for a
+ * <b>\<single|burst|periph></b>.
+ */
+ ALT_DMA_PROGRAM_INST_MOD_SINGLE,
+
+ /*!
+ * Depending on the DMA microcode instruction modified, this modifier
+ * specifies <b>B</b> case for a <b>[S|B]</b> or a <b>\<burst></b> for a
+ * <b>\<single|burst|periph></b>.
+ */
+ ALT_DMA_PROGRAM_INST_MOD_BURST,
+
+ /*!
+ * This DMA instruction modifier specifies a <b>\<periph></b> for a
+ * <b>\<single|burst|periph></b>.
+ */
+ ALT_DMA_PROGRAM_INST_MOD_PERIPH
+}
+ALT_DMA_PROGRAM_INST_MOD_t;
+
+/*!
+ * This function initializes a system memory buffer for use as a DMA microcode
+ * program buffer. This should be the first API call made on the program
+ * buffer type.
+ *
+ * \param pgm
+ * A pointer to a DMA program buffer structure.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR Details about error status code
+ */
+ALT_STATUS_CODE alt_dma_program_init(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * This function verifies that the DMA microcode program buffer is no longer
+ * in use and performs any needed uninitialization steps.
+ *
+ * \param pgm
+ * A pointer to a DMA program buffer structure.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR Details about error status code
+ */
+ALT_STATUS_CODE alt_dma_program_uninit(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * This function clears the existing DMA microcode program in the given
+ * program buffer.
+ *
+ * \param pgm
+ * A pointer to a DMA program buffer structure.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR Details about error status code.
+ */
+ALT_STATUS_CODE alt_dma_program_clear(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * This function validate that the given DMA microcode program buffer contains
+ * a well formed program. If caches are enabled, the program buffer contents
+ * will be cleaned to RAM.
+ *
+ * \param pgm
+ * A pointer to a DMA program buffer structure.
+ *
+ * \retval ALT_E_SUCCESS The given program is well formed.
+ * \retval ALT_E_ERROR The given program is not well formed.
+ * \retval ALT_E_TMO The cache operation timed out.
+ */
+ALT_STATUS_CODE alt_dma_program_validate(const ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * This function reports the number bytes incremented for the register
+ * specified. The purpose is to determine the progress of an ongoing DMA
+ * transfer.
+ *
+ * It is implemented by calculating the difference of the programmed SAR or DAR
+ * with the current channel SAR or DAR register value.
+ *
+ * \param pgm
+ * A pointer to a DMA program buffer structure.
+ *
+ * \param channel
+ * The channel that the program is running on.
+ *
+ * \param reg
+ * Register to change the value for. Valid for only
+ * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR.
+ *
+ * \param current
+ * The current snapshot value of the register read from the DMA
+ * channel.
+ *
+ * \param progress
+ * [out] A pointer to a memory location that will be used to store
+ * the number of bytes transfered.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR Details about error status code.
+ * \retval ALT_E_BAD_ARG The specified channel is invalid, the specified
+ * register is invalid, or the DMAMOV for the
+ * specified register has not yet been assembled
+ * in the current program buffer.
+ */
+ALT_STATUS_CODE alt_dma_program_progress_reg(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PROGRAM_REG_t reg,
+ uint32_t current, uint32_t * progress);
+
+/*!
+ * This function updates a pre-existing DMAMOV value affecting the SAR or DAR
+ * registers. This allows for pre-assembled programs that can be used on
+ * different source and destination addresses.
+ *
+ * \param pgm
+ * A pointer to a DMA program buffer structure.
+ *
+ * \param reg
+ * Register to change the value for. Valid for only
+ * ALT_DMA_PROGRAM_REG_SAR and ALT_DMA_PROGRAM_REG_DAR.
+ *
+ * \param val
+ * The value to update to.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR Details about error status code.
+ * \retval ALT_E_BAD_ARG The specified register is invalid or the DMAMOV
+ * for the specified register has not yet been
+ * assembled in the current program buffer.
+ */
+ALT_STATUS_CODE alt_dma_program_update_reg(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PROGRAM_REG_t reg, uint32_t val);
+
+/*!
+ */
+
+/*!
+ * Assembles a DMAADDH (Add Halfword) instruction into the microcode program
+ * buffer. This instruction uses 3 bytes of buffer space.
+ *
+ * \param pgm
+ * The DMA program buffer to contain the assembled instruction.
+ *
+ * \param addr_reg
+ * The channel address register (ALT_DMA_PROGRAM_REG_DAR or
+ * ALT_DMA_PROGRAM_REG_SAR) to add the value to.
+ *
+ * \param val
+ * The 16-bit unsigned value to add to the channel address
+ * register.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid channel register specified.
+ */
+// Assembler Syntax: DMAADDH <address_register>, <16-bit immediate>
+ALT_STATUS_CODE alt_dma_program_DMAADDH(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val);
+
+/*!
+ * Assembles a DMAADNH (Add Negative Halfword) instruction into the microcode
+ * program buffer. This instruction uses 3 bytes of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param addr_reg
+ * The channel address register (ALT_DMA_PROGRAM_REG_DAR or
+ * ALT_DMA_PROGRAM_REG_SAR) to add the value to.
+ *
+ * \param val
+ * The 16-bit unsigned value to add to the channel address
+ * register.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid channel register specified.
+ */
+// Assembler Syntax: DMAADNH <address_register>, <16-bit immediate>
+ALT_STATUS_CODE alt_dma_program_DMAADNH(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PROGRAM_REG_t addr_reg, uint16_t val);
+
+/*!
+ * Assembles a DMAEND (End) instruction into the microcode program buffer.
+ * This instruction uses 1 byte of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ */
+// Assembler Syntax: DMAEND
+ALT_STATUS_CODE alt_dma_program_DMAEND(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMAFLUSHP (Flush Peripheral) instruction into the microcode
+ * program buffer. This instruction uses 2 bytes of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param periph
+ * The peripheral to flush.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid peripheral specified.
+ */
+// Assembler Syntax: DMAFLUSHP <peripheral>
+ALT_STATUS_CODE alt_dma_program_DMAFLUSHP(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PERIPH_t periph);
+
+/*!
+ * Assembles a DMAGO (Go) instruction into the microcode program buffer. This
+ * instruction uses 6 bytes of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param channel
+ * The stopped channel to act upon.
+ *
+ * \param val
+ * The value to write to the channel program counter register.
+ *
+ * \param sec
+ * The security state for the operation.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid channel or security specified.
+ */
+// Assembler Syntax: DMAGO <channel_number>, <32-bit_immediate> [, ns]
+ALT_STATUS_CODE alt_dma_program_DMAGO(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_CHANNEL_t channel, uint32_t val,
+ ALT_DMA_SECURITY_t sec);
+
+/*!
+ * Assembles a DMAKILL (Kill) instruction into the microcode program buffer.
+ * This instruction uses 1 byte of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ */
+// Assembler Syntax: DMAKILL
+ALT_STATUS_CODE alt_dma_program_DMAKILL(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMALD (Load) instruction into the microcode program buffer.
+ * This instruction uses 1 byte of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param mod
+ * The program instruction modifier for the type of transfer.
+ * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and
+ * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid instruction modifier specified.
+ */
+// Assembler Syntax: DMALD[S|B]
+ALT_STATUS_CODE alt_dma_program_DMALD(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PROGRAM_INST_MOD_t mod);
+
+/*!
+ * Assembles a DMALDP (Load and notify Peripheral) instruction into the
+ * microcode program buffer. This instruction uses 2 bytes of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param mod
+ * The program instruction modifier for the type of transfer.
+ * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and
+ * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
+ *
+ * \param periph
+ * The peripheral to notify.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral
+ * specified.
+ */
+// Assembler Syntax: DMALDP<S|B> <peripheral>
+ALT_STATUS_CODE alt_dma_program_DMALDP(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph);
+
+/*!
+ * Assembles a DMALP (Loop) instruction into the microcode program buffer.
+ * This instruction uses 2 bytes of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param iterations
+ * The number of iterations to run for. Valid values are 1 - 256.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid iterations specified.
+ * \retval ALT_E_BAD_OPERATION All loop registers are in use.
+ */
+// Assembler Syntax: DMALP [<LC0>|<LC1>] <loop_iterations>
+ALT_STATUS_CODE alt_dma_program_DMALP(ALT_DMA_PROGRAM_t * pgm,
+ uint32_t iterations);
+
+/*!
+ * Assembles a DMALPEND (Loop End) instruction into the microcode program
+ * buffer. This instruction uses 2 bytes of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param mod
+ * The program instruction modifier for the loop terminator. Only
+ * ALT_DMA_PROGRAM_INST_MOD_NONE, ALT_DMA_PROGRAM_INST_MOD_SINGLE
+ * and ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid instruction modifier specified.
+ * \retval ALT_E_ARG_RANGE Loop size is too large to be supported.
+ * \retval ALT_E_BAD_OPERATION A valid DMALP or DMALPFE was not added to
+ * the program buffer before adding this
+ * DMALPEND instruction.
+ */
+// Assembler Syntax: DMALPEND[S|B]
+ALT_STATUS_CODE alt_dma_program_DMALPEND(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PROGRAM_INST_MOD_t mod);
+
+/*!
+ * Assembles a DMALPFE (Loop Forever) instruction into the microcode program
+ * buffer. No instruction is added to the buffer but a previous DMALPEND to
+ * create an infinite loop.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ */
+// Assembler Syntax: DMALPFE
+ALT_STATUS_CODE alt_dma_program_DMALPFE(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMAMOV (Move) instruction into the microcode program buffer.
+ * This instruction uses 6 bytes of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param chan_reg
+ * The channel non-looping register (ALT_DMA_PROGRAM_REG_SAR,
+ * ALT_DMA_PROGRAM_REG_DAR or ALT_DMA_PROGRAM_REG_CCR) to copy
+ * the value to.
+ *
+ * \param val
+ * The value to write to the specified register.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid channel register specified.
+ */
+// Assembler Syntax: DMAMOV <destination_register>, <32-bit_immediate>
+ALT_STATUS_CODE alt_dma_program_DMAMOV(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PROGRAM_REG_t chan_reg, uint32_t val);
+
+/*!
+ * Assembles a DMANOP (No Operation) instruction into the microcode program
+ * buffer. This instruction uses 1 byte of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ */
+// Assembler Syntax: DMANOP
+ALT_STATUS_CODE alt_dma_program_DMANOP(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMARMB (Read Memory Barrier) instruction into the microcode
+ * program buffer. This instruction uses 1 byte of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ */
+// Assembler Syntax: DMARMB
+ALT_STATUS_CODE alt_dma_program_DMARMB(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMASEV (Send Event) instruction into the microcode program
+ * buffer. This instruction uses 2 byte of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param evt
+ * The event to send.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid event specified.
+ */
+// Assembler Syntax: DMASEV <event_num>
+ALT_STATUS_CODE alt_dma_program_DMASEV(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_EVENT_t evt);
+
+/*!
+ * Assembles a DMAST (Store) instruction into the microcode program buffer.
+ * This instruction uses 1 byte of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param mod
+ * The program instruction modifier for the type of transfer.
+ * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and
+ * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ */
+// Assembler Syntax: DMAST[S|B]
+ALT_STATUS_CODE alt_dma_program_DMAST(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PROGRAM_INST_MOD_t mod);
+
+/*!
+ * Assembles a DMASTP (Store and notify Peripheral) instruction into the
+ * microcode program buffer. This instruction uses 2 bytes of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param mod
+ * The program instruction modifier for the type of transfer.
+ * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE and
+ * ALT_DMA_PROGRAM_INST_MOD_BURST are valid options.
+ *
+ * \param periph
+ * The peripheral to notify.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid instruction modifier or peripheral
+ * specified.
+ */
+// Assembler Syntax: DMASTP<S|B> <peripheral>
+ALT_STATUS_CODE alt_dma_program_DMASTP(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PROGRAM_INST_MOD_t mod, ALT_DMA_PERIPH_t periph);
+
+/*!
+ * Assembles a DMASTZ (Store Zero) instruction into the microcode program
+ * buffer. This instruction uses 1 byte of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ */
+// Assembler Syntax: DMASTZ
+ALT_STATUS_CODE alt_dma_program_DMASTZ(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * Assembles a DMAWFE (Wait For Event) instruction into the microcode program
+ * buffer. This instruction uses 2 byte of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param evt
+ * The event to wait for.
+ *
+ * \param invalid
+ * If invalid is set to true, the instruction will be configured
+ * to invalidate the instruction cache for the current DMA
+ * thread.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid event specified.
+ */
+// Assembler Syntax: DMAWFE <event_num>[, invalid]
+ALT_STATUS_CODE alt_dma_program_DMAWFE(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_EVENT_t evt, bool invalid);
+
+/*!
+ * Assembles a DMAWFP (Wait for Peripheral) instruction into the microcode
+ * program buffer. This instruction uses 2 bytes of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \param periph
+ * The peripheral to wait on.
+ *
+ * \param mod
+ * The program instruction modifier for the type of transfer.
+ * Only ALT_DMA_PROGRAM_INST_MOD_SINGLE,
+ * ALT_DMA_PROGRAM_INST_MOD_BURST, or
+ * ALT_DMA_PROGRAM_INST_MOD_PERIPH are valid options.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ * \retval ALT_E_BAD_ARG Invalid peripheral or instruction modifier
+ * specified.
+ */
+// Assembler Syntax: DMAWFP <peripheral>, <single|burst|periph>
+ALT_STATUS_CODE alt_dma_program_DMAWFP(ALT_DMA_PROGRAM_t * pgm,
+ ALT_DMA_PERIPH_t periph, ALT_DMA_PROGRAM_INST_MOD_t mod);
+
+/*!
+ * Assembles a DMAWMB (Write Memory Barrier) instruction into the microcode
+ * program buffer. This instruction uses 1 byte of buffer space.
+ *
+ * \param pgm
+ * The DMA programm buffer to contain the assembled instruction.
+ *
+ * \retval ALT_E_SUCCESS Successful instruction assembly status.
+ * \retval ALT_E_DMA_BUF_OVF DMA program buffer overflow.
+ */
+// Assembler Syntax: DMAWMB
+ALT_STATUS_CODE alt_dma_program_DMAWMB(ALT_DMA_PROGRAM_t * pgm);
+
+/*!
+ * \addtogroup DMA_CCR Support for DMAMOV CCR
+ *
+ * The ALT_DMA_CCR_OPT_* macro definitions are defined here to facilitate the
+ * dynamic microcode programming of the assembler directive:
+\verbatim
+
+DMAMOV CCR, [SB<1-16>] [SS<8|16|32|64|128>] [SA<I|F>]
+ [SP<imm3>] [SC<imm4>]
+ [DB<1-16>] [DS<8|16|32|64|128>] [DA<I|F>]
+ [DP<imm3>] [DC<imm4>]
+ [ES<8|16|32|64|128>]
+
+\endverbatim
+* with a DMAMOV instruction (see: alt_dma_program_DMAMOV()).
+*
+* For example the assembler directive:
+\verbatim
+DMAMOV CCR SB1 SS32 DB1 DS32
+\endverbatim
+* would be dynamically programmed with the following API call:
+\verbatim
+alt_dma_program_DMAMOV( pgm,
+ ALT_DMA_PROGRAM_REG_CCR,
+ ( ALT_DMA_CCR_OPT_SB1
+ | ALT_DMA_CCR_OPT_SS32
+ | ALT_DMA_CCR_OPT_SA_DEFAULT
+ | ALT_DMA_CCR_OPT_SP_DEFAULT
+ | ALT_DMA_CCR_OPT_SC_DEFAULT
+ | ALT_DMA_CCR_OPT_DB1
+ | ALT_DMA_CCR_OPT_DS32
+ | ALT_DMA_CCR_OPT_DA_DEFAULT
+ | ALT_DMA_CCR_OPT_DP_DEFAULT
+ | ALT_DMA_CCR_OPT_DC_DEFAULT
+ | ALT_DMA_CCR_OPT_ES8
+ )
+ );
+\endverbatim
+*
+* Each CCR option category should be specified regardless of whether it
+* specifies a custom value or the normal default value (i.e. an
+* ALT_DMA_CCR_OPT_*_DEFAULT.
+*
+* @{
+*/
+
+/*
+ * Source Address {Fixed,Incrementing}
+ */
+/*! Source Address Fixed address burst. */
+#define ALT_DMA_CCR_OPT_SAF (0 << 0)
+/*! Source Address Incrementing address burst. */
+#define ALT_DMA_CCR_OPT_SAI (1 << 0)
+/*! Source Address Default value. */
+#define ALT_DMA_CCR_OPT_SA_DEFAULT ALT_DMA_CCR_OPT_SAI
+
+/*
+ * Source burst Size (in bits)
+ */
+/*! Source burst Size of 8 bits. */
+#define ALT_DMA_CCR_OPT_SS8 (0 << 1)
+/*! Source burst Size of 16 bits. */
+#define ALT_DMA_CCR_OPT_SS16 (1 << 1)
+/*! Source burst Size of 32 bits. */
+#define ALT_DMA_CCR_OPT_SS32 (2 << 1)
+/*! Source burst Size of 64 bits. */
+#define ALT_DMA_CCR_OPT_SS64 (3 << 1)
+/*! Source burst Size of 128 bits. */
+#define ALT_DMA_CCR_OPT_SS128 (4 << 1)
+/*! Source burst Size default bits. */
+#define ALT_DMA_CCR_OPT_SS_DEFAULT ALT_DMA_CCR_OPT_SS8
+
+/*
+ * Source burst Length (in transfer(s))
+ */
+/*! Source Burst length of 1 transfer. */
+#define ALT_DMA_CCR_OPT_SB1 (0x0 << 4)
+/*! Source Burst length of 2 transfers. */
+#define ALT_DMA_CCR_OPT_SB2 (0x1 << 4)
+/*! Source Burst length of 3 transfers. */
+#define ALT_DMA_CCR_OPT_SB3 (0x2 << 4)
+/*! Source Burst length of 4 transfers. */
+#define ALT_DMA_CCR_OPT_SB4 (0x3 << 4)
+/*! Source Burst length of 5 transfers. */
+#define ALT_DMA_CCR_OPT_SB5 (0x4 << 4)
+/*! Source Burst length of 6 transfers. */
+#define ALT_DMA_CCR_OPT_SB6 (0x5 << 4)
+/*! Source Burst length of 7 transfers. */
+#define ALT_DMA_CCR_OPT_SB7 (0x6 << 4)
+/*! Source Burst length of 8 transfers. */
+#define ALT_DMA_CCR_OPT_SB8 (0x7 << 4)
+/*! Source Burst length of 9 transfers. */
+#define ALT_DMA_CCR_OPT_SB9 (0x8 << 4)
+/*! Source Burst length of 10 transfers. */
+#define ALT_DMA_CCR_OPT_SB10 (0x9 << 4)
+/*! Source Burst length of 11 transfers. */
+#define ALT_DMA_CCR_OPT_SB11 (0xa << 4)
+/*! Source Burst length of 12 transfers. */
+#define ALT_DMA_CCR_OPT_SB12 (0xb << 4)
+/*! Source Burst length of 13 transfers. */
+#define ALT_DMA_CCR_OPT_SB13 (0xc << 4)
+/*! Source Burst length of 14 transfers. */
+#define ALT_DMA_CCR_OPT_SB14 (0xd << 4)
+/*! Source Burst length of 15 transfers. */
+#define ALT_DMA_CCR_OPT_SB15 (0xe << 4)
+/*! Source Burst length of 16 transfers. */
+#define ALT_DMA_CCR_OPT_SB16 (0xf << 4)
+/*! Source Burst length default transfers. */
+#define ALT_DMA_CCR_OPT_SB_DEFAULT ALT_DMA_CCR_OPT_SB1
+
+/*
+ * Source Protection
+ */
+/*! Source Protection bits for AXI bus ARPROT[2:0]. */
+#define ALT_DMA_CCR_OPT_SP(imm3) ((imm3) << 8)
+/*! Source Protection bits default value. */
+#define ALT_DMA_CCR_OPT_SP_DEFAULT ALT_DMA_CCR_OPT_SP(0)
+
+/*
+ * Source cache
+ */
+/*! Source Cache bits for AXI bus ARCACHE[2:0]. */
+#define ALT_DMA_CCR_OPT_SC(imm4) ((imm4) << 11)
+/*! Source Cache bits default value. */
+#define ALT_DMA_CCR_OPT_SC_DEFAULT ALT_DMA_CCR_OPT_SC(0)
+
+/*
+ * Destination Address {Fixed,Incrementing}
+ */
+/*! Destination Address Fixed address burst. */
+#define ALT_DMA_CCR_OPT_DAF (0 << 14)
+/*! Destination Address Incrementing address burst. */
+#define ALT_DMA_CCR_OPT_DAI (1 << 14)
+/*! Destination Address Default value. */
+#define ALT_DMA_CCR_OPT_DA_DEFAULT ALT_DMA_CCR_OPT_DAI
+
+/*
+ * Destination burst Size (in bits)
+ */
+/*! Destination burst Size of 8 bits. */
+#define ALT_DMA_CCR_OPT_DS8 (0 << 15)
+/*! Destination burst Size of 16 bits. */
+#define ALT_DMA_CCR_OPT_DS16 (1 << 15)
+/*! Destination burst Size of 32 bits. */
+#define ALT_DMA_CCR_OPT_DS32 (2 << 15)
+/*! Destination burst Size of 64 bits. */
+#define ALT_DMA_CCR_OPT_DS64 (3 << 15)
+/*! Destination burst Size of 128 bits. */
+#define ALT_DMA_CCR_OPT_DS128 (4 << 15)
+/*! Destination burst Size default bits. */
+#define ALT_DMA_CCR_OPT_DS_DEFAULT ALT_DMA_CCR_OPT_DS8
+
+/*
+ * Destination Burst length (in transfer(s))
+ */
+/*! Destination Burst length of 1 transfer. */
+#define ALT_DMA_CCR_OPT_DB1 (0x0 << 18)
+/*! Destination Burst length of 2 transfers. */
+#define ALT_DMA_CCR_OPT_DB2 (0x1 << 18)
+/*! Destination Burst length of 3 transfers. */
+#define ALT_DMA_CCR_OPT_DB3 (0x2 << 18)
+/*! Destination Burst length of 4 transfers. */
+#define ALT_DMA_CCR_OPT_DB4 (0x3 << 18)
+/*! Destination Burst length of 5 transfers. */
+#define ALT_DMA_CCR_OPT_DB5 (0x4 << 18)
+/*! Destination Burst length of 6 transfers. */
+#define ALT_DMA_CCR_OPT_DB6 (0x5 << 18)
+/*! Destination Burst length of 7 transfers. */
+#define ALT_DMA_CCR_OPT_DB7 (0x6 << 18)
+/*! Destination Burst length of 8 transfers. */
+#define ALT_DMA_CCR_OPT_DB8 (0x7 << 18)
+/*! Destination Burst length of 9 transfers. */
+#define ALT_DMA_CCR_OPT_DB9 (0x8 << 18)
+/*! Destination Burst length of 10 transfers. */
+#define ALT_DMA_CCR_OPT_DB10 (0x9 << 18)
+/*! Destination Burst length of 11 transfers. */
+#define ALT_DMA_CCR_OPT_DB11 (0xa << 18)
+/*! Destination Burst length of 12 transfers. */
+#define ALT_DMA_CCR_OPT_DB12 (0xb << 18)
+/*! Destination Burst length of 13 transfers. */
+#define ALT_DMA_CCR_OPT_DB13 (0xc << 18)
+/*! Destination Burst length of 14 transfers. */
+#define ALT_DMA_CCR_OPT_DB14 (0xd << 18)
+/*! Destination Burst length of 15 transfers. */
+#define ALT_DMA_CCR_OPT_DB15 (0xe << 18)
+/*! Destination Burst length of 16 transfers. */
+#define ALT_DMA_CCR_OPT_DB16 (0xf << 18)
+/*! Destination Burst length default transfers. */
+#define ALT_DMA_CCR_OPT_DB_DEFAULT ALT_DMA_CCR_OPT_DB1
+
+/*
+ * Destination Protection
+ */
+/*! Destination Protection bits for AXI bus AWPROT[2:0]. */
+#define ALT_DMA_CCR_OPT_DP(imm3) ((imm3) << 22)
+/*! Destination Protection bits default value. */
+#define ALT_DMA_CCR_OPT_DP_DEFAULT ALT_DMA_CCR_OPT_DP(0)
+
+/*
+ * Destination Cache
+ */
+/*! Destination Cache bits for AXI bus AWCACHE[3,1:0]. */
+#define ALT_DMA_CCR_OPT_DC(imm4) ((imm4) << 25)
+/*! Destination Cache bits default value. */
+#define ALT_DMA_CCR_OPT_DC_DEFAULT ALT_DMA_CCR_OPT_DC(0)
+
+/*
+ * Endian Swap size (in bits)
+ */
+/*! Endian Swap: No swap, 8-bit data. */
+#define ALT_DMA_CCR_OPT_ES8 (0 << 28)
+/*! Endian Swap: Swap bytes within 16-bit data. */
+#define ALT_DMA_CCR_OPT_ES16 (1 << 28)
+/*! Endian Swap: Swap bytes within 32-bit data. */
+#define ALT_DMA_CCR_OPT_ES32 (2 << 28)
+/*! Endian Swap: Swap bytes within 64-bit data. */
+#define ALT_DMA_CCR_OPT_ES64 (3 << 28)
+/*! Endian Swap: Swap bytes within 128-bit data. */
+#define ALT_DMA_CCR_OPT_ES128 (4 << 28)
+/*! Endian Swap: Default byte swap. */
+#define ALT_DMA_CCR_OPT_ES_DEFAULT ALT_DMA_CCR_OPT_ES8
+
+/*! Default CCR register options for a DMAMOV CCR assembler directive. */
+#define ALT_DMA_CCR_OPT_DEFAULT \
+ (ALT_DMA_CCR_OPT_SB1 | ALT_DMA_CCR_OPT_SS8 | ALT_DMA_CCR_OPT_SAI | \
+ ALT_DMA_CCR_OPT_SP(0) | ALT_DMA_CCR_OPT_SC(0) | \
+ ALT_DMA_CCR_OPT_DB1 | ALT_DMA_CCR_OPT_DS8 | ALT_DMA_CCR_OPT_DAI | \
+ ALT_DMA_CCR_OPT_DP(0) | ALT_DMA_CCR_OPT_DC(0) | \
+ ALT_DMA_CCR_OPT_ES8)
+
+/*!
+ * @}
+ */
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_DMA_PROGRAM_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h
new file mode 100644
index 0000000000..0a7abaef8e
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_generalpurpose_io.h
@@ -0,0 +1,1254 @@
+/*! \file
+ * Altera - GPIO Module
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __ALT_GPIO_H__
+#define __ALT_GPIO_H__
+
+#include <stdint.h>
+#include "hwlib.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#define ALT_GPIO_BITMASK 0x1FFFFFFF
+
+/* If the GPIO special test mode flag was not defined in the makefile, */
+ /* set the ALT_GPIO_DATAREAD_TEST_MODE flag to false to specify that */
+ /* the production code version of alt_gpio_port_data_read() is included. */
+ /* If the flag is defined as true in the makefile, then the test version */
+ /* located in the test code file is substituted instead of the version */
+ /* in this file. */
+#ifndef ALT_GPIO_DATAREAD_TEST_MODE
+#define ALT_GPIO_DATAREAD_TEST_MODE false
+#endif
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_API The General Purpose Input/Output Manager API
+ *
+ * This module defines the General Purpose Input/Output Manager API for
+ * accessing, configuring, and controlling the General Purpose Input/Output
+ * Manager resources. These include both the general-purpose GPIO signals and
+ * the input-only GPI signals that are shared with the DDR interface.\n \n
+ * The GPIO API presents two views or perspectives of the GPIO signals. The first
+ * is to view the GPIO signals in a traditional way, as separate GPIO ports
+ * each comprised of a number of GPIO bits. The second perspective is of a
+ * unified flat view that presents the GPIO and GPI signals as a set of indexed
+ * bits, a view that allows the programmer to mostly ignore the port and pin
+ * hardware configuration and read/write/configure the GPIO and GPI signals
+ * independently of the underlying hardware implementation.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions
+ *
+ * This functional group contains functions to control, configure and manage
+ * the general-purpose IO signals as individual signals or as groups of signals.
+ * This group of functions can operate on multiple bits within the same GPIO
+ * port and accepts a bit mask to specify which bits an operation will operate on.
+ * Other bits within the same GPIO port are not changed.
+ *
+ * This example shows how multiple drivers or applications can use this feature
+ * to easily prevent conflict while accessing the same GPIO port:
+ * \verbatim
+ #define DRIVER_0_GPIO_MSK 0x0010FF03;
+ #define DRIVER_1_GPIO_MSK 0x002000F8;
+ #define DRIVER_2_GPIO_MSK 0x03C00004;
+ #define DRIVER_3_GPIO_MSK 0x000F0000;
+
+ alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_0_GPIO_MSK, init_val0);
+ alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, init_val1);
+ alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_2_GPIO_MSK, init_val2);
+ alt_gpio_port_data_write(ALT_GPIO_PORTA, DRIVER_3_GPIO_MSK, init_val3);
+ alt_gpio_port_int_type_set(ALT_GPIO_PORTA, DRIVER_1_GPIO_MSK, config_val1);
+ \endverbatim
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * This type definition enumerates the data direction (input or output) of
+ * the GPIO signals.
+ */
+
+typedef enum ALT_GPIO_PIN_DIR_e
+{
+ /*! # */
+ ALT_GPIO_PIN_INPUT,
+ /*! # */
+ ALT_GPIO_PIN_OUTPUT
+} ALT_GPIO_PIN_DIR_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the type of interrupt source
+ * (level-triggered or edge-triggered) of the GPIO signals.
+ */
+
+typedef enum ALT_GPIO_PIN_TYPE_e
+{
+ /*! # */
+ ALT_GPIO_PIN_LEVEL_TRIG_INT,
+ /*! # */
+ ALT_GPIO_PIN_EDGE_TRIG_INT
+} ALT_GPIO_PIN_TYPE_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the polarity of the interrupt sources
+ * (falling-edge or rising-edge for edge-triggered interrupts, active-low or
+ * active-high for level-triggered interrupts) of the GPIO signals.
+ */
+
+typedef enum ALT_GPIO_PIN_POL_e
+{
+ /*! Indicates active-low for level-triggered interrupts and
+ * falling-edge for edge-triggered interrupts */
+ ALT_GPIO_PIN_ACTIVE_LOW,
+
+ /*! Indicates active-high for level-triggered interrupts and
+ * rising-edge for edge-triggered interrupt */
+ ALT_GPIO_PIN_ACTIVE_HIGH
+} ALT_GPIO_PIN_POL_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates whether or not the debounce metastability
+ * flip-flops are inserted or not. These are used to debounce signals presented
+ * to the GPIO inputs. A signal must be steady for two periods of the
+ * gpio_db_clk clock before it is considered valid. The frequency of the
+ * gpio_db_clk clock may be set using the Clock Manager API.
+ */
+
+typedef enum ALT_GPIO_PIN_DEBOUNCE_e
+{
+ /*! # */
+ ALT_GPIO_PIN_NODEBOUNCE,
+ /*! # */
+ ALT_GPIO_PIN_DEBOUNCE
+} ALT_GPIO_PIN_DEBOUNCE_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates whether or not level-sensitive interrupts
+ * are synchronized to the internal pclk_intr clock. It has no effect for GPIO
+ * signals that are selected as outputs, or if the interrupt is not enabled,
+ * or if the interrupt is set to be edge-triggered. This is a port-wide option.
+ */
+
+typedef enum ALT_GPIO_PIN_SYNC_e
+{
+ /*! # */
+ ALT_GPIO_PIN_NOSYNC,
+ /*! # */
+ ALT_GPIO_PIN_SYNC
+} ALT_GPIO_PIN_SYNC_t;
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the possible data states of the GPIO bits.
+ */
+
+typedef enum ALT_GPIO_PIN_DATA_e
+{
+ /*! # */
+ ALT_GPIO_PIN_DATAZERO,
+ /*! # */
+ ALT_GPIO_PIN_DATAONE
+} ALT_GPIO_PIN_DATA_t;
+
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the GPIO ports that the GPIO manager
+ * handles.
+ */
+
+typedef enum ALT_GPIO_PORT_e
+{
+ /*!
+ * \b Port \b A - 29-bit GPIO port A.
+ */
+ ALT_GPIO_PORTA,
+
+ /*!
+ * \b Port \b B - 29-bit GPIO port B.
+ */
+ ALT_GPIO_PORTB,
+
+ /*!
+ * \b Port \b C - 29-bit GPIO port C. \n 13 bits are used for GPIO signals,
+ * 14 bits are used for GPI-only signals that are shared
+ * with the DDR interface, 2 bits are not used. Some signals
+ * may not be connected on some versions. See the relevant
+ * pin mux data.
+ */
+ ALT_GPIO_PORTC,
+
+ /*!
+ * \b Unknown \b Port - Used to indicate an error.
+ */
+ ALT_GPIO_PORT_UNKNOWN
+} ALT_GPIO_PORT_t;
+
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the individual bits within the GPIO ports
+ * used by the GPIO manager. The bit-ordering must match the hardware
+ * bit-ordering. Since the ordering and packing of bitfields is not
+ * standardized in C/C++, the following are defined as masks. \n
+ * For example, to set bits 3 and 4 of GPIO port B outputs (assuming the bits
+ * had previously been set to outputs), the user could use the syntax: \par
+ * \b alt_gpio_port_data_write(\b ALT_GPIO_PORTB, \b ALT_GPIO_BIT3 \b | \b
+ * ALT_GPIO_BIT4);
+ */
+
+typedef enum ALT_GPIO_PORTBIT_e
+{
+ /*! # */
+ ALT_GPIO_BIT0 = ALT_TWO_TO_POW0,
+ /*! # */
+ ALT_GPIO_BIT1 = ALT_TWO_TO_POW1,
+ /*! # */
+ ALT_GPIO_BIT2 = ALT_TWO_TO_POW2,
+ /*! # */
+ ALT_GPIO_BIT3 = ALT_TWO_TO_POW3,
+ /*! # */
+ ALT_GPIO_BIT4 = ALT_TWO_TO_POW4,
+ /*! # */
+ ALT_GPIO_BIT5 = ALT_TWO_TO_POW5,
+ /*! # */
+ ALT_GPIO_BIT6 = ALT_TWO_TO_POW6,
+ /*! # */
+ ALT_GPIO_BIT7 = ALT_TWO_TO_POW7,
+ /*! # */
+ ALT_GPIO_BIT8 = ALT_TWO_TO_POW8,
+ /*! # */
+ ALT_GPIO_BIT9 = ALT_TWO_TO_POW9,
+ /*! # */
+ ALT_GPIO_BIT10 = ALT_TWO_TO_POW10,
+ /*! # */
+ ALT_GPIO_BIT11 = ALT_TWO_TO_POW11,
+ /*! # */
+ ALT_GPIO_BIT12 = ALT_TWO_TO_POW12,
+ /*! # */
+ ALT_GPIO_BIT13 = ALT_TWO_TO_POW13,
+ /*! # */
+ ALT_GPIO_BIT14 = ALT_TWO_TO_POW14,
+ /*! # */
+ ALT_GPIO_BIT15 = ALT_TWO_TO_POW15,
+ /*! # */
+ ALT_GPIO_BIT16 = ALT_TWO_TO_POW16,
+ /*! # */
+ ALT_GPIO_BIT17 = ALT_TWO_TO_POW17,
+ /*! # */
+ ALT_GPIO_BIT18 = ALT_TWO_TO_POW18,
+ /*! # */
+ ALT_GPIO_BIT19 = ALT_TWO_TO_POW19,
+ /*! # */
+ ALT_GPIO_BIT20 = ALT_TWO_TO_POW20,
+ /*! # */
+ ALT_GPIO_BIT21 = ALT_TWO_TO_POW21,
+ /*! # */
+ ALT_GPIO_BIT22 = ALT_TWO_TO_POW22,
+ /*! # */
+ ALT_GPIO_BIT23 = ALT_TWO_TO_POW23,
+ /*! # */
+ ALT_GPIO_BIT24 = ALT_TWO_TO_POW24,
+ /*! # */
+ ALT_GPIO_BIT25 = ALT_TWO_TO_POW25,
+ /*! # */
+ ALT_GPIO_BIT26 = ALT_TWO_TO_POW26,
+ /*! # */
+ ALT_GPIO_BIT27 = ALT_TWO_TO_POW27,
+ /*! # */
+ ALT_GPIO_BIT28 = ALT_TWO_TO_POW28,
+ ALT_GPIO_BIT29 = ALT_TWO_TO_POW29, /* Not currently used */
+ ALT_GPIO_BIT30 = ALT_TWO_TO_POW30, /* Not currently used */
+ ALT_GPIO_BIT31 = (int32_t) (1UL<<31), /* Not currently used */
+
+ ALT_GPIO_BITNUM_MAX = (28),
+ ALT_GPIO_BIT_MAX = (1 << ALT_GPIO_BITNUM_MAX),
+ ALT_END_OF_GPIO_PORT_SIGNALS = (32)
+} ALT_GPIO_PORTBIT_t;
+
+
+
+/******************************************************************************/
+/*!
+ * Initialize the GPIO modules before use
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_gpio_init(void);
+
+/******************************************************************************/
+/*!
+ * Uninitialize the GPIO modules & return to reset state
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_gpio_uninit(void);
+
+/******************************************************************************/
+/*!
+ * Sets the specified GPIO data bits to use the data direction(s)
+ * specified.
+ *
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits (where mask bits equal one) to apply this
+ * operation to. Other bits (where mask bits equal zero) are
+ * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ * configure all data direction bits of the port.
+ * \param config
+ * The data-directions of the bits to be set in this operation.
+ * Individual bits are: \n \b 0 - Use as an input (default). \n
+ * \b 1 - Use as an output.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_datadir_set(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the data direction configuration of selected bits of the
+ * specified GPIO module.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits (where mask bits equal one) to read and
+ * return. Other bits (where mask bits equal zero) are returned
+ * as zero. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ * return all data direction bits of the port.
+ *
+ * \retval uint32_t \n Individual bits are: \n \b 0 - The signal is
+ * configured as an input.
+ * \n \b 1 - The signal is configured as an output.
+ *
+ */
+uint32_t alt_gpio_port_datadir_get(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask);
+
+/******************************************************************************/
+/*!
+ * Sets the GPIO data outputs of the specified GPIO module to a logic one or
+ * zero. Outputs are only set if the data direction for those bits is also
+ * set to configure them as outputs.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits (mask bits equal one) to apply this
+ * operation to. Other bits (mask bits equal zero) are
+ * not changed.
+ * \param val
+ * The 32-bit word to write to the GPIO outputs. Only the 29 LSBs
+ * are used. Setting the three MSBs causes an error.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_data_write(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask, uint32_t val);
+
+/******************************************************************************/
+/*!
+ * Returns the value of the data inputs of the specified GPIO module. This is
+ * the current logic value of the pin, whether set to be an input or an output.
+ * \n If a given signal is set to be an output, this input value can be read to
+ * determine if the pin is grounded, pulled high, or is floating.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits (where mask bits equal one) to return. Other
+ * bits (where mask bits equal zero) are returned as zero. Specify
+ * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all data bits of
+ * the port.
+ *
+ * \retval uint32_t The current value of the GPIO module input signals.
+ */
+uint32_t alt_gpio_port_data_read(ALT_GPIO_PORT_t gpio_pid, uint32_t mask);
+
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions
+ *
+ * This functional group contains functions to control and manage the
+ * interrupts of the General-Purpose IO modules.
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Sets edge-triggered or level-triggered interrupt configuration for the
+ * specified signals of the specified GPIO module.
+ *
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits (where mask bits equal one) to apply this
+ * operation to. Other bits (where mask bits equal zero) are
+ * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ * configure all interrupt type bits of the port.
+ * \param config
+ * The interrupt configuration to write. Individual bits
+ * are: \n \b 0 - Set the
+ * interrupt for this bit to be level-sensitive (default). \n \b
+ * 1 - Set the interrupt for this bit to be edge-sensitive.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_type_set(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the interrupt configuration (edge-triggered or level-triggered) for
+ * the specified bits of the specified GPIO module.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits (where mask bits equal one) to return. Other
+ * bits (where mask bits equal zero) are returned as zero. Specify
+ * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all configuration
+ * bits of the port.
+ * \retval uint32_t
+ * The current interrupt source configuration. Individual bits
+ * are: \n \b 0 - The interrupt for this bit is set to be
+ * level-sensitive. \n \b 1 -
+ * The interrupt for this bit is set to be edge-sensitive.
+ *
+ */
+uint32_t alt_gpio_port_int_type_get(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask);
+
+/******************************************************************************/
+/*!
+ * Sets the interrupt polarity of the signals of the specified GPIO register
+ * (when used as inputs) to active-high or active-low (for level-sensitive
+ * interrupts) or to rising-edge or falling-edge (for edge-sensitive interrupts).
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits (where mask bits equal one) to apply this
+ * operation to. Other bits (where mask bits equal zero) are
+ * not changed.
+ * \param config
+ * The interrupt polarity configuration to set. Individual bits
+ * are: \n \b 0 - Set the interrupt polarity for this bit to
+ * active-low or falling-edge mode (default). \n \b 1 - Set the
+ * interrupt polarity for this bit to active-high or rising-edge mode.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_pol_set(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the active-high or active-low polarity configuration for the
+ * possible interrupt sources of the specified GPIO module.
+ *
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits (where mask bits equal one) to return. Other
+ * bits (where mask bits equal zero) are returned as zero. Specify
+ * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all the
+ * configuration bits of the port.
+ *
+ * \retval uint32_t
+ * The current polarity configuration. Individual bits are: \n
+ * \b 0 = The interrupt polarity for this bit is set to
+ * active-low or falling-edge mode. \n \b 1 = The interrupt
+ * polarity for this bit is set to active-high or rising-edge mode.
+ *
+ */
+uint32_t alt_gpio_port_int_pol_get(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask);
+
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_API_CONFIG General-Purpose IO Configuration Functions
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Sets the debounce configuration for input signals of the specified GPIO
+ * module. If debounce is selected, metastability flip-flops are inserted to
+ * debounce signals presented to the GPIO inputs. A signal must be steady for
+ * two periods of the gpio_db_clk clock before it is considered valid. The
+ * frequency of the gpio_db_clk clock may be set using the Clock Manager API.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits (where mask bits equal one) to apply this
+ * operation to. Other bits (where mask bits equal zero) are
+ * not changed. Specify mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to
+ * configure the debounce setting for all bits of the port.
+ * \param config
+ * The debounce configuration to set. Individual bits are: \n
+ * \b 0 - Debounce is not selected for this signal (default). \n
+ * \b 1 - Debounce is selected for this signal.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_debounce_set(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the debounce configuration for the input signals of the specified
+ * GPIO register. If debounce is selected, metastability flip-flops are
+ * inserted to debounce signals presented to the GPIO inputs.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits (where mask bits equal one) to return. Other
+ * bits (where mask bits equal zero) are returned as zero. Specify
+ * mask = ALT_GPIO_BITMASK (0x1FFFFFFF) to return all debounce
+ * configuration bits of the port.
+ *
+ * \retval uint32_t
+ * The current debounce configuration.Individual bits are: \n
+ * \b 0 - Debounce is not selected for this signal. \n \b 1 -
+ * Debounce is selected for this signal.
+ *
+ */
+uint32_t alt_gpio_port_debounce_get(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask);
+
+/******************************************************************************/
+/*!
+ * Sets the synchronization configuration for the signals of the specified
+ * GPIO register. This allows for synchronizing level-sensitive interrupts to
+ * an internal clock signal. This is a port-wide option that controls all
+ * level-sensitive interrupt signals of that GPIO port.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param config
+ * \n \b Any \b non-zero \b value - Synchronize to internal clock signal.
+ * \n \b Zero - Do not synchronize to internal clock signal.
+ *
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_sync_set(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t config);
+
+/******************************************************************************/
+/*!
+ *
+ * Returns the synchronization configuration for the signals of the
+ * specified GPIO register. This allows for synchronizing level-sensitive
+ * interrupts to the internal clock signal. This is a port-wide option that
+ * controls all level-sensitive interrupt signals of that GPIO port.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+
+
+ * \retval ALT_E_TRUE Synchronization to clock is enabled for
+ * level-sensitive interrupts.
+ * \retval ALT_E_FALSE Synchronization to clock is disabled for
+ * level-sensitive interrupts.
+ * \retval ALT_E_BAD_ARG Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_sync_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Configures a group of GPIO signals with identical setup parameters. Allows
+ * for configuring all parameters of a given port at one time.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * The group of bits to apply this operation to. Other bits (mask
+ * set to zero) are not changed.
+ * \param dir
+ * Data direction.
+ * \param type
+ * Edge-triggered or level-triggered interrupts.
+ * \param pol
+ * Active-high or active-low polarity.
+ * \param debounc
+ * Debounce signals or not.
+ * \param data
+ * Set the data output to this value.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input argument.
+
+ */
+ALT_STATUS_CODE alt_gpio_port_config(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask, ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
+ ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounc,
+ uint32_t data);
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_INT General-Purpose IO Interrupt Functions
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Enables the specified GPIO data input interrupts.
+ *
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param config
+ * Individual bit interrupt enables \n
+ * \b 0 - Interrupt disabled. \n
+ * \b 1 - Interrupt enabled.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_enable(ALT_GPIO_PORT_t gpio_pid, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Disables the specified GPIO data module interrupt.
+ *
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param config
+ * Individual bit interrupt enables \n
+ * \b 0 - Interrupt disabled. \n
+ * \b 1 - Interrupt enabled.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Bad input argument.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_disable(ALT_GPIO_PORT_t gpio_pid, uint32_t config);
+
+/******************************************************************************/
+/*!
+ * Returns the current state of the specified GPIO port interrupts enables.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ *
+ * \retval uint32_t
+ * The interrupt enable configuration that was read. Individual bits
+ * are: \n \b 0 = The interrupt for this bit is not enabled. \n \b
+ * 1 = The interrupt for this bit is enabled.
+ */
+uint32_t alt_gpio_port_int_enable_get(ALT_GPIO_PORT_t gpio_pid);
+
+
+/******************************************************************************/
+/*!
+ * Masks or unmasks selected interrupt source bits of the data register of
+ * the specified GPIO module. Uses a second bit mask to determine which
+ * signals may be changed by this call.
+ *
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param mask
+ * Which bits to change among the port \n \b 0 =
+ * Do not change this bit. \n \b 1 = Allow this bit to change.
+ * \param val
+ * The interrupt mask to write. Individual bits are: \n \b 0 =
+ * Do not mask the interrupt for this bit (default). \n \b 1 =
+ * Mask the interrupt for this bit.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_mask_set(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t mask, uint32_t val);
+
+/******************************************************************************/
+/*!
+ * Returns the interrupt mask of the specified GPIO module.
+ *
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ *
+ * \retval uint32_t
+ * The interrupt mask that was read. Individual bits are: \n
+ * \b 0 = The interrupt for this bit is not masked. \n \b 1 = The
+ * interrupt for this bit is masked.
+ *
+ */
+uint32_t alt_gpio_port_int_mask_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Returns the interrupt pending status of all signals of the specified GPIO
+ * register.
+ *
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+
+ * \retval uint32_t
+ * The current interrupt pending status. Individual bits are: \n
+ * \b 0 - The interrupt for this bit is not pending. \n \b 1 -
+ * The interrupt for this bit is pending.
+ *
+ */
+uint32_t alt_gpio_port_int_status_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Clear the interrupt pending status of selected signals of the
+ * specified GPIO register.
+ *
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ * \param clrmask
+ * The interrupt bits to clear. Individual bits are: \n \b 0 -
+ * The interrupt for this bit will not be changed. \n \b 1 -
+ * The interrupt for this bit will be cleared.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input data.
+ */
+ALT_STATUS_CODE alt_gpio_port_int_status_clear(ALT_GPIO_PORT_t gpio_pid,
+ uint32_t clrmask);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index
+ *
+ * This functional group presents a perspective of the General-Purpose IO
+ * signals as individual GPIO and GPI bits spread across a number of signals
+ * across several GPIO ports. This allows the programmer the freedom to generally
+ * ignore the underlying port and signal structure of the GPIO hardware if
+ * desired.
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * This type definition enumerates the individual bits as one flat array spread
+ * across the multiple GPIO ports handled by the GPIO manager. The bit-ordering
+ * must match the hardware bit-ordering.
+ *
+ */
+typedef enum ALT_GPIO_1BIT_e
+{
+ /*! # */
+ ALT_GPIO_1BIT_0,
+ /*! # */
+ ALT_GPIO_1BIT_1,
+ /*! # */
+ ALT_GPIO_1BIT_2,
+ /*! # */
+ ALT_GPIO_1BIT_3,
+ /*! # */
+ ALT_GPIO_1BIT_4,
+ /*! # */
+ ALT_GPIO_1BIT_5,
+ /*! # */
+ ALT_GPIO_1BIT_6,
+ /*! # */
+ ALT_GPIO_1BIT_7,
+ /*! # */
+ ALT_GPIO_1BIT_8,
+ /*! # */
+ ALT_GPIO_1BIT_9,
+ /*! # */
+ ALT_GPIO_1BIT_10,
+ /*! # */
+ ALT_GPIO_1BIT_11,
+ /*! # */
+ ALT_GPIO_1BIT_12,
+ /*! # */
+ ALT_GPIO_1BIT_13,
+ /*! # */
+ ALT_GPIO_1BIT_14,
+ /*! # */
+ ALT_GPIO_1BIT_15,
+ /*! # */
+ ALT_GPIO_1BIT_16,
+ /*! # */
+ ALT_GPIO_1BIT_17,
+ /*! # */
+ ALT_GPIO_1BIT_18,
+ /*! # */
+ ALT_GPIO_1BIT_19,
+ /*! # */
+ ALT_GPIO_1BIT_20,
+ /*! # */
+ ALT_GPIO_1BIT_21,
+ /*! # */
+ ALT_GPIO_1BIT_22,
+ /*! # */
+ ALT_GPIO_1BIT_23,
+ /*! # */
+ ALT_GPIO_1BIT_24,
+ /*! # */
+ ALT_GPIO_1BIT_25,
+ /*! # */
+ ALT_GPIO_1BIT_26,
+ /*! # */
+ ALT_GPIO_1BIT_27,
+ /*! # */
+ ALT_GPIO_1BIT_28,
+ /*! # */
+ ALT_GPIO_1BIT_29,
+ /*! # */
+ ALT_GPIO_1BIT_30,
+ /*! # */
+ ALT_GPIO_1BIT_31,
+ /*! # */
+ ALT_GPIO_1BIT_32,
+ /*! # */
+ ALT_GPIO_1BIT_33,
+ /*! # */
+ ALT_GPIO_1BIT_34,
+ /*! # */
+ ALT_GPIO_1BIT_35,
+ /*! # */
+ ALT_GPIO_1BIT_36,
+ /*! # */
+ ALT_GPIO_1BIT_37,
+ /*! # */
+ ALT_GPIO_1BIT_38,
+ /*! # */
+ ALT_GPIO_1BIT_39,
+ /*! # */
+ ALT_GPIO_1BIT_40,
+ /*! # */
+ ALT_GPIO_1BIT_41,
+ /*! # */
+ ALT_GPIO_1BIT_42,
+ /*! # */
+ ALT_GPIO_1BIT_43,
+ /*! # */
+ ALT_GPIO_1BIT_44,
+ /*! # */
+ ALT_GPIO_1BIT_45,
+ /*! # */
+ ALT_GPIO_1BIT_46,
+ /*! # */
+ ALT_GPIO_1BIT_47,
+ /*! # */
+ ALT_GPIO_1BIT_48,
+ /*! # */
+ ALT_GPIO_1BIT_49,
+ /*! # */
+ ALT_GPIO_1BIT_50,
+ /*! # */
+ ALT_GPIO_1BIT_51,
+ /*! # */
+ ALT_GPIO_1BIT_52,
+ /*! # */
+ ALT_GPIO_1BIT_53,
+ /*! # */
+ ALT_GPIO_1BIT_54,
+ /*! # */
+ ALT_GPIO_1BIT_55,
+ /*! # */
+ ALT_GPIO_1BIT_56,
+ /*! # */
+ ALT_GPIO_1BIT_57,
+ /*! # */
+ ALT_GPIO_1BIT_58,
+ /*! # */
+ ALT_GPIO_1BIT_59,
+ /*! # */
+ ALT_GPIO_1BIT_60,
+ /*! # */
+ ALT_GPIO_1BIT_61,
+ /*! # */
+ ALT_GPIO_1BIT_62,
+ /*! # */
+ ALT_GPIO_1BIT_63,
+ /*! # */
+ ALT_GPIO_1BIT_64,
+ /*! # */
+ ALT_GPIO_1BIT_65,
+ /*! # */
+ ALT_GPIO_1BIT_66,
+ /*! # */
+ ALT_GPIO_1BIT_67, /* Not bonded out on some versions */
+ /*! # */
+ ALT_GPIO_1BIT_68, /* Not bonded out on some versions */
+ /*! # */
+ ALT_GPIO_1BIT_69, /* Not bonded out on some versions */
+
+ /*! The last of the input/output bits */
+ ALT_GPIO_1BIT_70, /* Not bonded out on some versions */
+
+
+ /*! This and the following signals are not present on all SoCs. \n
+ * If present, the selection between their use as 14 General-purpose inputs or
+ * use as 14 DDR interface signals is made in the IOCSR (IO Configuration Shift
+ * Register) and software to make this selection is in the IO Manager API. If
+ * they are present, they are restricted to using the same power supply voltage
+ * as the SDRAM module.*/
+ ALT_HLGPI_0, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_1, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_2, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_3, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_4, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_5, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_6, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_7, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_8, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_9, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_10, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_11, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_12, /* Not bonded out on some versions */
+ /*! # */
+ ALT_HLGPI_13, /* Not bonded out on some versions */
+
+ ALT_HLGPI_14, /* Not bonded out */
+
+ ALT_HLGPI_15, /* Not bonded out */
+
+ ALT_GPIO_INVALID,
+ ALT_END_OF_GPIO_SIGNALS = -1,
+ ALT_LAST_VALID_GPIO_BIT = ALT_HLGPI_15
+} ALT_GPIO_1BIT_t;
+
+
+/******************************************************************************/
+/*!
+ * This configuration record definition is used for configuring bits and
+ * groups of bits of the GPIO interface.
+ */
+typedef struct ALT_GPIO_CONFIG_RECORD_s
+{
+ /*!
+ * The index number of the signal to configure. */
+ ALT_GPIO_1BIT_t signal_number;
+ /*!
+ * The data direction of the signal. */
+ ALT_GPIO_PIN_DIR_t direction;
+ /*!
+ * Edge-triggered or level triggered interrupts. */
+ ALT_GPIO_PIN_TYPE_t type;
+ /*!
+ * Active-high or active-low trigger for the interrupt. */
+ ALT_GPIO_PIN_POL_t polarity;
+ /*!
+ * Enable or disable GPIO debounce capability. */
+ ALT_GPIO_PIN_DEBOUNCE_t debounce;
+ /*!
+ * If the signal is an output, the data value to be output. */
+ ALT_GPIO_PIN_DATA_t data;
+} ALT_GPIO_CONFIG_RECORD_t;
+
+/******************************************************************************/
+/*!
+ * This pin record type definition is comprised of the signal index and
+ * associated input or output data.
+ */
+typedef struct ALT_GPIO_PIN_RECORD_s
+{
+ /*!
+ * The index number of the signal. */
+ ALT_GPIO_1BIT_t signal_number;
+ /*!
+ * Data - zero or one. */
+ ALT_GPIO_PIN_DATA_t val;
+} ALT_GPIO_PIN_RECORD_t;
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_BITVIEW General-Purpose IO via Bit Index
+ *
+ * @{
+ */
+/******************************************************************************/
+/*!
+ * Configures all parameters for one bit (signal) of the GPIO ports.
+ *
+ * \param signal_num
+ * The GPIO port signal index.
+ * \param dir
+ * The data direction for this signal.
+ * \param type
+ * Edge-triggered or Level-triggered interrupt for this signal.
+ * \param pol
+ * Active-high or active-low interrupt polarity for this signal.
+ * \param debounce
+ * Enable the debounce flip-flops for this signal or not.
+ * \param data
+ * If the GPIO signal is set to be an output, set it to
+ * this value
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input argument.
+ */
+ALT_STATUS_CODE alt_gpio_bit_config(ALT_GPIO_1BIT_t signal_num,
+ ALT_GPIO_PIN_DIR_t dir, ALT_GPIO_PIN_TYPE_t type,
+ ALT_GPIO_PIN_POL_t pol, ALT_GPIO_PIN_DEBOUNCE_t debounce,
+ ALT_GPIO_PIN_DATA_t data);
+
+/******************************************************************************/
+/*!
+ * Returns the configuration parameters of a given GPIO bit.
+ *
+ * \param signal_num
+ * The GPIO port signal index.
+ * \param config
+ * Pointer to a single GPIO_CONFIG_RECORD_s configuration record.
+ * The fields of this configuration record are filled in
+ * by the function.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input argument.
+
+ */
+ALT_STATUS_CODE alt_gpio_bitconfig_get(ALT_GPIO_1BIT_t signal_num,
+ ALT_GPIO_CONFIG_RECORD_t *config);
+
+/******************************************************************************/
+/*!
+ * Configures a list of GPIO bits. The GPIO bits do not have to be
+ * configured the same, as was the case for the mask version of this function,
+ * alt_gpio_port_config(). Each bit may be configured differently and bits may
+ * be listed in any order.
+ *
+ * \param config_array
+ * Pointer to an array of GPIO_CONFIG_RECORD_s configuration
+ * records. These definitions contain all the parameters
+ * needed to set up the listed pins. All or
+ * any subset of the GPIO signals can be configured. Signals do
+ * not have to be listed in numerical order or be unique. If a
+ * signal number is listed multiple times, the last configuration
+ * listed is used. \n Configuration terminates either when \b len
+ * signals have been configured or if the next signal number index
+ * in the array is equal to \b ALT_END_OF_GPIO_SIGNALS (-1).
+ *
+ * \param len
+ * Length of array to configure.
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input argument.
+
+ */
+ALT_STATUS_CODE alt_gpio_group_config(ALT_GPIO_CONFIG_RECORD_t* config_array,
+ uint32_t len);
+
+/******************************************************************************/
+/*!
+ * Returns a list of the pin signal indices and the associated configuration
+ * settings (data direction, interrupt type, polarity, and debounce) of that
+ * list of signals.
+ *
+ * \param config_array
+ * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration
+ * records. Only the signal indices in the first field of each
+ * configuration record need be filled in. This function will
+ * fill in all the other fields of the configuration record,
+ * returning all configuration parameters in the array.
+ * Signals do not have to be listed in numerical order or be
+ * unique. If a signal number is listed multiple times, the
+ * configuration record will contain multiple entries for
+ * that signal. \n Configuration reading terminates either when
+ * \b len signal configurations have been read or if the next
+ * signal number index in the array is equal to
+ * \b ALT_END_OF_GPIO_SIGNALS (-1).
+ * \param len
+ * Length of configuration array to read and return.
+ *
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input argument.
+
+ */
+ALT_STATUS_CODE alt_gpio_group_config_get(ALT_GPIO_CONFIG_RECORD_t *config_array,
+ uint32_t len);
+
+/******************************************************************************/
+/*!
+ * Returns a list of the pin signal indices and the associated configuration
+ * settings (data direction, interrupt type, polarity, and debounce) of that
+ * list of signals. The difference between this version and
+ * alt_gpio_group_config_get() is this version follows a separate list of
+ * signal indices instead of having the signal list provided in the first
+ * field of the configuration records in the array.
+ *
+ * \param pinid_array
+ * Pointer to a list of signal index numbers. These indices
+ * are copied to the first field of each configuration record
+ * in the returned array.
+ * \param config_array
+ * Pointer to an array of ALT_GPIO_CONFIG_RECORD_t configuration
+ * records. This function will fill in the fields of the
+ * configuration record, returning all configuration parameters
+ * in the array. Signals do not have to be listed in numerical
+ * order or be unique. If a signal number is listed multiple
+ * times, the configuration record array will contain multiple
+ * identical entries for that signal. \n Configuration reading
+ * terminates either when \b len signal configurations have been
+ * read or if the next signal number index in the array is equal
+ * to \b ALT_END_OF_GPIO_SIGNALS (-1).
+ * \param len
+ * Length of configuration array to read.
+ *
+ *
+ * \retval ALT_E_SUCCESS The operation was successful.
+ * \retval ALT_E_ERROR The operation failed.
+ * \retval ALT_E_BAD_ARG Invalid input argument.
+ *
+ */
+ALT_STATUS_CODE alt_gpio_group_config_get2(ALT_GPIO_1BIT_t* pinid_array,
+ ALT_GPIO_CONFIG_RECORD_t *config_array, uint32_t len);
+
+
+/*! @} */
+/******************************************************************************/
+/*! \addtogroup ALT_GPIO_UTILITY General-Purpose IO Utility Functions
+ *
+ * These are useful utility functions for the general-purpose input & output
+ * module.
+ *
+ * @{ */
+/******************************************************************************/
+/*!
+ * Returns the ID code of the specified GPIO module.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ *
+ *
+ * \retval uint32_t The component code of the module, GPIO_MODULE_IDCODE.
+ */
+uint32_t alt_gpio_port_idcode_get(ALT_GPIO_PORT_t gpio_pid);
+
+/******************************************************************************/
+/*!
+ * Returns the version code of the specified GPIO module.
+ *
+ * \param gpio_pid
+ * The GPIO port identifier.
+ *
+ *
+ * \retval uint32_t The encoded revision number of the module.
+ */
+uint32_t alt_gpio_port_ver_get(ALT_GPIO_PORT_t gpio_pid);
+
+
+/******************************************************************************/
+/*!
+ * Extracts the GPIO port ID from the supplied GPIO Signal Index Number.
+ */
+ALT_GPIO_PORT_t alt_gpio_bit_to_pid(ALT_GPIO_1BIT_t pin_num);
+
+
+/******************************************************************************/
+/*!
+ * Extracts the GPIO signal (pin) offset from the supplied GPIO Signal Index
+ * Number.
+ * */
+ALT_GPIO_PORTBIT_t alt_gpio_bit_to_port_pin(ALT_GPIO_1BIT_t pin_num);
+
+/******************************************************************************/
+/*!
+ * Extracts the GPIO Signal Index Number from the supplied GPIO port ID and
+ * signal mask. If passed a bitmask composed of more than one signal, the
+ * signal number of the lowest bit in the bitmask presented is returned.
+ *
+ */
+ALT_GPIO_1BIT_t alt_gpio_port_pin_to_bit(ALT_GPIO_PORT_t pid,
+ uint32_t bitmask);
+
+
+/*! @} */
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __ALT_GPIO_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h
new file mode 100644
index 0000000000..7596d50d66
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_hwlibs_ver.h
@@ -0,0 +1,56 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __ALT_HWLIBS_VER_H__
+
+/***********************************************************************
+ *
+ * Set of macros to provide version information
+ *
+ ***********************************************************************/
+
+/* This is the major revision of the Altera ACDS Release */
+#define ALTERA_ACDS_MAJOR_REV 13
+
+/* This is the minor revision of the Altera ACDS Release */
+#define ALTERA_ACDS_MINOR_REV 1
+
+/* This is an internal HwLibs revision/feature control code. */
+/* End-users should NOT depend upon the value of this field */
+#define ALTERA_HWLIBS_REV 0
+
+/* This is a text string containing the current release and service pack IDs */
+#define ALTERA_ACDS_REV_STR "13.1"
+
+/* This is a text string containing the current SoC EDS ID */
+#define ALTERA_SOCEDS_REV_STR "Altera SoC Embedded Design Suite v13.1"
+
+
+#endif /* __ALT_HWLIBS_VER_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h
new file mode 100644
index 0000000000..7af55cf4ac
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_i2c.h
@@ -0,0 +1,2024 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+/*! \file
+ * Altera - I2C Controller API
+ */
+
+#ifndef __ALT_I2C_H__
+#define __ALT_I2C_H__
+
+#include "hwlib.h"
+#include "alt_clock_manager.h"
+#include "socal/alt_i2c.h"
+#include "socal/alt_rstmgr.h"
+#include "socal/hps.h"
+#include "socal/socal.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/******************************************************************************/
+/*! \addtogroup ALT_I2C I2C Controller API
+ *
+ * This module defines an API for configuring and managing the HPS I2C controllers.
+ *
+ * The I2C controller provides support for a communication link between integrated
+ * circuits on a board. It is a simple two-wire bus which consists of a serial
+ * data line (SDA) and a serial clock (SCL) for use in applications such as
+ * temperature sensors and voltage level translators to EEPROMs, A/D and D/A
+ * converters, CODECs, and many types of microprocessors.
+ *
+ * The Hard Processor System (HPS) provides four I2C controllers to enable system
+ * software to communicate serially with I2C buses. Each I2C controller can
+ * operate in master or slave mode, and support standard mode of up to 100
+ * kilobits per second (Kbps) or fast mode of up to 400 Kbps. These I2C
+ * controllers are instances of the Synopsys DesignWare APB I2C (DW_apb_i2c)
+ * controller.
+ *
+ * NOTE: Each I2C controller must be programmed to operate in either master or
+ * slave mode only. Operating as a master and slave simultaneously is not
+ * supported.
+ *
+ * Features of the I2C Controller:
+ * * Support both 100 KBps and 400 KBps modes
+ * * One of the following I2C operations: master or slave
+ * * Support both 7-bit and 10-bit addressing modes
+ * * Mixed read and write combined-format transactions
+ * * Bulk transmit mode
+ * * DMA handshaking interface
+ *
+ * For a complete details on the configuration and operation of I2C controller,
+ * consult the following references:
+ * * <em>Cyclone V Device Handbook Volume 3: Hard Processor System Technical
+ * Reference Manual, Chapter 20. I2C Controller (cv_54020-1.2)</em>
+ * * <em>Synopsys DesignWare DW_apb_i2c Databook DW_apb_i2c, Version 1.15a</em>
+ * * <em>The I2C-Bus Specification Version 2.1</em>
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the operational state of I2C by
+ * transfer operation.
+ */
+typedef enum ALT_I2C_TRANSFER_TYPE_e
+{
+ ALT_I2C_TRANSFER_NONE = 0, /*!< No transfer operation */
+ ALT_I2C_TRANSFER_START = 1, /*!< Start detect */
+ ALT_I2C_TRANSFER_COMPLETE = 2, /*!< All operations done */
+ ALT_I2C_TRANSFER_READ = 3, /*!< Read operation is active */
+ ALT_I2C_TRANSFER_WRITE = 4, /*!< Write operation is active */
+}
+ALT_I2C_TRANSFER_TYPE_t;
+
+
+/*
+ * A pointer or handle to the I2C controller device instance. The ALT_I2C_DEV_t is
+ * initialized by a call to alt_i2c_init() and subsequently used by the other I2C
+ * controller API functions as a reference to a specific device.
+ *
+ * \internal
+ * ALT_I2C_DEV_t may be a struct or reference to an opaque data
+ * structure. Whatever "internal" type is suited to the needs of the
+ * implementation.
+ * \endinternal
+ */
+typedef struct ALT_I2C_DEV_s
+{
+ void * location; /*!< HPS address of I2C instance. */
+ alt_freq_t clock_freq; /*!< Input clock frequency. */
+ uint32_t last_target; /*!< Last issued target address. */
+}
+ALT_I2C_DEV_t;
+
+/*!
+ * This type enumerates the HPS I2C controller instances.
+ */
+typedef enum ALT_I2C_CTLR_e
+{
+ ALT_I2C_I2C0 = (int)ALT_I2C0_OFST, /*!< I2C0 instance. */
+ ALT_I2C_I2C1 = (int)ALT_I2C1_OFST, /*!< I2C1 instance. */
+ ALT_I2C_I2C2 = (int)ALT_I2C2_OFST, /*!< I2C2 instance. */
+ ALT_I2C_I2C3 = (int)ALT_I2C3_OFST, /*!< I2C3 instance. */
+} ALT_I2C_CTLR_t;
+
+/*!
+ * This type enumerates the modes that the I2C controller may operate in.
+ *
+ * NOTE: Each I2C controller must be programmed to operate in either master or
+ * slave mode only. Operating as a master and slave simultaneously is not
+ * supported.
+ */
+typedef enum ALT_I2C_MODE_e
+{
+ ALT_I2C_MODE_SLAVE = ALT_I2C_CON_MST_MOD_E_DIS, /*!< Slave Mode */
+ ALT_I2C_MODE_MASTER = ALT_I2C_CON_MST_MOD_E_EN /*!< Master Mode */
+} ALT_I2C_MODE_t;
+
+/*!
+ * This type enumerates the I2C controller operational speed modes.
+ *
+ * The I2C controller can operate in standard mode (with data rates 0 to 100 Kbps)
+ * or fast mode (with data rates less than or equal to 400 Kbps). Additionally,
+ * fast mode devices are downward compatible. For instance, fast mode devices can
+ * communicate with standard mode devices in 0 to 100 Kbps I2C bus
+ * system. However, standard mode devices are not upward compatible and should not
+ * be incorporated in a fast-mode I2C bus system as they cannot follow the higher
+ * transfer rate and therefore unpredictable states would occur.
+ *
+ * This setting is relevant only if one is operating the I2C in master mode.
+ */
+typedef enum ALT_I2C_SPEED_e
+{
+ ALT_I2C_SPEED_STANDARD = ALT_I2C_CON_SPEED_E_STANDARD,
+ /*!< Standard mode (0 to 100 Kbps) */
+ ALT_I2C_SPEED_FAST = ALT_I2C_CON_SPEED_E_FAST
+ /*!< Fast mode (<= 400 Kbps) */
+} ALT_I2C_SPEED_t;
+
+/*!
+ * This type enumerates the two addressing modes formats supported by the I2C
+ * controller.
+ *
+ * The I2C controller does not support mixed address format - that is, a 7-bit
+ * address transaction followed by a 10-bit address transaction or vice versa -
+ * combined format transactions.
+ */
+typedef enum ALT_I2C_ADDR_MODE_e
+{
+ ALT_I2C_ADDR_MODE_7_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START7,
+ /*!< 7-Bit Address Format */
+ ALT_I2C_ADDR_MODE_10_BIT = ALT_I2C_TAR_IC_10BITADDR_MST_E_START10
+ /*!< 10-Bit Address Format */
+} ALT_I2C_ADDR_MODE_t;
+
+/*!
+ * This type enumerates interrupt status conditions for the I2C controller.
+ */
+typedef enum ALT_I2C_STATUS_e
+{
+ ALT_I2C_STATUS_RX_UNDER = 1UL << 0,
+ /*!< Set if the processor attempts to read the
+ * receive buffer when it is empty. If the I2C
+ * controller is disabled, this status keeps
+ * maintains its state until the master or slave
+ * state machines go into idle, then this
+ * interrupt is cleared.
+ */
+ ALT_I2C_STATUS_RX_OVER = 1UL << 1,
+ /*!< Set if the receive buffer is completely
+ * filled to capacity and an additional byte is
+ * received from an external I2C device. The I2C
+ * controller acknowledges this, but any data
+ * bytes received after the FIFO is full are
+ * discarded. If the I2C controller is disabled,
+ * this status maintains its statue until the
+ * master or slave state machines go into idle,
+ * then this interrupt is cleared.
+ */
+ ALT_I2C_STATUS_RX_FULL = 1UL << 2,
+ /*!< Set when the receive buffer reaches or goes
+ * above the RX_TL threshold. It is
+ * automatically cleared by hardware when buffer
+ * level goes below the threshold. If the I2C
+ * controller is disabled, the RX FIFO is
+ * flushed and held in reset; therefore the RX
+ * FIFO is not full. So this bit is cleared once
+ * the I2C controller is disabled, regardless of
+ * the activity that continues.
+ */
+ ALT_I2C_STATUS_TX_OVER = 1UL << 3,
+ /*!< Set during transmit if the transmit buffer is
+ * filled to capacity and the processor attempts
+ * to issue another I2C command. When the I2C
+ * controller is disabled, this bit maintains
+ * its state until the master or slave state
+ * machines go into idle, then this interrupt is
+ * cleared.
+ */
+ ALT_I2C_STATUS_TX_EMPTY = 1UL << 4,
+ /*!< This bit is set to 1 when the transmit buffer
+ * is at or below the configured threshold
+ * value. It is automatically cleared by
+ * hardware when the buffer level goes above the
+ * threshold. When the I2C controller is
+ * disabled, the TX FIFO is flushed and held in
+ * reset. The TX FIFO appears as if it has no
+ * data in it, so this bit is set to 1, provided
+ * there is activity in the master or slave
+ * state machines. When there is no longer
+ * activity, then this bit is set to 0.
+ *
+ */
+ ALT_I2C_STATUS_RD_REQ = 1UL << 5,
+ /*!< This bit is set to 1 when I2C is acting as a
+ * slave and another I2C master is attempting to
+ * read data from the I2C. The I2C holds the bus
+ * in a wait state until this interrupt is
+ * serviced, which means that the slave has been
+ * addressed by a remote master that is asking
+ * for data to be transferred. The processor
+ * must respond to this interrupt and then write
+ * the requested data. This bit is set to 0 just
+ * after the processor by calling
+ * alt_i2c_int_clear() with
+ * ALT_I2C_STATUS_RD_REQ in the mask..
+ */
+ ALT_I2C_STATUS_TX_ABORT = 1UL << 6,
+ /*!< This bit indicates if I2C, as an I2C
+ * transmitter, is unable to complete the
+ * intended actions on the contents of the
+ * transmit FIFO. This situation can occur both
+ * as an I2C master or an I2C slave, and is
+ * referred to as a 'transmit abort'. When this
+ * bit is set to 1, the IC_TX_ABRT_SOURCE
+ * register indicates the reason why the
+ * transmit abort takes places.
+ *
+ * NOTE: The I2C flushes/resets/empties the TX
+ * FIFO whenever this bit is set. The TX FIFO
+ * remains in this flushed state until the
+ * register alt_i2c_int_clear() with
+ * ALT_I2C_STATUS_TX_ABORT in the mask is
+ * called. Once this happens, the TX FIFO is
+ * then ready to accept more data bytes from the
+ * APB interface.
+ */
+ ALT_I2C_STATUS_RX_DONE = 1UL << 7,
+ /*!< When the I2C is acting as a
+ * slave-transmitter, this bit is set to 1 if
+ * the master does not acknowledge a transmitted
+ * byte. This occurs on the last byte of the
+ * transmission, indicating that the
+ * transmission is done.
+ */
+ ALT_I2C_STATUS_ACTIVITY = 1UL << 8,
+ /*!< This bit captures I2C activity and stays set
+ * until it is cleared. There are four ways to
+ * clear it:
+ * * Disabling the I2C controller
+ * * Calling alt_i2c_int_clear() with
+ * ALT_I2C_STATUS_ACTIVITY in the mask.
+ * * Calling alt_i2c_int_clear() with
+ * ALT_I2C_STATUS_ALL in the mask.
+ * * System reset
+ *
+ * Once this bit is set, it stays set unless one
+ * of the four methods is used to clear it. Even
+ * if the I2C module is idle, this bit remains
+ * set until cleared, indicating that there was
+ * activity on the bus.
+ */
+ ALT_I2C_STATUS_STOP_DET = 1UL << 9,
+ /*!< Indicates whether a STOP condition has
+ * occurred on the I2C interface regardless of
+ * whether I2C is operating in slave or master
+ * mode.
+ */
+ ALT_I2C_STATUS_START_DET = 1UL << 10,
+ /*!< Indicates whether a START or RESTART
+ * condition has occurred on the I2C interface
+ * regardless of whether I2C is operating in
+ * slave or master mode.
+ */
+ ALT_I2C_STATUS_INT_CALL = 1UL << 11,
+ /*!< Set only when a General Call address is
+ * received and it is acknowledged. It stays set
+ * until it is cleared either by disabling I2C
+ * or when alt_i2c_int_clear() with
+ * ALT_I2C_STATUS_CALL in the mask is
+ * called. I2C stores the received data in the
+ * Rx buffer.
+ */
+ ALT_I2C_STATUS_INT_ALL = 0xFFF,
+ /*!< All Combined and Individual Interrupts. This
+ * enumeration value can be used to clear,
+ * disable, and enable the combined interrupt
+ * and all individual interrupt status
+ * conditions. As a side effect, when passed to
+ * alt_i2c_int_clear(), clears the source causes
+ * (\ref ALT_I2C_TX_ABORT_CAUSE_t) of the
+ * ALT_I2C_STATUS_TX_ABORT condition.
+ */
+} ALT_I2C_STATUS_t;
+
+/*!
+ * This type enumerates the source causes of a ALT_I2C_STATUS_TX_ABORT condition.
+ *
+ * The active ALT_I2C_TX_ABORT_CAUSE_t source conditions are cleared when
+ * alt_i2c_int_clear() with is called ALT_I2C_STATUS_TX_ABORT in the mask or
+ * alt_i2c_int_clear() is called with ALT_I2C_STATUS_ALL in the mask.
+ *
+ * \internal
+ * Discuss special handling of abrt_sbyte_norstrt TX_ABRT source required in ???() function.
+ * \endinternal
+ */
+typedef enum ALT_I2C_TX_ABORT_CAUSE_e
+{
+ ALT_I2C_TX_ABORT_CAUSE_7B_ADDR_NOACK = 1UL << 0,
+ /*!< Master Abort 7 Bit Address - If set (1),
+ * Master is in 7-bit addressing mode and the
+ * address sent was not acknowledged by any
+ * slave.
+ *
+ * Role of I2C: Master-Transmitter or
+ * Master-Receiver
+ */
+ ALT_I2C_TX_ABORT_CAUSE_10ADDR1_NOACK = 1UL << 1,
+ /*!< Master Abort 10 Bit Address Byte 1 - If set
+ * (1), Master is in 10-bit address mode and the
+ * first 10-bit address byte was not
+ * acknowledged by any slave.
+ *
+ * Role of I2C: Master-Transmitter or
+ * Master-Receiver
+ */
+ ALT_I2C_TX_ABORT_CAUSE_10ADDR2_NOACK = 1UL << 2,
+ /*!< Master Abort 10 Bit Address Byte 2 - If set
+ * (1), Master is in 10-bit address mode and the
+ * second address byte of the 10-bit address was
+ * not acknowledged by any slave
+ *
+ * Role of I2C: Master-Transmitter or
+ * Master-Receiver
+ */
+ ALT_I2C_TX_ABORT_CAUSE_TXDATA_NOACK = 1UL << 3,
+ /*!< Master Abort TX NOACK Bit - If set (1),
+ * Master has received an acknowledgement for
+ * the address, but when it sent data byte(s)
+ * following the address, it did not receive an
+ * acknowledge from the remote slave(s). This is
+ * a master-mode only bit.
+ *
+ * Role of I2C: Master-Transmitter.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_GCALL_NOACK = 1UL << 4,
+ /*!< Master Abort GC Noack Bit - If set (1), I2C
+ * controller in master mode sent a General Call
+ * and no slave on the bus acknowledged the
+ * General Call.
+ *
+ * Role of I2C: Master-Transmitter.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_GCALL_RD = 1UL << 5,
+ /*!< Master Abort GC Read Bit - If set (1), I2C
+ * controller in master mode sent a General Call
+ * but the user programmed the byte following
+ * the General Call to be a read from the bus
+ * (IC_DATA_CMD[9] is set to 1).
+ *
+ * Role of I2C: Master-Transmitter.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_HS_ACKDET = 1UL << 6,
+ /*!< Master HS MC Ack - If set (1), Master is in
+ * High Speed mode and the High Speed Master
+ * code was acknowledged (wrong behavior).
+ *
+ * Role of I2C: Master.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_SBYTE_ACKDET = 1UL << 7,
+ /*!< Master Abort START Byte - If set (1), Master
+ * has sent a START Byte and the START Byte was
+ * acknowledged (wrong behavior).
+ *
+ * Role of I2C: Master.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_HS_NORSTRT = 1UL << 8,
+ /*!< Master HS Restart Disabled - If set (1), the
+ * restart is disabled (IC_RESTART_EN bit
+ * (IC_CON[5]) = 0) and the user is trying to
+ * use the master to transfer data in High Speed
+ * mode.
+ *
+ * Role of I2C: Master-Transmitter or
+ * Master-Receiver
+ */
+ ALT_I2C_TX_ABORT_CAUSE_SBYTE_NORSTRT = 1UL << 9,
+ /*!< Master Abort START No Restart - To clear, the
+ * source of the ABRT_SBYTE_NORSTRT must be
+ * fixed first; restart must be enabled
+ * (IC_CON[5]=1), the SPECIAL bit must be
+ * cleared (IC_TAR[11]), or the GC_OR_START bit
+ * must be cleared (IC_TAR[10]). Once the source
+ * of the ABRT_SBYTE_NORSTRT is fixed, then this
+ * bit can be cleared in the same manner as
+ * other bits in this register. If the source of
+ * the ABRT_SBYTE_NORSTRT is not fixed before
+ * attempting to clear this bit, bit 9 clears
+ * for one cycle and then gets re-asserted.
+ *
+ * If set (1), the restart is disabled
+ * (IC_RESTART_EN bit (IC_CON[5]) = 0) and the
+ * user is trying to send a START Byte.
+ *
+ * Role of I2C: Master.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_10B_RD_NORSTRT = 1UL << 10,
+ /*!< Master Abort 10 Bit No Restart - If set (1),
+ * the restart is disabled (IC_RESTART_EN bit
+ * (IC_CON[5]) = 0) and the master sends a read
+ * command in 10-bit addressing mode.
+ *
+ * Role of I2C: Master Receiver.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_MST_DIS = 1UL << 11,
+ /*!< Master Operation with Master Disabled - If set
+ * (1), user tries to initiate a Master
+ * operation with the Master mode disabled.
+ *
+ * Role of I2C: Master or Slave-Receiver.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_ARB_LOST = 1UL << 12,
+ /*!< Master Abort Arbitration Lost - If set (1),
+ * master has lost arbitration, or if
+ * IC_TX_ABRT_SOURCE[14] is also set, then the
+ * slave transmitter has lost arbitration. Note:
+ * I2C can be both master and slave at the same
+ * time.
+ *
+ * Role of I2C: Master or Slave-Transmitter.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_SLVFLUSH_TXFIFO = 1UL << 13,
+ /*!< Slave Abort Flush TXFIFO - If set (1), Slave
+ * has received a read command and some data
+ * exists in the TX FIFO so the slave issues a
+ * TX_ABRT interrupt to flush old data in TX
+ * FIFO.
+ *
+ * Role of I2C: Slave-Transmitter.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_SLV_ARBLOST = 1UL << 14,
+ /*!< Slave Abort Arbitration Lost - If set (1),
+ * Slave lost the bus while transmitting data to
+ * a remote master. IC_TX_ABRT_SOURCE[12] is set
+ * at the same time.
+ *
+ * Note: Even though the slave never owns the
+ * bus, something could go wrong on the
+ * bus. This is a fail safe check. For instance,
+ * during a data transmission at the low-to-high
+ * transition of SCL, if what is on the data bus
+ * is not what is supposed to be transmitted,
+ * then DW_apb_i2c no longer own the bus.
+ *
+ * Role of I2C: Slave-Transmitter.
+ */
+ ALT_I2C_TX_ABORT_CAUSE_SLVRD_INTX = 1UL << 15
+ /*!< Slave Abort Read TX - If set (1),
+ * when the processor side responds to a
+ * slave mode request for data to be transmitted
+ * to a remote master and user writes a 1 in CMD
+ * (bit 8) of IC_DATA_CMD register.
+ *
+ * Role of I2C: Slave-Transmitter.
+ */
+} ALT_I2C_TX_ABORT_CAUSE_t;
+
+/*!
+ * This type defines a structure for configuration of the SCL high and low counts
+ * to ensure proper I/O timing with the device interface.
+ *
+ * The SCL count values are only relevant if the I2C controller is enabled to as
+ * an I2C master. The SCL count values are ignored when the I2C controller is
+ * enabled as an I2C slave.
+ *
+ * See: Clock Frequency Configuration section of <em>Chapter 20. I2C
+ * Controller</em> in the <em>Cyclone V Device Handbook Volume 3: Hard
+ * Processor System Technical Reference Manual</em> for a complete discussion
+ * of calculation of the proper SCL clock high and low times.
+ */
+typedef struct ALT_I2C_MASTER_CONFIG_s
+{
+ ALT_I2C_ADDR_MODE_t addr_mode;
+ /*!< The address mode (7 or 10 bit) when
+ * acting as a master.
+ */
+ bool restart_enable;
+ /*!< This setting determines whether RESTART
+ * conditions may be sent when acting as a
+ * master. When the \e restart_enable is
+ * false, the I2C controller master is
+ * incapable of performing the following
+ * functions:
+ * * Sending a START BYTE
+ * * Performing any high-speed mode
+ * operation
+ * * Performing direction changes in
+ * combined format mode
+ * * Performing a read operation with a
+ * 10-bit address
+ */
+ ALT_I2C_SPEED_t speed_mode;
+ /*!< The speed mode of the I2C operation.
+ */
+ uint16_t ss_scl_hcnt;
+ /*!< The SCL clock high-period count for
+ * standard speed.
+ */
+ uint16_t ss_scl_lcnt;
+ /*!< The SCL clock low-period count for
+ * standard speed.
+ */
+ uint16_t fs_scl_hcnt;
+ /*!< The SCL clock high-period count for fast
+ * speed.
+ */
+ uint16_t fs_scl_lcnt;
+ /*!< The SCL clock low-period count for fast
+ * speed.
+ */
+ uint8_t fs_spklen;
+ /*!< The duration, measured in ic_clk cycles,
+ * of the longest spike that is filtered out
+ * by the spike suppression logic when the
+ * component is operating in SS or FS modes.
+ */
+} ALT_I2C_MASTER_CONFIG_t;
+
+/*!
+ * This type defines a structure for configuration of the I2C controller when it
+ * is operating in slave mode.
+ */
+typedef struct ALT_I2C_SLAVE_CONFIG_s
+{
+ ALT_I2C_ADDR_MODE_t addr_mode; /*!< The address mode (7 or 10 bit) when
+ * acting as a slave.
+ */
+ uint32_t addr; /*!< The slave address to which the I2C
+ * controller responds when acting as a
+ * slave.
+ */
+ bool nack_enable; /*!< Enable generation of a NACK. when the
+ * I2C controller is a
+ * slave-receiver. If \b true, it can
+ * only generate a NACK after a data
+ * byte is received; hence, the data
+ * transfer is aborted and the data
+ * received is not pushed onto the
+ * receive buffer. When \b false, it
+ * generates NACK/ACK, depending on
+ * normal criteria.
+ * * \b true = generate NACK after data
+ * byte received
+ * * \b false = generate NACK/ACK normally
+ */
+} ALT_I2C_SLAVE_CONFIG_t;
+
+/*!
+ * Initialize the specified I2C controller instance for use and return a device
+ * handle referencing it.
+ *
+ * \param i2c
+ * The HPS I2C controller instance to initialize.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * Initialization process:
+ * * Initialize internal driver state
+ * * Check clock setup (ALT_CLK_L4_SP)
+ * * Take I2C instance out of reset (System Manager)
+ * * Disable and clear all interrupts and status conditions
+ * * Setup and initialize any expected initial I2C controller state
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_init(const ALT_I2C_CTLR_t i2c, ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Reset the specified I2C controller instance for use.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * Reset process:
+ * * Disable controller
+ * * Initialize internal driver state
+ * * Check clock setup (ALT_CLK_L4_SP)
+ * * Take I2C instance out of reset (System Manager)
+ * * Disable and clear all interrupts and status conditions
+ * * Setup and initialize any expected initial I2C controller state
+ * * Enable controller
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_reset(ALT_I2C_DEV_t * i2c_dev);
+
+/*!
+ * Uninitialize the I2C controller referenced by the \e i2c_dev handle.
+ *
+ * This function attempts to gracefully shutdown the I2C controller by waiting for
+ * any inpcomplete transactions to finish and then putting the I2C controller into
+ * reset.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_uninit(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Disables the I2C controller.
+ *
+ * When the I2C controller is disabled, the following occurs:
+ * * The TX FIFO and RX FIFO get flushed.
+ * * The I2C interrupt status conditions remain active until the I2C controller
+ * goes into IDLE state.
+ *
+ * If the controller is transmitting, it stops as well as deletes the contents of
+ * the transmit buffer after the current transfer is complete. If the module is
+ * receiving, the controller stops the current transfer at the end of the current
+ * byte and does not acknowledge the transfer.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_ENABLE.ENABLE = 0
+ * Follow the procedure in section 3.8.3 Disabling DW_apb_i2c of the DW Databook.
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_disable(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Enables the I2C controller.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_ENABLE.ENABLE = 1
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_enable(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Returns ALT_E_TRUE if the I2C controller is enabled.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_ENABLE.ENABLE == 1
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_is_enabled(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Gets the current configuration of the I2C controller when operating in master
+ * mode.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param cfg
+ * [out] Pointer to a ALT_I2C_MASTER_CONFIG_t structure for holding
+ * the returned I2C master mode configuration parameters.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_master_config_get(ALT_I2C_DEV_t *i2c_dev,
+ ALT_I2C_MASTER_CONFIG_t* cfg);
+
+/*!
+ * Sets the configuration of the I2C controller with operational parameters for
+ * operating in master mode.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param cfg
+ * Pointer to a ALT_I2C_MASTER_CONFIG_t structure holding the desired
+ * I2C master mode operational parameters.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_master_config_set(ALT_I2C_DEV_t *i2c_dev,
+ const ALT_I2C_MASTER_CONFIG_t* cfg);
+
+/*!
+ * This is a utility function that returns the speed based on parameters of the
+ * I2C master configuration.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param cfg
+ * A pointer to the master confugurations.
+ *
+ * \param speed_in_hz
+ * [out] Speed (Hz) of the I2C bus currently configured at.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ */
+ALT_STATUS_CODE alt_i2c_master_config_speed_get(ALT_I2C_DEV_t *i2c_dev,
+ const ALT_I2C_MASTER_CONFIG_t* cfg,
+ uint32_t * speed_in_hz);
+
+/*!
+ * This is a utility function that computes parameters for the I2C master
+ * configuration that best matches the speed requested.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param cfg
+ * A pointer to the master confugurations.
+ *
+ * \param speed_in_hz
+ * Speed (Hz) of the I2C bus to configure.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_master_config_speed_set(ALT_I2C_DEV_t *i2c_dev,
+ ALT_I2C_MASTER_CONFIG_t * cfg,
+ uint32_t speed_in_hz);
+
+/*!
+ * Definition included for backwards compatibility.
+ */
+#define alt_i2c_cfg_to_speed(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_get((i2c_dev), (cfg), (speed_in_hz))
+
+/*!
+ * Definition included for backwards compatibility.
+ */
+#define alt_i2c_speed_to_cfg(i2c_dev, speed_in_hz, cfg) alt_i2c_master_config_speed_set((i2c_dev), (cfg), (speed_in_hz))
+
+/*!
+ * Gets the current configuration of the I2C controller when operating in slave
+ * mode.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param cfg
+ * [out] Pointer to a ALT_I2C_SLAVE_CONFIG_t structure for holding
+ * the returned I2C slave mode configuration parameters.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_slave_config_get(ALT_I2C_DEV_t *i2c_dev,
+ ALT_I2C_SLAVE_CONFIG_t* cfg);
+
+/*!
+ * Sets the configuration of the I2C controller with operational parameters for
+ * operating in slave mode.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param cfg
+ * Pointer to a ALT_I2C_SLAVE_CONFIG_t structure holding the desired
+ * I2C slave mode operational parameters.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_slave_config_set(ALT_I2C_DEV_t *i2c_dev,
+ const ALT_I2C_SLAVE_CONFIG_t* cfg);
+
+/*! \addtogroup ALT_I2C_SDA_HOLD SDA Hold Time Configuration
+ *
+ * The I2C protocol specification requires 300ns of hold time on the SDA signal in
+ * standard and fast speed modes. Board delays on the SCL and SDA signals can mean
+ * that the hold-time requirement is met at the I2C master, but not at the I2C
+ * slave (or vice-versa). Because each system may encounter differing board signal
+ * delays, the I2C controller provides the capability to adjust of the SDA
+ * hold-time.
+ *
+ * The functions in this section provide software configuration of SDA hold time
+ * for the I2C controller.
+ *
+ * @{
+ */
+
+/*!
+ * Gets the currently configured value for the SDA hold time in I2C controller
+ * clock (\ref ALT_CLK_L4_SP) clock ticks.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param hold_time
+ * [out] The configured SDA hold time in \ref ALT_CLK_L4_SP clock
+ * ticks.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_sda_hold_time_get(ALT_I2C_DEV_t *i2c_dev,
+ uint16_t *hold_time);
+
+/*!
+ * Sets the configured value for the SDA hold time in terms of I2C controller
+ * clock (\ref ALT_CLK_L4_SP) clock ticks.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param hold_time
+ * The SDA hold time in \ref ALT_CLK_L4_SP clock ticks.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_SDA_HOLD is 16 bits wide. hold_time must be in range 0..65535.
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_sda_hold_time_set(ALT_I2C_DEV_t *i2c_dev,
+ const uint16_t hold_time);
+
+/*! @} */
+
+/*!
+ * Gets the current operational mode of the I2C controller.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param mode
+ * [out] The current operational mode enabled for the I2C
+ * controller.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_op_mode_get(ALT_I2C_DEV_t *i2c_dev,
+ ALT_I2C_MODE_t* mode);
+
+/*!
+ * Sets the operational mode of the I2C controller.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param mode
+ * The operational mode to enable for the I2C controller.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_op_mode_set(ALT_I2C_DEV_t *i2c_dev,
+ const ALT_I2C_MODE_t mode);
+
+/*!
+ * Returns ALT_E_TRUE if the I2C controller is busy. The I2C controller is busy if
+ * either the Slave Finite State Machine (FSM) is not in the IDLE state or the
+ * Master Finite State Machine (FSM) is not in the IDLE state.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_STATUS.ACTIVITY == 1
+ * NOTE: IC_STATUS[0] that is, the ACTIVITY bit is the OR of SLV_ACTIVITY and
+ * MST_ACTIVITY bits.
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_is_busy(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * This function reads a single data byte from the receive FIFO.
+ *
+ * This function is used to perform low level access to the data bytes
+ * received by the I2C controller and buffered in the receive FIFO. It
+ * may be used by master-receivers or slave receivers.
+ *
+ * This function does not check for valid data in the receive FIFO
+ * beforehand and may cause an underflow if improperly used. It is
+ * meant to be called from a context where preconditions have been
+ * previously asserted such as in the implementation of the
+ * alt_i2c_slave_receive() or alt_i2c_master_receive() function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param val
+ * [out] The single data byte read from the receive FIFO.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_read(ALT_I2C_DEV_t *i2c_dev, uint8_t *val);
+
+/*!
+ * This function writes a single data byte to the transmit FIFO.
+ *
+ * This function is used to perform low level writes of data to the
+ * transmit FIFO for transmission by the I2C controller. It may be
+ * used by slave receivers.
+ *
+ * This function does not check whether the transmit FIFO is full or
+ * not beforehand and may cause an overflow if improperly used. It is
+ * meant to be called from a context where preconditions have been
+ * previously asserted such as in the implementation of the
+ * alt_i2c_slave_transmit() function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param val
+ * The data byte to write to the transmission FIFO.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_write(ALT_I2C_DEV_t *i2c_dev, const uint8_t val);
+
+/*!
+ * This function acts in the role of a slave-receiver by receiving a single data
+ * byte from the I2C bus in response to a write command from the master.
+ *
+ * This API is suitable for being called during an interrupt context. It is the
+ * programmer's responsibility to ensure that there is data in the RX FIFO to
+ * accomodate the request made.
+ *
+ * The I2C controller must be in slave mode before calling this function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param data
+ * [out] A pointer to a buffer to contain the received data byte.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_slave_receive(ALT_I2C_DEV_t *i2c_dev,
+ uint8_t *data);
+
+/*!
+ * This function acts in the role of a slave-transmitter by transmitting a single
+ * data byte to the I2C bus in response to a read request from the master.
+ *
+ * This API is suitable for being called during an interrupt context. It is the
+ * programmer's responsibility to ensure that there is enough space in the TX
+ * FIFO to accomodate the request made.
+ *
+ * The I2C controller must be in slave mode before calling this function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param data
+ * The data byte to transmit.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_slave_transmit(ALT_I2C_DEV_t *i2c_dev,
+ const uint8_t data);
+
+/*!
+ * This function acts in the role of a slave-transmitter by transmitting data in
+ * bulk to the I2C bus in response to a series of read requests from a master.
+ *
+ * In the standard I2C protocol, all transactions are single byte transactions and
+ * the slave responds to a remote master read request by writing one byte into the
+ * slave's TX FIFO. When a slave (slave-transmitter) is issued with a read request
+ * from the remote master (master-receiver), at a minimum there should be at least
+ * one entry placed into the slave-transmitter's TX FIFO. The I2C controller is
+ * capable of handling more data in the TX FIFO so that subsequent read requests
+ * can receive that data without raising an interrupt or software having to poll
+ * to request more data. This eliminates overhead latencies from being incurred by
+ * servicing the interrupt or polling for data requests each time had there been a
+ * restriction of having only one entry placed in the TX FIFO.
+ *
+ * If the remote master acknowledges the data sent by the slave-transmitter and
+ * there is no data in the slave's TX FIFO, the I2C controller raises the read
+ * request interrupt and waits for data to be written into the TX FIFO before it
+ * can be sent to the remote master.
+ *
+ * If the programmer knows in advance that the master is requesting a packet of \e
+ * n bytes, then when another master request for data is received, the TX FIFO
+ * could be written with \e n number bytes and the master receives it as a
+ * continuous stream of data. For example, the slave continues to send data to the
+ * master as long as the master is acknowledging the data sent and there is data
+ * available in the TX FIFO. There is no need to hold the SCL line low or to issue
+ * READ request again.
+ *
+ * If the remote master is to receive \e n bytes from the slave but the programmer
+ * wrote a number of bytes larger than \e n to the TX FIFO, then when the slave
+ * finishes sending the requested \e n bytes, it clears the TX FIFO and ignores
+ * any excess bytes.
+ *
+ * This API is suitable for being called during an interrupt context. It is the
+ * programmer's responsibility to ensure that there is enough space in the TX
+ * FIFO to accomodate the request made.
+ *
+ * The I2C controller must be in slave mode before calling this function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param data
+ * A pointer to the data buffer to transmit.
+ *
+ * \param size
+ * The size of the data buffer in bytes to place in the TX FIFO.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * See: Section <em>Slave-Transfer Operation for Bulk Transfers</em> of the DW
+ * Databook for details of implementation and error conditions that may occur.
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_slave_bulk_transmit(ALT_I2C_DEV_t *i2c_dev,
+ const void * data,
+ const size_t size);
+
+/*!
+ * This function returns the current target address.
+ *
+ * The I2C controller must be in master mode before calling this function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param target_addr
+ * [out] The 7 or 10 bit slave target address.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code.
+ */
+ALT_STATUS_CODE alt_i2c_master_target_get(ALT_I2C_DEV_t * i2c_dev, uint32_t * target_addr);
+
+/*!
+ * This function updates the target slave address for any upcoming I2C bus IO.
+ *
+ * This API is not suitlabe for being called in an interrupt context as it
+ * will wait for the TX FIFO to flush before applying the changes. If the TX
+ * FIFO is known to be empty and the controller idle, then it can be safely
+ * called.
+ *
+ * The I2C controller must be in master mode before calling this function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param target_addr
+ * The 7 or 10 bit slave target address.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code.
+ */
+ALT_STATUS_CODE alt_i2c_master_target_set(ALT_I2C_DEV_t * i2c_dev, uint32_t target_addr);
+
+/*!
+ * This function acts in the role of a master-transmitter by issuing a write
+ * command and transmitting data to the I2C bus.
+ *
+ * This API is not suitable for being called in an interrupt context as it may
+ * wait for certain controller states before completing.
+ *
+ * The I2C controller must be in master mode before calling this function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param data
+ * A pointer to a data buffer to transmit
+ *
+ * \param size
+ * The size of the data buffer in bytes to place in the TX FIFO.
+ *
+ * \param issue_restart
+ * This parameter controls whether a RESTART is issued before the
+ * byte is sent or received. If:
+ * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t
+ * is \b true, a RESTART is issued before the data is sent/received
+ * (according to the value of CMD), regardless of whether or not
+ * the transfer direction is changing from the previous command; if
+ * \e restart_enabled is \b false, a STOP followed by a START is
+ * issued instead.
+ * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t
+ * is \b true, a RESTART is issued only if the transfer direction
+ * is changing from the previous command; if \e restart_enabled is
+ * \b false, a STOP followed by a START is issued instead.
+ *
+ * \param issue_stop
+ * This parameter controls whether a STOP is issued after the byte is
+ * sent or received. If:
+ * * \b true - STOP is issued after this byte, regardless of whether or
+ * not the Tx FIFO is empty. If the Tx FIFO is not empty, the
+ * master immediately tries to start a new transfer by issuing a
+ * START and arbitrating for the bus.
+ * * \b false - STOP is not issued after this byte, regardless of
+ * whether or not the Tx FIFO is empty. If the Tx FIFO is not
+ * empty, the master continues the current transfer by
+ * sending/receiving data bytes according to the value of the CMD
+ * bit. If the Tx FIFO is empty, the master holds the SCL line low
+ * and stalls the bus until a new command is available in the Tx
+ * FIFO.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_master_transmit(ALT_I2C_DEV_t *i2c_dev,
+ const void * data,
+ const size_t size,
+ const bool issue_restart,
+ const bool issue_stop);
+
+/*!
+ * This function acts in the role of a master-receiver by receiving one or more
+ * data bytes transmitted from a slave in response to read requests issued from
+ * this master.
+ *
+ * This function causes the master to issue the required number of read requests
+ * to the slave and read the received data bytes from the Rx FIFO.
+ *
+ * The \e issue_restart and \e issue_stop parameters apply to the final read
+ * request transaction in the \e num_data_entries sequence required to fulfill the
+ * aggregate receive request.
+ *
+ * This API is not suitable for being called in an interrupt context as it may
+ * wait for certain controller states before completing.
+ *
+ * The I2C controller must be in master mode before calling this function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param data
+ * [out] The data buffer to receive the requested \e size bytes.
+ *
+ * \param size
+ * The size of the data buffer to read from the RX FIFO.
+ *
+ * \param issue_restart
+ * This parameter controls whether a RESTART is issued before the
+ * byte is sent or received. If:
+ * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t
+ * is \b true, a RESTART is issued before the data is sent/received
+ * (according to the value of CMD), regardless of whether or not
+ * the transfer direction is changing from the previous command; if
+ * \e restart_enabled is \b false, a STOP followed by a START is
+ * issued instead.
+ * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t
+ * is \b true, a RESTART is issued only if the transfer direction
+ * is changing from the previous command; if \e restart_enabled is
+ * \b false, a STOP followed by a START is issued instead.
+ *
+ * \param issue_stop
+ * This parameter controls whether a STOP is issued after the byte is
+ * sent or received. If:
+ * * \b true - STOP is issued after this byte, regardless of whether or
+ * not the Tx FIFO is empty. If the Tx FIFO is not empty, the
+ * master immediately tries to start a new transfer by issuing a
+ * START and arbitrating for the bus.
+ * * \b false - STOP is not issued after this byte, regardless of
+ * whether or not the Tx FIFO is empty. If the Tx FIFO is not
+ * empty, the master continues the current transfer by
+ * sending/receiving data bytes according to the value of the CMD
+ * bit. If the Tx FIFO is empty, the master holds the SCL line low
+ * and stalls the bus until a new command is available in the Tx
+ * FIFO.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_master_receive(ALT_I2C_DEV_t *i2c_dev,
+ void * data,
+ const size_t size,
+ const bool issue_restart,
+ const bool issue_stop);
+
+/*!
+ * This function causes the I2C controller master to issue a READ request on the
+ * bus. This function is typically used during master-receiver transfers.
+ *
+ * The I2C controller must be in master mode before calling this function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param issue_restart
+ * This parameter controls whether a RESTART is issued before the
+ * byte is sent or received. If:
+ * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t
+ * is \b true, a RESTART is issued before the data is sent/received
+ * (according to the value of CMD), regardless of whether or not
+ * the transfer direction is changing from the previous command; if
+ * \e restart_enabled is \b false, a STOP followed by a START is
+ * issued instead.
+ * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t
+ * is \b true, a RESTART is issued only if the transfer direction
+ * is changing from the previous command; if \e restart_enabled is
+ * \b false, a STOP followed by a START is issued instead.
+ *
+ * \param issue_stop
+ * This parameter controls whether a STOP is issued after the byte is
+ * sent or received. If:
+ * * \b true - STOP is issued after this byte, regardless of whether or
+ * not the Tx FIFO is empty. If the Tx FIFO is not empty, the
+ * master immediately tries to start a new transfer by issuing a
+ * START and arbitrating for the bus.
+ * * \b false - STOP is not issued after this byte, regardless of
+ * whether or not the Tx FIFO is empty. If the Tx FIFO is not
+ * empty, the master continues the current transfer by
+ * sending/receiving data bytes according to the value of the CMD
+ * bit. If the Tx FIFO is empty, the master holds the SCL line low
+ * and stalls the bus until a new command is available in the Tx
+ * FIFO.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * Write IC_DATA_CMD.CMD = 1 (read request). IC_DATA_CMD.DAT is
+ * written with "don't care" values as these bits are ignored by the
+ * I2C controller .
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_issue_read(ALT_I2C_DEV_t *i2c_dev,
+ const bool issue_restart,
+ const bool issue_stop);
+
+/*!
+ * This function causes the I2C controller master to issue a send byte on the
+ * bus. This function is typically used during master-transmitter/slave-transmitter
+ * transfers.
+ *
+ * The I2C controller must be in master mode before calling this function.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param value
+ * The data item to be transmitted.
+ *
+ * \param issue_restart
+ * This parameter controls whether a RESTART is issued before the
+ * byte is sent or received. If:
+ * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t
+ * is \b true, a RESTART is issued before the data is sent/received
+ * (according to the value of CMD), regardless of whether or not
+ * the transfer direction is changing from the previous command; if
+ * \e restart_enabled is \b false, a STOP followed by a START is
+ * issued instead.
+ * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t
+ * is \b true, a RESTART is issued only if the transfer direction
+ * is changing from the previous command; if \e restart_enabled is
+ * \b false, a STOP followed by a START is issued instead.
+ *
+ * \param issue_stop
+ * This parameter controls whether a STOP is issued after the byte is
+ * sent or received. If:
+ * * \b true - STOP is issued after this byte, regardless of whether or
+ * not the Tx FIFO is empty. If the Tx FIFO is not empty, the
+ * master immediately tries to start a new transfer by issuing a
+ * START and arbitrating for the bus.
+ * * \b false - STOP is not issued after this byte, regardless of
+ * whether or not the Tx FIFO is empty. If the Tx FIFO is not
+ * empty, the master continues the current transfer by
+ * sending/receiving data bytes according to the value of the CMD
+ * bit. If the Tx FIFO is empty, the master holds the SCL line low
+ * and stalls the bus until a new command is available in the Tx
+ * FIFO.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * Write IC_DATA_CMD.CMD = 0 (write request).
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_issue_write(ALT_I2C_DEV_t *i2c_dev,
+ const uint8_t value,
+ const bool issue_restart,
+ const bool issue_stop);
+
+/******************************************************************************/
+/*! \addtogroup ALT_I2C_GEN_CALL General Call
+ *
+ * The functions in this group support General Call addresses.
+ *
+ * The general call address is for addressing every device connected to the I2C
+ * bus at the same time. However, if a device does not need any of the data
+ * supplied within the general call structure, it can ignore this address by not
+ * issuing an acknowledgment. If a device does require data from a general call
+ * address, it acknowledges this address and behaves as a slave-receiver. The
+ * master does not actually know how many devices acknowledged if one or more
+ * devices respond. The second and following bytes are acknowledged by every
+ * slave-receiver capable of handling this data. A slave who cannot process one of
+ * these bytes must ignore it by not-acknowledging. If one or more slaves
+ * acknowledge, the not-acknowledge will not be seen by the master.
+ *
+ * The functions in this group do not provide any general call functional command
+ * interpretation or implementation (e.g. software reset).
+ *
+ * @{
+ */
+
+/*!
+ * This function acts in the role of a master-transmitter by issuing a general
+ * call command to all devices connected to the I2C bus.
+ *
+ * The \e issue_restart and \e issue_stop parameters apply to the final write
+ * transaction in the \e num_data_entries byte transmission sequence.
+ *
+ * The I2C controller must be in master mode before calling this function.
+ *
+ * The target slave address will be modified by this function. Call
+ * alt_i2c_master_target_set() to reset the slave target address for
+ * subsequent IO.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param data
+ * An array of data byte(s) to transmit.
+ *
+ * \param num_data_entries
+ * The number of entries (bytes) in \e data to place in the TX FIFO.
+ *
+ * \param issue_restart
+ * This parameter controls whether a RESTART is issued before the
+ * byte is sent or received. If:
+ * * \b true - if \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t
+ * is \b true, a RESTART is issued before the data is sent/received
+ * (according to the value of CMD), regardless of whether or not
+ * the transfer direction is changing from the previous command; if
+ * \e restart_enabled is \b false, a STOP followed by a START is
+ * issued instead.
+ * * \b false - If \e restart_enabled in \ref ALT_I2C_MASTER_CONFIG_t
+ * is \b true, a RESTART is issued only if the transfer direction
+ * is changing from the previous command; if \e restart_enabled is
+ * \b false, a STOP followed by a START is issued instead.
+ *
+ * \param issue_stop
+ * This parameter controls whether a STOP is issued after the byte is
+ * sent or received. If:
+ * * \b true - STOP is issued after this byte, regardless of whether or
+ * not the Tx FIFO is empty. If the Tx FIFO is not empty, the
+ * master immediately tries to start a new transfer by issuing a
+ * START and arbitrating for the bus.
+ * * \b false - STOP is not issued after this byte, regardless of
+ * whether or not the Tx FIFO is empty. If the Tx FIFO is not
+ * empty, the master continues the current transfer by
+ * sending/receiving data bytes according to the value of the CMD
+ * bit. If the Tx FIFO is empty, the master holds the SCL line low
+ * and stalls the bus until a new command is available in the Tx
+ * FIFO.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_master_general_call(ALT_I2C_DEV_t *i2c_dev,
+ const void * data,
+ const size_t size,
+ const bool issue_restart,
+ const bool issue_stop);
+
+/*!
+ * Disables the I2C controller from responding to a General Call address. The
+ * controller will respond with a NACK and no General Call status conditions or
+ * interrupts are generated.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 0
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_general_call_ack_disable(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Enables the I2C controller to respond with an ACK when it receives a General
+ * Call address.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_ACK_GENERAL_CALL.ACK_GEN_CALL = 1
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_general_call_ack_enable(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Returns ALT_E_TRUE if the I2C controller is enabled to respond to General Call
+ * addresses.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_ACK_GENERAL_CALL.ACK_GEN_CALL == 1
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_general_call_ack_is_enabled(ALT_I2C_DEV_t *i2c_dev);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ALT_I2C_INT Interrupt and Status Conditions
+ *
+ * The functions in this group provide management for the I2C controller status
+ * conditions and interrupts.
+ *
+ * Each I2C controller has a single combined interrupt output (\b
+ * ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ). The following events can generate an
+ * interrupt:
+ * * General Call Address Received
+ * * Start or Restart Condition Occurred
+ * * Stop Condition Occurred
+ * * I2C Controller Activity
+ * * Receive Done
+ * * Transmit Abort
+ * * Read Request
+ * * Transmit Buffer Empty
+ * * Transmit Overflow
+ * * Receive Buffer Full
+ * * Receive Overflow
+ * * Receive Underflow
+ *
+ * These interrupt status conditions may be monitored either by polling their
+ * status or by configuring interrupt handlers using the HWLIB Interrupt
+ * Controller API.
+ *
+ * Functions to get the current status, enable or disable (i.e. mass or unmask),
+ * and clear interrupt status conditions for the I2C controller are defined in
+ * this section.
+ *
+ * @{
+ */
+
+/*!
+ * Returns the current I2C controller interrupt status conditions.
+ *
+ * This function returns the current value of the I2C controller interrupt status
+ * register value which reflects the current I2C controller status conditions that
+ * are not disabled (i.e. masked).
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param status
+ * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t
+ * interrupt and status conditions.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_INTR_STAT
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_int_status_get(ALT_I2C_DEV_t *i2c_dev,
+ uint32_t *status);
+
+/*!
+ * Returns the I2C controller raw interrupt status conditions irrespective of
+ * the interrupt status condition enablement state.
+ *
+ * This function returns the current value of the I2C controller raw interrupt
+ * status register value which reflects the current I2C controller status
+ * conditions regardless of whether they are disabled (i.e. masked) or not.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param status
+ * [out] A pointer to a bit mask of the active \ref ALT_I2C_STATUS_t
+ * interrupt and status conditions.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_INTR_STAT
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_int_raw_status_get(ALT_I2C_DEV_t *i2c_dev,
+ uint32_t *status);
+
+/*!
+ * Clears the specified I2C controller interrupt status conditions identified
+ * in the mask.
+ *
+ * This function clears one or more of the status conditions as contributors to
+ * the \b ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ interrupt signal state.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param mask
+ * Specifies the QSPI interrupt status conditions to clear. \e mask
+ * is a mask of logically OR'ed \ref ALT_I2C_STATUS_t values that
+ * designate the status conditions to clear.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_int_clear(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask);
+
+/*!
+ * Disable the specified I2C controller interrupt status conditions identified in
+ * the mask.
+ *
+ * This function disables one or more of the status conditions as contributors to
+ * the \b ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ interrupt signal state.
+ *
+ * NOTE: A cleared bit for any status condition in the mask value does not have
+ * the effect of enabling it as a contributor to the \b
+ * ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ interrupt signal state. The function
+ * alt_i2c_int_enable() is used to enable status source conditions.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param mask
+ * Specifies the status conditions to disable as interrupt source
+ * contributors. \e mask is a mask of logically OR'ed \ref
+ * ALT_I2C_STATUS_t values that designate the status conditions to
+ * disable.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_int_disable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask);
+
+/*!
+ * Enable the specified I2C controller interrupt status conditions identified in
+ * the mask.
+ *
+ * This function enables one or more of the status conditions as contributors to
+ * the \b ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ interrupt signal state.
+ *
+ * NOTE: A cleared bit for any status condition in the mask value does not have
+ * the effect of disabling it as a contributor to the \b
+ * ALT_INT_INTERRUPT_I2C<em>n</em>_IRQ interrupt signal state. The function
+ * alt_i2c_int_disable() is used to disable status source conditions.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param mask
+ * Specifies the status conditions to enable as interrupt source
+ * contributors. \e mask is a mask of logically OR'ed \ref
+ * ALT_I2C_STATUS_t values that designate the status conditions to
+ * enable.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_int_enable(ALT_I2C_DEV_t *i2c_dev, const uint32_t mask);
+
+/*!
+ * Gets the cause of I2C transmission abort. A I2C transmission abort indicates
+ * that the I2C transmitter is unable to complete the intended actions on the
+ * contents of the transmit FIFO. This situation can occur both as an I2C master
+ * or an I2C slave, and is referred to as a "transmit abort".
+ *
+ * The returned value of this function is the value of the IC_TX_ABRT_SOURCE
+ * register which indicates the cause why the transmit abort occurred.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param cause
+ * [out] A pointer to a bit mask of the \ref ALT_I2C_TX_ABORT_CAUSE_t
+ * causes of the transmission abort.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_TX_ABRT_SOURCE
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_tx_abort_cause_get(ALT_I2C_DEV_t *i2c_dev,
+ ALT_I2C_TX_ABORT_CAUSE_t *cause);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ALT_I2C_RX_FIFO RX FIFO Management
+ *
+ * The receive FIFO has a configurable threshold value that controls the level of
+ * entries (or above) that sets the RX_FULL status condition and triggers an
+ * interrupt. The valid range is 0 - (ALT_I2C_RX_FIFO_NUM_ENTRIES-1), with the
+ * additional restriction that I2C controller does not allow this value to be set
+ * to a value larger than the depth of the buffer. If an attempt is made to do
+ * that, the actual value set will be the maximum depth of the buffer. A value of
+ * 0 sets the threshold for 1 entry, and a value of (ALT_I2C_RX_FIFO_NUM_ENTRIES-1)
+ * sets the threshold for ALT_I2C_RX_FIFO_NUM_ENTRIES entries.
+ *
+ * @{
+ */
+
+/*!
+ * The number of entries (depth) of the I2C controller receive FIFO.
+ */
+#define ALT_I2C_RX_FIFO_NUM_ENTRIES 64
+
+/*!
+ * Returns ALT_E_TRUE when the receive FIFO is empty.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_STATUS.RFNE == 0
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_rx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Returns ALT_E_TRUE when the receive FIFO is completely full.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_STATUS.RFF == 1
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_rx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Returns the number of valid entries in the receive FIFO.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param num_entries
+ * [out] The number of entries in the receive FIFO.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_RXFLR.RXFLR
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_rx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev,
+ uint32_t *num_entries);
+
+/*!
+ * Gets the current receive FIFO threshold level value.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param threshold
+ * [out] The current threshold value.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_RX_TL.RX_TL
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev,
+ uint8_t *threshold);
+
+/*!
+ * Sets the current receive FIFO threshold level value.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param threshold
+ * The threshold value.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_RX_TL.RX_TL = threshold
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_rx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev,
+ const uint8_t threshold);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ALT_I2C_TX_FIFO TX FIFO Management
+ *
+ * The transmit FIFO has a configurable threshold value that controls the level of
+ * entries (or below) that sets the TX_EMPTY status condition and triggers an
+ * interrupt. The valid range is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES-1), with the
+ * additional restriction that I2C controller does not allow this value to be set
+ * to a value larger than the depth of the buffer. If an attempt is made to do
+ * that, the actual value set will be the maximum depth of the buffer. A value of
+ * 0 sets the threshold for 0 entries, and a value of (ALT_I2C_TX_FIFO_NUM_ENTRIES-1)
+ * sets the threshold for (ALT_I2C_TX_FIFO_NUM_ENTRIES-1) entries.
+ *
+ * @{
+ */
+
+/*!
+ * The number of entries (depth) of the I2C controller transmit FIFO.
+ */
+#define ALT_I2C_TX_FIFO_NUM_ENTRIES 64
+
+/*!
+ * Returns ALT_E_TRUE when the transmit FIFO is empty.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_STATUS.TFE == 1
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_tx_fifo_is_empty(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Returns ALT_E_TRUE when the transmit FIFO is completely full.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_STATUS.TFNF == 0
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_tx_fifo_is_full(ALT_I2C_DEV_t *i2c_dev);
+
+/*!
+ * Returns the number of valid entries in the transmit FIFO.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param num_entries
+ * [out] The number of entries in the transmit FIFO.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_TXFLR.TXFLR
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_tx_fifo_level_get(ALT_I2C_DEV_t *i2c_dev,
+ uint32_t *num_entries);
+
+/*!
+ * Gets the current transmit FIFO threshold level value.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param threshold
+ * [out] The current threshold value.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_TX_TL.TX_TL
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_get(ALT_I2C_DEV_t *i2c_dev,
+ uint8_t *threshold);
+
+/*!
+ * Sets the current transmit FIFO threshold level value.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param threshold
+ * The threshold value.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ *
+ * \internal
+ * IC_TX_TL.TX_TL = threshold
+ * \endinternal
+ */
+ALT_STATUS_CODE alt_i2c_tx_fifo_threshold_set(ALT_I2C_DEV_t *i2c_dev,
+ const uint8_t threshold);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup ALT_I2C_DMA DMA Interface
+ *
+ * The DMA interface has a configurable threshold value that controls the
+ * level of entries that triggers the burst handshaking request used for DMA
+ * integration.
+ *
+ * For the TX threshold, if the number of entries in the TX FIFO is at or
+ * below the set threshold, a DMA handshaking request will be made. The valid
+ * range for the TX threshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1).
+ *
+ * For the RX threshold, if the number of entries in the RX FIFO is above the
+ * set threshold, a DMA handshaking request will be made. The valid range for
+ * the RX treshold is 0 - (ALT_I2C_TX_FIFO_NUM_ENTRIES - 1).
+ *
+ * Having a higher threshold can improve the AXI bus utilization at the
+ * expense of the likelyhoold of overflow / underflow conditions.
+ * @{
+ */
+
+/*!
+ * Gets the current RX DMA threshold level value.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param threshold
+ * [out] The threshold value.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ */
+ALT_STATUS_CODE alt_i2c_rx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold);
+
+/*!
+ * Sets the current RX DMA threshold level value.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param threshold
+ * The threshold value.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ */
+ALT_STATUS_CODE alt_i2c_rx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold);
+
+/*!
+ * Gets the current TX DMA threshold level value.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param threshold
+ * [out] The threshold value.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ */
+ALT_STATUS_CODE alt_i2c_tx_dma_threshold_get(ALT_I2C_DEV_t * i2c_dev, uint8_t * threshold);
+
+/*!
+ * Sets the current TX DMA threshold level value.
+ *
+ * \param i2c_dev
+ * A pointer to the I2C controller device block instance.
+ *
+ * \param threshold
+ * The threshold value.
+ *
+ * \retval ALT_E_SUCCESS Successful status.
+ * \retval ALT_E_ERROR Details about error status code
+ */
+ALT_STATUS_CODE alt_i2c_tx_dma_threshold_set(ALT_I2C_DEV_t * i2c_dev, uint8_t threshold);
+
+/*! @} */
+
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __ALT_I2C_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h
new file mode 100644
index 0000000000..004fd3188c
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_interrupt_common.h
@@ -0,0 +1,533 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __ALT_INT_COMMON_H__
+#define __ALT_INT_COMMON_H__
+
+#include "hwlib.h"
+#include <stdbool.h>
+#include <stddef.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+/*!
+ * \addtogroup INT_COMMON Interrupt Controller Common Definitions
+ *
+ * This module contains the definitions common to the Interrupt Controller
+ * Low-Level API and Interrupt Controller Manager Interface.
+ *
+ * @{
+ */
+
+/*!
+ * This type definition enumerates all the interrupt identification types.
+ */
+typedef enum ALT_INT_INTERRUPT_e
+{
+ ALT_INT_INTERRUPT_SGI0 = 0, /*!< # */
+ ALT_INT_INTERRUPT_SGI1 = 1, /*!< # */
+ ALT_INT_INTERRUPT_SGI2 = 2, /*!< # */
+ ALT_INT_INTERRUPT_SGI3 = 3, /*!< # */
+ ALT_INT_INTERRUPT_SGI4 = 4, /*!< # */
+ ALT_INT_INTERRUPT_SGI5 = 5, /*!< # */
+ ALT_INT_INTERRUPT_SGI6 = 6, /*!< # */
+ ALT_INT_INTERRUPT_SGI7 = 7, /*!< # */
+ ALT_INT_INTERRUPT_SGI8 = 8, /*!< # */
+ ALT_INT_INTERRUPT_SGI9 = 9, /*!< # */
+ ALT_INT_INTERRUPT_SGI10 = 10, /*!< # */
+ ALT_INT_INTERRUPT_SGI11 = 11, /*!< # */
+ ALT_INT_INTERRUPT_SGI12 = 12, /*!< # */
+ ALT_INT_INTERRUPT_SGI13 = 13, /*!< # */
+ ALT_INT_INTERRUPT_SGI14 = 14, /*!< # */
+ ALT_INT_INTERRUPT_SGI15 = 15,
+ /*!<
+ * Software Generated Interrupts (SGI), 0 - 15.
+ * * All interrupts in this group are software triggered.
+ */
+
+ ALT_INT_INTERRUPT_PPI_TIMER_GLOBAL = 27, /*!< # */
+ ALT_INT_INTERRUPT_PPI_TIMER_PRIVATE = 29, /*!< # */
+ ALT_INT_INTERRUPT_PPI_TIMER_WATCHDOG = 30, /*!< # */
+ /*!<
+ * Private Peripheral Interrupts (PPI) for the Global Timer, per CPU
+ * private timer, and watchdog timer.
+ * * All interrupts in this group are edge triggered.
+ */
+
+ ALT_INT_INTERRUPT_CPU0_PARITYFAIL = 32, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_PARITYFAIL_BTAC = 33, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_PARITYFAIL_GHB = 34, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_TAG = 35, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_PARITYFAIL_I_DATA = 36, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_PARITYFAIL_TLB = 37, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_OUTER = 38, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_TAG = 39, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_PARITYFAIL_D_DATA = 40, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_DEFLAGS0 = 41, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_DEFLAGS1 = 42, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_DEFLAGS2 = 43, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_DEFLAGS3 = 44, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_DEFLAGS4 = 45, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_DEFLAGS5 = 46, /*!< # */
+ ALT_INT_INTERRUPT_CPU0_DEFLAGS6 = 47,
+ /*!<
+ * Interrupts sourced from CPU0.
+ *
+ * The ALT_INT_INTERRUPT_CPU0_PARITYFAIL interrupt combines the
+ * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
+ * for CPU0.
+ *
+ * * PARITYFAIL interrupts in this group are edge triggered.
+ * * DEFFLAGS interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_CPU1_PARITYFAIL = 48, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_PARITYFAIL_BTAC = 49, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_PARITYFAIL_GHB = 50, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_TAG = 51, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_PARITYFAIL_I_DATA = 52, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_PARITYFAIL_TLB = 53, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_OUTER = 54, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_TAG = 55, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_PARITYFAIL_D_DATA = 56, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_DEFLAGS0 = 57, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_DEFLAGS1 = 58, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_DEFLAGS2 = 59, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_DEFLAGS3 = 60, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_DEFLAGS4 = 61, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_DEFLAGS5 = 62, /*!< # */
+ ALT_INT_INTERRUPT_CPU1_DEFLAGS6 = 63,
+ /*!<
+ * Interrupts sourced from CPU1.
+ *
+ * The ALT_INT_INTERRUPT_CPU1_PARITYFAIL interrupt combines the
+ * BTAC, GHB, I_TAG, I_DATA, TLB, D_OUTER, D_TAG, and D_DATA interrupts
+ * for CPU1.
+ *
+ * * PARITYFAIL interrupts in this group are edge triggered.
+ * * DEFFLAGS interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_SCU_PARITYFAIL0 = 64, /*!< # */
+ ALT_INT_INTERRUPT_SCU_PARITYFAIL1 = 65, /*!< # */
+ ALT_INT_INTERRUPT_SCU_EV_ABORT = 66,
+ /*!<
+ * Interrupts sourced from the Snoop Control Unit (SCU).
+ * * All interrupts in this group are edge triggered.
+ */
+
+ ALT_INT_INTERRUPT_L2_ECC_BYTE_WR_IRQ = 67, /*!< # */
+ ALT_INT_INTERRUPT_L2_ECC_CORRECTED_IRQ = 68, /*!< # */
+ ALT_INT_INTERRUPT_L2_ECC_UNCORRECTED_IRQ = 69, /*!< # */
+ ALT_INT_INTERRUPT_L2_COMBINED_IRQ = 70,
+ /*!<
+ * Interrupts sourced from the L2 Cache Controller.
+ *
+ * The ALT_INT_INTERRUPT_L2_COMBINED_IRQ interrupt combines the cache
+ * controller internal DECERRINTR, ECNTRINTR, ERRRDINTR, ERRRTINTR,
+ * ERRWDINTR, ERRWTINTR, PARRDINTR, PARRTINTR, and SLVERRINTR interrupts.
+ * Consult the L2C documentation for information on these interrupts.
+ *
+ * * ECC interrupts in this group are edge triggered.
+ * * Other interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_DDR_ECC_ERROR_IRQ = 71,
+ /*!<
+ * Interrupts sourced from the SDRAM Controller.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ0 = 72, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ1 = 73, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ2 = 74, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ3 = 75, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ4 = 76, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ5 = 77, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ6 = 78, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ7 = 79, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ8 = 80, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ9 = 81, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ10 = 82, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ11 = 83, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ12 = 84, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ13 = 85, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ14 = 86, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ15 = 87, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ16 = 88, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ17 = 89, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ18 = 90, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ19 = 91, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ20 = 92, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ21 = 93, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ22 = 94, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ23 = 95, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ24 = 96, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ25 = 97, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ26 = 98, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ27 = 99, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ28 = 100, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ29 = 101, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ30 = 102, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ31 = 103, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ32 = 104, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ33 = 105, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ34 = 106, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ35 = 107, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ36 = 108, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ37 = 109, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ38 = 110, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ39 = 111, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ40 = 112, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ41 = 113, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ42 = 114, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ43 = 115, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ44 = 116, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ45 = 117, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ46 = 118, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ47 = 119, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ48 = 120, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ49 = 121, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ50 = 122, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ51 = 123, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ52 = 124, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ53 = 125, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ54 = 126, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ55 = 127, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ56 = 128, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ57 = 129, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ58 = 130, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ59 = 131, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ60 = 132, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ61 = 133, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ62 = 134, /*!< # */
+ ALT_INT_INTERRUPT_F2S_FPGA_IRQ63 = 135,
+ /*!<
+ * Interrupt request from the FPGA logic, 0 - 63.
+ * * Trigger type depends on the implementation in the FPGA.
+ */
+
+ ALT_INT_INTERRUPT_DMA_IRQ0 = 136, /*!< # */
+ ALT_INT_INTERRUPT_DMA_IRQ1 = 137, /*!< # */
+ ALT_INT_INTERRUPT_DMA_IRQ2 = 138, /*!< # */
+ ALT_INT_INTERRUPT_DMA_IRQ3 = 139, /*!< # */
+ ALT_INT_INTERRUPT_DMA_IRQ4 = 140, /*!< # */
+ ALT_INT_INTERRUPT_DMA_IRQ5 = 141, /*!< # */
+ ALT_INT_INTERRUPT_DMA_IRQ6 = 142, /*!< # */
+ ALT_INT_INTERRUPT_DMA_IRQ7 = 143, /*!< # */
+ ALT_INT_INTERRUPT_DMA_IRQ_ABORT = 144, /*!< # */
+ ALT_INT_INTERRUPT_DMA_ECC_CORRECTED_IRQ = 145, /*!< # */
+ ALT_INT_INTERRUPT_DMA_ECC_UNCORRECTED_IRQ = 146,
+ /*!<
+ * Interrupts sourced from the DMA Controller.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_EMAC0_IRQ = 147, /*!< # */
+ ALT_INT_INTERRUPT_EMAC0_TX_ECC_CORRECTED_IRQ = 148, /*!< # */
+ ALT_INT_INTERRUPT_EMAC0_TX_ECC_UNCORRECTED_IRQ = 149, /*!< # */
+ ALT_INT_INTERRUPT_EMAC0_RX_ECC_CORRECTED_IRQ = 150, /*!< # */
+ ALT_INT_INTERRUPT_EMAC0_RX_ECC_UNCORRECTED_IRQ = 151,
+ /*!<
+ * Interrupts sourced from the Ethernet MAC 0 (EMAC0).
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_EMAC1_IRQ = 152, /*!< # */
+ ALT_INT_INTERRUPT_EMAC1_TX_ECC_CORRECTED_IRQ = 153, /*!< # */
+ ALT_INT_INTERRUPT_EMAC1_TX_ECC_UNCORRECTED_IRQ = 154, /*!< # */
+ ALT_INT_INTERRUPT_EMAC1_RX_ECC_CORRECTED_IRQ = 155, /*!< # */
+ ALT_INT_INTERRUPT_EMAC1_RX_ECC_UNCORRECTED_IRQ = 156,
+ /*!<
+ * Interrupts sourced from the Ethernet MAC 1 (EMAC1).
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_USB0_IRQ = 157, /*!< # */
+ ALT_INT_INTERRUPT_USB0_ECC_CORRECTED = 158, /*!< # */
+ ALT_INT_INTERRUPT_USB0_ECC_UNCORRECTED = 159,
+ /*!<
+ * Interrupts sourced from the USB OTG 0.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_USB1_IRQ = 160, /*!< # */
+ ALT_INT_INTERRUPT_USB1_ECC_CORRECTED = 161, /*!< # */
+ ALT_INT_INTERRUPT_USB1_ECC_UNCORRECTED = 162,
+ /*!<
+ * Interrupts sourced from the USB OTG 1.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_CAN0_STS_IRQ = 163, /*!< # */
+ ALT_INT_INTERRUPT_CAN0_MO_IRQ = 164, /*!< # */
+ ALT_INT_INTERRUPT_CAN0_ECC_CORRECTED_IRQ = 165, /*!< # */
+ ALT_INT_INTERRUPT_CAN0_ECC_UNCORRECTED_IRQ = 166,
+ /*!<
+ * Interrupts sourced from the CAN Controller 0.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_CAN1_STS_IRQ = 167, /*!< # */
+ ALT_INT_INTERRUPT_CAN1_MO_IRQ = 168, /*!< # */
+ ALT_INT_INTERRUPT_CAN1_ECC_CORRECTED_IRQ = 169, /*!< # */
+ ALT_INT_INTERRUPT_CAN1_ECC_UNCORRECTED_IRQ = 170,
+ /*!<
+ * Interrupts sourced from the CAN Controller 1.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_SDMMC_IRQ = 171, /*!< # */
+ ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_CORRECTED = 172, /*!< # */
+ ALT_INT_INTERRUPT_SDMMC_PORTA_ECC_UNCORRECTED = 173, /*!< # */
+ ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_CORRECTED = 174, /*!< # */
+ ALT_INT_INTERRUPT_SDMMC_PORTB_ECC_UNCORRECTED = 175,
+ /*!<
+ * Interrupts sourced from the SDMMC Controller.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_NAND_IRQ = 176, /*!< # */
+ ALT_INT_INTERRUPT_NANDR_ECC_CORRECTED_IRQ = 177, /*!< # */
+ ALT_INT_INTERRUPT_NANDR_ECC_UNCORRECTED_IRQ = 178, /*!< # */
+ ALT_INT_INTERRUPT_NANDW_ECC_CORRECTED_IRQ = 179, /*!< # */
+ ALT_INT_INTERRUPT_NANDW_ECC_UNCORRECTED_IRQ = 180, /*!< # */
+ ALT_INT_INTERRUPT_NANDE_ECC_CORRECTED_IRQ = 181, /*!< # */
+ ALT_INT_INTERRUPT_NANDE_ECC_UNCORRECTED_IRQ = 182,
+ /*!<
+ * Interrupts sourced from the NAND Controller.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_QSPI_IRQ = 183, /*!< # */
+ ALT_INT_INTERRUPT_QSPI_ECC_CORRECTED_IRQ = 184, /*!< # */
+ ALT_INT_INTERRUPT_QSPI_ECC_UNCORRECTED_IRQ = 185,
+ /*!<
+ * Interrupts sourced from the QSPI Controller.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_SPI0_IRQ = 186, /*!< # */
+ ALT_INT_INTERRUPT_SPI1_IRQ = 187, /*!< # */
+ ALT_INT_INTERRUPT_SPI2_IRQ = 188, /*!< # */
+ ALT_INT_INTERRUPT_SPI3_IRQ = 189,
+ /*!<
+ * Interrupts sourced from the SPI Controllers 0 - 3.
+ * SPI0_IRQ corresponds to SPIM0. SPI1_IRQ corresponds to SPIM1.
+ * SPI2_IRQ corresponds to SPIS0. SPI3_IRQ corresponds to SPIS1.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_I2C0_IRQ = 190, /*!< # */
+ ALT_INT_INTERRUPT_I2C1_IRQ = 191, /*!< # */
+ ALT_INT_INTERRUPT_I2C2_IRQ = 192, /*!< # */
+ ALT_INT_INTERRUPT_I2C3_IRQ = 193,
+ /*!<
+ * Interrupts sourced from the I2C Controllers 0 - 3.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_UART0 = 194, /*!< # */
+ ALT_INT_INTERRUPT_UART1 = 195,
+ /*!<
+ * Interrupts sourced from the UARTs 0 - 1.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_GPIO0 = 196, /*!< # */
+ ALT_INT_INTERRUPT_GPIO1 = 197, /*!< # */
+ ALT_INT_INTERRUPT_GPIO2 = 198,
+ /*!<
+ * Interrupts sourced from the GPIO 0 - 2.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_TIMER_L4SP_0_IRQ = 199, /*!< # */
+ ALT_INT_INTERRUPT_TIMER_L4SP_1_IRQ = 200, /*!< # */
+ ALT_INT_INTERRUPT_TIMER_OSC1_0_IRQ = 201, /*!< # */
+ ALT_INT_INTERRUPT_TIMER_OSC1_1_IRQ = 202,
+ /*!<
+ * Interrupts sourced from the Timer controllers.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_WDOG0_IRQ = 203, /*!< # */
+ ALT_INT_INTERRUPT_WDOG1_IRQ = 204,
+ /*!<
+ * Interrupts sourced from the Watchdog Timers 0 - 1.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_CLKMGR_IRQ = 205,
+ /*!<
+ * Interrupts sourced from the Clock Manager.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_MPUWAKEUP_IRQ = 206,
+ /*!<
+ * Interrupts sourced from the Clock Manager MPU Wakeup.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_FPGA_MAN_IRQ = 207,
+ /*!<
+ * Interrupts sourced from the FPGA Manager.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_NCTIIRQ0 = 208, /*!< # */
+ ALT_INT_INTERRUPT_NCTIIRQ1 = 209,
+ /*!<
+ * Interrupts sourced from the CoreSight for CPU0 and CPU1's CTI.
+ * * All interrupts in this group are level triggered.
+ */
+
+ ALT_INT_INTERRUPT_RAM_ECC_CORRECTED_IRQ = 210, /*!< # */
+ ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ = 211
+ /*!<
+ * Interrupts sourced from the On-chip RAM.
+ * * All interrupts in this group are level triggered.
+ */
+
+} ALT_INT_INTERRUPT_t;
+
+/*!
+ * This is the CPU target type. It is used to specify a set of CPUs on the
+ * system. If only bit 0 is set then it specifies a set of CPUs containing
+ * only CPU 0. Multiple CPUs can be specified by setting the appropriate bit
+ * up to the number of CPUs on the system.
+ */
+typedef uint32_t alt_int_cpu_target_t;
+
+/*!
+ * This type definition enumerates all the interrupt trigger types.
+ */
+typedef enum ALT_INT_TRIGGER_e
+{
+ /*!
+ * Edge triggered interrupt. This applies to Private Peripheral Interrupts
+ * (PPI) and Shared Peripheral Interrupts (SPI) only, with interrupt IDs
+ * 16 - 1019.
+ */
+ ALT_INT_TRIGGER_EDGE,
+
+ /*!
+ * Level triggered interrupt. This applies to Private Peripheral
+ * Interrupts (PPI) and Shared Peripheral Interrupts (SPI) only, with
+ * interrupt IDs 16 - 1019.
+ */
+ ALT_INT_TRIGGER_LEVEL,
+
+ /*!
+ * Software triggered interrupt. This applies to Software Generated
+ * Interrupts (SGI) only, with interrupt IDs 0 - 15.
+ */
+ ALT_INT_TRIGGER_SOFTWARE,
+
+ /*!
+ * All triggering types except for those in the Shared Peripheral Interrupts
+ * (SPI) F2S FPGA family interrupts can be determined by the system
+ * automatically. In all functions which ask for the triggering type, the
+ * ALT_INT_TRIGGER_AUTODETECT can be used to select the correct trigger
+ * type for all non F2S interrupt types.
+ */
+ ALT_INT_TRIGGER_AUTODETECT,
+
+ /*!
+ * The interrupt triggering information is not applicable. This is possibly
+ * due to querying an invalid interrupt identifier.
+ */
+ ALT_INT_TRIGGER_NA
+}
+ALT_INT_TRIGGER_t;
+
+/*!
+ * This type definition enumerates all the target list filter options. This is
+ * used by the trigger Software Generated Interrupt (SGI) feature to issue a
+ * SGI to the specified processor(s) in the system. Depending on the target
+ * list filter and the target list, interrupts can be routed to any
+ * combinations of CPUs.
+ */
+typedef enum ALT_INT_SGI_TARGET_e
+{
+ /*!
+ * This filter list uses the target list parameter to specify which CPUs
+ * to send the interrupt to. If target list is 0, no interrupts are sent.
+ */
+ ALT_INT_SGI_TARGET_LIST,
+
+ /*!
+ * This filter list sends the interrupt all CPUs except the current CPU.
+ * The target list parameter is ignored.
+ */
+ ALT_INT_SGI_TARGET_ALL_EXCL_SENDER,
+
+ /*!
+ * This filter list sends the interrupt to the current CPU only. The
+ * target list parameter is ignored.
+ */
+ ALT_INT_SGI_TARGET_SENDER_ONLY
+}
+ALT_INT_SGI_TARGET_t;
+
+/*!
+ * Extracts the CPUID field from the ICCIAR register.
+ */
+#define ALT_INT_ICCIAR_CPUID_GET(icciar) ((icciar >> 10) & 0x7)
+
+/*!
+ * Extracts the ACKINTID field from the ICCIAR register.
+ */
+#define ALT_INT_ICCIAR_ACKINTID_GET(icciar) (icciar & 0x3FF)
+
+/*!
+ * The callback to use when an interrupt needs to be serviced.
+ *
+ * \param icciar The Interrupt Controller CPU Interrupt
+ * Acknowledgement Register value (ICCIAR) value
+ * corresponding to the current interrupt.
+ *
+ * \param context The user provided context.
+ */
+typedef void (*alt_int_callback_t)(uint32_t icciar, void * context);
+
+/*!
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __ALT_INT_COMMON_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h
new file mode 100644
index 0000000000..2ead15df86
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_mpu_registers.h
@@ -0,0 +1,156 @@
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __ALT_MPUSCU_H__
+#define __ALT_MPUSCU_H__
+
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+
+/************************************************************************************************************/
+/* alt_mpuscu.h */
+/* */
+/* Definitions for the ARM Snoop Control Unit, which contains the Snoop Control Unit, the Watchdog */
+/* Timer, the Private Timer, the Global Timer, the Interrupt Controller, and the Interrupt Distributor. */
+/* */
+/************************************************************************************************************/
+
+#ifndef ALT_HPS_ADDR
+#define ALT_HPS_ADDR 0x00
+#endif
+
+
+/* ALT_MPUSCU_OFST is defined as a offset from ALT_HPS_ADDR in the SoCAL file hps.h */
+/* and is the address of the base of the Snoop Control Unit (SCU) */
+#define GLOBALTMR_BASE (ALT_MPUSCU_OFST + GLOBALTMR_MODULE_BASE_OFFSET)
+#define CPU_WDTGPT_TMR_BASE (ALT_MPUSCU_OFST + WDOG_TIMER_MODULE_BASE_OFFSET)
+#define CPU_PRIVATE_TMR_BASE (ALT_MPUSCU_OFST + CPU_PRIV_TIMER_MODULE_BASE_OFFSET)
+#define CPU_INT_CTRL_BASE (ALT_MPUSCU_OFST + INT_CONTROLLER_MODULE_BASE_OFFSET)
+#define CPU_INT_DIST_BASE (ALT_MPUSCU_OFST + INT_DISTRIBUTOR_MODULE_BASE_OFFSET)
+
+
+ /* offsets */
+ /* Global Timer offsets */
+#define GLOBALTMR_MODULE_BASE_OFFSET 0x00000200
+#define GLOBALTMR_CNTR_LO_REG_OFFSET 0x00000000
+#define GLOBALTMR_CNTR_HI_REG_OFFSET 0x00000004
+#define GLOBALTMR_CTRL_REG_OFFSET 0x00000008
+#define GLOBALTMR_INT_STAT_REG_OFFSET 0x0000000C
+#define GLOBALTMR_COMP_LO_REG_OFFSET 0x00000010
+#define GLOBALTMR_COMP_HI_REG_OFFSET 0x00000014
+#define GLOBALTMR_AUTOINC_REG_OFFSET 0x00000018
+
+/* Global Timer bitmasks */
+#define GLOBALTMR_ENABLE_BIT 0x00000001
+#define GLOBALTMR_COMP_ENABLE_BIT 0x00000002
+#define GLOBALTMR_INT_ENABLE_BIT 0x00000004
+#define GLOBALTMR_AUTOINC_ENABLE_BIT 0x00000008
+#define GLOBALTMR_PS_MASK 0x0000FF00
+#define GLOBALTMR_PS_SHIFT 8
+#define GLOBALTMR_INT_STATUS_BIT 0x00000001
+
+/* Global timer constants */
+#define GLOBALTMR_MAX 0xFFFFFFFF
+#define GLOBALTMR_PS_MAX 0x000000FF
+
+
+/* Private timer offsets */
+#define CPU_PRIV_TIMER_MODULE_BASE_OFFSET 0x00000600
+#define CPU_PRIV_TMR_LOAD_REG_OFFSET 0x00000000
+#define CPU_PRIV_TMR_CNTR_REG_OFFSET 0x00000004
+#define CPU_PRIV_TMR_CTRL_REG_OFFSET 0x00000008
+#define CPU_PRIV_TMR_INT_STATUS_REG_OFFSET 0x0000000C
+
+/* Private timer bitmasks */
+#define CPU_PRIV_TMR_ENABLE 0x00000001
+#define CPU_PRIV_TMR_AUTO_RELOAD 0x00000002
+#define CPU_PRIV_TMR_INT_EN 0x00000004
+#define CPU_PRIV_TMR_PS_MASK 0x0000FF00
+#define CPU_PRIV_TMR_PS_SHIFT 8
+#define CPU_PRIV_TMR_INT_STATUS 0x00000001
+
+/* Private timer constants */
+#define CPU_PRIV_TMR_MAX 0xFFFFFFFF
+#define CPU_PRIV_TMR_PS_MAX 0x000000FF
+
+
+
+ /* Watchdog timer offsets */
+#define WDOG_TIMER_MODULE_BASE_OFFSET 0x00000620
+#define WDOG_LOAD_REG_OFFSET 0x00000000
+#define WDOG_CNTR_REG_OFFSET 0x00000004
+#define WDOG_CTRL_REG_OFFSET 0x00000008
+#define WDOG_INTSTAT_REG_OFFSET 0x0000000C
+#define WDOG_RSTSTAT_REG_OFFSET 0x00000010
+#define WDOG_DISABLE_REG_OFFSET 0x00000014
+
+ /* Watchdog timer bitmasks : */
+ /* Control Register bitmasks */
+#define WDOG_TMR_ENABLE 0x00000001
+#define WDOG_AUTO_RELOAD 0x00000002
+#define WDOG_INT_EN 0x00000004
+#define WDOG_WDT_MODE 0x00000008
+#define WDOG_PS_MASK 0x0000FF00
+#define WDOG_PS_SHIFT 8
+ /* Interrupt Status Register bitmasks */
+#define WDOG_INT_STAT_BIT 0x00000001
+ /* Reset Status Register bitmasks */
+#define WDOG_RST_STAT_BIT 0x00000001
+
+ /* Watchdog timer constants */
+#define WDOG_TMR_MAX UINT32_MAX
+#define WDOG_PS_MAX UINT8_MAX
+#define WDOG_DISABLE_VAL0 0x12345678
+#define WDOG_DISABLE_VAL1 0x87654321
+
+
+
+ /* Interrupt Manager offsets */
+/* <Add definitions here> */
+#define INT_CONTROLLER_MODULE_BASE_OFFSET 0x00000100
+#define INT_DISTRIBUTOR_MODULE_BASE_OFFSET 0x00001000
+#define INT_DIST_TYPE_REG 0x00000004
+
+
+/* Upper bound of the MPUSCU address space */
+#define MPUSCU_MAX 0x00001FFF
+
+
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* __ALT_MPUSCU_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h
new file mode 100644
index 0000000000..21fd3a957d
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_qspi_private.h
@@ -0,0 +1,167 @@
+/******************************************************************************
+ *
+ * Copyright 2013 Altera Corporation. All Rights Reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ *
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+ * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+/*! \file
+ * Altera - QSPI Flash Controller Module
+ */
+
+#ifndef __ALT_QSPI_PRIVATE_H__
+#define __ALT_QSPI_PRIVATE_H__
+
+#include "socal/socal.h"
+
+//
+// This section provisions support for various flash devices.
+//
+
+#define ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT 1
+
+/////
+
+#define ALT_QSPI_PAGE_ADDR_MSK 0xFFFFFF00
+#define ALT_QSPI_PAGE_SIZE 0x00000100 // 256 B
+#define ALT_QSPI_SUBSECTOR_ADDR_MSK 0xFFFFF000
+#define ALT_QSPI_SUBSECTOR_SIZE 0x00001000 // 4096 B
+#define ALT_QSPI_SECTOR_ADDR_MSK 0xFFFF0000
+#define ALT_QSPI_SECTOR_SIZE 0x00010000 // 64 KiB
+#define ALT_QSPI_BANK_ADDR_MSK 0xFF000000
+#define ALT_QSPI_BANK_SIZE 0x01000000 // 16 MiB
+
+#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
+#define ALT_QSPI_N25Q_DIE_ADDR_MSK 0xFE000000
+#define ALT_QSPI_N25Q_DIE_SIZE 0x02000000 // 32 MiB
+#endif
+
+/////
+
+// Default delay timing (in ns) for N25Q.
+// These values are from the N25Q handbook. The timing correctness is difficult
+// to test because the test setup does not feature mutliple chips.
+#define ALT_QSPI_TSHSL_NS_DEF (50)
+#define ALT_QSPI_TSD2D_NS_DEF (0)
+#define ALT_QSPI_TCHSH_NS_DEF (4)
+#define ALT_QSPI_TSLCH_NS_DEF (4)
+
+/*
+// Default delay timing (in ns)
+#define ALT_QSPI_TSHSL_NS_DEF (200)
+#define ALT_QSPI_TSD2D_NS_DEF (255)
+#define ALT_QSPI_TCHSH_NS_DEF (20)
+#define ALT_QSPI_TSLCH_NS_DEF (20)
+*/
+
+// Flash commands
+#define ALT_QSPI_STIG_OPCODE_READ (0x03)
+#define ALT_QSPI_STIG_OPCODE_4BYTE_READ (0x13)
+#define ALT_QSPI_STIG_OPCODE_FASTREAD (0x0B)
+#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_OUTPUT (0x3B)
+#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_OUTPUT (0x6B)
+#define ALT_QSPI_STIG_OPCODE_FASTREAD_DUAL_IO (0xBB)
+#define ALT_QSPI_STIG_OPCODE_FASTREAD_QUAD_IO (0xEB)
+#define ALT_QSPI_STIG_OPCODE_PP (0x02)
+#define ALT_QSPI_STIG_OPCODE_DUAL_PP (0xA2)
+#define ALT_QSPI_STIG_OPCODE_QUAD_PP (0x32)
+#define ALT_QSPI_STIG_OPCODE_RDID (0x9F)
+#define ALT_QSPI_STIG_OPCODE_WREN (0x06)
+#define ALT_QSPI_STIG_OPCODE_WRDIS (0x04)
+#define ALT_QSPI_STIG_OPCODE_RDSR (0x05)
+#define ALT_QSPI_STIG_OPCODE_WRSR (0x01)
+#define ALT_QSPI_STIG_OPCODE_SUBSEC_ERASE (0x20)
+#define ALT_QSPI_STIG_OPCODE_SEC_ERASE (0xD8)
+#define ALT_QSPI_STIG_OPCODE_BULK_ERASE (0xC7)
+#define ALT_QSPI_STIG_OPCODE_DIE_ERASE (0xC4)
+#define ALT_QSPI_STIG_OPCODE_CHIP_ERASE (0x60)
+#define ALT_QSPI_STIG_OPCODE_RD_EXT_REG (0xC8)
+#define ALT_QSPI_STIG_OPCODE_WR_EXT_REG (0xC5)
+#define ALT_QSPI_STIG_OPCODE_RD_STAT_REG (0x05)
+#define ALT_QSPI_STIG_OPCODE_WR_STAT_REG (0x01)
+#define ALT_QSPI_STIG_OPCODE_ENTER_4BYTE_MODE (0xB7)
+#define ALT_QSPI_STIG_OPCODE_EXIT_4BYTE_MODE (0xE9)
+
+// Micron commands, for 512 Mib, 1 Gib (64 MiB, 128 MiB) parts.
+#if ALT_QSPI_PROVISION_MICRON_N25Q_SUPPORT
+#define ALT_QSPI_STIG_OPCODE_RESET_EN (0x66)
+#define ALT_QSPI_STIG_OPCODE_RESET_MEM (0x99)
+#define ALT_QSPI_STIG_OPCODE_RDFLGSR (0x70)
+#define ALT_QSPI_STIG_OPCODE_CLRFLGSR (0x50)
+#define ALT_QSPI_STIG_OPCODE_DISCVR_PARAM (0x5A)
+#endif
+
+// Spansion commands
+// #define OPCODE_ECRM (0xFF) // Exit continuous read mode
+
+#define QSPI_READ_CLK_MHZ (50)
+#define QSPI_FASTREAD_CLK_MHZ (100)
+
+// Manufacturer ID
+#define ALT_QSPI_STIG_RDID_JEDECID_MICRON (0x20)
+#define ALT_QSPI_STIG_RDID_JEDECID_NUMONYX (0x20) // Same as Micron
+#define ALT_QSPI_STIG_RDID_JEDECID_SPANSION (0xEF)
+#define ALT_QSPI_STIG_RDID_JEDECID_WINBOND (0xEF) // Same as Spansion
+#define ALT_QSPI_STIG_RDID_JEDECID_MACRONIC (0xC2)
+#define ALT_QSPI_STIG_RDID_JEDECID_ATMEL (0x1F)
+
+#define ALT_QSPI_STIG_RDID_JEDECID_GET(value) ((value >> 0) & 0xff)
+#define ALT_QSPI_STIG_RDID_CAPACITYID_GET(value) ((value >> 16) & 0xff)
+
+#define ALT_QSPI_STIG_FLAGSR_ERASEPROGRAMREADY_GET(value) ((value >> 7) & 0x1)
+#define ALT_QSPI_STIG_FLAGSR_ERASEREADY_GET(value) ((value >> 7) & 0x1)
+#define ALT_QSPI_STIG_FLAGSR_PROGRAMREADY_GET(value) ((value >> 7) & 0x1)
+#define ALT_QSPI_STIG_FLAGSR_ERASEERROR_GET(value) ((value >> 5) & 0x1)
+#define ALT_QSPI_STIG_FLAGSR_PROGRAMERROR_GET(value) ((value >> 4) & 0x1)
+#define ALT_QSPI_STIG_FLAGSR_ADDRESSINGMODE_GET(value) ((value >> 1) & 0x1)
+#define ALT_QSPI_STIG_FLAGSR_PROTECTIONERROR_GET(value) ((value >> 0) & 0x1)
+
+#define ALT_QSPI_STIG_SR_BUSY_GET(value) ((value >> 0) & 0x1)
+
+/////
+
+#define ALT_QSPI_TIMEOUT_INFINITE (0xffffffff)
+
+ALT_STATUS_CODE alt_qspi_replace(uint32_t dst, const void * src, size_t size);
+
+ALT_STATUS_CODE alt_qspi_stig_cmd(uint32_t opcode, uint32_t dummy, uint32_t timeout);
+ALT_STATUS_CODE alt_qspi_stig_rd_cmd(uint8_t opcode, uint32_t dummy,
+ uint32_t num_bytes, uint32_t * output,
+ uint32_t timeout);
+ALT_STATUS_CODE alt_qspi_stig_wr_cmd(uint8_t opcode, uint32_t dummy,
+ uint32_t num_bytes, const uint32_t * input,
+ uint32_t timeout);
+ALT_STATUS_CODE alt_qspi_stig_addr_cmd(uint8_t opcode, uint32_t dummy,
+ uint32_t address,
+ uint32_t timeout);
+
+ALT_STATUS_CODE alt_qspi_device_wren(void);
+ALT_STATUS_CODE alt_qspi_device_wrdis(void);
+ALT_STATUS_CODE alt_qspi_device_rdid(uint32_t * rdid);
+ALT_STATUS_CODE alt_qspi_discovery_parameter(uint32_t * param);
+ALT_STATUS_CODE alt_qspi_device_bank_select(uint32_t bank);
+
+#endif // __ALT_PRIVATE_QSPI_H__
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h
new file mode 100644
index 0000000000..d719e3f05e
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_reset_manager.h
@@ -0,0 +1,291 @@
+/*! \file
+ * Altera - SoC Reset Manager
+ */
+
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __ALT_RESET_MGR_H__
+#define __ALT_RESET_MGR_H__
+
+#include "hwlib.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*! \addtogroup RST_MGR The Reset Manager
+ *
+ * The Reset Manager API defines functions for accessing, configuring, and
+ * controlling the HPS reset behavior.
+ * @{
+ */
+
+/******************************************************************************/
+/*! \addtogroup RST_MGR_STATUS Reset Status
+ *
+ * This functional group provides information on various aspects of SoC reset
+ * status and timeout events.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * This type definition enumerates the set of reset causes and timeout events as
+ * register mask values.
+ */
+typedef enum ALT_RESET_EVENT_e
+{
+ /*! Power-On Voltage Detector Cold Reset */
+ ALT_RESET_EVENT_PORVOLTRST = 0x00000001,
+
+ /*! nPOR Pin Cold Reset */
+ ALT_RESET_EVENT_NPORPINRST = 0x00000002,
+
+ /*! FPGA Core Cold Reset */
+ ALT_RESET_EVENT_FPGACOLDRST = 0x00000004,
+
+ /*! CONFIG_IO Cold Reset */
+ ALT_RESET_EVENT_CONFIGIOCOLDRST = 0x00000008,
+
+ /*! Software Cold Reset */
+ ALT_RESET_EVENT_SWCOLDRST = 0x00000010,
+
+ /*! nRST Pin Warm Reset */
+ ALT_RESET_EVENT_NRSTPINRST = 0x00000100,
+
+ /*! FPGA Core Warm Reset */
+ ALT_RESET_EVENT_FPGAWARMRST = 0x00000200,
+
+ /*! Software Warm Reset */
+ ALT_RESET_EVENT_SWWARMRST = 0x00000400,
+
+ /*! MPU Watchdog 0 Warm Reset */
+ ALT_RESET_EVENT_MPUWD0RST = 0x00001000,
+
+ /*! MPU Watchdog 1 Warm Reset */
+ ALT_RESET_EVENT_MPUWD1RST = 0x00002000,
+
+ /*! L4 Watchdog 0 Warm Reset */
+ ALT_RESET_EVENT_L4WD0RST = 0x00004000,
+
+ /*! L4 Watchdog 1 Warm Reset */
+ ALT_RESET_EVENT_L4WD1RST = 0x00008000,
+
+ /*! FPGA Core Debug Reset */
+ ALT_RESET_EVENT_FPGADBGRST = 0x00040000,
+
+ /*! DAP Debug Reset */
+ ALT_RESET_EVENT_CDBGREQRST = 0x00080000,
+
+ /*! SDRAM Self-Refresh Timeout */
+ ALT_RESET_EVENT_SDRSELFREFTIMEOUT = 0x01000000,
+
+ /*! FPGA manager handshake Timeout */
+ ALT_RESET_EVENT_FPGAMGRHSTIMEOUT = 0x02000000,
+
+ /*! SCAN manager handshake Timeout */
+ ALT_RESET_EVENT_SCANHSTIMEOUT = 0x04000000,
+
+ /*! FPGA handshake Timeout */
+ ALT_RESET_EVENT_FPGAHSTIMEOUT = 0x08000000,
+
+ /*! ETR Stall Timeout */
+ ALT_RESET_EVENT_ETRSTALLTIMEOUT = 0x10000000
+} ALT_RESET_EVENT_t;
+
+/******************************************************************************/
+/*!
+ * Gets the reset and timeout events that caused the last reset.
+ *
+ * The ALT_RESET_EVENT_t enumeration values should be used to selectively
+ * examine the returned reset cause(s).
+ *
+ * \returns A mask of the reset and/or timeout events that caused the last
+ * reset.
+ */
+uint32_t alt_reset_event_get(void);
+
+/******************************************************************************/
+/*!
+ * Clears the reset and timeout events that caused the last reset.
+ *
+ * \param event_mask
+ * A mask of the selected reset and timeout events to clear in the
+ * Reset Manager \e stat register. The mask selection can be formed
+ * using the ALT_RESET_EVENT_t enumeration values.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_reset_event_clear(uint32_t event_mask);
+
+/*! @} */
+
+/******************************************************************************/
+/*! \addtogroup RST_MGR_CTRL Reset Control
+ *
+ * This functional group provides global and selective reset control for the SoC
+ * and its constituent modules.
+ *
+ * @{
+ */
+
+/******************************************************************************/
+/*!
+ * Initiate a cold reset of the SoC.
+ *
+ * If this function is successful, then it should never return.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_reset_cold_reset(void);
+
+/******************************************************************************/
+/*!
+ * Initiate a warm reset of the SoC.
+ *
+ * Perform a hardware sequenced warm reset of the SoC. A hardware sequenced
+ * reset handshake with certain modules can optionally be requested in an
+ * attempt to ensure an orderly reset transition.
+ *
+ * \param warm_reset_delay
+ * Specifies the number of cycles after the Reset Manager releases
+ * the Clock Manager reset before releasing any other hardware
+ * controlled resets. Value must be greater than 16 and less than
+ * 256.
+ *
+ * \param nRST_pin_clk_assertion
+ * Specifies that number of clock cycles (osc1_clk?) to externally
+ * assert the warm reset pin (nRST). 0 <= \e nRST_pin_clk_assertion <=
+ * (2**20 - 1). A value of 0 prevents any assertion of nRST.
+ *
+ * \param sdram_refresh
+ * Controls whether the contents of SDRAM survive a hardware
+ * sequenced warm reset. The reset manager requests the SDRAM
+ * controller to put SDRAM devices into self-refresh mode before
+ * asserting warm reset signals. An argument value of \b true
+ * enables the option, \b false disables the option.
+ *
+ * \param fpga_mgr_handshake
+ * Controls whether a handshake between the reset manager and FPGA
+ * manager occurs before a warm reset. The handshake is used to
+ * warn the FPGA manager that a warm reset is imminent so it can
+ * prepare for it by driving its output clock to a quiescent state
+ * to avoid glitches. An argument value of \b true enables the
+ * option, \b false disables the option.
+ *
+ * \param scan_mgr_handshake
+ * Controls whether a handshake between the reset manager and scan
+ * manager occurs before a warm reset. The handshake is used to
+ * warn the scan manager that a warm reset is imminent so it can
+ * prepare for it by driving its output clock to a quiescent state
+ * to avoid glitches. An argument value of \b true enables the
+ * option, \b false disables the option.
+ *
+ * \param fpga_handshake
+ * Controls whether a handshake between the reset manager and the
+ * FPGA occurs before a warm reset. The handshake is used to warn
+ * the FPGA that a warm reset is imminent so that the FPGA prepare
+ * for the reset event in soft IP. An argument value of \b true
+ * enables the option, \b false disables the option.
+ *
+ * \param etr_stall
+ * Controls whether the ETR is requested to idle its AXI master
+ * interface (i.e. finish outstanding transactions and not initiate
+ * any more) to the L3 Interconnect before a warm reset. An
+ * argument value of \b true enables the option, \b false disables
+ * the option.
+ *
+ * \retval ALT_E_SUCCESS The operation was succesful.
+ * \retval ALT_E_ERROR The operation failed.
+ */
+ALT_STATUS_CODE alt_reset_warm_reset(uint32_t warm_reset_delay,
+ uint32_t nRST_pin_clk_assertion,
+ bool sdram_refresh,
+ bool fpga_mgr_handshake,
+ bool scan_mgr_handshake,
+ bool fpga_handshake,
+ bool etr_stall);
+
+#if 0
+/*! \addtogroup RST_MGR_MPU
+ *
+ * This functional group provides reset control for the Cortex-A9 MPU module.
+ *
+ * @{
+ */
+
+/*! @} */
+
+/*! \addtogroup RST_MGR_PERIPH
+ *
+ * This functional group provides inidividual reset control for the HPS
+ * peripheral modules.
+ *
+ * @{
+ */
+
+/*! @} */
+
+/*! \addtogroup RST_MGR_BRG
+ *
+ * This functional group provides inidividual reset control for the bridge
+ * interfaces between the HPS and FPGA.
+ *
+ * @{
+ */
+
+/*! @} */
+
+/*! \addtogroup RST_MGR_MISC
+ *
+ * This functional group provides inidividual reset control for miscellaneous
+ * HPS modules.
+ *
+ * @{
+ */
+
+/*! @} */
+
+#endif
+
+/*! @} */
+
+/*! @} */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __ALT_RESET_MGR_H__ */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/hwlib.h b/bsps/arm/altera-cyclone-v/include/bsp/hwlib.h
new file mode 100644
index 0000000000..aba7e877c4
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/hwlib.h
@@ -0,0 +1,189 @@
+/******************************************************************************
+*
+* Copyright 2013 Altera Corporation. All Rights Reserved.
+*
+* Redistribution and use in source and binary forms, with or without
+* modification, are permitted provided that the following conditions are met:
+*
+* 1. Redistributions of source code must retain the above copyright notice,
+* this list of conditions and the following disclaimer.
+*
+* 2. Redistributions in binary form must reproduce the above copyright notice,
+* this list of conditions and the following disclaimer in the documentation
+* and/or other materials provided with the distribution.
+*
+* 3. The name of the author may not be used to endorse or promote products
+* derived from this software without specific prior written permission.
+*
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+* OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+* IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+* OF SUCH DAMAGE.
+*
+******************************************************************************/
+
+#ifndef __HWLIB_H__
+#define __HWLIB_H__
+
+#ifdef __cplusplus
+#include <cstddef>
+#include <cstdbool>
+#include <cstdint>
+#else /* __cplusplus */
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+#endif /* __cplusplus */
+
+#include "alt_hwlibs_ver.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*!
+ * The type definition for status codes returned by the HWLIB.
+ */
+typedef int32_t ALT_STATUS_CODE;
+
+/*! Definitions of status codes returned by the HWLIB. */
+
+/*! The operation was successful. */
+#define ALT_E_SUCCESS 0
+
+/*! The operation failed. */
+#define ALT_E_ERROR (-1)
+/*! FPGA configuration error detected.*/
+#define ALT_E_FPGA_CFG (-2)
+/*! FPGA CRC error detected. */
+#define ALT_E_FPGA_CRC (-3)
+/*! An error occurred on the FPGA configuration bitstream input source. */
+#define ALT_E_FPGA_CFG_STM (-4)
+/*! The FPGA is powered off. */
+#define ALT_E_FPGA_PWR_OFF (-5)
+/*! The SoC does not currently control the FPGA. */
+#define ALT_E_FPGA_NO_SOC_CTRL (-6)
+/*! The FPGA is not in USER mode. */
+#define ALT_E_FPGA_NOT_USER_MODE (-7)
+/*! An argument violates a range constraint. */
+#define ALT_E_ARG_RANGE (-8)
+/*! A bad argument value was passed. */
+#define ALT_E_BAD_ARG (-9)
+/*! The operation is invalid or illegal. */
+#define ALT_E_BAD_OPERATION (-10)
+/*! An invalid option was selected. */
+#define ALT_E_INV_OPTION (-11)
+/*! An operation or response timeout period expired. */
+#define ALT_E_TMO (-12)
+/*! The argument value is reserved or unavailable. */
+#define ALT_E_RESERVED (-13)
+/*! A clock is not enabled or violates an operational constraint. */
+#define ALT_E_BAD_CLK (-14)
+/*! The version ID is invalid. */
+#define ALT_E_BAD_VERSION (-15)
+/*! The buffer does not contain enough free space for the operation. */
+#define ALT_E_BUF_OVF (-20)
+
+/*!
+ * Indicates a FALSE condition.
+ */
+#define ALT_E_FALSE (0)
+/*!
+ * Indicates a TRUE condition.
+ */
+#define ALT_E_TRUE (1)
+
+/* Note, additional positive status codes may be defined to return
+ * a TRUE condition with additional information */
+
+
+/* Some other useful definitions */
+
+/*!
+ * Specifies the current major and minor revision of the HWLibs. The
+ * MS four decimal digits specify the Altera ACDS release number, the
+ * LS two decimal digits specify minor revisions of the HWLibs, if any.
+ *
+ * A typical use is:
+ * \code
+ * #if ALTERA_HWLIBS_VERSION_CODE >= ALT_HWLIBS_VERSION(13, 1, 0)
+ * \endcode
+ * for a dependency on the major or minor ACDS revision
+ * or
+ * \code
+ * #if ALTERA_HWLIBS_VERSION_CODE == ALT_HWLIBS_VERSION(13, 0, 12)
+ * \endcode
+ * for a dependency on the hwlibs revision
+ *
+ */
+#define ALT_HWLIBS_VERSION(a,b,c) (((a)*10000)+((b)*100)+(c))
+
+#define ALTERA_HWLIBS_VERSION_CODE ALT_HWLIBS_VERSION(ALTERA_ACDS_MAJOR_REV, \
+ ALTERA_ACDS_MINOR_REV, ALTERA_HWLIBS_REV)
+
+/*!
+ * Allow some parts of the documentation to be hidden by setting to zero
+ */
+#define ALTERA_INTERNAL_ONLY_DOCS 1
+
+
+/*!
+ * Provide base address of MPU address space
+ */
+
+#ifndef ALT_HPS_ADDR
+#define ALT_HPS_ADDR 0
+#endif
+
+/*!
+ * These constants are sometimes useful:
+ */
+#define ALT_MILLISECS_IN_A_SEC 1000
+#define ALT_MICROSECS_IN_A_SEC 1000000
+#define ALT_NANOSECS_IN_A_SEC 1000000000
+
+#define ALT_TWO_TO_POW0 (1)
+#define ALT_TWO_TO_POW1 (1<<1)
+#define ALT_TWO_TO_POW2 (1<<2)
+#define ALT_TWO_TO_POW3 (1<<3)
+#define ALT_TWO_TO_POW4 (1<<4)
+#define ALT_TWO_TO_POW5 (1<<5)
+#define ALT_TWO_TO_POW6 (1<<6)
+#define ALT_TWO_TO_POW7 (1<<7)
+#define ALT_TWO_TO_POW8 (1<<8)
+#define ALT_TWO_TO_POW9 (1<<9)
+#define ALT_TWO_TO_POW10 (1<<10)
+#define ALT_TWO_TO_POW11 (1<<11)
+#define ALT_TWO_TO_POW12 (1<<12)
+#define ALT_TWO_TO_POW13 (1<<13)
+#define ALT_TWO_TO_POW14 (1<<14)
+#define ALT_TWO_TO_POW15 (1<<15)
+#define ALT_TWO_TO_POW16 (1<<16)
+#define ALT_TWO_TO_POW17 (1<<17)
+#define ALT_TWO_TO_POW18 (1<<18)
+#define ALT_TWO_TO_POW19 (1<<19)
+#define ALT_TWO_TO_POW20 (1<<20)
+#define ALT_TWO_TO_POW21 (1<<21)
+#define ALT_TWO_TO_POW22 (1<<22)
+#define ALT_TWO_TO_POW23 (1<<23)
+#define ALT_TWO_TO_POW24 (1<<24)
+#define ALT_TWO_TO_POW25 (1<<25)
+#define ALT_TWO_TO_POW26 (1<<26)
+#define ALT_TWO_TO_POW27 (1<<27)
+#define ALT_TWO_TO_POW28 (1<<28)
+#define ALT_TWO_TO_POW29 (1<<29)
+#define ALT_TWO_TO_POW30 (1<<30)
+#define ALT_TWO_TO_POW31 (1<<31)
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+#endif /* __HWLIB_H__ */
+
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h b/bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h
new file mode 100644
index 0000000000..9a4411d637
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/i2cdrv.h
@@ -0,0 +1,76 @@
+/*
+ * Copyright (c) 2014 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ * <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef I2CDRV_H
+#define I2CDRV_H
+
+#include <rtems.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+rtems_device_driver i2cdrv_initialize(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+);
+
+rtems_device_driver i2cdrv_open(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+);
+
+rtems_device_driver i2cdrv_close(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+);
+
+rtems_device_driver i2cdrv_read(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+);
+
+rtems_device_driver i2cdrv_write(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+);
+
+rtems_device_driver i2cdrv_ioctl(
+ rtems_device_major_number major,
+ rtems_device_minor_number minor,
+ void *arg
+);
+
+#define I2C_DRIVER_TABLE_ENTRY \
+ { \
+ i2cdrv_initialize, \
+ i2cdrv_open, \
+ i2cdrv_close, \
+ i2cdrv_read, \
+ i2cdrv_write, \
+ i2cdrv_ioctl \
+ }
+
+#define I2C_IOC_SET_SLAVE_ADDRESS 1
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* I2CDRV_H */
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/irq.h b/bsps/arm/altera-cyclone-v/include/bsp/irq.h
new file mode 100644
index 0000000000..c136500415
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/irq.h
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH. All rights reserved.
+ *
+ * embedded brains GmbH
+ * Dornierstr. 4
+ * 82178 Puchheim
+ * Germany
+ * <info@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H
+#define LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H
+
+#ifndef ASM
+
+#include <rtems/irq.h>
+#include <rtems/irq-extension.h>
+
+#include <bsp/arm-a9mpcore-irq.h>
+#include <bsp/arm-gic-irq.h>
+#include <bsp/alt_interrupt_common.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+/* Use interrupt IDs as defined in alt_interrupt_common.h */
+#define BSP_INTERRUPT_VECTOR_MIN ALT_INT_INTERRUPT_SGI0
+#define BSP_INTERRUPT_VECTOR_MAX ALT_INT_INTERRUPT_RAM_ECC_UNCORRECTED_IRQ
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ASM */
+
+#endif /* LIBBSP_ARM_ALTERA_CYCLONE_V_IRQ_H */ \ No newline at end of file
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h
new file mode 100644
index 0000000000..3a6bf0fffa
--- /dev/null
+++ b/bsps/arm/altera-cyclone-v/include/bsp/socal/alt_acpidmap.h
@@ -0,0 +1,3569 @@
+/*******************************************************************************
+* *
+* Copyright 2013 Altera Corporation. All Rights Reserved. *
+* *
+* Redistribution and use in source and binary forms, with or without *
+* modification, are permitted provided that the following conditions are met: *
+* *
+* 1. Redistributions of source code must retain the above copyright notice, *
+* this list of conditions and the following disclaimer. *
+* *
+* 2. Redistributions in binary form must reproduce the above copyright notice, *
+* this list of conditions and the following disclaimer in the documentation *
+* and/or other materials provided with the distribution. *
+* *
+* 3. The name of the author may not be used to endorse or promote products *
+* derived from this software without specific prior written permission. *
+* *
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR *
+* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF *
+* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO *
+* EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, *
+* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, *
+* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; *
+* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, *
+* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR *
+* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF *
+* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *
+* *
+*******************************************************************************/
+
+/* Altera - ALT_ACPIDMAP */
+
+#ifndef __ALTERA_ALT_ACPIDMAP_H__
+#define __ALTERA_ALT_ACPIDMAP_H__
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif /* __cplusplus */
+
+/*
+ * Component : ACP ID Mapper Registers - ALT_ACPIDMAP
+ * ACP ID Mapper Registers
+ *
+ * Registers in the ACP ID Mapper module
+ *
+ */
+/*
+ * Register : Read AXI Master Mapping Register for Fixed Virtual ID 2 - vid2rd
+ *
+ * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ *
+ * Register Layout
+ *
+ * Bits | Access | Reset | Description
+ * :--------|:-------|:------|:-----------------------------
+ * [3:0] | ??? | 0x0 | *UNDEFINED*
+ * [8:4] | RW | 0x1 | ARUSER value to SCU for ID=2
+ * [11:9] | ??? | 0x0 | *UNDEFINED*
+ * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder
+ * [15:14] | ??? | 0x0 | *UNDEFINED*
+ * [27:16] | RW | 0x4 | Remap Master ID = DAP ID
+ * [30:28] | ??? | 0x0 | *UNDEFINED*
+ * [31] | RW | 0x1 | Force Mapping for ID=2
+ *
+ */
+/*
+ * Field : ARUSER value to SCU for ID=2 - user
+ *
+ * This value is propagated to SCU as ARUSERS.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_USER_LSB 4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_USER_MSB 8
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_USER_WIDTH 5
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_USER register field value. */
+#define ALT_ACPIDMAP_VID2RD_USER_SET_MSK 0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_USER register field value. */
+#define ALT_ACPIDMAP_VID2RD_USER_CLR_MSK 0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID2RD_USER register field. */
+#define ALT_ACPIDMAP_VID2RD_USER_RESET 0x1
+/* Extracts the ALT_ACPIDMAP_VID2RD_USER field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID2RD_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder - page
+ *
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_LSB 12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_MSB 13
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_WIDTH 2
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_SET_MSK 0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_CLR_MSK 0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID2RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_RESET 0x0
+/* Extracts the ALT_ACPIDMAP_VID2RD_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID2RD_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID = DAP ID - mid
+ *
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_MID_LSB 16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_MID_MSB 27
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_MID_WIDTH 12
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_MID register field value. */
+#define ALT_ACPIDMAP_VID2RD_MID_SET_MSK 0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_MID register field value. */
+#define ALT_ACPIDMAP_VID2RD_MID_CLR_MSK 0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID2RD_MID register field. */
+#define ALT_ACPIDMAP_VID2RD_MID_RESET 0x4
+/* Extracts the ALT_ACPIDMAP_VID2RD_MID field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID2RD_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping for ID=2 - force
+ *
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_LSB 31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_MSB 31
+/* The width in bits of the ALT_ACPIDMAP_VID2RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_WIDTH 1
+/* The mask used to set the ALT_ACPIDMAP_VID2RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_SET_MSK 0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID2RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_CLR_MSK 0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID2RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_RESET 0x1
+/* Extracts the ALT_ACPIDMAP_VID2RD_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID2RD_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2RD_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ *
+ * The struct declaration for register ALT_ACPIDMAP_VID2RD.
+ */
+struct ALT_ACPIDMAP_VID2RD_s
+{
+ uint32_t : 4; /* *UNDEFINED* */
+ uint32_t user : 5; /* ARUSER value to SCU for ID=2 */
+ uint32_t : 3; /* *UNDEFINED* */
+ uint32_t page : 2; /* ARADDR 1GB Page Decoder */
+ uint32_t : 2; /* *UNDEFINED* */
+ uint32_t mid : 12; /* Remap Master ID = DAP ID */
+ uint32_t : 3; /* *UNDEFINED* */
+ uint32_t force : 1; /* Force Mapping for ID=2 */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID2RD. */
+typedef volatile struct ALT_ACPIDMAP_VID2RD_s ALT_ACPIDMAP_VID2RD_t;
+#endif /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID2RD register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID2RD_OFST 0x0
+
+/*
+ * Register : Write AXI Master Mapping Register for Fixed Virtual ID 2 - vid2wr
+ *
+ * The Write AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ *
+ * Register Layout
+ *
+ * Bits | Access | Reset | Description
+ * :--------|:-------|:------|:-----------------------------
+ * [3:0] | ??? | 0x0 | *UNDEFINED*
+ * [8:4] | RW | 0x1 | AWUSER value to SCU for ID=2
+ * [11:9] | ??? | 0x0 | *UNDEFINED*
+ * [13:12] | RW | 0x0 | AWADDR 1GB Page Decoder
+ * [15:14] | ??? | 0x0 | *UNDEFINED*
+ * [27:16] | RW | 0x4 | Remap Master ID = DAP ID
+ * [30:28] | ??? | 0x0 | *UNDEFINED*
+ * [31] | RW | 0x1 | Force Mapping for ID=2
+ *
+ */
+/*
+ * Field : AWUSER value to SCU for ID=2 - user
+ *
+ * This value is propagated to SCU as AWUSERS.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_USER_LSB 4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_USER_MSB 8
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_USER_WIDTH 5
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_USER register field value. */
+#define ALT_ACPIDMAP_VID2WR_USER_SET_MSK 0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_USER register field value. */
+#define ALT_ACPIDMAP_VID2WR_USER_CLR_MSK 0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID2WR_USER register field. */
+#define ALT_ACPIDMAP_VID2WR_USER_RESET 0x1
+/* Extracts the ALT_ACPIDMAP_VID2WR_USER field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID2WR_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : AWADDR 1GB Page Decoder - page
+ *
+ * AWADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_LSB 12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_MSB 13
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_WIDTH 2
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_SET_MSK 0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_PAGE register field value. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_CLR_MSK 0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID2WR_PAGE register field. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_RESET 0x0
+/* Extracts the ALT_ACPIDMAP_VID2WR_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID2WR_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID = DAP ID - mid
+ *
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_MID_LSB 16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_MID_MSB 27
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_MID_WIDTH 12
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_MID register field value. */
+#define ALT_ACPIDMAP_VID2WR_MID_SET_MSK 0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_MID register field value. */
+#define ALT_ACPIDMAP_VID2WR_MID_CLR_MSK 0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID2WR_MID register field. */
+#define ALT_ACPIDMAP_VID2WR_MID_RESET 0x4
+/* Extracts the ALT_ACPIDMAP_VID2WR_MID field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID2WR_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping for ID=2 - force
+ *
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_LSB 31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID2WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_MSB 31
+/* The width in bits of the ALT_ACPIDMAP_VID2WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_WIDTH 1
+/* The mask used to set the ALT_ACPIDMAP_VID2WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_SET_MSK 0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID2WR_FORCE register field value. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_CLR_MSK 0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID2WR_FORCE register field. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_RESET 0x1
+/* Extracts the ALT_ACPIDMAP_VID2WR_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID2WR_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID2WR_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ *
+ * The struct declaration for register ALT_ACPIDMAP_VID2WR.
+ */
+struct ALT_ACPIDMAP_VID2WR_s
+{
+ uint32_t : 4; /* *UNDEFINED* */
+ uint32_t user : 5; /* AWUSER value to SCU for ID=2 */
+ uint32_t : 3; /* *UNDEFINED* */
+ uint32_t page : 2; /* AWADDR 1GB Page Decoder */
+ uint32_t : 2; /* *UNDEFINED* */
+ uint32_t mid : 12; /* Remap Master ID = DAP ID */
+ uint32_t : 3; /* *UNDEFINED* */
+ uint32_t force : 1; /* Force Mapping for ID=2 */
+};
+
+/* The typedef declaration for register ALT_ACPIDMAP_VID2WR. */
+typedef volatile struct ALT_ACPIDMAP_VID2WR_s ALT_ACPIDMAP_VID2WR_t;
+#endif /* __ASSEMBLY__ */
+
+/* The byte offset of the ALT_ACPIDMAP_VID2WR register from the beginning of the component. */
+#define ALT_ACPIDMAP_VID2WR_OFST 0x4
+
+/*
+ * Register : Read AXI Master Mapping Register for Fixed Virtual ID 3 - vid3rd
+ *
+ * The Read AXI Master Mapping Register contains the USER, ADDR page, and ID
+ * signals mapping values for particular transaction with 12-bit ID which locks the
+ * fixed 3-bit virtual ID.
+ *
+ * Register Layout
+ *
+ * Bits | Access | Reset | Description
+ * :--------|:-------|:------|:------------------------
+ * [3:0] | ??? | 0x0 | *UNDEFINED*
+ * [8:4] | RW | 0x0 | ARUSER value to SCU
+ * [11:9] | ??? | 0x0 | *UNDEFINED*
+ * [13:12] | RW | 0x0 | ARADDR 1GB Page Decoder
+ * [15:14] | ??? | 0x0 | *UNDEFINED*
+ * [27:16] | RW | 0x0 | Remap Master ID
+ * [30:28] | ??? | 0x0 | *UNDEFINED*
+ * [31] | RW | 0x0 | Force Mapping
+ *
+ */
+/*
+ * Field : ARUSER value to SCU - user
+ *
+ * This value is propagated to SCU as ARUSERS.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_USER_LSB 4
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_USER_MSB 8
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_USER_WIDTH 5
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_USER register field value. */
+#define ALT_ACPIDMAP_VID3RD_USER_SET_MSK 0x000001f0
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_USER register field value. */
+#define ALT_ACPIDMAP_VID3RD_USER_CLR_MSK 0xfffffe0f
+/* The reset value of the ALT_ACPIDMAP_VID3RD_USER register field. */
+#define ALT_ACPIDMAP_VID3RD_USER_RESET 0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_USER field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_USER_GET(value) (((value) & 0x000001f0) >> 4)
+/* Produces a ALT_ACPIDMAP_VID3RD_USER register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_USER_SET(value) (((value) << 4) & 0x000001f0)
+
+/*
+ * Field : ARADDR 1GB Page Decoder - page
+ *
+ * ARADDR remap to 1st, 2nd, 3rd, or 4th 1GB memory region.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_LSB 12
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_MSB 13
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_WIDTH 2
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_SET_MSK 0x00003000
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_PAGE register field value. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_CLR_MSK 0xffffcfff
+/* The reset value of the ALT_ACPIDMAP_VID3RD_PAGE register field. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_RESET 0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_PAGE field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_GET(value) (((value) & 0x00003000) >> 12)
+/* Produces a ALT_ACPIDMAP_VID3RD_PAGE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_PAGE_SET(value) (((value) << 12) & 0x00003000)
+
+/*
+ * Field : Remap Master ID - mid
+ *
+ * The 12-bit ID of the master to remap to 3-bit virtual ID N, where N is the 3-bit
+ * ID to use.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_MID_LSB 16
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_MID_MSB 27
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_MID_WIDTH 12
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_MID register field value. */
+#define ALT_ACPIDMAP_VID3RD_MID_SET_MSK 0x0fff0000
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_MID register field value. */
+#define ALT_ACPIDMAP_VID3RD_MID_CLR_MSK 0xf000ffff
+/* The reset value of the ALT_ACPIDMAP_VID3RD_MID register field. */
+#define ALT_ACPIDMAP_VID3RD_MID_RESET 0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_MID field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_MID_GET(value) (((value) & 0x0fff0000) >> 16)
+/* Produces a ALT_ACPIDMAP_VID3RD_MID register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_MID_SET(value) (((value) << 16) & 0x0fff0000)
+
+/*
+ * Field : Force Mapping - force
+ *
+ * Set to 1 to force the mapping between the 12-bit ID and 3-bit virtual ID N. Set
+ * to 0 to allow the 3-bit ID N to be dynamically allocated.
+ *
+ * Field Access Macros:
+ *
+ */
+/* The Least Significant Bit (LSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_LSB 31
+/* The Most Significant Bit (MSB) position of the ALT_ACPIDMAP_VID3RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_MSB 31
+/* The width in bits of the ALT_ACPIDMAP_VID3RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_WIDTH 1
+/* The mask used to set the ALT_ACPIDMAP_VID3RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_SET_MSK 0x80000000
+/* The mask used to clear the ALT_ACPIDMAP_VID3RD_FORCE register field value. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_CLR_MSK 0x7fffffff
+/* The reset value of the ALT_ACPIDMAP_VID3RD_FORCE register field. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_RESET 0x0
+/* Extracts the ALT_ACPIDMAP_VID3RD_FORCE field value from a register. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_GET(value) (((value) & 0x80000000) >> 31)
+/* Produces a ALT_ACPIDMAP_VID3RD_FORCE register field value suitable for setting the register. */
+#define ALT_ACPIDMAP_VID3RD_FORCE_SET(value) (((value) << 31) & 0x80000000)
+
+#ifndef __ASSEMBLY__
+/*
+ * WARNING: The C register and register group struct declarations are provided for
+ * convenience and illustrative purposes. They should, however, be used with
+ * caution as the C language standard provides no guarantees about the alignment or
+ * atomicity of device memory accesses. The recommended practice for writing
+ * hardware drivers is to use the SoCAL access macros and alt_read_word() and
+ * alt_write_word() functions.
+ *
+ * The struct declaration for register ALT_ACPIDMAP_VID3RD.
+ */
+struct ALT_ACPIDMAP_VID3RD_s
+{
+ uint32_t : 4; /* *UNDEFINED* */
+ uint32_t user : 5; /* ARUSER value to SCU */
+ uint32_t : 3; /* *UNDEFINED* */
+ uint32_t page : 2; /* ARADDR 1GB Page Decoder */
+ uint32_t : 2; /* *UNDEF