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authorChris Johns <chrisj@rtems.org>2017-12-23 18:18:56 +1100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-01-25 08:45:26 +0100
commit2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 (patch)
tree44759efe9374f13200a97e96d91bd9a2b7e5ce2a /bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h
parentMAINTAINERS: Add myself to Write After Approval. (diff)
downloadrtems-2afb22b7e1ebcbe40373ff7e0efae7d207c655a9.tar.bz2
Remove make preinstall
A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
Diffstat (limited to 'bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h')
-rwxr-xr-xbsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h47
1 files changed, 47 insertions, 0 deletions
diff --git a/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h
new file mode 100755
index 0000000000..85af10738f
--- /dev/null
+++ b/bsps/arm/stm32f4/include/bsp/stm32f4xxxx_pwr.h
@@ -0,0 +1,47 @@
+/*
+ * Copyright (c) 2013 Chris Nott. All rights reserved.
+ *
+ * Virtual Logic
+ * 21-25 King St.
+ * Rockdale NSW 2216
+ * Australia
+ * <rtems@vl.com.au>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H
+#define LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H
+
+#include <bsp/utility.h>
+
+struct stm32f4_pwr_s {
+
+ uint32_t cr; // Control register
+#define STM32F4_PWR_CR_VOS BSP_BIT32(14) // Regulator scaling output selection
+#define STM32F4_PWR_CR_FPDS BSP_BIT32(9) // Flash power-down in stop mode
+#define STM32F4_PWR_CR_DBP BSP_BIT32(8) // Disable backup domain write protection
+#define STM32F4_PWR_CR_PLS BSP_FLD32(val, 5, 7) // PVD level selection
+#define STM32F4_PWR_CR_PLS_GET(reg) BSP_FLD32GET(reg, 5, 7)
+#define STM32F4_PWR_CR_PLS_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7)
+#define STM32F4_PWR_CR_PVDE BSP_BIT32(4) // Power voltage detector enable
+#define STM32F4_PWR_CR_CSBF BSP_BIT32(3) // Clear standby flag
+#define STM32F4_PWR_CR_CWUF BSP_BIT32(2) // Clear wakeup flag
+#define STM32F4_PWR_CR_PDDS BSP_BIT32(1) // Power-down deepsleep
+#define STM32F4_PWR_CR_LPDS BSP_BIT32(0) // Low-power deepsleep
+
+ uint32_t csr; // Control / status register
+#define STM32F4_PWR_CSR_VOSRDY BSP_BIT32(14) // Regulator voltage scaling output selection ready bit
+#define STM32F4_PWR_CSR_BRE BSP_BIT32(9) // Backup domain regulator enable
+#define STM32F4_PWR_CSR_EWUP BSP_BIT32(8) // Enable WKUP pin
+#define STM32F4_PWR_CSR_BRR BSP_BIT32(3) // Backup regulator ready
+#define STM32F4_PWR_CSR_PVDO BSP_BIT32(2) // PVD output
+#define STM32F4_PWR_CSR_SBF BSP_BIT32(1) // Standby flag
+#define STM32F4_PWR_CSR_WUF BSP_BIT32(0) // Wakeup flag
+
+} __attribute__ ((packed));
+typedef struct stm32f4_pwr_s stm32f4_pwr;
+
+#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_PWR_H */