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authorSebastian Huber <sebastian.huber@embedded-brains.de>2021-07-09 10:40:35 +0200
committerSebastian Huber <sebastian.huber@embedded-brains.de>2021-07-09 10:43:10 +0200
commita398909dc2312d11bfcd20643de1b2aa162b5abf (patch)
treea903040c293c43e097066b956f02d4cae53554ae /bsps/arm/shared/start/start.S
parent89b652a54dd3ff1ff6fa0639d55b0aa2ec92d7b1 (diff)
downloadrtems-a398909dc2312d11bfcd20643de1b2aa162b5abf.tar.bz2
bsps/arm: Fix SMP start
Skip the data cache initialization if we are a secondary processor. The bug was introduced by e164df5e33608576443b4cd5923a9046358ee773 and did not show up in tests using Qemu since the data cache behaviour is not emulated.
Diffstat (limited to 'bsps/arm/shared/start/start.S')
-rw-r--r--bsps/arm/shared/start/start.S6
1 files changed, 6 insertions, 0 deletions
diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S
index be87a16f7a..bc87e7b36d 100644
--- a/bsps/arm/shared/start/start.S
+++ b/bsps/arm/shared/start/start.S
@@ -404,6 +404,12 @@ _start:
mcr p15, 0, r1, c1, c0, 0
isb
+#ifdef RTEMS_SMP
+ /* Skip the data cache initialization if we are a secondary processor */
+ cmp r7, #0
+ bne .Ldata_caches_initialized
+#endif
+
/* Check previous SCTLR[C] and initialize data caches */
tst r0, #0x4
bne .Lclean_invalidate_data_caches