From a398909dc2312d11bfcd20643de1b2aa162b5abf Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Fri, 9 Jul 2021 10:40:35 +0200 Subject: bsps/arm: Fix SMP start Skip the data cache initialization if we are a secondary processor. The bug was introduced by e164df5e33608576443b4cd5923a9046358ee773 and did not show up in tests using Qemu since the data cache behaviour is not emulated. --- bsps/arm/shared/start/start.S | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'bsps/arm/shared/start/start.S') diff --git a/bsps/arm/shared/start/start.S b/bsps/arm/shared/start/start.S index be87a16f7a..bc87e7b36d 100644 --- a/bsps/arm/shared/start/start.S +++ b/bsps/arm/shared/start/start.S @@ -404,6 +404,12 @@ _start: mcr p15, 0, r1, c1, c0, 0 isb +#ifdef RTEMS_SMP + /* Skip the data cache initialization if we are a secondary processor */ + cmp r7, #0 + bne .Ldata_caches_initialized +#endif + /* Check previous SCTLR[C] and initialize data caches */ tst r0, #0x4 bne .Lclean_invalidate_data_caches -- cgit v1.2.3