Remove make preinstall

A speciality of the RTEMS build system was the make preinstall step.  It
copied header files from arbitrary locations into the build tree.  The
header files were included via the -Bsome/build/tree/path GCC command
line option.

This has at least seven problems:

* The make preinstall step itself needs time and disk space.

* Errors in header files show up in the build tree copy.  This makes it
  hard for editors to open the right file to fix the error.

* There is no clear relationship between source and build tree header
  files.  This makes an audit of the build process difficult.

* The visibility of all header files in the build tree makes it
  difficult to enforce API barriers.  For example it is discouraged to
  use BSP-specifics in the cpukit.

* An introduction of a new build system is difficult.

* Include paths specified by the -B option are system headers.  This
  may suppress warnings.

* The parallel build had sporadic failures on some hosts.

This patch removes the make preinstall step.   All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc.  Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.

The new cpukit include directories are:

* cpukit/include

* cpukit/score/cpu/@RTEMS_CPU@/include

* cpukit/libnetworking

The new BSP include directories are:

* bsps/include

* bsps/@RTEMS_CPU@/include

* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include

There are build tree include directories for generated files.

The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.

The "bootstrap -p" option was removed.  The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.

Update #3254.

1 files changed, 121 insertions, 0 deletions

diff --git a/bsps/arm/include/bsp/arm-errata.h b/bsps/arm/include/bsp/arm-errata.h
new file mode 100644
index 0000000000..5108c98f15
--- /dev/null
+++ b/bsps/arm/include/bsp/arm-errata.h
@@ -0,0 +1,121 @@
+/**
+ * @file arm-errata.h
+ *
+ * @ingroup arm_shared
+ *
+ * @brief Create #defines which state which erratas shall get applied
+ */
+
+/*
+ * Copyright (c) 2014 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.org/license/LICENSE.
+ */
+
+#ifndef ARM_ERRATA_H_
+#define ARM_ERRATA_H_
+
+#include <bsp/arm-release-id.h>
+#include <libcpu/arm-cp15.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+static inline arm_release_id arm_errata_get_processor_release(void)
+{
+  const uint32_t MIDR          = arm_cp15_get_id_code();
+  const uint8_t  REVISION      = (MIDR & 0xF00000U) >> 20;
+  const uint8_t  PATCH_LEVEL   = (MIDR & 0xFU);
+
+  return ARM_RELEASE_ID_FROM_NUMBER_AND_PATCH_LEVEL(
+    REVISION,
+    PATCH_LEVEL
+  );
+}
+
+static inline bool arm_errata_is_applicable_processor_errata_764369(void)
+{
+#if defined(RTEMS_SMP)
+  const arm_release_id RELEASE       = arm_errata_get_processor_release();
+  bool                 is_applicable = false;
+
+  /* Errata information for Cortex-A9 processors.
+   * Information taken from ARMs
+   * "Cortex-A series processors
+   * - Cortex-A9
+   * - Software Developers Errata Notice
+   * - Revision r4 revisions
+   * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice"
+   * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html
+   * Please see this document for more information on these erratas */
+
+  switch( RELEASE ) {
+    case ARM_RELEASE_ID_R4_P1:
+    case ARM_RELEASE_ID_R4_P4:
+    case ARM_RELEASE_ID_R3_P0:
+    case ARM_RELEASE_ID_R2_P10:
+    case ARM_RELEASE_ID_R2_P8:
+    case ARM_RELEASE_ID_R2_P6:
+    case ARM_RELEASE_ID_R2_P4:
+    case ARM_RELEASE_ID_R2_P3:
+    case ARM_RELEASE_ID_R2_P2:
+    case ARM_RELEASE_ID_R2_P0:
+      is_applicable = true;
+      break;
+    default:
+      is_applicable = false;
+      break;
+  }
+
+  return is_applicable;
+#else
+  return false;
+#endif
+}
+
+static inline bool arm_errata_is_applicable_processor_errata_775420(void)
+{
+  const arm_release_id RELEASE       = arm_errata_get_processor_release();
+  bool                 is_applicable = false;
+
+  /* Errata information for Cortex-A9 processors.
+  * Information taken from ARMs
+  * "Cortex-A series processors
+  * - Cortex-A9
+  * - Software Developers Errata Notice
+  * - Revision r4 revisions
+  * - ARM Cortex-A9 processors r4 release Software Developers Errata Notice"
+  * The corresponding link is: http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html
+  * Please see this document for more information on these erratas */
+
+  switch( RELEASE ) {
+    case ARM_RELEASE_ID_R2_P10:
+    case ARM_RELEASE_ID_R2_P8:
+    case ARM_RELEASE_ID_R2_P6:
+    case ARM_RELEASE_ID_R2_P4:
+    case ARM_RELEASE_ID_R2_P3:
+    case ARM_RELEASE_ID_R2_P2:
+      is_applicable = true;
+      break;
+    default:
+      is_applicable = false;
+      break;
+  }
+
+  return is_applicable;
+}
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* ARM_ERRATA_H_ */