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authorChristian Mauderer <christian.mauderer@embedded-brains.de>2020-10-12 13:40:30 +0200
committerChristian Mauderer <christian.mauderer@embedded-brains.de>2020-11-20 08:53:18 +0100
commit48f6a6c302a3e1a3f8915e2503d0fe618d1af285 (patch)
treeb5d570ddd5e432519c5a9d42b4cf6725d8161551 /bsps/arm/imxrt/include
parentcpu/armv7m: Add table based init for ARMV7M_MPU (diff)
downloadrtems-48f6a6c302a3e1a3f8915e2503d0fe618d1af285.tar.bz2
bsp/imxrt: Import files from MCUXpresso SDK V2.8.5
The following files have been imported: cp ${SDK}/boards/evkbimxrt1050/project_template/clock_config.c nxp/boards/evkbimxrt1050 cp ${SDK}/boards/evkbimxrt1050/project_template/clock_config.h include/fsl_clock_config.h cp ${SDK}/boards/evkbimxrt1050/project_template/dcd.c start/flash-dcd.c cp ${SDK}/boards/evkbimxrt1050/project_template/pin_mux.c nxp/boards/evkbimxrt1050 cp ${SDK}/boards/evkbimxrt1050/project_template/pin_mux.h include/fsl_pin_mux.h cp ${SDK}/boards/evkbimxrt1050/xip/evkbimxrt1050_flexspi_nor_config.h include/fsl_flexspi_nor_config.h cp ${SDK}/devices/MIMXRT1052/MIMXRT1052.h include cp ${SDK}/devices/MIMXRT1052/MIMXRT1052_features.h include cp ${SDK}/devices/MIMXRT1052/drivers/fsl_*.c nxp/devices/MIMXRT1052/drivers cp ${SDK}/devices/MIMXRT1052/drivers/fsl_*.h include cp ${SDK}/devices/MIMXRT1052/fsl_device_registers.h include cp ${SDK}/devices/MIMXRT1052/system_MIMXRT1052.h include/ cp ${SDK}/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c nxp/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.c cp ${SDK}/devices/MIMXRT1052/xip/fsl_flexspi_nor_boot.h include Update #4180
Diffstat (limited to 'bsps/arm/imxrt/include')
-rw-r--r--bsps/arm/imxrt/include/MIMXRT1052.h46183
-rw-r--r--bsps/arm/imxrt/include/MIMXRT1052_features.h688
-rw-r--r--bsps/arm/imxrt/include/evkbimxrt1050_flexspi_nor_config.h268
-rw-r--r--bsps/arm/imxrt/include/fsl_adc.h427
-rw-r--r--bsps/arm/imxrt/include/fsl_adc_etc.h336
-rw-r--r--bsps/arm/imxrt/include/fsl_aipstz.h134
-rw-r--r--bsps/arm/imxrt/include/fsl_aoi.h186
-rw-r--r--bsps/arm/imxrt/include/fsl_bee.h254
-rw-r--r--bsps/arm/imxrt/include/fsl_cache.h457
-rw-r--r--bsps/arm/imxrt/include/fsl_clock.h1550
-rw-r--r--bsps/arm/imxrt/include/fsl_clock_config.h119
-rw-r--r--bsps/arm/imxrt/include/fsl_cmp.h321
-rw-r--r--bsps/arm/imxrt/include/fsl_common.h672
-rw-r--r--bsps/arm/imxrt/include/fsl_csi.h724
-rw-r--r--bsps/arm/imxrt/include/fsl_dcdc.h496
-rw-r--r--bsps/arm/imxrt/include/fsl_dcp.h569
-rw-r--r--bsps/arm/imxrt/include/fsl_device_registers.h36
-rw-r--r--bsps/arm/imxrt/include/fsl_dmamux.h177
-rw-r--r--bsps/arm/imxrt/include/fsl_edma.h951
-rw-r--r--bsps/arm/imxrt/include/fsl_elcdif.h747
-rw-r--r--bsps/arm/imxrt/include/fsl_enc.h458
-rw-r--r--bsps/arm/imxrt/include/fsl_enet.h1855
-rw-r--r--bsps/arm/imxrt/include/fsl_ewm.h218
-rw-r--r--bsps/arm/imxrt/include/fsl_flexcan.h1422
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio.h700
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_camera.h230
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_camera_edma.h130
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_i2c_master.h486
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_i2s.h560
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_i2s_edma.h203
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_mculcd.h685
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_mculcd_edma.h153
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_spi.h702
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_spi_edma.h207
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_uart.h570
-rw-r--r--bsps/arm/imxrt/include/fsl_flexio_uart_edma.h178
-rw-r--r--bsps/arm/imxrt/include/fsl_flexram.h276
-rw-r--r--bsps/arm/imxrt/include/fsl_flexram_allocate.h99
-rw-r--r--bsps/arm/imxrt/include/fsl_flexspi.h837
-rw-r--r--bsps/arm/imxrt/include/fsl_flexspi_nor_boot.h122
-rw-r--r--bsps/arm/imxrt/include/fsl_gpc.h231
-rw-r--r--bsps/arm/imxrt/include/fsl_gpio.h342
-rw-r--r--bsps/arm/imxrt/include/fsl_gpt.h509
-rw-r--r--bsps/arm/imxrt/include/fsl_iomuxc.h1242
-rw-r--r--bsps/arm/imxrt/include/fsl_kpp.h180
-rw-r--r--bsps/arm/imxrt/include/fsl_lpi2c.h1266
-rw-r--r--bsps/arm/imxrt/include/fsl_lpi2c_edma.h157
-rw-r--r--bsps/arm/imxrt/include/fsl_lpspi.h1122
-rw-r--r--bsps/arm/imxrt/include/fsl_lpspi_edma.h301
-rw-r--r--bsps/arm/imxrt/include/fsl_lpuart.h862
-rw-r--r--bsps/arm/imxrt/include/fsl_lpuart_edma.h173
-rw-r--r--bsps/arm/imxrt/include/fsl_ocotp.h153
-rw-r--r--bsps/arm/imxrt/include/fsl_pin_mux.h938
-rw-r--r--bsps/arm/imxrt/include/fsl_pit.h332
-rw-r--r--bsps/arm/imxrt/include/fsl_pmu.h671
-rw-r--r--bsps/arm/imxrt/include/fsl_pwm.h987
-rw-r--r--bsps/arm/imxrt/include/fsl_pxp.h1438
-rw-r--r--bsps/arm/imxrt/include/fsl_qtmr.h439
-rw-r--r--bsps/arm/imxrt/include/fsl_rtwdog.h425
-rw-r--r--bsps/arm/imxrt/include/fsl_sai.h1572
-rw-r--r--bsps/arm/imxrt/include/fsl_sai_edma.h268
-rw-r--r--bsps/arm/imxrt/include/fsl_semc.h831
-rw-r--r--bsps/arm/imxrt/include/fsl_snvs_hp.h626
-rw-r--r--bsps/arm/imxrt/include/fsl_snvs_lp.h555
-rw-r--r--bsps/arm/imxrt/include/fsl_spdif.h746
-rw-r--r--bsps/arm/imxrt/include/fsl_spdif_edma.h192
-rw-r--r--bsps/arm/imxrt/include/fsl_src.h602
-rw-r--r--bsps/arm/imxrt/include/fsl_tempmon.h126
-rw-r--r--bsps/arm/imxrt/include/fsl_trng.h228
-rw-r--r--bsps/arm/imxrt/include/fsl_tsc.h524
-rw-r--r--bsps/arm/imxrt/include/fsl_usdhc.h1581
-rw-r--r--bsps/arm/imxrt/include/fsl_wdog.h305
-rw-r--r--bsps/arm/imxrt/include/fsl_xbara.h183
-rw-r--r--bsps/arm/imxrt/include/fsl_xbarb.h82
-rw-r--r--bsps/arm/imxrt/include/system_MIMXRT1052.h129
75 files changed, 85704 insertions, 0 deletions
diff --git a/bsps/arm/imxrt/include/MIMXRT1052.h b/bsps/arm/imxrt/include/MIMXRT1052.h
new file mode 100644
index 0000000000..7cd99eb8f2
--- /dev/null
+++ b/bsps/arm/imxrt/include/MIMXRT1052.h
@@ -0,0 +1,46183 @@
+/*
+** ###################################################################
+** Processors: MIMXRT1052CVJ5B
+** MIMXRT1052CVL5B
+** MIMXRT1052DVJ6B
+** MIMXRT1052DVL6B
+**
+** Compilers: Freescale C/C++ for Embedded ARM
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** Keil ARM C/C++ Compiler
+** MCUXpresso Compiler
+**
+** Reference manual: IMXRT1050RM Rev.2.1, 12/2018 | IMXRT1050SRM Rev.2
+** Version: rev. 1.3, 2019-04-29
+** Build: b191115
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for MIMXRT1052
+**
+** Copyright 1997-2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2019 NXP
+** All rights reserved.
+**
+** SPDX-License-Identifier: BSD-3-Clause
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 0.1 (2017-01-10)
+** Initial version.
+** - rev. 1.0 (2018-09-21)
+** Update interrupt vector table and dma request source.
+** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
+** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
+** - rev. 1.1 (2018-11-16)
+** Update header files to align with IMXRT1050RM Rev.1.
+** - rev. 1.2 (2018-11-27)
+** Update header files to align with IMXRT1050RM Rev.2.1.
+** - rev. 1.3 (2019-04-29)
+** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MIMXRT1052.h
+ * @version 1.3
+ * @date 2019-04-29
+ * @brief CMSIS Peripheral Access Layer for MIMXRT1052
+ *
+ * CMSIS Peripheral Access Layer for MIMXRT1052
+ */
+
+#ifndef _MIMXRT1052_H_
+#define _MIMXRT1052_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0003U
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 168 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */
+ DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */
+ DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */
+ DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */
+ DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */
+ DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */
+ DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */
+ DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */
+ DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */
+ DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */
+ DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */
+ DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */
+ DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */
+ DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */
+ DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */
+ DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */
+ DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */
+ CTI0_ERROR_IRQn = 17, /**< CTI0_Error */
+ CTI1_ERROR_IRQn = 18, /**< CTI1_Error */
+ CORE_IRQn = 19, /**< CorePlatform exception IRQ */
+ LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */
+ LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */
+ LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */
+ LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */
+ LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */
+ LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */
+ LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */
+ LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */
+ LPI2C1_IRQn = 28, /**< LPI2C1 interrupt */
+ LPI2C2_IRQn = 29, /**< LPI2C2 interrupt */
+ LPI2C3_IRQn = 30, /**< LPI2C3 interrupt */
+ LPI2C4_IRQn = 31, /**< LPI2C4 interrupt */
+ LPSPI1_IRQn = 32, /**< LPSPI1 single interrupt vector for all sources */
+ LPSPI2_IRQn = 33, /**< LPSPI2 single interrupt vector for all sources */
+ LPSPI3_IRQn = 34, /**< LPSPI3 single interrupt vector for all sources */
+ LPSPI4_IRQn = 35, /**< LPSPI4 single interrupt vector for all sources */
+ CAN1_IRQn = 36, /**< CAN1 interrupt */
+ CAN2_IRQn = 37, /**< CAN2 interrupt */
+ FLEXRAM_IRQn = 38, /**< FlexRAM address out of range Or access hit IRQ */
+ KPP_IRQn = 39, /**< Keypad nterrupt */
+ TSC_DIG_IRQn = 40, /**< TSC interrupt */
+ GPR_IRQ_IRQn = 41, /**< GPR interrupt */
+ LCDIF_IRQn = 42, /**< LCDIF interrupt */
+ CSI_IRQn = 43, /**< CSI interrupt */
+ PXP_IRQn = 44, /**< PXP interrupt */
+ WDOG2_IRQn = 45, /**< WDOG2 interrupt */
+ SNVS_HP_WRAPPER_IRQn = 46, /**< SRTC Consolidated Interrupt. Non TZ */
+ SNVS_HP_WRAPPER_TZ_IRQn = 47, /**< SRTC Security Interrupt. TZ */
+ SNVS_LP_WRAPPER_IRQn = 48, /**< ON-OFF button press shorter than 5 secs (pulse event) */
+ CSU_IRQn = 49, /**< CSU interrupt */
+ DCP_IRQn = 50, /**< DCP_IRQ interrupt */
+ DCP_VMI_IRQn = 51, /**< DCP_VMI_IRQ interrupt */
+ Reserved68_IRQn = 52, /**< Reserved interrupt */
+ TRNG_IRQn = 53, /**< TRNG interrupt */
+ SJC_IRQn = 54, /**< SJC interrupt */
+ BEE_IRQn = 55, /**< BEE interrupt */
+ SAI1_IRQn = 56, /**< SAI1 interrupt */
+ SAI2_IRQn = 57, /**< SAI1 interrupt */
+ SAI3_RX_IRQn = 58, /**< SAI3 interrupt */
+ SAI3_TX_IRQn = 59, /**< SAI3 interrupt */
+ SPDIF_IRQn = 60, /**< SPDIF interrupt */
+ PMU_EVENT_IRQn = 61, /**< Brown-out event interrupt */
+ Reserved78_IRQn = 62, /**< Reserved interrupt */
+ TEMP_LOW_HIGH_IRQn = 63, /**< TempSensor low/high interrupt */
+ TEMP_PANIC_IRQn = 64, /**< TempSensor panic interrupt */
+ USB_PHY1_IRQn = 65, /**< USBPHY (UTMI0), Interrupt */
+ USB_PHY2_IRQn = 66, /**< USBPHY (UTMI0), Interrupt */
+ ADC1_IRQn = 67, /**< ADC1 interrupt */
+ ADC2_IRQn = 68, /**< ADC2 interrupt */
+ DCDC_IRQn = 69, /**< DCDC interrupt */
+ Reserved86_IRQn = 70, /**< Reserved interrupt */
+ Reserved87_IRQn = 71, /**< Reserved interrupt */
+ GPIO1_INT0_IRQn = 72, /**< Active HIGH Interrupt from INT0 from GPIO */
+ GPIO1_INT1_IRQn = 73, /**< Active HIGH Interrupt from INT1 from GPIO */
+ GPIO1_INT2_IRQn = 74, /**< Active HIGH Interrupt from INT2 from GPIO */
+ GPIO1_INT3_IRQn = 75, /**< Active HIGH Interrupt from INT3 from GPIO */
+ GPIO1_INT4_IRQn = 76, /**< Active HIGH Interrupt from INT4 from GPIO */
+ GPIO1_INT5_IRQn = 77, /**< Active HIGH Interrupt from INT5 from GPIO */
+ GPIO1_INT6_IRQn = 78, /**< Active HIGH Interrupt from INT6 from GPIO */
+ GPIO1_INT7_IRQn = 79, /**< Active HIGH Interrupt from INT7 from GPIO */
+ GPIO1_Combined_0_15_IRQn = 80, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
+ GPIO1_Combined_16_31_IRQn = 81, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
+ GPIO2_Combined_0_15_IRQn = 82, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
+ GPIO2_Combined_16_31_IRQn = 83, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
+ GPIO3_Combined_0_15_IRQn = 84, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
+ GPIO3_Combined_16_31_IRQn = 85, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
+ GPIO4_Combined_0_15_IRQn = 86, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
+ GPIO4_Combined_16_31_IRQn = 87, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
+ GPIO5_Combined_0_15_IRQn = 88, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
+ GPIO5_Combined_16_31_IRQn = 89, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
+ FLEXIO1_IRQn = 90, /**< FLEXIO1 interrupt */
+ FLEXIO2_IRQn = 91, /**< FLEXIO2 interrupt */
+ WDOG1_IRQn = 92, /**< WDOG1 interrupt */
+ RTWDOG_IRQn = 93, /**< RTWDOG interrupt */
+ EWM_IRQn = 94, /**< EWM interrupt */
+ CCM_1_IRQn = 95, /**< CCM IRQ1 interrupt */
+ CCM_2_IRQn = 96, /**< CCM IRQ2 interrupt */
+ GPC_IRQn = 97, /**< GPC interrupt */
+ SRC_IRQn = 98, /**< SRC interrupt */
+ Reserved115_IRQn = 99, /**< Reserved interrupt */
+ GPT1_IRQn = 100, /**< GPT1 interrupt */
+ GPT2_IRQn = 101, /**< GPT2 interrupt */
+ PWM1_0_IRQn = 102, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
+ PWM1_1_IRQn = 103, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
+ PWM1_2_IRQn = 104, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
+ PWM1_3_IRQn = 105, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
+ PWM1_FAULT_IRQn = 106, /**< PWM1 fault or reload error interrupt */
+ Reserved123_IRQn = 107, /**< Reserved interrupt */
+ FLEXSPI_IRQn = 108, /**< FlexSPI0 interrupt */
+ SEMC_IRQn = 109, /**< Reserved interrupt */
+ USDHC1_IRQn = 110, /**< USDHC1 interrupt */
+ USDHC2_IRQn = 111, /**< USDHC2 interrupt */
+ USB_OTG2_IRQn = 112, /**< USBO2 USB OTG2 */
+ USB_OTG1_IRQn = 113, /**< USBO2 USB OTG1 */
+ ENET_IRQn = 114, /**< ENET interrupt */
+ ENET_1588_Timer_IRQn = 115, /**< ENET_1588_Timer interrupt */
+ XBAR1_IRQ_0_1_IRQn = 116, /**< XBAR1 interrupt */
+ XBAR1_IRQ_2_3_IRQn = 117, /**< XBAR1 interrupt */
+ ADC_ETC_IRQ0_IRQn = 118, /**< ADCETC IRQ0 interrupt */
+ ADC_ETC_IRQ1_IRQn = 119, /**< ADCETC IRQ1 interrupt */
+ ADC_ETC_IRQ2_IRQn = 120, /**< ADCETC IRQ2 interrupt */
+ ADC_ETC_ERROR_IRQ_IRQn = 121, /**< ADCETC Error IRQ interrupt */
+ PIT_IRQn = 122, /**< PIT interrupt */
+ ACMP1_IRQn = 123, /**< ACMP interrupt */
+ ACMP2_IRQn = 124, /**< ACMP interrupt */
+ ACMP3_IRQn = 125, /**< ACMP interrupt */
+ ACMP4_IRQn = 126, /**< ACMP interrupt */
+ Reserved143_IRQn = 127, /**< Reserved interrupt */
+ Reserved144_IRQn = 128, /**< Reserved interrupt */
+ ENC1_IRQn = 129, /**< ENC1 interrupt */
+ ENC2_IRQn = 130, /**< ENC2 interrupt */
+ ENC3_IRQn = 131, /**< ENC3 interrupt */
+ ENC4_IRQn = 132, /**< ENC4 interrupt */
+ TMR1_IRQn = 133, /**< TMR1 interrupt */
+ TMR2_IRQn = 134, /**< TMR2 interrupt */
+ TMR3_IRQn = 135, /**< TMR3 interrupt */
+ TMR4_IRQn = 136, /**< TMR4 interrupt */
+ PWM2_0_IRQn = 137, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
+ PWM2_1_IRQn = 138, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
+ PWM2_2_IRQn = 139, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
+ PWM2_3_IRQn = 140, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
+ PWM2_FAULT_IRQn = 141, /**< PWM2 fault or reload error interrupt */
+ PWM3_0_IRQn = 142, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */
+ PWM3_1_IRQn = 143, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */
+ PWM3_2_IRQn = 144, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */
+ PWM3_3_IRQn = 145, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */
+ PWM3_FAULT_IRQn = 146, /**< PWM3 fault or reload error interrupt */
+ PWM4_0_IRQn = 147, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */
+ PWM4_1_IRQn = 148, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
+ PWM4_2_IRQn = 149, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
+ PWM4_3_IRQn = 150, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
+ PWM4_FAULT_IRQn = 151 /**< PWM4 fault or reload error interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M7 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
+#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
+#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
+#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+
+#include "core_cm7.h" /* Core Peripheral Access Layer */
+#include "system_MIMXRT1052.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Mapping Information
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+ kDmaRequestMuxFlexIO1Request0Request1 = 0|0x100U, /**< FlexIO1 Request0 and Request1 */
+ kDmaRequestMuxFlexIO2Request0Request1 = 1|0x100U, /**< FlexIO2 Request0 and Request1 */
+ kDmaRequestMuxLPUART1Tx = 2|0x100U, /**< LPUART1 Transmit */
+ kDmaRequestMuxLPUART1Rx = 3|0x100U, /**< LPUART1 Receive */
+ kDmaRequestMuxLPUART3Tx = 4|0x100U, /**< LPUART3 Transmit */
+ kDmaRequestMuxLPUART3Rx = 5|0x100U, /**< LPUART3 Receive */
+ kDmaRequestMuxLPUART5Tx = 6|0x100U, /**< LPUART5 Transmit */
+ kDmaRequestMuxLPUART5Rx = 7|0x100U, /**< LPUART5 Receive */
+ kDmaRequestMuxLPUART7Tx = 8|0x100U, /**< LPUART7 Transmit */
+ kDmaRequestMuxLPUART7Rx = 9|0x100U, /**< LPUART7 Receive */
+ kDmaRequestMuxCSI = 12|0x100U, /**< CSI */
+ kDmaRequestMuxLPSPI1Rx = 13|0x100U, /**< LPSPI1 Receive */
+ kDmaRequestMuxLPSPI1Tx = 14|0x100U, /**< LPSPI1 Transmit */
+ kDmaRequestMuxLPSPI3Rx = 15|0x100U, /**< LPSPI3 Receive */
+ kDmaRequestMuxLPSPI3Tx = 16|0x100U, /**< LPSPI3 Transmit */
+ kDmaRequestMuxLPI2C1 = 17|0x100U, /**< LPI2C1 */
+ kDmaRequestMuxLPI2C3 = 18|0x100U, /**< LPI2C3 */
+ kDmaRequestMuxSai1Rx = 19|0x100U, /**< SAI1 Receive */
+ kDmaRequestMuxSai1Tx = 20|0x100U, /**< SAI1 Transmit */
+ kDmaRequestMuxSai2Rx = 21|0x100U, /**< SAI2 Receive */
+ kDmaRequestMuxSai2Tx = 22|0x100U, /**< SAI2 Transmit */
+ kDmaRequestMuxADC_ETC = 23|0x100U, /**< ADC_ETC */
+ kDmaRequestMuxADC1 = 24|0x100U, /**< ADC1 */
+ kDmaRequestMuxACMP1 = 25|0x100U, /**< ACMP1 */
+ kDmaRequestMuxACMP3 = 26|0x100U, /**< ACMP3 */
+ kDmaRequestMuxFlexSPIRx = 28|0x100U, /**< FlexSPI Receive */
+ kDmaRequestMuxFlexSPITx = 29|0x100U, /**< FlexSPI Transmit */
+ kDmaRequestMuxXBAR1Request0 = 30|0x100U, /**< XBAR1 Request 0 */
+ kDmaRequestMuxXBAR1Request1 = 31|0x100U, /**< XBAR1 Request 1 */
+ kDmaRequestMuxFlexPWM1CaptureSub0 = 32|0x100U, /**< FlexPWM1 Capture sub-module0 */
+ kDmaRequestMuxFlexPWM1CaptureSub1 = 33|0x100U, /**< FlexPWM1 Capture sub-module1 */
+ kDmaRequestMuxFlexPWM1CaptureSub2 = 34|0x100U, /**< FlexPWM1 Capture sub-module2 */
+ kDmaRequestMuxFlexPWM1CaptureSub3 = 35|0x100U, /**< FlexPWM1 Capture sub-module3 */
+ kDmaRequestMuxFlexPWM1ValueSub0 = 36|0x100U, /**< FlexPWM1 Value sub-module0 */
+ kDmaRequestMuxFlexPWM1ValueSub1 = 37|0x100U, /**< FlexPWM1 Value sub-module1 */
+ kDmaRequestMuxFlexPWM1ValueSub2 = 38|0x100U, /**< FlexPWM1 Value sub-module2 */
+ kDmaRequestMuxFlexPWM1ValueSub3 = 39|0x100U, /**< FlexPWM1 Value sub-module3 */
+ kDmaRequestMuxFlexPWM3CaptureSub0 = 40|0x100U, /**< FlexPWM3 Capture sub-module0 */
+ kDmaRequestMuxFlexPWM3CaptureSub1 = 41|0x100U, /**< FlexPWM3 Capture sub-module1 */
+ kDmaRequestMuxFlexPWM3CaptureSub2 = 42|0x100U, /**< FlexPWM3 Capture sub-module2 */
+ kDmaRequestMuxFlexPWM3CaptureSub3 = 43|0x100U, /**< FlexPWM3 Capture sub-module3 */
+ kDmaRequestMuxFlexPWM3ValueSub0 = 44|0x100U, /**< FlexPWM3 Value sub-module0 */
+ kDmaRequestMuxFlexPWM3ValueSub1 = 45|0x100U, /**< FlexPWM3 Value sub-module1 */
+ kDmaRequestMuxFlexPWM3ValueSub2 = 46|0x100U, /**< FlexPWM3 Value sub-module2 */
+ kDmaRequestMuxFlexPWM3ValueSub3 = 47|0x100U, /**< FlexPWM3 Value sub-module3 */
+ kDmaRequestMuxQTIMER1CaptTimer0 = 48|0x100U, /**< TMR1 Capture timer 0 */
+ kDmaRequestMuxQTIMER1CaptTimer1 = 49|0x100U, /**< TMR1 Capture timer 1 */
+ kDmaRequestMuxQTIMER1CaptTimer2 = 50|0x100U, /**< TMR1 Capture timer 2 */
+ kDmaRequestMuxQTIMER1CaptTimer3 = 51|0x100U, /**< TMR1 Capture timer 3 */
+ kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 52|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
+ kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 53|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
+ kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 54|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
+ kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 55|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
+ kDmaRequestMuxQTIMER3CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 56|0x100U, /**< TMR3 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
+ kDmaRequestMuxQTIMER3CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 57|0x100U, /**< TMR3 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
+ kDmaRequestMuxQTIMER3CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 58|0x100U, /**< TMR3 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
+ kDmaRequestMuxQTIMER3CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 59|0x100U, /**< TMR3 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
+ kDmaRequestMuxFlexIO1Request2Request3 = 64|0x100U, /**< FlexIO1 Request2 and Request3 */
+ kDmaRequestMuxFlexIO2Request2Request3 = 65|0x100U, /**< FlexIO2 Request2 and Request3 */
+ kDmaRequestMuxLPUART2Tx = 66|0x100U, /**< LPUART2 Transmit */
+ kDmaRequestMuxLPUART2Rx = 67|0x100U, /**< LPUART2 Receive */
+ kDmaRequestMuxLPUART4Tx = 68|0x100U, /**< LPUART4 Transmit */
+ kDmaRequestMuxLPUART4Rx = 69|0x100U, /**< LPUART4 Receive */
+ kDmaRequestMuxLPUART6Tx = 70|0x100U, /**< LPUART6 Transmit */
+ kDmaRequestMuxLPUART6Rx = 71|0x100U, /**< LPUART6 Receive */
+ kDmaRequestMuxLPUART8Tx = 72|0x100U, /**< LPUART8 Transmit */
+ kDmaRequestMuxLPUART8Rx = 73|0x100U, /**< LPUART8 Receive */
+ kDmaRequestMuxPxp = 75|0x100U, /**< PXP */
+ kDmaRequestMuxLCDIF = 76|0x100U, /**< LCDIF */
+ kDmaRequestMuxLPSPI2Rx = 77|0x100U, /**< LPSPI2 Receive */
+ kDmaRequestMuxLPSPI2Tx = 78|0x100U, /**< LPSPI2 Transmit */
+ kDmaRequestMuxLPSPI4Rx = 79|0x100U, /**< LPSPI4 Receive */
+ kDmaRequestMuxLPSPI4Tx = 80|0x100U, /**< LPSPI4 Transmit */
+ kDmaRequestMuxLPI2C2 = 81|0x100U, /**< LPI2C2 */
+ kDmaRequestMuxLPI2C4 = 82|0x100U, /**< LPI2C4 */
+ kDmaRequestMuxSai3Rx = 83|0x100U, /**< SAI3 Receive */
+ kDmaRequestMuxSai3Tx = 84|0x100U, /**< SAI3 Transmit */
+ kDmaRequestMuxSpdifRx = 85|0x100U, /**< SPDIF Receive */
+ kDmaRequestMuxSpdifTx = 86|0x100U, /**< SPDIF Transmit */
+ kDmaRequestMuxADC2 = 88|0x100U, /**< ADC2 */
+ kDmaRequestMuxACMP2 = 89|0x100U, /**< ACMP2 */
+ kDmaRequestMuxACMP4 = 90|0x100U, /**< ACMP4 */
+ kDmaRequestMuxEnetTimer0 = 92|0x100U, /**< ENET Timer0 */
+ kDmaRequestMuxEnetTimer1 = 93|0x100U, /**< ENET Timer1 */
+ kDmaRequestMuxXBAR1Request2 = 94|0x100U, /**< XBAR1 Request 2 */
+ kDmaRequestMuxXBAR1Request3 = 95|0x100U, /**< XBAR1 Request 3 */
+ kDmaRequestMuxFlexPWM2CaptureSub0 = 96|0x100U, /**< FlexPWM2 Capture sub-module0 */
+ kDmaRequestMuxFlexPWM2CaptureSub1 = 97|0x100U, /**< FlexPWM2 Capture sub-module1 */
+ kDmaRequestMuxFlexPWM2CaptureSub2 = 98|0x100U, /**< FlexPWM2 Capture sub-module2 */
+ kDmaRequestMuxFlexPWM2CaptureSub3 = 99|0x100U, /**< FlexPWM2 Capture sub-module3 */
+ kDmaRequestMuxFlexPWM2ValueSub0 = 100|0x100U, /**< FlexPWM2 Value sub-module0 */
+ kDmaRequestMuxFlexPWM2ValueSub1 = 101|0x100U, /**< FlexPWM2 Value sub-module1 */
+ kDmaRequestMuxFlexPWM2ValueSub2 = 102|0x100U, /**< FlexPWM2 Value sub-module2 */
+ kDmaRequestMuxFlexPWM2ValueSub3 = 103|0x100U, /**< FlexPWM2 Value sub-module3 */
+ kDmaRequestMuxFlexPWM4CaptureSub0 = 104|0x100U, /**< FlexPWM4 Capture sub-module0 */
+ kDmaRequestMuxFlexPWM4CaptureSub1 = 105|0x100U, /**< FlexPWM4 Capture sub-module1 */
+ kDmaRequestMuxFlexPWM4CaptureSub2 = 106|0x100U, /**< FlexPWM4 Capture sub-module2 */
+ kDmaRequestMuxFlexPWM4CaptureSub3 = 107|0x100U, /**< FlexPWM4 Capture sub-module3 */
+ kDmaRequestMuxFlexPWM4ValueSub0 = 108|0x100U, /**< FlexPWM4 Value sub-module0 */
+ kDmaRequestMuxFlexPWM4ValueSub1 = 109|0x100U, /**< FlexPWM4 Value sub-module1 */
+ kDmaRequestMuxFlexPWM4ValueSub2 = 110|0x100U, /**< FlexPWM4 Value sub-module2 */
+ kDmaRequestMuxFlexPWM4ValueSub3 = 111|0x100U, /**< FlexPWM4 Value sub-module3 */
+ kDmaRequestMuxQTIMER2CaptTimer0 = 112|0x100U, /**< TMR2 Capture timer 0 */
+ kDmaRequestMuxQTIMER2CaptTimer1 = 113|0x100U, /**< TMR2 Capture timer 1 */
+ kDmaRequestMuxQTIMER2CaptTimer2 = 114|0x100U, /**< TMR2 Capture timer 2 */
+ kDmaRequestMuxQTIMER2CaptTimer3 = 115|0x100U, /**< TMR2 Capture timer 3 */
+ kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 116|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
+ kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 117|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
+ kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 118|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
+ kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 119|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
+ kDmaRequestMuxQTIMER4CaptTimer0Cmpld1Timer0Cmpld2Timer1 = 120|0x100U, /**< TMR4 capture timer 0, cmpld1 in timer 0 or cmpld2 in timer 1 */
+ kDmaRequestMuxQTIMER4CaptTimer1Cmpld1Timer1Cmpld2Timer0 = 121|0x100U, /**< TMR4 capture timer 1, cmpld1 in timer 1 or cmpld2 in timer 0 */
+ kDmaRequestMuxQTIMER4CaptTimer2Cmpld1Timer2Cmpld2Timer3 = 122|0x100U, /**< TMR4 capture timer 2, cmpld1 in timer 2 or cmpld2 in timer 3 */
+ kDmaRequestMuxQTIMER4CaptTimer3Cmpld1Timer3Cmpld2Timer2 = 123|0x100U, /**< TMR4 capture timer 3, cmpld1 in timer 3 or cmpld2 in timer 2 */
+} dma_request_source_t;
+
+/* @} */
+
+/*!
+ * @addtogroup iomuxc_pads
+ * @{ */
+
+/*******************************************************************************
+ * Definitions
+*******************************************************************************/
+
+/*!
+ * @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
+ *
+ * Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
+ */
+typedef enum _iomuxc_sw_mux_ctl_pad
+{
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
+ kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
+} iomuxc_sw_mux_ctl_pad_t;
+
+/* @} */
+
+/*!
+ * @addtogroup iomuxc_pads
+ * @{ */
+
+/*******************************************************************************
+ * Definitions
+*******************************************************************************/
+
+/*!
+ * @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
+ *
+ * Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
+ */
+typedef enum _iomuxc_sw_pad_ctl_pad
+{
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B0_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_00 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_01 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_02 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_03 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_04 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_05 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_06 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_07 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_08 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_09 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_10 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_11 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_12 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_13 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_14 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_B1_15 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_00 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_01 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_02 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_03 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_04 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_05 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_06 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_07 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_08 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_09 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_10 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_11 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_12 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_13 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_14 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B0_15 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_00 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_01 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_02 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_03 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_04 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_05 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_06 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_07 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_08 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_09 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_10 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_11 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_12 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_13 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_14 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_B1_15 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_00 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_01 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_02 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_03 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_04 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B0_05 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_06 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_07 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_08 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_09 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_10 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
+ kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_11 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
+} iomuxc_sw_pad_ctl_pad_t;
+
+/* @} */
+
+/*!
+ * @brief Enumeration for the IOMUXC select input
+ *
+ * Defines the enumeration for the IOMUXC select input collections.
+ */
+typedef enum _iomuxc_select_input
+{
+ kIOMUXC_ANATOP_USB_OTG1_ID_SELECT_INPUT = 0U, /**< IOMUXC select input index */
+ kIOMUXC_ANATOP_USB_OTG2_ID_SELECT_INPUT = 1U, /**< IOMUXC select input index */
+ kIOMUXC_CCM_PMIC_READY_SELECT_INPUT = 2U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_DATA02_SELECT_INPUT = 3U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_DATA03_SELECT_INPUT = 4U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_DATA04_SELECT_INPUT = 5U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_DATA05_SELECT_INPUT = 6U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_DATA06_SELECT_INPUT = 7U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_DATA07_SELECT_INPUT = 8U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_DATA08_SELECT_INPUT = 9U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_DATA09_SELECT_INPUT = 10U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_HSYNC_SELECT_INPUT = 11U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_PIXCLK_SELECT_INPUT = 12U, /**< IOMUXC select input index */
+ kIOMUXC_CSI_VSYNC_SELECT_INPUT = 13U, /**< IOMUXC select input index */
+ kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 14U, /**< IOMUXC select input index */
+ kIOMUXC_ENET_MDIO_SELECT_INPUT = 15U, /**< IOMUXC select input index */
+ kIOMUXC_ENET0_RXDATA_SELECT_INPUT = 16U, /**< IOMUXC select input index */
+ kIOMUXC_ENET1_RXDATA_SELECT_INPUT = 17U, /**< IOMUXC select input index */
+ kIOMUXC_ENET_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */
+ kIOMUXC_ENET_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */
+ kIOMUXC_ENET0_TIMER_SELECT_INPUT = 20U, /**< IOMUXC select input index */
+ kIOMUXC_ENET_TXCLK_SELECT_INPUT = 21U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 22U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 23U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM1_PWMA3_SELECT_INPUT = 24U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM1_PWMA0_SELECT_INPUT = 25U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM1_PWMA1_SELECT_INPUT = 26U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM1_PWMA2_SELECT_INPUT = 27U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM1_PWMB3_SELECT_INPUT = 28U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM1_PWMB0_SELECT_INPUT = 29U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM1_PWMB1_SELECT_INPUT = 30U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM1_PWMB2_SELECT_INPUT = 31U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM2_PWMA3_SELECT_INPUT = 32U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM2_PWMA0_SELECT_INPUT = 33U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM2_PWMA1_SELECT_INPUT = 34U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM2_PWMA2_SELECT_INPUT = 35U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM2_PWMB3_SELECT_INPUT = 36U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM2_PWMB0_SELECT_INPUT = 37U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM2_PWMB1_SELECT_INPUT = 38U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM2_PWMB2_SELECT_INPUT = 39U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM4_PWMA0_SELECT_INPUT = 40U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM4_PWMA1_SELECT_INPUT = 41U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM4_PWMA2_SELECT_INPUT = 42U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXPWM4_PWMA3_SELECT_INPUT = 43U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXSPIA_DQS_SELECT_INPUT = 44U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXSPIA_DATA0_SELECT_INPUT = 45U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXSPIA_DATA1_SELECT_INPUT = 46U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXSPIA_DATA2_SELECT_INPUT = 47U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXSPIA_DATA3_SELECT_INPUT = 48U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXSPIB_DATA0_SELECT_INPUT = 49U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXSPIB_DATA1_SELECT_INPUT = 50U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXSPIB_DATA2_SELECT_INPUT = 51U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXSPIB_DATA3_SELECT_INPUT = 52U, /**< IOMUXC select input index */
+ kIOMUXC_FLEXSPIA_SCK_SELECT_INPUT = 53U, /**< IOMUXC select input index */
+ kIOMUXC_LPI2C1_SCL_SELECT_INPUT = 54U, /**< IOMUXC select input index */
+ kIOMUXC_LPI2C1_SDA_SELECT_INPUT = 55U, /**< IOMUXC select input index */
+ kIOMUXC_LPI2C2_SCL_SELECT_INPUT = 56U, /**< IOMUXC select input index */
+ kIOMUXC_LPI2C2_SDA_SELECT_INPUT = 57U, /**< IOMUXC select input index */
+ kIOMUXC_LPI2C3_SCL_SELECT_INPUT = 58U, /**< IOMUXC select input index */
+ kIOMUXC_LPI2C3_SDA_SELECT_INPUT = 59U, /**< IOMUXC select input index */
+ kIOMUXC_LPI2C4_SCL_SELECT_INPUT = 60U, /**< IOMUXC select input index */
+ kIOMUXC_LPI2C4_SDA_SELECT_INPUT = 61U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI1_PCS0_SELECT_INPUT = 62U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI1_SCK_SELECT_INPUT = 63U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI1_SDI_SELECT_INPUT = 64U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI1_SDO_SELECT_INPUT = 65U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI2_PCS0_SELECT_INPUT = 66U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI2_SCK_SELECT_INPUT = 67U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI2_SDI_SELECT_INPUT = 68U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI2_SDO_SELECT_INPUT = 69U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI3_PCS0_SELECT_INPUT = 70U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI3_SCK_SELECT_INPUT = 71U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI3_SDI_SELECT_INPUT = 72U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI3_SDO_SELECT_INPUT = 73U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI4_PCS0_SELECT_INPUT = 74U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI4_SCK_SELECT_INPUT = 75U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI4_SDI_SELECT_INPUT = 76U, /**< IOMUXC select input index */
+ kIOMUXC_LPSPI4_SDO_SELECT_INPUT = 77U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART2_RX_SELECT_INPUT = 78U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART2_TX_SELECT_INPUT = 79U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART3_CTS_B_SELECT_INPUT = 80U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART3_RX_SELECT_INPUT = 81U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART3_TX_SELECT_INPUT = 82U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART4_RX_SELECT_INPUT = 83U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART4_TX_SELECT_INPUT = 84U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART5_RX_SELECT_INPUT = 85U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART5_TX_SELECT_INPUT = 86U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART6_RX_SELECT_INPUT = 87U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART6_TX_SELECT_INPUT = 88U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART7_RX_SELECT_INPUT = 89U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART7_TX_SELECT_INPUT = 90U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART8_RX_SELECT_INPUT = 91U, /**< IOMUXC select input index */
+ kIOMUXC_LPUART8_TX_SELECT_INPUT = 92U, /**< IOMUXC select input index */
+ kIOMUXC_NMI_SELECT_INPUT = 93U, /**< IOMUXC select input index */
+ kIOMUXC_QTIMER2_TIMER0_SELECT_INPUT = 94U, /**< IOMUXC select input index */
+ kIOMUXC_QTIMER2_TIMER1_SELECT_INPUT = 95U, /**< IOMUXC select input index */
+ kIOMUXC_QTIMER2_TIMER2_SELECT_INPUT = 96U, /**< IOMUXC select input index */
+ kIOMUXC_QTIMER2_TIMER3_SELECT_INPUT = 97U, /**< IOMUXC select input index */
+ kIOMUXC_QTIMER3_TIMER0_SELECT_INPUT = 98U, /**< IOMUXC select input index */
+ kIOMUXC_QTIMER3_TIMER1_SELECT_INPUT = 99U, /**< IOMUXC select input index */
+ kIOMUXC_QTIMER3_TIMER2_SELECT_INPUT = 100U, /**< IOMUXC select input index */
+ kIOMUXC_QTIMER3_TIMER3_SELECT_INPUT = 101U, /**< IOMUXC select input index */
+ kIOMUXC_SAI1_MCLK2_SELECT_INPUT = 102U, /**< IOMUXC select input index */
+ kIOMUXC_SAI1_RX_BCLK_SELECT_INPUT = 103U, /**< IOMUXC select input index */
+ kIOMUXC_SAI1_RX_DATA0_SELECT_INPUT = 104U, /**< IOMUXC select input index */
+ kIOMUXC_SAI1_RX_DATA1_SELECT_INPUT = 105U, /**< IOMUXC select input index */
+ kIOMUXC_SAI1_RX_DATA2_SELECT_INPUT = 106U, /**< IOMUXC select input index */
+ kIOMUXC_SAI1_RX_DATA3_SELECT_INPUT = 107U, /**< IOMUXC select input index */
+ kIOMUXC_SAI1_RX_SYNC_SELECT_INPUT = 108U, /**< IOMUXC select input index */
+ kIOMUXC_SAI1_TX_BCLK_SELECT_INPUT = 109U, /**< IOMUXC select input index */
+ kIOMUXC_SAI1_TX_SYNC_SELECT_INPUT = 110U, /**< IOMUXC select input index */
+ kIOMUXC_SAI2_MCLK2_SELECT_INPUT = 111U, /**< IOMUXC select input index */
+ kIOMUXC_SAI2_RX_BCLK_SELECT_INPUT = 112U, /**< IOMUXC select input index */
+ kIOMUXC_SAI2_RX_DATA0_SELECT_INPUT = 113U, /**< IOMUXC select input index */
+ kIOMUXC_SAI2_RX_SYNC_SELECT_INPUT = 114U, /**< IOMUXC select input index */
+ kIOMUXC_SAI2_TX_BCLK_SELECT_INPUT = 115U, /**< IOMUXC select input index */
+ kIOMUXC_SAI2_TX_SYNC_SELECT_INPUT = 116U, /**< IOMUXC select input index */
+ kIOMUXC_SPDIF_IN_SELECT_INPUT = 117U, /**< IOMUXC select input index */
+ kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 118U, /**< IOMUXC select input index */
+ kIOMUXC_USB_OTG1_OC_SELECT_INPUT = 119U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC1_CD_B_SELECT_INPUT = 120U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC1_WP_SELECT_INPUT = 121U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_CLK_SELECT_INPUT = 122U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_CD_B_SELECT_INPUT = 123U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_CMD_SELECT_INPUT = 124U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_DATA0_SELECT_INPUT = 125U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_DATA1_SELECT_INPUT = 126U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_DATA2_SELECT_INPUT = 127U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_DATA3_SELECT_INPUT = 128U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_DATA4_SELECT_INPUT = 129U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_DATA5_SELECT_INPUT = 130U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_DATA6_SELECT_INPUT = 131U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_DATA7_SELECT_INPUT = 132U, /**< IOMUXC select input index */
+ kIOMUXC_USDHC2_WP_SELECT_INPUT = 133U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN02_SELECT_INPUT = 134U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN03_SELECT_INPUT = 135U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN04_SELECT_INPUT = 136U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN05_SELECT_INPUT = 137U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN06_SELECT_INPUT = 138U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN07_SELECT_INPUT = 139U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN08_SELECT_INPUT = 140U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN09_SELECT_INPUT = 141U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN17_SELECT_INPUT = 142U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN18_SELECT_INPUT = 143U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN20_SELECT_INPUT = 144U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN22_SELECT_INPUT = 145U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN23_SELECT_INPUT = 146U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN24_SELECT_INPUT = 147U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN14_SELECT_INPUT = 148U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN15_SELECT_INPUT = 149U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN16_SELECT_INPUT = 150U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN25_SELECT_INPUT = 151U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN19_SELECT_INPUT = 152U, /**< IOMUXC select input index */
+ kIOMUXC_XBAR1_IN21_SELECT_INPUT = 153U, /**< IOMUXC select input index */
+} iomuxc_select_input_t;
+
+typedef enum _xbar_input_signal
+{
+ kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */
+ kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */
+ kXBARA1_InputIomuxXbarIn02 = 2|0x100U, /**< IOMUX_XBAR_IN02 output assigned to XBARA1_IN2 input. */
+ kXBARA1_InputIomuxXbarIn03 = 3|0x100U, /**< IOMUX_XBAR_IN03 output assigned to XBARA1_IN3 input. */
+ kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
+ kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
+ kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
+ kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
+ kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
+ kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
+ kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
+ kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
+ kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
+ kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
+ kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
+ kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
+ kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
+ kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
+ kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
+ kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
+ kXBARA1_InputIomuxXbarIn20 = 20|0x100U, /**< IOMUX_XBAR_IN20 output assigned to XBARA1_IN20 input. */
+ kXBARA1_InputIomuxXbarIn21 = 21|0x100U, /**< IOMUX_XBAR_IN21 output assigned to XBARA1_IN21 input. */
+ kXBARA1_InputIomuxXbarIn22 = 22|0x100U, /**< IOMUX_XBAR_IN22 output assigned to XBARA1_IN22 input. */
+ kXBARA1_InputIomuxXbarIn23 = 23|0x100U, /**< IOMUX_XBAR_IN23 output assigned to XBARA1_IN23 input. */
+ kXBARA1_InputIomuxXbarIn24 = 24|0x100U, /**< IOMUX_XBAR_IN24 output assigned to XBARA1_IN24 input. */
+ kXBARA1_InputIomuxXbarIn25 = 25|0x100U, /**< IOMUX_XBAR_IN25 output assigned to XBARA1_IN25 input. */
+ kXBARA1_InputAcmp1Out = 26|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN26 input. */
+ kXBARA1_InputAcmp2Out = 27|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN27 input. */
+ kXBARA1_InputAcmp3Out = 28|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN28 input. */
+ kXBARA1_InputAcmp4Out = 29|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN29 input. */
+ kXBARA1_InputRESERVED30 = 30|0x100U, /**< XBARA1_IN30 input is reserved. */
+ kXBARA1_InputRESERVED31 = 31|0x100U, /**< XBARA1_IN31 input is reserved. */
+ kXBARA1_InputQtimer3Tmr0Output = 32|0x100U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARA1_IN32 input. */
+ kXBARA1_InputQtimer3Tmr1Output = 33|0x100U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARA1_IN33 input. */
+ kXBARA1_InputQtimer3Tmr2Output = 34|0x100U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARA1_IN34 input. */
+ kXBARA1_InputQtimer3Tmr3Output = 35|0x100U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARA1_IN35 input. */
+ kXBARA1_InputQtimer4Tmr0Output = 36|0x100U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARA1_IN36 input. */
+ kXBARA1_InputQtimer4Tmr1Output = 37|0x100U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARA1_IN37 input. */
+ kXBARA1_InputQtimer4Tmr2Output = 38|0x100U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARA1_IN38 input. */
+ kXBARA1_InputQtimer4Tmr3Output = 39|0x100U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARA1_IN39 input. */
+ kXBARA1_InputFlexpwm1Pwm1OutTrig01 = 40|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN40 input. */
+ kXBARA1_InputFlexpwm1Pwm2OutTrig01 = 41|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN41 input. */
+ kXBARA1_InputFlexpwm1Pwm3OutTrig01 = 42|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN42 input. */
+ kXBARA1_InputFlexpwm1Pwm4OutTrig01 = 43|0x100U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN43 input. */
+ kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 44|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN44 input. */
+ kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 45|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN45 input. */
+ kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 46|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN46 input. */
+ kXBARA1_InputFlexpwm2Pwm4OutTrig01 = 47|0x100U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN47 input. */
+ kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 48|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN48 input. */
+ kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 49|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN49 input. */
+ kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 50|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN50 input. */
+ kXBARA1_InputFlexpwm3Pwm4OutTrig01 = 51|0x100U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN51 input. */
+ kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 52|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN52 input. */
+ kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 53|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN53 input. */
+ kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 54|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN54 input. */
+ kXBARA1_InputFlexpwm4Pwm4OutTrig01 = 55|0x100U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARA1_IN55 input. */
+ kXBARA1_InputPitTrigger0 = 56|0x100U, /**< PIT_TRIGGER0 output assigned to XBARA1_IN56 input. */
+ kXBARA1_InputPitTrigger1 = 57|0x100U, /**< PIT_TRIGGER1 output assigned to XBARA1_IN57 input. */
+ kXBARA1_InputPitTrigger2 = 58|0x100U, /**< PIT_TRIGGER2 output assigned to XBARA1_IN58 input. */
+ kXBARA1_InputPitTrigger3 = 59|0x100U, /**< PIT_TRIGGER3 output assigned to XBARA1_IN59 input. */
+ kXBARA1_InputEnc1PosMatch = 60|0x100U, /**< ENC1_POS_MATCH output assigned to XBARA1_IN60 input. */
+ kXBARA1_InputEnc2PosMatch = 61|0x100U, /**< ENC2_POS_MATCH output assigned to XBARA1_IN61 input. */
+ kXBARA1_InputEnc3PosMatch = 62|0x100U, /**< ENC3_POS_MATCH output assigned to XBARA1_IN62 input. */
+ kXBARA1_InputEnc4PosMatch = 63|0x100U, /**< ENC4_POS_MATCH output assigned to XBARA1_IN63 input. */
+ kXBARA1_InputDmaDone0 = 64|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN64 input. */
+ kXBARA1_InputDmaDone1 = 65|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN65 input. */
+ kXBARA1_InputDmaDone2 = 66|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN66 input. */
+ kXBARA1_InputDmaDone3 = 67|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN67 input. */
+ kXBARA1_InputDmaDone4 = 68|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN68 input. */
+ kXBARA1_InputDmaDone5 = 69|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN69 input. */
+ kXBARA1_InputDmaDone6 = 70|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN70 input. */
+ kXBARA1_InputDmaDone7 = 71|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN71 input. */
+ kXBARA1_InputAoi1Out0 = 72|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN72 input. */
+ kXBARA1_InputAoi1Out1 = 73|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN73 input. */
+ kXBARA1_InputAoi1Out2 = 74|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN74 input. */
+ kXBARA1_InputAoi1Out3 = 75|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN75 input. */
+ kXBARA1_InputAoi2Out0 = 76|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN76 input. */
+ kXBARA1_InputAoi2Out1 = 77|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN77 input. */
+ kXBARA1_InputAoi2Out2 = 78|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN78 input. */
+ kXBARA1_InputAoi2Out3 = 79|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN79 input. */
+ kXBARA1_InputAdcEtcXbar0Coco0 = 80|0x100U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARA1_IN80 input. */
+ kXBARA1_InputAdcEtcXbar0Coco1 = 81|0x100U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARA1_IN81 input. */
+ kXBARA1_InputAdcEtcXbar0Coco2 = 82|0x100U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARA1_IN82 input. */
+ kXBARA1_InputAdcEtcXbar0Coco3 = 83|0x100U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARA1_IN83 input. */
+ kXBARA1_InputAdcEtcXbar1Coco0 = 84|0x100U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARA1_IN84 input. */
+ kXBARA1_InputAdcEtcXbar1Coco1 = 85|0x100U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARA1_IN85 input. */
+ kXBARA1_InputAdcEtcXbar1Coco2 = 86|0x100U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARA1_IN86 input. */
+ kXBARA1_InputAdcEtcXbar1Coco3 = 87|0x100U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARA1_IN87 input. */
+ kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */
+ kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */
+ kXBARB2_InputRESERVED2 = 2|0x200U, /**< XBARB2_IN2 input is reserved. */
+ kXBARB2_InputRESERVED3 = 3|0x200U, /**< XBARB2_IN3 input is reserved. */
+ kXBARB2_InputRESERVED4 = 4|0x200U, /**< XBARB2_IN4 input is reserved. */
+ kXBARB2_InputRESERVED5 = 5|0x200U, /**< XBARB2_IN5 input is reserved. */
+ kXBARB2_InputAcmp1Out = 6|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN6 input. */
+ kXBARB2_InputAcmp2Out = 7|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN7 input. */
+ kXBARB2_InputAcmp3Out = 8|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN8 input. */
+ kXBARB2_InputAcmp4Out = 9|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN9 input. */
+ kXBARB2_InputRESERVED10 = 10|0x200U, /**< XBARB2_IN10 input is reserved. */
+ kXBARB2_InputRESERVED11 = 11|0x200U, /**< XBARB2_IN11 input is reserved. */
+ kXBARB2_InputQtimer3Tmr0Output = 12|0x200U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB2_IN12 input. */
+ kXBARB2_InputQtimer3Tmr1Output = 13|0x200U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB2_IN13 input. */
+ kXBARB2_InputQtimer3Tmr2Output = 14|0x200U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB2_IN14 input. */
+ kXBARB2_InputQtimer3Tmr3Output = 15|0x200U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB2_IN15 input. */
+ kXBARB2_InputQtimer4Tmr0Output = 16|0x200U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB2_IN16 input. */
+ kXBARB2_InputQtimer4Tmr1Output = 17|0x200U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB2_IN17 input. */
+ kXBARB2_InputQtimer4Tmr2Output = 18|0x200U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB2_IN18 input. */
+ kXBARB2_InputQtimer4Tmr3Output = 19|0x200U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB2_IN19 input. */
+ kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 20|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN20 input. */
+ kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 21|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN21 input. */
+ kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 22|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN22 input. */
+ kXBARB2_InputFlexpwm1Pwm4OutTrig01 = 23|0x200U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN23 input. */
+ kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 24|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN24 input. */
+ kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 25|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN25 input. */
+ kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 26|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN26 input. */
+ kXBARB2_InputFlexpwm2Pwm4OutTrig01 = 27|0x200U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN27 input. */
+ kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 28|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN28 input. */
+ kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 29|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN29 input. */
+ kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 30|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN30 input. */
+ kXBARB2_InputFlexpwm3Pwm4OutTrig01 = 31|0x200U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN31 input. */
+ kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 32|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN32 input. */
+ kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 33|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN33 input. */
+ kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 34|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
+ kXBARB2_InputFlexpwm4Pwm4OutTrig01 = 35|0x200U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
+ kXBARB2_InputPitTrigger0 = 36|0x200U, /**< PIT_TRIGGER0 output assigned to XBARB2_IN36 input. */
+ kXBARB2_InputPitTrigger1 = 37|0x200U, /**< PIT_TRIGGER1 output assigned to XBARB2_IN37 input. */
+ kXBARB2_InputAdcEtcXbar0Coco0 = 38|0x200U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB2_IN38 input. */
+ kXBARB2_InputAdcEtcXbar0Coco1 = 39|0x200U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB2_IN39 input. */
+ kXBARB2_InputAdcEtcXbar0Coco2 = 40|0x200U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB2_IN40 input. */
+ kXBARB2_InputAdcEtcXbar0Coco3 = 41|0x200U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB2_IN41 input. */
+ kXBARB2_InputAdcEtcXbar1Coco0 = 42|0x200U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB2_IN42 input. */
+ kXBARB2_InputAdcEtcXbar1Coco1 = 43|0x200U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB2_IN43 input. */
+ kXBARB2_InputAdcEtcXbar1Coco2 = 44|0x200U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB2_IN44 input. */
+ kXBARB2_InputAdcEtcXbar1Coco3 = 45|0x200U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB2_IN45 input. */
+ kXBARB2_InputEnc1PosMatch = 46|0x200U, /**< ENC1_POS_MATCH output assigned to XBARB2_IN46 input. */
+ kXBARB2_InputEnc2PosMatch = 47|0x200U, /**< ENC2_POS_MATCH output assigned to XBARB2_IN47 input. */
+ kXBARB2_InputEnc3PosMatch = 48|0x200U, /**< ENC3_POS_MATCH output assigned to XBARB2_IN48 input. */
+ kXBARB2_InputEnc4PosMatch = 49|0x200U, /**< ENC4_POS_MATCH output assigned to XBARB2_IN49 input. */
+ kXBARB2_InputDmaDone0 = 50|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN50 input. */
+ kXBARB2_InputDmaDone1 = 51|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN51 input. */
+ kXBARB2_InputDmaDone2 = 52|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN52 input. */
+ kXBARB2_InputDmaDone3 = 53|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN53 input. */
+ kXBARB2_InputDmaDone4 = 54|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN54 input. */
+ kXBARB2_InputDmaDone5 = 55|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN55 input. */
+ kXBARB2_InputDmaDone6 = 56|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN56 input. */
+ kXBARB2_InputDmaDone7 = 57|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN57 input. */
+ kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */
+ kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */
+ kXBARB3_InputRESERVED2 = 2|0x300U, /**< XBARB3_IN2 input is reserved. */
+ kXBARB3_InputRESERVED3 = 3|0x300U, /**< XBARB3_IN3 input is reserved. */
+ kXBARB3_InputRESERVED4 = 4|0x300U, /**< XBARB3_IN4 input is reserved. */
+ kXBARB3_InputRESERVED5 = 5|0x300U, /**< XBARB3_IN5 input is reserved. */
+ kXBARB3_InputAcmp1Out = 6|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN6 input. */
+ kXBARB3_InputAcmp2Out = 7|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN7 input. */
+ kXBARB3_InputAcmp3Out = 8|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN8 input. */
+ kXBARB3_InputAcmp4Out = 9|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN9 input. */
+ kXBARB3_InputRESERVED10 = 10|0x300U, /**< XBARB3_IN10 input is reserved. */
+ kXBARB3_InputRESERVED11 = 11|0x300U, /**< XBARB3_IN11 input is reserved. */
+ kXBARB3_InputQtimer3Tmr0Output = 12|0x300U, /**< QTIMER3_TMR0_OUTPUT output assigned to XBARB3_IN12 input. */
+ kXBARB3_InputQtimer3Tmr1Output = 13|0x300U, /**< QTIMER3_TMR1_OUTPUT output assigned to XBARB3_IN13 input. */
+ kXBARB3_InputQtimer3Tmr2Output = 14|0x300U, /**< QTIMER3_TMR2_OUTPUT output assigned to XBARB3_IN14 input. */
+ kXBARB3_InputQtimer3Tmr3Output = 15|0x300U, /**< QTIMER3_TMR3_OUTPUT output assigned to XBARB3_IN15 input. */
+ kXBARB3_InputQtimer4Tmr0Output = 16|0x300U, /**< QTIMER4_TMR0_OUTPUT output assigned to XBARB3_IN16 input. */
+ kXBARB3_InputQtimer4Tmr1Output = 17|0x300U, /**< QTIMER4_TMR1_OUTPUT output assigned to XBARB3_IN17 input. */
+ kXBARB3_InputQtimer4Tmr2Output = 18|0x300U, /**< QTIMER4_TMR2_OUTPUT output assigned to XBARB3_IN18 input. */
+ kXBARB3_InputQtimer4Tmr3Output = 19|0x300U, /**< QTIMER4_TMR3_OUTPUT output assigned to XBARB3_IN19 input. */
+ kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 20|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN20 input. */
+ kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 21|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN21 input. */
+ kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 22|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN22 input. */
+ kXBARB3_InputFlexpwm1Pwm4OutTrig01 = 23|0x300U, /**< FLEXPWM1_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN23 input. */
+ kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 24|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN24 input. */
+ kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 25|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN25 input. */
+ kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 26|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN26 input. */
+ kXBARB3_InputFlexpwm2Pwm4OutTrig01 = 27|0x300U, /**< FLEXPWM2_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN27 input. */
+ kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 28|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN28 input. */
+ kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 29|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN29 input. */
+ kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 30|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN30 input. */
+ kXBARB3_InputFlexpwm3Pwm4OutTrig01 = 31|0x300U, /**< FLEXPWM3_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN31 input. */
+ kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 32|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN32 input. */
+ kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 33|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN33 input. */
+ kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 34|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
+ kXBARB3_InputFlexpwm4Pwm4OutTrig01 = 35|0x300U, /**< FLEXPWM4_PWM4_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
+ kXBARB3_InputPitTrigger0 = 36|0x300U, /**< PIT_TRIGGER0 output assigned to XBARB3_IN36 input. */
+ kXBARB3_InputPitTrigger1 = 37|0x300U, /**< PIT_TRIGGER1 output assigned to XBARB3_IN37 input. */
+ kXBARB3_InputAdcEtcXbar0Coco0 = 38|0x300U, /**< ADC_ETC_XBAR0_COCO0 output assigned to XBARB3_IN38 input. */
+ kXBARB3_InputAdcEtcXbar0Coco1 = 39|0x300U, /**< ADC_ETC_XBAR0_COCO1 output assigned to XBARB3_IN39 input. */
+ kXBARB3_InputAdcEtcXbar0Coco2 = 40|0x300U, /**< ADC_ETC_XBAR0_COCO2 output assigned to XBARB3_IN40 input. */
+ kXBARB3_InputAdcEtcXbar0Coco3 = 41|0x300U, /**< ADC_ETC_XBAR0_COCO3 output assigned to XBARB3_IN41 input. */
+ kXBARB3_InputAdcEtcXbar1Coco0 = 42|0x300U, /**< ADC_ETC_XBAR1_COCO0 output assigned to XBARB3_IN42 input. */
+ kXBARB3_InputAdcEtcXbar1Coco1 = 43|0x300U, /**< ADC_ETC_XBAR1_COCO1 output assigned to XBARB3_IN43 input. */
+ kXBARB3_InputAdcEtcXbar1Coco2 = 44|0x300U, /**< ADC_ETC_XBAR1_COCO2 output assigned to XBARB3_IN44 input. */
+ kXBARB3_InputAdcEtcXbar1Coco3 = 45|0x300U, /**< ADC_ETC_XBAR1_COCO3 output assigned to XBARB3_IN45 input. */
+ kXBARB3_InputEnc1PosMatch = 46|0x300U, /**< ENC1_POS_MATCH output assigned to XBARB3_IN46 input. */
+ kXBARB3_InputEnc2PosMatch = 47|0x300U, /**< ENC2_POS_MATCH output assigned to XBARB3_IN47 input. */
+ kXBARB3_InputEnc3PosMatch = 48|0x300U, /**< ENC3_POS_MATCH output assigned to XBARB3_IN48 input. */
+ kXBARB3_InputEnc4PosMatch = 49|0x300U, /**< ENC4_POS_MATCH output assigned to XBARB3_IN49 input. */
+ kXBARB3_InputDmaDone0 = 50|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN50 input. */
+ kXBARB3_InputDmaDone1 = 51|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN51 input. */
+ kXBARB3_InputDmaDone2 = 52|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN52 input. */
+ kXBARB3_InputDmaDone3 = 53|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN53 input. */
+ kXBARB3_InputDmaDone4 = 54|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN54 input. */
+ kXBARB3_InputDmaDone5 = 55|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN55 input. */
+ kXBARB3_InputDmaDone6 = 56|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN56 input. */
+ kXBARB3_InputDmaDone7 = 57|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN57 input. */
+} xbar_input_signal_t;
+
+typedef enum _xbar_output_signal
+{
+ kXBARA1_OutputDmaChMuxReq30 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ30 */
+ kXBARA1_OutputDmaChMuxReq31 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ31 */
+ kXBARA1_OutputDmaChMuxReq94 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ94 */
+ kXBARA1_OutputDmaChMuxReq95 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ95 */
+ kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
+ kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
+ kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
+ kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
+ kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
+ kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
+ kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
+ kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
+ kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
+ kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
+ kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
+ kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
+ kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
+ kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
+ kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
+ kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
+ kXBARA1_OutputAcmp1Sample = 20|0x100U, /**< XBARA1_OUT20 output assigned to ACMP1_SAMPLE */
+ kXBARA1_OutputAcmp2Sample = 21|0x100U, /**< XBARA1_OUT21 output assigned to ACMP2_SAMPLE */
+ kXBARA1_OutputAcmp3Sample = 22|0x100U, /**< XBARA1_OUT22 output assigned to ACMP3_SAMPLE */
+ kXBARA1_OutputAcmp4Sample = 23|0x100U, /**< XBARA1_OUT23 output assigned to ACMP4_SAMPLE */
+ kXBARA1_OutputRESERVED24 = 24|0x100U, /**< XBARA1_OUT24 output is reserved. */
+ kXBARA1_OutputRESERVED25 = 25|0x100U, /**< XBARA1_OUT25 output is reserved. */
+ kXBARA1_OutputFlexpwm1Exta0 = 26|0x100U, /**< XBARA1_OUT26 output assigned to FLEXPWM1_EXTA0 */
+ kXBARA1_OutputFlexpwm1Exta1 = 27|0x100U, /**< XBARA1_OUT27 output assigned to FLEXPWM1_EXTA1 */
+ kXBARA1_OutputFlexpwm1Exta2 = 28|0x100U, /**< XBARA1_OUT28 output assigned to FLEXPWM1_EXTA2 */
+ kXBARA1_OutputFlexpwm1Exta3 = 29|0x100U, /**< XBARA1_OUT29 output assigned to FLEXPWM1_EXTA3 */
+ kXBARA1_OutputFlexpwm1ExtSync0 = 30|0x100U, /**< XBARA1_OUT30 output assigned to FLEXPWM1_EXT_SYNC0 */
+ kXBARA1_OutputFlexpwm1ExtSync1 = 31|0x100U, /**< XBARA1_OUT31 output assigned to FLEXPWM1_EXT_SYNC1 */
+ kXBARA1_OutputFlexpwm1ExtSync2 = 32|0x100U, /**< XBARA1_OUT32 output assigned to FLEXPWM1_EXT_SYNC2 */
+ kXBARA1_OutputFlexpwm1ExtSync3 = 33|0x100U, /**< XBARA1_OUT33 output assigned to FLEXPWM1_EXT_SYNC3 */
+ kXBARA1_OutputFlexpwm1ExtClk = 34|0x100U, /**< XBARA1_OUT34 output assigned to FLEXPWM1_EXT_CLK */
+ kXBARA1_OutputFlexpwm1Fault0 = 35|0x100U, /**< XBARA1_OUT35 output assigned to FLEXPWM1_FAULT0 */
+ kXBARA1_OutputFlexpwm1Fault1 = 36|0x100U, /**< XBARA1_OUT36 output assigned to FLEXPWM1_FAULT1 */
+ kXBARA1_OutputFlexpwm1234Fault2 = 37|0x100U, /**< XBARA1_OUT37 output assigned to FLEXPWM1_2_3_4_FAULT2 */
+ kXBARA1_OutputFlexpwm1234Fault3 = 38|0x100U, /**< XBARA1_OUT38 output assigned to FLEXPWM1_2_3_4_FAULT3 */
+ kXBARA1_OutputFlexpwm1ExtForce = 39|0x100U, /**< XBARA1_OUT39 output assigned to FLEXPWM1_EXT_FORCE */
+ kXBARA1_OutputFlexpwm234Exta0 = 40|0x100U, /**< XBARA1_OUT40 output assigned to FLEXPWM2_3_4_EXTA0 */
+ kXBARA1_OutputFlexpwm234Exta1 = 41|0x100U, /**< XBARA1_OUT41 output assigned to FLEXPWM2_3_4_EXTA1 */
+ kXBARA1_OutputFlexpwm234Exta2 = 42|0x100U, /**< XBARA1_OUT42 output assigned to FLEXPWM2_3_4_EXTA2 */
+ kXBARA1_OutputFlexpwm234Exta3 = 43|0x100U, /**< XBARA1_OUT43 output assigned to FLEXPWM2_3_4_EXTA3 */
+ kXBARA1_OutputFlexpwm2ExtSync0 = 44|0x100U, /**< XBARA1_OUT44 output assigned to FLEXPWM2_EXT_SYNC0 */
+ kXBARA1_OutputFlexpwm2ExtSync1 = 45|0x100U, /**< XBARA1_OUT45 output assigned to FLEXPWM2_EXT_SYNC1 */
+ kXBARA1_OutputFlexpwm2ExtSync2 = 46|0x100U, /**< XBARA1_OUT46 output assigned to FLEXPWM2_EXT_SYNC2 */
+ kXBARA1_OutputFlexpwm2ExtSync3 = 47|0x100U, /**< XBARA1_OUT47 output assigned to FLEXPWM2_EXT_SYNC3 */
+ kXBARA1_OutputFlexpwm234ExtClk = 48|0x100U, /**< XBARA1_OUT48 output assigned to FLEXPWM2_3_4_EXT_CLK */
+ kXBARA1_OutputFlexpwm2Fault0 = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM2_FAULT0 */
+ kXBARA1_OutputFlexpwm2Fault1 = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM2_FAULT1 */
+ kXBARA1_OutputFlexpwm2ExtForce = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM2_EXT_FORCE */
+ kXBARA1_OutputFlexpwm3ExtSync0 = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM3_EXT_SYNC0 */
+ kXBARA1_OutputFlexpwm3ExtSync1 = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM3_EXT_SYNC1 */
+ kXBARA1_OutputFlexpwm3ExtSync2 = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM3_EXT_SYNC2 */
+ kXBARA1_OutputFlexpwm3ExtSync3 = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM3_EXT_SYNC3 */
+ kXBARA1_OutputFlexpwm3Fault0 = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM3_FAULT0 */
+ kXBARA1_OutputFlexpwm3Fault1 = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM3_FAULT1 */
+ kXBARA1_OutputFlexpwm3ExtForce = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM3_EXT_FORCE */
+ kXBARA1_OutputFlexpwm4ExtSync0 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM4_EXT_SYNC0 */
+ kXBARA1_OutputFlexpwm4ExtSync1 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM4_EXT_SYNC1 */
+ kXBARA1_OutputFlexpwm4ExtSync2 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM4_EXT_SYNC2 */
+ kXBARA1_OutputFlexpwm4ExtSync3 = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM4_EXT_SYNC3 */
+ kXBARA1_OutputFlexpwm4Fault0 = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM4_FAULT0 */
+ kXBARA1_OutputFlexpwm4Fault1 = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM4_FAULT1 */
+ kXBARA1_OutputFlexpwm4ExtForce = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM4_EXT_FORCE */
+ kXBARA1_OutputEnc1PhaseAInput = 66|0x100U, /**< XBARA1_OUT66 output assigned to ENC1_PHASE_A_INPUT */
+ kXBARA1_OutputEnc1PhaseBInput = 67|0x100U, /**< XBARA1_OUT67 output assigned to ENC1_PHASE_B_INPUT */
+ kXBARA1_OutputEnc1Index = 68|0x100U, /**< XBARA1_OUT68 output assigned to ENC1_INDEX */
+ kXBARA1_OutputEnc1Home = 69|0x100U, /**< XBARA1_OUT69 output assigned to ENC1_HOME */
+ kXBARA1_OutputEnc1Trigger = 70|0x100U, /**< XBARA1_OUT70 output assigned to ENC1_TRIGGER */
+ kXBARA1_OutputEnc2PhaseAInput = 71|0x100U, /**< XBARA1_OUT71 output assigned to ENC2_PHASE_A_INPUT */
+ kXBARA1_OutputEnc2PhaseBInput = 72|0x100U, /**< XBARA1_OUT72 output assigned to ENC2_PHASE_B_INPUT */
+ kXBARA1_OutputEnc2Index = 73|0x100U, /**< XBARA1_OUT73 output assigned to ENC2_INDEX */
+ kXBARA1_OutputEnc2Home = 74|0x100U, /**< XBARA1_OUT74 output assigned to ENC2_HOME */
+ kXBARA1_OutputEnc2Trigger = 75|0x100U, /**< XBARA1_OUT75 output assigned to ENC2_TRIGGER */
+ kXBARA1_OutputEnc3PhaseAInput = 76|0x100U, /**< XBARA1_OUT76 output assigned to ENC3_PHASE_A_INPUT */
+ kXBARA1_OutputEnc3PhaseBInput = 77|0x100U, /**< XBARA1_OUT77 output assigned to ENC3_PHASE_B_INPUT */
+ kXBARA1_OutputEnc3Index = 78|0x100U, /**< XBARA1_OUT78 output assigned to ENC3_INDEX */
+ kXBARA1_OutputEnc3Home = 79|0x100U, /**< XBARA1_OUT79 output assigned to ENC3_HOME */
+ kXBARA1_OutputEnc3Trigger = 80|0x100U, /**< XBARA1_OUT80 output assigned to ENC3_TRIGGER */
+ kXBARA1_OutputEnc4PhaseAInput = 81|0x100U, /**< XBARA1_OUT81 output assigned to ENC4_PHASE_A_INPUT */
+ kXBARA1_OutputEnc4PhaseBInput = 82|0x100U, /**< XBARA1_OUT82 output assigned to ENC4_PHASE_B_INPUT */
+ kXBARA1_OutputEnc4Index = 83|0x100U, /**< XBARA1_OUT83 output assigned to ENC4_INDEX */
+ kXBARA1_OutputEnc4Home = 84|0x100U, /**< XBARA1_OUT84 output assigned to ENC4_HOME */
+ kXBARA1_OutputEnc4Trigger = 85|0x100U, /**< XBARA1_OUT85 output assigned to ENC4_TRIGGER */
+ kXBARA1_OutputQtimer1Tmr0Input = 86|0x100U, /**< XBARA1_OUT86 output assigned to QTIMER1_TMR0_INPUT */
+ kXBARA1_OutputQtimer1Tmr1Input = 87|0x100U, /**< XBARA1_OUT87 output assigned to QTIMER1_TMR1_INPUT */
+ kXBARA1_OutputQtimer1Tmr2Input = 88|0x100U, /**< XBARA1_OUT88 output assigned to QTIMER1_TMR2_INPUT */
+ kXBARA1_OutputQtimer1Tmr3Input = 89|0x100U, /**< XBARA1_OUT89 output assigned to QTIMER1_TMR3_INPUT */
+ kXBARA1_OutputQtimer2Tmr0Input = 90|0x100U, /**< XBARA1_OUT90 output assigned to QTIMER2_TMR0_INPUT */
+ kXBARA1_OutputQtimer2Tmr1Input = 91|0x100U, /**< XBARA1_OUT91 output assigned to QTIMER2_TMR1_INPUT */
+ kXBARA1_OutputQtimer2Tmr2Input = 92|0x100U, /**< XBARA1_OUT92 output assigned to QTIMER2_TMR2_INPUT */
+ kXBARA1_OutputQtimer2Tmr3Input = 93|0x100U, /**< XBARA1_OUT93 output assigned to QTIMER2_TMR3_INPUT */
+ kXBARA1_OutputQtimer3Tmr0Input = 94|0x100U, /**< XBARA1_OUT94 output assigned to QTIMER3_TMR0_INPUT */
+ kXBARA1_OutputQtimer3Tmr1Input = 95|0x100U, /**< XBARA1_OUT95 output assigned to QTIMER3_TMR1_INPUT */
+ kXBARA1_OutputQtimer3Tmr2Input = 96|0x100U, /**< XBARA1_OUT96 output assigned to QTIMER3_TMR2_INPUT */
+ kXBARA1_OutputQtimer3Tmr3Input = 97|0x100U, /**< XBARA1_OUT97 output assigned to QTIMER3_TMR3_INPUT */
+ kXBARA1_OutputQtimer4Tmr0Input = 98|0x100U, /**< XBARA1_OUT98 output assigned to QTIMER4_TMR0_INPUT */
+ kXBARA1_OutputQtimer4Tmr1Input = 99|0x100U, /**< XBARA1_OUT99 output assigned to QTIMER4_TMR1_INPUT */
+ kXBARA1_OutputQtimer4Tmr2Input = 100|0x100U, /**< XBARA1_OUT100 output assigned to QTIMER4_TMR2_INPUT */
+ kXBARA1_OutputQtimer4Tmr3Input = 101|0x100U, /**< XBARA1_OUT101 output assigned to QTIMER4_TMR3_INPUT */
+ kXBARA1_OutputEwmEwmIn = 102|0x100U, /**< XBARA1_OUT102 output assigned to EWM_EWM_IN */
+ kXBARA1_OutputAdcEtcXbar0Trig0 = 103|0x100U, /**< XBARA1_OUT103 output assigned to ADC_ETC_XBAR0_TRIG0 */
+ kXBARA1_OutputAdcEtcXbar0Trig1 = 104|0x100U, /**< XBARA1_OUT104 output assigned to ADC_ETC_XBAR0_TRIG1 */
+ kXBARA1_OutputAdcEtcXbar0Trig2 = 105|0x100U, /**< XBARA1_OUT105 output assigned to ADC_ETC_XBAR0_TRIG2 */
+ kXBARA1_OutputAdcEtcXbar0Trig3 = 106|0x100U, /**< XBARA1_OUT106 output assigned to ADC_ETC_XBAR0_TRIG3 */
+ kXBARA1_OutputAdcEtcXbar1Trig0 = 107|0x100U, /**< XBARA1_OUT107 output assigned to ADC_ETC_XBAR1_TRIG0 */
+ kXBARA1_OutputAdcEtcXbar1Trig1 = 108|0x100U, /**< XBARA1_OUT108 output assigned to ADC_ETC_XBAR1_TRIG1 */
+ kXBARA1_OutputAdcEtcXbar1Trig2 = 109|0x100U, /**< XBARA1_OUT109 output assigned to ADC_ETC_XBAR1_TRIG2 */
+ kXBARA1_OutputAdcEtcXbar1Trig3 = 110|0x100U, /**< XBARA1_OUT110 output assigned to ADC_ETC_XBAR1_TRIG3 */
+ kXBARA1_OutputLpi2c1TrgInput = 111|0x100U, /**< XBARA1_OUT111 output assigned to LPI2C1_TRG_INPUT */
+ kXBARA1_OutputLpi2c2TrgInput = 112|0x100U, /**< XBARA1_OUT112 output assigned to LPI2C2_TRG_INPUT */
+ kXBARA1_OutputLpi2c3TrgInput = 113|0x100U, /**< XBARA1_OUT113 output assigned to LPI2C3_TRG_INPUT */
+ kXBARA1_OutputLpi2c4TrgInput = 114|0x100U, /**< XBARA1_OUT114 output assigned to LPI2C4_TRG_INPUT */
+ kXBARA1_OutputLpspi1TrgInput = 115|0x100U, /**< XBARA1_OUT115 output assigned to LPSPI1_TRG_INPUT */
+ kXBARA1_OutputLpspi2TrgInput = 116|0x100U, /**< XBARA1_OUT116 output assigned to LPSPI2_TRG_INPUT */
+ kXBARA1_OutputLpspi3TrgInput = 117|0x100U, /**< XBARA1_OUT117 output assigned to LPSPI3_TRG_INPUT */
+ kXBARA1_OutputLpspi4TrgInput = 118|0x100U, /**< XBARA1_OUT118 output assigned to LPSPI4_TRG_INPUT */
+ kXBARA1_OutputLpuart1TrgInput = 119|0x100U, /**< XBARA1_OUT119 output assigned to LPUART1_TRG_INPUT */
+ kXBARA1_OutputLpuart2TrgInput = 120|0x100U, /**< XBARA1_OUT120 output assigned to LPUART2_TRG_INPUT */
+ kXBARA1_OutputLpuart3TrgInput = 121|0x100U, /**< XBARA1_OUT121 output assigned to LPUART3_TRG_INPUT */
+ kXBARA1_OutputLpuart4TrgInput = 122|0x100U, /**< XBARA1_OUT122 output assigned to LPUART4_TRG_INPUT */
+ kXBARA1_OutputLpuart5TrgInput = 123|0x100U, /**< XBARA1_OUT123 output assigned to LPUART5_TRG_INPUT */
+ kXBARA1_OutputLpuart6TrgInput = 124|0x100U, /**< XBARA1_OUT124 output assigned to LPUART6_TRG_INPUT */
+ kXBARA1_OutputLpuart7TrgInput = 125|0x100U, /**< XBARA1_OUT125 output assigned to LPUART7_TRG_INPUT */
+ kXBARA1_OutputLpuart8TrgInput = 126|0x100U, /**< XBARA1_OUT126 output assigned to LPUART8_TRG_INPUT */
+ kXBARA1_OutputFlexio1TriggerIn0 = 127|0x100U, /**< XBARA1_OUT127 output assigned to FLEXIO1_TRIGGER_IN0 */
+ kXBARA1_OutputFlexio1TriggerIn1 = 128|0x100U, /**< XBARA1_OUT128 output assigned to FLEXIO1_TRIGGER_IN1 */
+ kXBARA1_OutputFlexio2TriggerIn0 = 129|0x100U, /**< XBARA1_OUT129 output assigned to FLEXIO2_TRIGGER_IN0 */
+ kXBARA1_OutputFlexio2TriggerIn1 = 130|0x100U, /**< XBARA1_OUT130 output assigned to FLEXIO2_TRIGGER_IN1 */
+ kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */
+ kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */
+ kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */
+ kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */
+ kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */
+ kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */
+ kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */
+ kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */
+ kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */
+ kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */
+ kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */
+ kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */
+ kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */
+ kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */
+ kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */
+ kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */
+ kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */
+ kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */
+ kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */
+ kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */
+ kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */
+ kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */
+ kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */
+ kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */
+ kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */
+ kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */
+ kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */
+ kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */
+ kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */
+ kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */
+ kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */
+ kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */
+} xbar_output_signal_t;
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang diagnostic push
+ #else
+ #pragma push
+ #pragma anon_unions
+ #endif
+#elif defined(__CWCC__)
+ #pragma push
+ #pragma cpp_extensions on
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t HC[8]; /**< Control register for hardware triggers, array offset: 0x0, array step: 0x4 */
+ __I uint32_t HS; /**< Status register for HW triggers, offset: 0x20 */
+ __I uint32_t R[8]; /**< Data result register for HW triggers, array offset: 0x24, array step: 0x4 */
+ __IO uint32_t CFG; /**< Configuration register, offset: 0x44 */
+ __IO uint32_t GC; /**< General control register, offset: 0x48 */
+ __IO uint32_t GS; /**< General status register, offset: 0x4C */
+ __IO uint32_t CV; /**< Compare value register, offset: 0x50 */
+ __IO uint32_t OFS; /**< Offset correction value register, offset: 0x54 */
+ __IO uint32_t CAL; /**< Calibration value register, offset: 0x58 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name HC - Control register for hardware triggers */
+/*! @{ */
+#define ADC_HC_ADCH_MASK (0x1FU)
+#define ADC_HC_ADCH_SHIFT (0U)
+/*! ADCH - Input Channel Select
+ * 0b10000..External channel selection from ADC_ETC
+ * 0b11000..Reserved.
+ * 0b11001..VREFSH = internal channel, for ADC self-test, hard connected to VRH internally
+ * 0b11010..Reserved.
+ * 0b11011..Reserved.
+ * 0b11111..Conversion Disabled. Hardware Triggers will not initiate any conversion.
+ */
+#define ADC_HC_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_ADCH_SHIFT)) & ADC_HC_ADCH_MASK)
+#define ADC_HC_AIEN_MASK (0x80U)
+#define ADC_HC_AIEN_SHIFT (7U)
+/*! AIEN - Conversion Complete Interrupt Enable/Disable Control
+ * 0b1..Conversion complete interrupt enabled
+ * 0b0..Conversion complete interrupt disabled
+ */
+#define ADC_HC_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_HC_AIEN_SHIFT)) & ADC_HC_AIEN_MASK)
+/*! @} */
+
+/* The count of ADC_HC */
+#define ADC_HC_COUNT (8U)
+
+/*! @name HS - Status register for HW triggers */
+/*! @{ */
+#define ADC_HS_COCO0_MASK (0x1U)
+#define ADC_HS_COCO0_SHIFT (0U)
+/*! COCO0 - Conversion Complete Flag
+ */
+#define ADC_HS_COCO0(x) (((uint32_t)(((uint32_t)(x)) << ADC_HS_COCO0_SHIFT)) & ADC_HS_COCO0_MASK)
+/*! @} */
+
+/*! @name R - Data result register for HW triggers */
+/*! @{ */
+#define ADC_R_CDATA_MASK (0xFFFU)
+#define ADC_R_CDATA_SHIFT (0U)
+/*! CDATA - Data (result of an ADC conversion)
+ */
+#define ADC_R_CDATA(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_CDATA_SHIFT)) & ADC_R_CDATA_MASK)
+/*! @} */
+
+/* The count of ADC_R */
+#define ADC_R_COUNT (8U)
+
+/*! @name CFG - Configuration register */
+/*! @{ */
+#define ADC_CFG_ADICLK_MASK (0x3U)
+#define ADC_CFG_ADICLK_SHIFT (0U)
+/*! ADICLK - Input Clock Select
+ * 0b00..IPG clock
+ * 0b01..IPG clock divided by 2
+ * 0b10..Reserved
+ * 0b11..Asynchronous clock (ADACK)
+ */
+#define ADC_CFG_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADICLK_SHIFT)) & ADC_CFG_ADICLK_MASK)
+#define ADC_CFG_MODE_MASK (0xCU)
+#define ADC_CFG_MODE_SHIFT (2U)
+/*! MODE - Conversion Mode Selection
+ * 0b00..8-bit conversion
+ * 0b01..10-bit conversion
+ * 0b10..12-bit conversion
+ * 0b11..Reserved
+ */
+#define ADC_CFG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_MODE_SHIFT)) & ADC_CFG_MODE_MASK)
+#define ADC_CFG_ADLSMP_MASK (0x10U)
+#define ADC_CFG_ADLSMP_SHIFT (4U)
+/*! ADLSMP - Long Sample Time Configuration
+ * 0b0..Short sample mode.
+ * 0b1..Long sample mode.
+ */
+#define ADC_CFG_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLSMP_SHIFT)) & ADC_CFG_ADLSMP_MASK)
+#define ADC_CFG_ADIV_MASK (0x60U)
+#define ADC_CFG_ADIV_SHIFT (5U)
+/*! ADIV - Clock Divide Select
+ * 0b00..Input clock
+ * 0b01..Input clock / 2
+ * 0b10..Input clock / 4
+ * 0b11..Input clock / 8
+ */
+#define ADC_CFG_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADIV_SHIFT)) & ADC_CFG_ADIV_MASK)
+#define ADC_CFG_ADLPC_MASK (0x80U)
+#define ADC_CFG_ADLPC_SHIFT (7U)
+/*! ADLPC - Low-Power Configuration
+ * 0b0..ADC hard block not in low power mode.
+ * 0b1..ADC hard block in low power mode.
+ */
+#define ADC_CFG_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADLPC_SHIFT)) & ADC_CFG_ADLPC_MASK)
+#define ADC_CFG_ADSTS_MASK (0x300U)
+#define ADC_CFG_ADSTS_SHIFT (8U)
+/*! ADSTS
+ * 0b00..Sample period (ADC clocks) = 2 if ADLSMP=0b Sample period (ADC clocks) = 12 if ADLSMP=1b
+ * 0b01..Sample period (ADC clocks) = 4 if ADLSMP=0b Sample period (ADC clocks) = 16 if ADLSMP=1b
+ * 0b10..Sample period (ADC clocks) = 6 if ADLSMP=0b Sample period (ADC clocks) = 20 if ADLSMP=1b
+ * 0b11..Sample period (ADC clocks) = 8 if ADLSMP=0b Sample period (ADC clocks) = 24 if ADLSMP=1b
+ */
+#define ADC_CFG_ADSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADSTS_SHIFT)) & ADC_CFG_ADSTS_MASK)
+#define ADC_CFG_ADHSC_MASK (0x400U)
+#define ADC_CFG_ADHSC_SHIFT (10U)
+/*! ADHSC - High Speed Configuration
+ * 0b0..Normal conversion selected.
+ * 0b1..High speed conversion selected.
+ */
+#define ADC_CFG_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADHSC_SHIFT)) & ADC_CFG_ADHSC_MASK)
+#define ADC_CFG_REFSEL_MASK (0x1800U)
+#define ADC_CFG_REFSEL_SHIFT (11U)
+/*! REFSEL - Voltage Reference Selection
+ * 0b00..Selects VREFH/VREFL as reference voltage.
+ * 0b01..Reserved
+ * 0b10..Reserved
+ * 0b11..Reserved
+ */
+#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
+#define ADC_CFG_ADTRG_MASK (0x2000U)
+#define ADC_CFG_ADTRG_SHIFT (13U)
+/*! ADTRG - Conversion Trigger Select
+ * 0b0..Software trigger selected
+ * 0b1..Hardware trigger selected
+ */
+#define ADC_CFG_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_ADTRG_SHIFT)) & ADC_CFG_ADTRG_MASK)
+#define ADC_CFG_AVGS_MASK (0xC000U)
+#define ADC_CFG_AVGS_SHIFT (14U)
+/*! AVGS - Hardware Average select
+ * 0b00..4 samples averaged
+ * 0b01..8 samples averaged
+ * 0b10..16 samples averaged
+ * 0b11..32 samples averaged
+ */
+#define ADC_CFG_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_AVGS_SHIFT)) & ADC_CFG_AVGS_MASK)
+#define ADC_CFG_OVWREN_MASK (0x10000U)
+#define ADC_CFG_OVWREN_SHIFT (16U)
+/*! OVWREN - Data Overwrite Enable
+ * 0b1..Enable the overwriting.
+ * 0b0..Disable the overwriting. Existing Data in Data result register will not be overwritten by subsequent converted data.
+ */
+#define ADC_CFG_OVWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_OVWREN_SHIFT)) & ADC_CFG_OVWREN_MASK)
+/*! @} */
+
+/*! @name GC - General control register */
+/*! @{ */
+#define ADC_GC_ADACKEN_MASK (0x1U)
+#define ADC_GC_ADACKEN_SHIFT (0U)
+/*! ADACKEN - Asynchronous clock output enable
+ * 0b0..Asynchronous clock output disabled; Asynchronous clock only enabled if selected by ADICLK and a conversion is active.
+ * 0b1..Asynchronous clock and clock output enabled regardless of the state of the ADC
+ */
+#define ADC_GC_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADACKEN_SHIFT)) & ADC_GC_ADACKEN_MASK)
+#define ADC_GC_DMAEN_MASK (0x2U)
+#define ADC_GC_DMAEN_SHIFT (1U)
+/*! DMAEN - DMA Enable
+ * 0b0..DMA disabled (default)
+ * 0b1..DMA enabled
+ */
+#define ADC_GC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_DMAEN_SHIFT)) & ADC_GC_DMAEN_MASK)
+#define ADC_GC_ACREN_MASK (0x4U)
+#define ADC_GC_ACREN_SHIFT (2U)
+/*! ACREN - Compare Function Range Enable
+ * 0b0..Range function disabled. Only the compare value 1 of ADC_CV register (CV1) is compared.
+ * 0b1..Range function enabled. Both compare values of ADC_CV registers (CV1 and CV2) are compared.
+ */
+#define ADC_GC_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACREN_SHIFT)) & ADC_GC_ACREN_MASK)
+#define ADC_GC_ACFGT_MASK (0x8U)
+#define ADC_GC_ACFGT_SHIFT (3U)
+/*! ACFGT - Compare Function Greater Than Enable
+ * 0b0..Configures "Less Than Threshold, Outside Range Not Inclusive and Inside Range Not Inclusive"
+ * functionality based on the values placed in the ADC_CV register.
+ * 0b1..Configures "Greater Than Or Equal To Threshold, Outside Range Inclusive and Inside Range Inclusive"
+ * functionality based on the values placed in the ADC_CV registers.
+ */
+#define ADC_GC_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFGT_SHIFT)) & ADC_GC_ACFGT_MASK)
+#define ADC_GC_ACFE_MASK (0x10U)
+#define ADC_GC_ACFE_SHIFT (4U)
+/*! ACFE - Compare Function Enable
+ * 0b0..Compare function disabled
+ * 0b1..Compare function enabled
+ */
+#define ADC_GC_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ACFE_SHIFT)) & ADC_GC_ACFE_MASK)
+#define ADC_GC_AVGE_MASK (0x20U)
+#define ADC_GC_AVGE_SHIFT (5U)
+/*! AVGE - Hardware average enable
+ * 0b0..Hardware average function disabled
+ * 0b1..Hardware average function enabled
+ */
+#define ADC_GC_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_AVGE_SHIFT)) & ADC_GC_AVGE_MASK)
+#define ADC_GC_ADCO_MASK (0x40U)
+#define ADC_GC_ADCO_SHIFT (6U)
+/*! ADCO - Continuous Conversion Enable
+ * 0b0..One conversion or one set of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
+ * 0b1..Continuous conversions or sets of conversions if the hardware average function is enabled (AVGE=1) after initiating a conversion.
+ */
+#define ADC_GC_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_ADCO_SHIFT)) & ADC_GC_ADCO_MASK)
+#define ADC_GC_CAL_MASK (0x80U)
+#define ADC_GC_CAL_SHIFT (7U)
+/*! CAL - Calibration
+ */
+#define ADC_GC_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_GC_CAL_SHIFT)) & ADC_GC_CAL_MASK)
+/*! @} */
+
+/*! @name GS - General status register */
+/*! @{ */
+#define ADC_GS_ADACT_MASK (0x1U)
+#define ADC_GS_ADACT_SHIFT (0U)
+/*! ADACT - Conversion Active
+ * 0b0..Conversion not in progress.
+ * 0b1..Conversion in progress.
+ */
+#define ADC_GS_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_ADACT_SHIFT)) & ADC_GS_ADACT_MASK)
+#define ADC_GS_CALF_MASK (0x2U)
+#define ADC_GS_CALF_SHIFT (1U)
+/*! CALF - Calibration Failed Flag
+ * 0b0..Calibration completed normally.
+ * 0b1..Calibration failed. ADC accuracy specifications are not guaranteed.
+ */
+#define ADC_GS_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_CALF_SHIFT)) & ADC_GS_CALF_MASK)
+#define ADC_GS_AWKST_MASK (0x4U)
+#define ADC_GS_AWKST_SHIFT (2U)
+/*! AWKST - Asynchronous wakeup interrupt status
+ * 0b1..Asynchronous wake up interrupt occurred in stop mode.
+ * 0b0..No asynchronous interrupt.
+ */
+#define ADC_GS_AWKST(x) (((uint32_t)(((uint32_t)(x)) << ADC_GS_AWKST_SHIFT)) & ADC_GS_AWKST_MASK)
+/*! @} */
+
+/*! @name CV - Compare value register */
+/*! @{ */
+#define ADC_CV_CV1_MASK (0xFFFU)
+#define ADC_CV_CV1_SHIFT (0U)
+/*! CV1 - Compare Value 1
+ */
+#define ADC_CV_CV1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV1_SHIFT)) & ADC_CV_CV1_MASK)
+#define ADC_CV_CV2_MASK (0xFFF0000U)
+#define ADC_CV_CV2_SHIFT (16U)
+/*! CV2 - Compare Value 2
+ */
+#define ADC_CV_CV2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CV2_SHIFT)) & ADC_CV_CV2_MASK)
+/*! @} */
+
+/*! @name OFS - Offset correction value register */
+/*! @{ */
+#define ADC_OFS_OFS_MASK (0xFFFU)
+#define ADC_OFS_OFS_SHIFT (0U)
+/*! OFS - Offset value
+ */
+#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+#define ADC_OFS_SIGN_MASK (0x1000U)
+#define ADC_OFS_SIGN_SHIFT (12U)
+/*! SIGN - Sign bit
+ * 0b0..The offset value is added with the raw result
+ * 0b1..The offset value is subtracted from the raw converted value
+ */
+#define ADC_OFS_SIGN(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_SIGN_SHIFT)) & ADC_OFS_SIGN_MASK)
+/*! @} */
+
+/*! @name CAL - Calibration value register */
+/*! @{ */
+#define ADC_CAL_CAL_CODE_MASK (0xFU)
+#define ADC_CAL_CAL_CODE_SHIFT (0U)
+/*! CAL_CODE - Calibration Result Value
+ */
+#define ADC_CAL_CAL_CODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CAL_CAL_CODE_SHIFT)) & ADC_CAL_CAL_CODE_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC1 base address */
+#define ADC1_BASE (0x400C4000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1 ((ADC_Type *)ADC1_BASE)
+/** Peripheral ADC2 base address */
+#define ADC2_BASE (0x400C8000u)
+/** Peripheral ADC2 base pointer */
+#define ADC2 ((ADC_Type *)ADC2_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { 0u, ADC1_BASE, ADC2_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { (ADC_Type *)0u, ADC1, ADC2 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ADC_ETC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC_ETC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */
+ __IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
+ __IO uint32_t DONE2_ERR_IRQ; /**< ETC DONE_2 and DONE_ERR IRQ State Register, offset: 0x8 */
+ __IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */
+ struct { /* offset: 0x10, array step: 0x28 */
+ __IO uint32_t TRIGn_CTRL; /**< ETC_TRIG0 Control Register..ETC_TRIG7 Control Register, array offset: 0x10, array step: 0x28 */
+ __IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register, array offset: 0x14, array step: 0x28 */
+ __IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
+ __IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
+ __IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
+ __IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
+ __I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
+ __I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
+ __I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
+ __I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
+ } TRIG[8];
+} ADC_ETC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC_ETC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - ADC_ETC Global Control Register */
+/*! @{ */
+#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
+#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
+#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
+#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK (0x100U)
+#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT (8U)
+#define ADC_ETC_CTRL_EXT0_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_ENABLE_MASK)
+#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK (0xE00U)
+#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT (9U)
+#define ADC_ETC_CTRL_EXT0_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT0_TRIG_PRIORITY_MASK)
+#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK (0x1000U)
+#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT (12U)
+#define ADC_ETC_CTRL_EXT1_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_ENABLE_MASK)
+#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK (0xE000U)
+#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT (13U)
+#define ADC_ETC_CTRL_EXT1_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_SHIFT)) & ADC_ETC_CTRL_EXT1_TRIG_PRIORITY_MASK)
+#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
+#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
+#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
+#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
+#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
+#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
+#define ADC_ETC_CTRL_TSC_BYPASS_MASK (0x40000000U)
+#define ADC_ETC_CTRL_TSC_BYPASS_SHIFT (30U)
+#define ADC_ETC_CTRL_TSC_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TSC_BYPASS_SHIFT)) & ADC_ETC_CTRL_TSC_BYPASS_MASK)
+#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
+#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
+#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
+/*! @} */
+
+/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
+/*! @{ */
+#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
+#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
+#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
+/*! @} */
+
+/*! @name DONE2_ERR_IRQ - ETC DONE_2 and DONE_ERR IRQ State Register */
+/*! @{ */
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_DONE2_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_DONE2_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_DONE2_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_DONE2_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_DONE2_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_DONE2_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_DONE2_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_DONE2_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG0_ERR_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG1_ERR_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG2_ERR_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG3_ERR_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG4_ERR_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG5_ERR_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG6_ERR_MASK)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
+#define ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_ERR_IRQ_TRIG7_ERR_MASK)
+/*! @} */
+
+/*! @name DMA_CTRL - ETC DMA control Register */
+/*! @{ */
+#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
+#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
+#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
+#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
+#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
+#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
+#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
+#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
+#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
+#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
+#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
+#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
+#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
+#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
+#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
+#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
+#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
+#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
+#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
+#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
+#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
+#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
+#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
+#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
+#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
+#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
+#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
+#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
+#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
+#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
+#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
+#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
+#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
+#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
+/*! @} */
+
+/*! @name TRIGn_CTRL - ETC_TRIG0 Control Register..ETC_TRIG7 Control Register */
+/*! @{ */
+#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
+#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
+#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
+#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
+#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
+#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
+#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
+#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
+#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
+#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
+#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
+#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
+#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
+#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
+#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
+/*! @} */
+
+/* The count of ADC_ETC_TRIGn_CTRL */
+#define ADC_ETC_TRIGn_CTRL_COUNT (8U)
+
+/*! @name TRIGn_COUNTER - ETC_TRIG0 Counter Register..ETC_TRIG7 Counter Register */
+/*! @{ */
+#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
+#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
+#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
+#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
+#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
+#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
+/*! @} */
+
+/* The count of ADC_ETC_TRIGn_COUNTER */
+#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
+
+/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
+/*! @{ */
+#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
+#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
+#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
+#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
+#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
+#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
+#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
+#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
+#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
+#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
+/*! @} */
+
+/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
+#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
+
+/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
+/*! @{ */
+#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
+#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
+#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
+#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
+#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
+#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
+#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
+#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
+#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
+#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
+/*! @} */
+
+/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
+#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
+
+/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
+/*! @{ */
+#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
+#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
+#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
+#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
+#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
+#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
+#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
+#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
+#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
+#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
+/*! @} */
+
+/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
+#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
+
+/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
+/*! @{ */
+#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
+#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
+#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
+#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
+#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
+#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
+#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
+#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
+#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
+#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
+/*! @} */
+
+/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
+#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
+
+/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
+/*! @{ */
+#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
+#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
+#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
+#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
+#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
+#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
+/*! @} */
+
+/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
+#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
+
+/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
+/*! @{ */
+#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
+#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
+#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
+#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
+#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
+#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
+/*! @} */
+
+/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
+#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
+
+/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
+/*! @{ */
+#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
+#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
+#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
+#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
+#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
+#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
+/*! @} */
+
+/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
+#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
+
+/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
+/*! @{ */
+#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
+#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
+#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
+#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
+#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
+#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
+/*! @} */
+
+/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
+#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_ETC_Register_Masks */
+
+
+/* ADC_ETC - Peripheral instance base addresses */
+/** Peripheral ADC_ETC base address */
+#define ADC_ETC_BASE (0x403B0000u)
+/** Peripheral ADC_ETC base pointer */
+#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
+/** Array initializer of ADC_ETC peripheral base addresses */
+#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
+/** Array initializer of ADC_ETC peripheral base pointers */
+#define ADC_ETC_BASE_PTRS { ADC_ETC }
+/** Interrupt vectors for the ADC_ETC peripheral type */
+#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn } }
+#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_ETC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AIPSTZ Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPSTZ_Peripheral_Access_Layer AIPSTZ Peripheral Access Layer
+ * @{
+ */
+
+/** AIPSTZ - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MPR; /**< Master Priviledge Registers, offset: 0x0 */
+ uint8_t RESERVED_0[60];
+ __IO uint32_t OPACR; /**< Off-Platform Peripheral Access Control Registers, offset: 0x40 */
+ __IO uint32_t OPACR1; /**< Off-Platform Peripheral Access Control Registers, offset: 0x44 */
+ __IO uint32_t OPACR2; /**< Off-Platform Peripheral Access Control Registers, offset: 0x48 */
+ __IO uint32_t OPACR3; /**< Off-Platform Peripheral Access Control Registers, offset: 0x4C */
+ __IO uint32_t OPACR4; /**< Off-Platform Peripheral Access Control Registers, offset: 0x50 */
+} AIPSTZ_Type;
+
+/* ----------------------------------------------------------------------------
+ -- AIPSTZ Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPSTZ_Register_Masks AIPSTZ Register Masks
+ * @{
+ */
+
+/*! @name MPR - Master Priviledge Registers */
+/*! @{ */
+#define AIPSTZ_MPR_MPROT5_MASK (0xF00U)
+#define AIPSTZ_MPR_MPROT5_SHIFT (8U)
+/*! MPROT5
+ * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ * 0bxx0x..This master is not trusted for write accesses.
+ * 0bxx1x..This master is trusted for write accesses.
+ * 0bx0xx..This master is not trusted for read accesses.
+ * 0bx1xx..This master is trusted for read accesses.
+ * 0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT5_SHIFT)) & AIPSTZ_MPR_MPROT5_MASK)
+#define AIPSTZ_MPR_MPROT3_MASK (0xF0000U)
+#define AIPSTZ_MPR_MPROT3_SHIFT (16U)
+/*! MPROT3
+ * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ * 0bxx0x..This master is not trusted for write accesses.
+ * 0bxx1x..This master is trusted for write accesses.
+ * 0bx0xx..This master is not trusted for read accesses.
+ * 0bx1xx..This master is trusted for read accesses.
+ * 0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT3_SHIFT)) & AIPSTZ_MPR_MPROT3_MASK)
+#define AIPSTZ_MPR_MPROT2_MASK (0xF00000U)
+#define AIPSTZ_MPR_MPROT2_SHIFT (20U)
+/*! MPROT2
+ * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ * 0bxx0x..This master is not trusted for write accesses.
+ * 0bxx1x..This master is trusted for write accesses.
+ * 0bx0xx..This master is not trusted for read accesses.
+ * 0bx1xx..This master is trusted for read accesses.
+ * 0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT2_SHIFT)) & AIPSTZ_MPR_MPROT2_MASK)
+#define AIPSTZ_MPR_MPROT1_MASK (0xF000000U)
+#define AIPSTZ_MPR_MPROT1_SHIFT (24U)
+/*! MPROT1
+ * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ * 0bxx0x..This master is not trusted for write accesses.
+ * 0bxx1x..This master is trusted for write accesses.
+ * 0bx0xx..This master is not trusted for read accesses.
+ * 0bx1xx..This master is trusted for read accesses.
+ * 0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT1_SHIFT)) & AIPSTZ_MPR_MPROT1_MASK)
+#define AIPSTZ_MPR_MPROT0_MASK (0xF0000000U)
+#define AIPSTZ_MPR_MPROT0_SHIFT (28U)
+/*! MPROT0
+ * 0bxxx0..Accesses from this master are forced to user-mode (ips_supervisor_access is forced to zero) regardless of the hprot[1] access attribute.
+ * 0bxxx1..Accesses from this master are not forced to user-mode. The hprot[1] access attribute is used directly to determine ips_supervisor_access.
+ * 0bxx0x..This master is not trusted for write accesses.
+ * 0bxx1x..This master is trusted for write accesses.
+ * 0bx0xx..This master is not trusted for read accesses.
+ * 0bx1xx..This master is trusted for read accesses.
+ * 0b1xxx..Write accesses from this master are allowed to be buffered
+ */
+#define AIPSTZ_MPR_MPROT0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_MPR_MPROT0_SHIFT)) & AIPSTZ_MPR_MPROT0_MASK)
+/*! @} */
+
+/*! @name OPACR - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR_OPAC7_MASK (0xFU)
+#define AIPSTZ_OPACR_OPAC7_SHIFT (0U)
+/*! OPAC7
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC7(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC7_SHIFT)) & AIPSTZ_OPACR_OPAC7_MASK)
+#define AIPSTZ_OPACR_OPAC6_MASK (0xF0U)
+#define AIPSTZ_OPACR_OPAC6_SHIFT (4U)
+/*! OPAC6
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC6(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC6_SHIFT)) & AIPSTZ_OPACR_OPAC6_MASK)
+#define AIPSTZ_OPACR_OPAC5_MASK (0xF00U)
+#define AIPSTZ_OPACR_OPAC5_SHIFT (8U)
+/*! OPAC5
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC5(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC5_SHIFT)) & AIPSTZ_OPACR_OPAC5_MASK)
+#define AIPSTZ_OPACR_OPAC4_MASK (0xF000U)
+#define AIPSTZ_OPACR_OPAC4_SHIFT (12U)
+/*! OPAC4
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC4(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC4_SHIFT)) & AIPSTZ_OPACR_OPAC4_MASK)
+#define AIPSTZ_OPACR_OPAC3_MASK (0xF0000U)
+#define AIPSTZ_OPACR_OPAC3_SHIFT (16U)
+/*! OPAC3
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC3(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC3_SHIFT)) & AIPSTZ_OPACR_OPAC3_MASK)
+#define AIPSTZ_OPACR_OPAC2_MASK (0xF00000U)
+#define AIPSTZ_OPACR_OPAC2_SHIFT (20U)
+/*! OPAC2
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC2(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC2_SHIFT)) & AIPSTZ_OPACR_OPAC2_MASK)
+#define AIPSTZ_OPACR_OPAC1_MASK (0xF000000U)
+#define AIPSTZ_OPACR_OPAC1_SHIFT (24U)
+/*! OPAC1
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC1(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC1_SHIFT)) & AIPSTZ_OPACR_OPAC1_MASK)
+#define AIPSTZ_OPACR_OPAC0_MASK (0xF0000000U)
+#define AIPSTZ_OPACR_OPAC0_SHIFT (28U)
+/*! OPAC0
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR_OPAC0(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR_OPAC0_SHIFT)) & AIPSTZ_OPACR_OPAC0_MASK)
+/*! @} */
+
+/*! @name OPACR1 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR1_OPAC15_MASK (0xFU)
+#define AIPSTZ_OPACR1_OPAC15_SHIFT (0U)
+/*! OPAC15
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC15(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC15_SHIFT)) & AIPSTZ_OPACR1_OPAC15_MASK)
+#define AIPSTZ_OPACR1_OPAC14_MASK (0xF0U)
+#define AIPSTZ_OPACR1_OPAC14_SHIFT (4U)
+/*! OPAC14
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC14(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC14_SHIFT)) & AIPSTZ_OPACR1_OPAC14_MASK)
+#define AIPSTZ_OPACR1_OPAC13_MASK (0xF00U)
+#define AIPSTZ_OPACR1_OPAC13_SHIFT (8U)
+/*! OPAC13
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC13(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC13_SHIFT)) & AIPSTZ_OPACR1_OPAC13_MASK)
+#define AIPSTZ_OPACR1_OPAC12_MASK (0xF000U)
+#define AIPSTZ_OPACR1_OPAC12_SHIFT (12U)
+/*! OPAC12
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC12(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC12_SHIFT)) & AIPSTZ_OPACR1_OPAC12_MASK)
+#define AIPSTZ_OPACR1_OPAC11_MASK (0xF0000U)
+#define AIPSTZ_OPACR1_OPAC11_SHIFT (16U)
+/*! OPAC11
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC11(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC11_SHIFT)) & AIPSTZ_OPACR1_OPAC11_MASK)
+#define AIPSTZ_OPACR1_OPAC10_MASK (0xF00000U)
+#define AIPSTZ_OPACR1_OPAC10_SHIFT (20U)
+/*! OPAC10
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC10(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC10_SHIFT)) & AIPSTZ_OPACR1_OPAC10_MASK)
+#define AIPSTZ_OPACR1_OPAC9_MASK (0xF000000U)
+#define AIPSTZ_OPACR1_OPAC9_SHIFT (24U)
+/*! OPAC9
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC9(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC9_SHIFT)) & AIPSTZ_OPACR1_OPAC9_MASK)
+#define AIPSTZ_OPACR1_OPAC8_MASK (0xF0000000U)
+#define AIPSTZ_OPACR1_OPAC8_SHIFT (28U)
+/*! OPAC8
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR1_OPAC8(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR1_OPAC8_SHIFT)) & AIPSTZ_OPACR1_OPAC8_MASK)
+/*! @} */
+
+/*! @name OPACR2 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR2_OPAC23_MASK (0xFU)
+#define AIPSTZ_OPACR2_OPAC23_SHIFT (0U)
+/*! OPAC23
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC23(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC23_SHIFT)) & AIPSTZ_OPACR2_OPAC23_MASK)
+#define AIPSTZ_OPACR2_OPAC22_MASK (0xF0U)
+#define AIPSTZ_OPACR2_OPAC22_SHIFT (4U)
+/*! OPAC22
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC22(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC22_SHIFT)) & AIPSTZ_OPACR2_OPAC22_MASK)
+#define AIPSTZ_OPACR2_OPAC21_MASK (0xF00U)
+#define AIPSTZ_OPACR2_OPAC21_SHIFT (8U)
+/*! OPAC21
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC21(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC21_SHIFT)) & AIPSTZ_OPACR2_OPAC21_MASK)
+#define AIPSTZ_OPACR2_OPAC20_MASK (0xF000U)
+#define AIPSTZ_OPACR2_OPAC20_SHIFT (12U)
+/*! OPAC20
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC20(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC20_SHIFT)) & AIPSTZ_OPACR2_OPAC20_MASK)
+#define AIPSTZ_OPACR2_OPAC19_MASK (0xF0000U)
+#define AIPSTZ_OPACR2_OPAC19_SHIFT (16U)
+/*! OPAC19
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC19(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC19_SHIFT)) & AIPSTZ_OPACR2_OPAC19_MASK)
+#define AIPSTZ_OPACR2_OPAC18_MASK (0xF00000U)
+#define AIPSTZ_OPACR2_OPAC18_SHIFT (20U)
+/*! OPAC18
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC18(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC18_SHIFT)) & AIPSTZ_OPACR2_OPAC18_MASK)
+#define AIPSTZ_OPACR2_OPAC17_MASK (0xF000000U)
+#define AIPSTZ_OPACR2_OPAC17_SHIFT (24U)
+/*! OPAC17
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC17(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC17_SHIFT)) & AIPSTZ_OPACR2_OPAC17_MASK)
+#define AIPSTZ_OPACR2_OPAC16_MASK (0xF0000000U)
+#define AIPSTZ_OPACR2_OPAC16_SHIFT (28U)
+/*! OPAC16
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR2_OPAC16(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR2_OPAC16_SHIFT)) & AIPSTZ_OPACR2_OPAC16_MASK)
+/*! @} */
+
+/*! @name OPACR3 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR3_OPAC31_MASK (0xFU)
+#define AIPSTZ_OPACR3_OPAC31_SHIFT (0U)
+/*! OPAC31
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC31(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC31_SHIFT)) & AIPSTZ_OPACR3_OPAC31_MASK)
+#define AIPSTZ_OPACR3_OPAC30_MASK (0xF0U)
+#define AIPSTZ_OPACR3_OPAC30_SHIFT (4U)
+/*! OPAC30
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC30(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC30_SHIFT)) & AIPSTZ_OPACR3_OPAC30_MASK)
+#define AIPSTZ_OPACR3_OPAC29_MASK (0xF00U)
+#define AIPSTZ_OPACR3_OPAC29_SHIFT (8U)
+/*! OPAC29
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC29(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC29_SHIFT)) & AIPSTZ_OPACR3_OPAC29_MASK)
+#define AIPSTZ_OPACR3_OPAC28_MASK (0xF000U)
+#define AIPSTZ_OPACR3_OPAC28_SHIFT (12U)
+/*! OPAC28
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC28(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC28_SHIFT)) & AIPSTZ_OPACR3_OPAC28_MASK)
+#define AIPSTZ_OPACR3_OPAC27_MASK (0xF0000U)
+#define AIPSTZ_OPACR3_OPAC27_SHIFT (16U)
+/*! OPAC27
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC27(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC27_SHIFT)) & AIPSTZ_OPACR3_OPAC27_MASK)
+#define AIPSTZ_OPACR3_OPAC26_MASK (0xF00000U)
+#define AIPSTZ_OPACR3_OPAC26_SHIFT (20U)
+/*! OPAC26
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC26(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC26_SHIFT)) & AIPSTZ_OPACR3_OPAC26_MASK)
+#define AIPSTZ_OPACR3_OPAC25_MASK (0xF000000U)
+#define AIPSTZ_OPACR3_OPAC25_SHIFT (24U)
+/*! OPAC25
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC25(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC25_SHIFT)) & AIPSTZ_OPACR3_OPAC25_MASK)
+#define AIPSTZ_OPACR3_OPAC24_MASK (0xF0000000U)
+#define AIPSTZ_OPACR3_OPAC24_SHIFT (28U)
+/*! OPAC24
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR3_OPAC24(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR3_OPAC24_SHIFT)) & AIPSTZ_OPACR3_OPAC24_MASK)
+/*! @} */
+
+/*! @name OPACR4 - Off-Platform Peripheral Access Control Registers */
+/*! @{ */
+#define AIPSTZ_OPACR4_OPAC33_MASK (0xF000000U)
+#define AIPSTZ_OPACR4_OPAC33_SHIFT (24U)
+/*! OPAC33
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR4_OPAC33(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC33_SHIFT)) & AIPSTZ_OPACR4_OPAC33_MASK)
+#define AIPSTZ_OPACR4_OPAC32_MASK (0xF0000000U)
+#define AIPSTZ_OPACR4_OPAC32_SHIFT (28U)
+/*! OPAC32
+ * 0bxxx0..Accesses from an untrusted master are allowed.
+ * 0bxxx1..Accesses from an untrusted master are not allowed. If an access is attempted by an untrusted master,
+ * the access is terminated with an error response and no peripheral access is initiated on the IPS bus.
+ * 0bxx0x..This peripheral allows write accesses.
+ * 0bxx1x..This peripheral is write protected. If a write access is attempted, the access is terminated with an
+ * error response and no peripheral access is initiated on the IPS bus.
+ * 0bx0xx..This peripheral does not require supervisor privilege level for accesses.
+ * 0bx1xx..This peripheral requires supervisor privilege level for accesses. The master privilege level must
+ * indicate supervisor via the hprot[1] access attribute, and the MPROTx[MPL] control bit for the master must
+ * be set. If not, the access is terminated with an error response and no peripheral access is initiated
+ * on the IPS bus.
+ * 0b1xxx..Write accesses to this peripheral are allowed to be buffered by the AIPSTZ.
+ */
+#define AIPSTZ_OPACR4_OPAC32(x) (((uint32_t)(((uint32_t)(x)) << AIPSTZ_OPACR4_OPAC32_SHIFT)) & AIPSTZ_OPACR4_OPAC32_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group AIPSTZ_Register_Masks */
+
+
+/* AIPSTZ - Peripheral instance base addresses */
+/** Peripheral AIPSTZ1 base address */
+#define AIPSTZ1_BASE (0x4007C000u)
+/** Peripheral AIPSTZ1 base pointer */
+#define AIPSTZ1 ((AIPSTZ_Type *)AIPSTZ1_BASE)
+/** Peripheral AIPSTZ2 base address */
+#define AIPSTZ2_BASE (0x4017C000u)
+/** Peripheral AIPSTZ2 base pointer */
+#define AIPSTZ2 ((AIPSTZ_Type *)AIPSTZ2_BASE)
+/** Peripheral AIPSTZ3 base address */
+#define AIPSTZ3_BASE (0x4027C000u)
+/** Peripheral AIPSTZ3 base pointer */
+#define AIPSTZ3 ((AIPSTZ_Type *)AIPSTZ3_BASE)
+/** Peripheral AIPSTZ4 base address */
+#define AIPSTZ4_BASE (0x4037C000u)
+/** Peripheral AIPSTZ4 base pointer */
+#define AIPSTZ4 ((AIPSTZ_Type *)AIPSTZ4_BASE)
+/** Array initializer of AIPSTZ peripheral base addresses */
+#define AIPSTZ_BASE_ADDRS { 0u, AIPSTZ1_BASE, AIPSTZ2_BASE, AIPSTZ3_BASE, AIPSTZ4_BASE }
+/** Array initializer of AIPSTZ peripheral base pointers */
+#define AIPSTZ_BASE_PTRS { (AIPSTZ_Type *)0u, AIPSTZ1, AIPSTZ2, AIPSTZ3, AIPSTZ4 }
+
+/*!
+ * @}
+ */ /* end of group AIPSTZ_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- AOI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
+ * @{
+ */
+
+/** AOI - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x4 */
+ __IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
+ __IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
+ } BFCRT[4];
+} AOI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- AOI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AOI_Register_Masks AOI Register Masks
+ * @{
+ */
+
+/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
+/*! @{ */
+#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
+#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
+/*! PT1_DC - Product term 1, D input configuration
+ * 0b00..Force the D input in this product term to a logical zero
+ * 0b01..Pass the D input in this product term
+ * 0b10..Complement the D input in this product term
+ * 0b11..Force the D input in this product term to a logical one
+ */
+#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
+#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
+#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
+/*! PT1_CC - Product term 1, C input configuration
+ * 0b00..Force the C input in this product term to a logical zero
+ * 0b01..Pass the C input in this product term
+ * 0b10..Complement the C input in this product term
+ * 0b11..Force the C input in this product term to a logical one
+ */
+#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
+#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
+#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
+/*! PT1_BC - Product term 1, B input configuration
+ * 0b00..Force the B input in this product term to a logical zero
+ * 0b01..Pass the B input in this product term
+ * 0b10..Complement the B input in this product term
+ * 0b11..Force the B input in this product term to a logical one
+ */
+#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
+#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
+#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
+/*! PT1_AC - Product term 1, A input configuration
+ * 0b00..Force the A input in this product term to a logical zero
+ * 0b01..Pass the A input in this product term
+ * 0b10..Complement the A input in this product term
+ * 0b11..Force the A input in this product term to a logical one
+ */
+#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
+#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
+#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
+/*! PT0_DC - Product term 0, D input configuration
+ * 0b00..Force the D input in this product term to a logical zero
+ * 0b01..Pass the D input in this product term
+ * 0b10..Complement the D input in this product term
+ * 0b11..Force the D input in this product term to a logical one
+ */
+#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
+#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
+#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
+/*! PT0_CC - Product term 0, C input configuration
+ * 0b00..Force the C input in this product term to a logical zero
+ * 0b01..Pass the C input in this product term
+ * 0b10..Complement the C input in this product term
+ * 0b11..Force the C input in this product term to a logical one
+ */
+#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
+#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
+#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
+/*! PT0_BC - Product term 0, B input configuration
+ * 0b00..Force the B input in this product term to a logical zero
+ * 0b01..Pass the B input in this product term
+ * 0b10..Complement the B input in this product term
+ * 0b11..Force the B input in this product term to a logical one
+ */
+#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
+#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
+#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
+/*! PT0_AC - Product term 0, A input configuration
+ * 0b00..Force the A input in this product term to a logical zero
+ * 0b01..Pass the A input in this product term
+ * 0b10..Complement the A input in this product term
+ * 0b11..Force the A input in this product term to a logical one
+ */
+#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
+/*! @} */
+
+/* The count of AOI_BFCRT01 */
+#define AOI_BFCRT01_COUNT (4U)
+
+/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
+/*! @{ */
+#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
+#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
+/*! PT3_DC - Product term 3, D input configuration
+ * 0b00..Force the D input in this product term to a logical zero
+ * 0b01..Pass the D input in this product term
+ * 0b10..Complement the D input in this product term
+ * 0b11..Force the D input in this product term to a logical one
+ */
+#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
+#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
+#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
+/*! PT3_CC - Product term 3, C input configuration
+ * 0b00..Force the C input in this product term to a logical zero
+ * 0b01..Pass the C input in this product term
+ * 0b10..Complement the C input in this product term
+ * 0b11..Force the C input in this product term to a logical one
+ */
+#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
+#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
+#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
+/*! PT3_BC - Product term 3, B input configuration
+ * 0b00..Force the B input in this product term to a logical zero
+ * 0b01..Pass the B input in this product term
+ * 0b10..Complement the B input in this product term
+ * 0b11..Force the B input in this product term to a logical one
+ */
+#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
+#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
+#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
+/*! PT3_AC - Product term 3, A input configuration
+ * 0b00..Force the A input in this product term to a logical zero
+ * 0b01..Pass the A input in this product term
+ * 0b10..Complement the A input in this product term
+ * 0b11..Force the A input in this product term to a logical one
+ */
+#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
+#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
+#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
+/*! PT2_DC - Product term 2, D input configuration
+ * 0b00..Force the D input in this product term to a logical zero
+ * 0b01..Pass the D input in this product term
+ * 0b10..Complement the D input in this product term
+ * 0b11..Force the D input in this product term to a logical one
+ */
+#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
+#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
+#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
+/*! PT2_CC - Product term 2, C input configuration
+ * 0b00..Force the C input in this product term to a logical zero
+ * 0b01..Pass the C input in this product term
+ * 0b10..Complement the C input in this product term
+ * 0b11..Force the C input in this product term to a logical one
+ */
+#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
+#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
+#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
+/*! PT2_BC - Product term 2, B input configuration
+ * 0b00..Force the B input in this product term to a logical zero
+ * 0b01..Pass the B input in this product term
+ * 0b10..Complement the B input in this product term
+ * 0b11..Force the B input in this product term to a logical one
+ */
+#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
+#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
+#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
+/*! PT2_AC - Product term 2, A input configuration
+ * 0b00..Force the A input in this product term to a logical zero
+ * 0b01..Pass the A input in this product term
+ * 0b10..Complement the A input in this product term
+ * 0b11..Force the A input in this product term to a logical one
+ */
+#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
+/*! @} */
+
+/* The count of AOI_BFCRT23 */
+#define AOI_BFCRT23_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group AOI_Register_Masks */
+
+
+/* AOI - Peripheral instance base addresses */
+/** Peripheral AOI1 base address */
+#define AOI1_BASE (0x403B4000u)
+/** Peripheral AOI1 base pointer */
+#define AOI1 ((AOI_Type *)AOI1_BASE)
+/** Peripheral AOI2 base address */
+#define AOI2_BASE (0x403B8000u)
+/** Peripheral AOI2 base pointer */
+#define AOI2 ((AOI_Type *)AOI2_BASE)
+/** Array initializer of AOI peripheral base addresses */
+#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
+/** Array initializer of AOI peripheral base pointers */
+#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
+
+/*!
+ * @}
+ */ /* end of group AOI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- BEE Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BEE_Peripheral_Access_Layer BEE Peripheral Access Layer
+ * @{
+ */
+
+/** BEE - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control Register, offset: 0x0 */
+ __IO uint32_t ADDR_OFFSET0; /**< Offset region 0 Register, offset: 0x4 */
+ __IO uint32_t ADDR_OFFSET1; /**< Offset region 1 Register, offset: 0x8 */
+ __IO uint32_t AES_KEY0_W0; /**< AES Key 0 Register, offset: 0xC */
+ __IO uint32_t AES_KEY0_W1; /**< AES Key 1 Register, offset: 0x10 */
+ __IO uint32_t AES_KEY0_W2; /**< AES Key 2 Register, offset: 0x14 */
+ __IO uint32_t AES_KEY0_W3; /**< AES Key 3 Register, offset: 0x18 */
+ __IO uint32_t STATUS; /**< Status Register, offset: 0x1C */
+ __O uint32_t CTR_NONCE0_W0; /**< NONCE00 Register, offset: 0x20 */
+ __O uint32_t CTR_NONCE0_W1; /**< NONCE01 Register, offset: 0x24 */
+ __O uint32_t CTR_NONCE0_W2; /**< NONCE02 Register, offset: 0x28 */
+ __O uint32_t CTR_NONCE0_W3; /**< NONCE03 Register, offset: 0x2C */
+ __O uint32_t CTR_NONCE1_W0; /**< NONCE10 Register, offset: 0x30 */
+ __O uint32_t CTR_NONCE1_W1; /**< NONCE11 Register, offset: 0x34 */
+ __O uint32_t CTR_NONCE1_W2; /**< NONCE12 Register, offset: 0x38 */
+ __O uint32_t CTR_NONCE1_W3; /**< NONCE13 Register, offset: 0x3C */
+ __IO uint32_t REGION1_TOP; /**< Region1 Top Address Register, offset: 0x40 */
+ __IO uint32_t REGION1_BOT; /**< Region1 Bottom Address Register, offset: 0x44 */
+} BEE_Type;
+
+/* ----------------------------------------------------------------------------
+ -- BEE Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup BEE_Register_Masks BEE Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+/*! @{ */
+#define BEE_CTRL_BEE_ENABLE_MASK (0x1U)
+#define BEE_CTRL_BEE_ENABLE_SHIFT (0U)
+/*! BEE_ENABLE
+ * 0b0..Disable BEE
+ * 0b1..Enable BEE
+ */
+#define BEE_CTRL_BEE_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_SHIFT)) & BEE_CTRL_BEE_ENABLE_MASK)
+#define BEE_CTRL_CTRL_CLK_EN_MASK (0x2U)
+#define BEE_CTRL_CTRL_CLK_EN_SHIFT (1U)
+#define BEE_CTRL_CTRL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_MASK)
+#define BEE_CTRL_CTRL_SFTRST_N_MASK (0x4U)
+#define BEE_CTRL_CTRL_SFTRST_N_SHIFT (2U)
+#define BEE_CTRL_CTRL_SFTRST_N(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_MASK)
+#define BEE_CTRL_KEY_VALID_MASK (0x10U)
+#define BEE_CTRL_KEY_VALID_SHIFT (4U)
+#define BEE_CTRL_KEY_VALID(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_SHIFT)) & BEE_CTRL_KEY_VALID_MASK)
+#define BEE_CTRL_KEY_REGION_SEL_MASK (0x20U)
+#define BEE_CTRL_KEY_REGION_SEL_SHIFT (5U)
+/*! KEY_REGION_SEL
+ * 0b0..Load AES key for region0
+ * 0b1..Load AES key for region1
+ */
+#define BEE_CTRL_KEY_REGION_SEL(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_MASK)
+#define BEE_CTRL_AC_PROT_EN_MASK (0x40U)
+#define BEE_CTRL_AC_PROT_EN_SHIFT (6U)
+#define BEE_CTRL_AC_PROT_EN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_SHIFT)) & BEE_CTRL_AC_PROT_EN_MASK)
+#define BEE_CTRL_LITTLE_ENDIAN_MASK (0x80U)
+#define BEE_CTRL_LITTLE_ENDIAN_SHIFT (7U)
+/*! LITTLE_ENDIAN
+ * 0b0..The input and output data of the AES core is swapped as below: {B15,B14,B13,B12,B11,B10,B9,B8,
+ * B7,B6,B5,B4,B3,B2,B1,B0} swap to {B0,B1,B2,B3,B4,B5,B6,B7, B8,B9,B10,B11,B12,B13,B14,B15}, where B0~B15 refers to
+ * Byte0 to Byte15.
+ * 0b1..The input and output data of AES core is not swapped.
+ */
+#define BEE_CTRL_LITTLE_ENDIAN(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_MASK)
+#define BEE_CTRL_SECURITY_LEVEL_R0_MASK (0x300U)
+#define BEE_CTRL_SECURITY_LEVEL_R0_SHIFT (8U)
+#define BEE_CTRL_SECURITY_LEVEL_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_MASK)
+#define BEE_CTRL_CTRL_AES_MODE_R0_MASK (0x400U)
+#define BEE_CTRL_CTRL_AES_MODE_R0_SHIFT (10U)
+/*! CTRL_AES_MODE_R0
+ * 0b0..ECB
+ * 0b1..CTR
+ */
+#define BEE_CTRL_CTRL_AES_MODE_R0(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_MASK)
+#define BEE_CTRL_SECURITY_LEVEL_R1_MASK (0x3000U)
+#define BEE_CTRL_SECURITY_LEVEL_R1_SHIFT (12U)
+#define BEE_CTRL_SECURITY_LEVEL_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_MASK)
+#define BEE_CTRL_CTRL_AES_MODE_R1_MASK (0x4000U)
+#define BEE_CTRL_CTRL_AES_MODE_R1_SHIFT (14U)
+/*! CTRL_AES_MODE_R1
+ * 0b0..ECB
+ * 0b1..CTR
+ */
+#define BEE_CTRL_CTRL_AES_MODE_R1(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_MASK)
+#define BEE_CTRL_BEE_ENABLE_LOCK_MASK (0x10000U)
+#define BEE_CTRL_BEE_ENABLE_LOCK_SHIFT (16U)
+#define BEE_CTRL_BEE_ENABLE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_BEE_ENABLE_LOCK_SHIFT)) & BEE_CTRL_BEE_ENABLE_LOCK_MASK)
+#define BEE_CTRL_CTRL_CLK_EN_LOCK_MASK (0x20000U)
+#define BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT (17U)
+#define BEE_CTRL_CTRL_CLK_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_CLK_EN_LOCK_SHIFT)) & BEE_CTRL_CTRL_CLK_EN_LOCK_MASK)
+#define BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK (0x40000U)
+#define BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT (18U)
+#define BEE_CTRL_CTRL_SFTRST_N_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_SFTRST_N_LOCK_SHIFT)) & BEE_CTRL_CTRL_SFTRST_N_LOCK_MASK)
+#define BEE_CTRL_REGION1_ADDR_LOCK_MASK (0x80000U)
+#define BEE_CTRL_REGION1_ADDR_LOCK_SHIFT (19U)
+#define BEE_CTRL_REGION1_ADDR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_ADDR_LOCK_SHIFT)) & BEE_CTRL_REGION1_ADDR_LOCK_MASK)
+#define BEE_CTRL_KEY_VALID_LOCK_MASK (0x100000U)
+#define BEE_CTRL_KEY_VALID_LOCK_SHIFT (20U)
+#define BEE_CTRL_KEY_VALID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_VALID_LOCK_SHIFT)) & BEE_CTRL_KEY_VALID_LOCK_MASK)
+#define BEE_CTRL_KEY_REGION_SEL_LOCK_MASK (0x200000U)
+#define BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT (21U)
+#define BEE_CTRL_KEY_REGION_SEL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_KEY_REGION_SEL_LOCK_SHIFT)) & BEE_CTRL_KEY_REGION_SEL_LOCK_MASK)
+#define BEE_CTRL_AC_PROT_EN_LOCK_MASK (0x400000U)
+#define BEE_CTRL_AC_PROT_EN_LOCK_SHIFT (22U)
+#define BEE_CTRL_AC_PROT_EN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_AC_PROT_EN_LOCK_SHIFT)) & BEE_CTRL_AC_PROT_EN_LOCK_MASK)
+#define BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK (0x800000U)
+#define BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT (23U)
+#define BEE_CTRL_LITTLE_ENDIAN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_LITTLE_ENDIAN_LOCK_SHIFT)) & BEE_CTRL_LITTLE_ENDIAN_LOCK_MASK)
+#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK (0x3000000U)
+#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT (24U)
+#define BEE_CTRL_SECURITY_LEVEL_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R0_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R0_LOCK_MASK)
+#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK (0x4000000U)
+#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT (26U)
+#define BEE_CTRL_CTRL_AES_MODE_R0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R0_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R0_LOCK_MASK)
+#define BEE_CTRL_REGION0_KEY_LOCK_MASK (0x8000000U)
+#define BEE_CTRL_REGION0_KEY_LOCK_SHIFT (27U)
+#define BEE_CTRL_REGION0_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION0_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION0_KEY_LOCK_MASK)
+#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK (0x30000000U)
+#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT (28U)
+#define BEE_CTRL_SECURITY_LEVEL_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_SECURITY_LEVEL_R1_LOCK_SHIFT)) & BEE_CTRL_SECURITY_LEVEL_R1_LOCK_MASK)
+#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK (0x40000000U)
+#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT (30U)
+#define BEE_CTRL_CTRL_AES_MODE_R1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_CTRL_AES_MODE_R1_LOCK_SHIFT)) & BEE_CTRL_CTRL_AES_MODE_R1_LOCK_MASK)
+#define BEE_CTRL_REGION1_KEY_LOCK_MASK (0x80000000U)
+#define BEE_CTRL_REGION1_KEY_LOCK_SHIFT (31U)
+#define BEE_CTRL_REGION1_KEY_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTRL_REGION1_KEY_LOCK_SHIFT)) & BEE_CTRL_REGION1_KEY_LOCK_MASK)
+/*! @} */
+
+/*! @name ADDR_OFFSET0 - Offset region 0 Register */
+/*! @{ */
+#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK (0xFFFFU)
+#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT (0U)
+#define BEE_ADDR_OFFSET0_ADDR_OFFSET0(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_MASK)
+#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK (0xFFFF0000U)
+#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT (16U)
+#define BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_SHIFT)) & BEE_ADDR_OFFSET0_ADDR_OFFSET0_LOCK_MASK)
+/*! @} */
+
+/*! @name ADDR_OFFSET1 - Offset region 1 Register */
+/*! @{ */
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK (0xFFFFU)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT (0U)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_MASK)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK (0xFFFF0000U)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT (16U)
+#define BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_SHIFT)) & BEE_ADDR_OFFSET1_ADDR_OFFSET1_LOCK_MASK)
+/*! @} */
+
+/*! @name AES_KEY0_W0 - AES Key 0 Register */
+/*! @{ */
+#define BEE_AES_KEY0_W0_KEY0_MASK (0xFFFFFFFFU)
+#define BEE_AES_KEY0_W0_KEY0_SHIFT (0U)
+/*! KEY0 - AES 128 key from software
+ */
+#define BEE_AES_KEY0_W0_KEY0(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W0_KEY0_SHIFT)) & BEE_AES_KEY0_W0_KEY0_MASK)
+/*! @} */
+
+/*! @name AES_KEY0_W1 - AES Key 1 Register */
+/*! @{ */
+#define BEE_AES_KEY0_W1_KEY1_MASK (0xFFFFFFFFU)
+#define BEE_AES_KEY0_W1_KEY1_SHIFT (0U)
+/*! KEY1 - AES 128 key from software
+ */
+#define BEE_AES_KEY0_W1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W1_KEY1_SHIFT)) & BEE_AES_KEY0_W1_KEY1_MASK)
+/*! @} */
+
+/*! @name AES_KEY0_W2 - AES Key 2 Register */
+/*! @{ */
+#define BEE_AES_KEY0_W2_KEY2_MASK (0xFFFFFFFFU)
+#define BEE_AES_KEY0_W2_KEY2_SHIFT (0U)
+/*! KEY2 - AES 128 key from software
+ */
+#define BEE_AES_KEY0_W2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W2_KEY2_SHIFT)) & BEE_AES_KEY0_W2_KEY2_MASK)
+/*! @} */
+
+/*! @name AES_KEY0_W3 - AES Key 3 Register */
+/*! @{ */
+#define BEE_AES_KEY0_W3_KEY3_MASK (0xFFFFFFFFU)
+#define BEE_AES_KEY0_W3_KEY3_SHIFT (0U)
+/*! KEY3 - AES 128 key from software
+ */
+#define BEE_AES_KEY0_W3_KEY3(x) (((uint32_t)(((uint32_t)(x)) << BEE_AES_KEY0_W3_KEY3_SHIFT)) & BEE_AES_KEY0_W3_KEY3_MASK)
+/*! @} */
+
+/*! @name STATUS - Status Register */
+/*! @{ */
+#define BEE_STATUS_IRQ_VEC_MASK (0xFFU)
+#define BEE_STATUS_IRQ_VEC_SHIFT (0U)
+#define BEE_STATUS_IRQ_VEC(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_IRQ_VEC_SHIFT)) & BEE_STATUS_IRQ_VEC_MASK)
+#define BEE_STATUS_BEE_IDLE_MASK (0x100U)
+#define BEE_STATUS_BEE_IDLE_SHIFT (8U)
+#define BEE_STATUS_BEE_IDLE(x) (((uint32_t)(((uint32_t)(x)) << BEE_STATUS_BEE_IDLE_SHIFT)) & BEE_STATUS_BEE_IDLE_MASK)
+/*! @} */
+
+/*! @name CTR_NONCE0_W0 - NONCE00 Register */
+/*! @{ */
+#define BEE_CTR_NONCE0_W0_NONCE00_MASK (0xFFFFFFFFU)
+#define BEE_CTR_NONCE0_W0_NONCE00_SHIFT (0U)
+#define BEE_CTR_NONCE0_W0_NONCE00(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W0_NONCE00_SHIFT)) & BEE_CTR_NONCE0_W0_NONCE00_MASK)
+/*! @} */
+
+/*! @name CTR_NONCE0_W1 - NONCE01 Register */
+/*! @{ */
+#define BEE_CTR_NONCE0_W1_NONCE01_MASK (0xFFFFFFFFU)
+#define BEE_CTR_NONCE0_W1_NONCE01_SHIFT (0U)
+#define BEE_CTR_NONCE0_W1_NONCE01(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W1_NONCE01_SHIFT)) & BEE_CTR_NONCE0_W1_NONCE01_MASK)
+/*! @} */
+
+/*! @name CTR_NONCE0_W2 - NONCE02 Register */
+/*! @{ */
+#define BEE_CTR_NONCE0_W2_NONCE02_MASK (0xFFFFFFFFU)
+#define BEE_CTR_NONCE0_W2_NONCE02_SHIFT (0U)
+#define BEE_CTR_NONCE0_W2_NONCE02(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W2_NONCE02_SHIFT)) & BEE_CTR_NONCE0_W2_NONCE02_MASK)
+/*! @} */
+
+/*! @name CTR_NONCE0_W3 - NONCE03 Register */
+/*! @{ */
+#define BEE_CTR_NONCE0_W3_NONCE03_MASK (0xFFFFFFFFU)
+#define BEE_CTR_NONCE0_W3_NONCE03_SHIFT (0U)
+#define BEE_CTR_NONCE0_W3_NONCE03(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE0_W3_NONCE03_SHIFT)) & BEE_CTR_NONCE0_W3_NONCE03_MASK)
+/*! @} */
+
+/*! @name CTR_NONCE1_W0 - NONCE10 Register */
+/*! @{ */
+#define BEE_CTR_NONCE1_W0_NONCE10_MASK (0xFFFFFFFFU)
+#define BEE_CTR_NONCE1_W0_NONCE10_SHIFT (0U)
+#define BEE_CTR_NONCE1_W0_NONCE10(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W0_NONCE10_SHIFT)) & BEE_CTR_NONCE1_W0_NONCE10_MASK)
+/*! @} */
+
+/*! @name CTR_NONCE1_W1 - NONCE11 Register */
+/*! @{ */
+#define BEE_CTR_NONCE1_W1_NONCE11_MASK (0xFFFFFFFFU)
+#define BEE_CTR_NONCE1_W1_NONCE11_SHIFT (0U)
+#define BEE_CTR_NONCE1_W1_NONCE11(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W1_NONCE11_SHIFT)) & BEE_CTR_NONCE1_W1_NONCE11_MASK)
+/*! @} */
+
+/*! @name CTR_NONCE1_W2 - NONCE12 Register */
+/*! @{ */
+#define BEE_CTR_NONCE1_W2_NONCE12_MASK (0xFFFFFFFFU)
+#define BEE_CTR_NONCE1_W2_NONCE12_SHIFT (0U)
+#define BEE_CTR_NONCE1_W2_NONCE12(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W2_NONCE12_SHIFT)) & BEE_CTR_NONCE1_W2_NONCE12_MASK)
+/*! @} */
+
+/*! @name CTR_NONCE1_W3 - NONCE13 Register */
+/*! @{ */
+#define BEE_CTR_NONCE1_W3_NONCE13_MASK (0xFFFFFFFFU)
+#define BEE_CTR_NONCE1_W3_NONCE13_SHIFT (0U)
+#define BEE_CTR_NONCE1_W3_NONCE13(x) (((uint32_t)(((uint32_t)(x)) << BEE_CTR_NONCE1_W3_NONCE13_SHIFT)) & BEE_CTR_NONCE1_W3_NONCE13_MASK)
+/*! @} */
+
+/*! @name REGION1_TOP - Region1 Top Address Register */
+/*! @{ */
+#define BEE_REGION1_TOP_REGION1_TOP_MASK (0xFFFFFFFFU)
+#define BEE_REGION1_TOP_REGION1_TOP_SHIFT (0U)
+/*! REGION1_TOP - Address upper limit of region1
+ */
+#define BEE_REGION1_TOP_REGION1_TOP(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_TOP_REGION1_TOP_SHIFT)) & BEE_REGION1_TOP_REGION1_TOP_MASK)
+/*! @} */
+
+/*! @name REGION1_BOT - Region1 Bottom Address Register */
+/*! @{ */
+#define BEE_REGION1_BOT_REGION1_BOT_MASK (0xFFFFFFFFU)
+#define BEE_REGION1_BOT_REGION1_BOT_SHIFT (0U)
+/*! REGION1_BOT - Address lower limit of region1
+ */
+#define BEE_REGION1_BOT_REGION1_BOT(x) (((uint32_t)(((uint32_t)(x)) << BEE_REGION1_BOT_REGION1_BOT_SHIFT)) & BEE_REGION1_BOT_REGION1_BOT_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group BEE_Register_Masks */
+
+
+/* BEE - Peripheral instance base addresses */
+/** Peripheral BEE base address */
+#define BEE_BASE (0x403EC000u)
+/** Peripheral BEE base pointer */
+#define BEE ((BEE_Type *)BEE_BASE)
+/** Array initializer of BEE peripheral base addresses */
+#define BEE_BASE_ADDRS { BEE_BASE }
+/** Array initializer of BEE peripheral base pointers */
+#define BEE_BASE_PTRS { BEE }
+
+/*!
+ * @}
+ */ /* end of group BEE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAN Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
+ __IO uint32_t CTRL1; /**< Control 1 Register, offset: 0x4 */
+ __IO uint32_t TIMER; /**< Free Running Timer Register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+ __IO uint32_t RX14MASK; /**< Rx Buffer 14 Mask Register, offset: 0x14 */
+ __IO uint32_t RX15MASK; /**< Rx Buffer 15 Mask Register, offset: 0x18 */
+ __IO uint32_t ECR; /**< Error Counter Register, offset: 0x1C */
+ __IO uint32_t ESR1; /**< Error and Status 1 Register, offset: 0x20 */
+ __IO uint32_t IMASK2; /**< Interrupt Masks 2 Register, offset: 0x24 */
+ __IO uint32_t IMASK1; /**< Interrupt Masks 1 Register, offset: 0x28 */
+ __IO uint32_t IFLAG2; /**< Interrupt Flags 2 Register, offset: 0x2C */
+ __IO uint32_t IFLAG1; /**< Interrupt Flags 1 Register, offset: 0x30 */
+ __IO uint32_t CTRL2; /**< Control 2 Register, offset: 0x34 */
+ __I uint32_t ESR2; /**< Error and Status 2 Register, offset: 0x38 */
+ uint8_t RESERVED_1[8];
+ __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
+ __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask Register, offset: 0x48 */
+ __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
+ uint8_t RESERVED_2[8];
+ __I uint32_t DBG1; /**< Debug 1 register, offset: 0x58 */
+ __I uint32_t DBG2; /**< Debug 2 register, offset: 0x5C */
+ uint8_t RESERVED_3[32];
+ struct { /* offset: 0x80, array step: 0x10 */
+ __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
+ __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
+ __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
+ __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+ } MB[64];
+ uint8_t RESERVED_4[1024];
+ __IO uint32_t RXIMR[64]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+ uint8_t RESERVED_5[96];
+ __IO uint32_t GFWR; /**< Glitch Filter Width Registers, offset: 0x9E0 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CAN Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration Register */
+/*! @{ */
+#define CAN_MCR_MAXMB_MASK (0x7FU)
+#define CAN_MCR_MAXMB_SHIFT (0U)
+#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK (0x300U)
+#define CAN_MCR_IDAM_SHIFT (8U)
+/*! IDAM
+ * 0b00..Format A One full ID (standard or extended) per ID filter Table element.
+ * 0b01..Format B Two full standard IDs or two partial 14-bit extended IDs per ID filter Table element.
+ * 0b10..Format C Four partial 8-bit IDs (standard or extended) per ID filter Table element.
+ * 0b11..Format D All frames rejected.
+ */
+#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK (0x1000U)
+#define CAN_MCR_AEN_SHIFT (12U)
+/*! AEN
+ * 0b1..Abort enabled
+ * 0b0..Abort disabled
+ */
+#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK (0x2000U)
+#define CAN_MCR_LPRIOEN_SHIFT (13U)
+/*! LPRIOEN
+ * 0b1..Local Priority enabled
+ * 0b0..Local Priority disabled
+ */
+#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK (0x10000U)
+#define CAN_MCR_IRMQ_SHIFT (16U)
+/*! IRMQ
+ * 0b1..Individual Rx masking and queue feature are enabled.
+ * 0b0..Individual Rx masking and queue feature are disabled.For backward compatibility, the reading of C/S word locks the MB even if it is EMPTY.
+ */
+#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK (0x20000U)
+#define CAN_MCR_SRXDIS_SHIFT (17U)
+/*! SRXDIS
+ * 0b1..Self reception disabled
+ * 0b0..Self reception enabled
+ */
+#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK (0x80000U)
+#define CAN_MCR_WAKSRC_SHIFT (19U)
+/*! WAKSRC
+ * 0b1..FLEXCAN uses the filtered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus
+ * 0b0..FLEXCAN uses the unfiltered FLEXCAN_RX input to detect recessive to dominant edges on the CAN bus.
+ */
+#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK (0x100000U)
+#define CAN_MCR_LPMACK_SHIFT (20U)
+/*! LPMACK
+ * 0b1..FLEXCAN is either in Disable Mode, or Stop mode
+ * 0b0..FLEXCAN not in any of the low power modes
+ */
+#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK (0x200000U)
+#define CAN_MCR_WRNEN_SHIFT (21U)
+/*! WRNEN
+ * 0b1..TWRN_INT and RWRN_INT bits are set when the respective error counter transition from <96 to >= 96.
+ * 0b0..TWRN_INT and RWRN_INT bits are zero, independent of the values in the error counters.
+ */
+#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK (0x400000U)
+#define CAN_MCR_SLFWAK_SHIFT (22U)
+/*! SLFWAK
+ * 0b1..FLEXCAN Self Wake Up feature is enabled
+ * 0b0..FLEXCAN Self Wake Up feature is disabled
+ */
+#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK (0x800000U)
+#define CAN_MCR_SUPV_SHIFT (23U)
+/*! SUPV
+ * 0b1..FlexCAN is in Supervisor Mode. Affected registers allow only Supervisor access. Unrestricted access
+ * behaves as though the access was done to an unimplemented register location
+ * 0b0..FlexCAN is in User Mode. Affected registers allow both Supervisor and Unrestricted accesses
+ */
+#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK (0x1000000U)
+#define CAN_MCR_FRZACK_SHIFT (24U)
+/*! FRZACK
+ * 0b1..FLEXCAN in Freeze Mode, prescaler stopped
+ * 0b0..FLEXCAN not in Freeze Mode, prescaler running
+ */
+#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK (0x2000000U)
+#define CAN_MCR_SOFTRST_SHIFT (25U)
+/*! SOFTRST
+ * 0b1..Reset the registers
+ * 0b0..No reset request
+ */
+#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK (0x4000000U)
+#define CAN_MCR_WAKMSK_SHIFT (26U)
+/*! WAKMSK
+ * 0b1..Wake Up Interrupt is enabled
+ * 0b0..Wake Up Interrupt is disabled
+ */
+#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK (0x8000000U)
+#define CAN_MCR_NOTRDY_SHIFT (27U)
+/*! NOTRDY
+ * 0b1..FLEXCAN module is either in Disable Mode, Stop Mode or Freeze Mode
+ * 0b0..FLEXCAN module is either in Normal Mode, Listen-Only Mode or Loop-Back Mode
+ */
+#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK (0x10000000U)
+#define CAN_MCR_HALT_SHIFT (28U)
+/*! HALT
+ * 0b1..Enters Freeze Mode if the FRZ bit is asserted.
+ * 0b0..No Freeze Mode request.
+ */
+#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK (0x20000000U)
+#define CAN_MCR_RFEN_SHIFT (29U)
+/*! RFEN
+ * 0b1..FIFO enabled
+ * 0b0..FIFO not enabled
+ */
+#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK (0x40000000U)
+#define CAN_MCR_FRZ_SHIFT (30U)
+/*! FRZ
+ * 0b1..Enabled to enter Freeze Mode
+ * 0b0..Not enabled to enter Freeze Mode
+ */
+#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK (0x80000000U)
+#define CAN_MCR_MDIS_SHIFT (31U)
+/*! MDIS
+ * 0b1..Disable the FLEXCAN module
+ * 0b0..Enable the FLEXCAN module
+ */
+#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
+/*! @} */
+
+/*! @name CTRL1 - Control 1 Register */
+/*! @{ */
+#define CAN_CTRL1_PROPSEG_MASK (0x7U)
+#define CAN_CTRL1_PROPSEG_SHIFT (0U)
+#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK (0x8U)
+#define CAN_CTRL1_LOM_SHIFT (3U)
+/*! LOM
+ * 0b1..FLEXCAN module operates in Listen Only Mode
+ * 0b0..Listen Only Mode is deactivated
+ */
+#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK (0x10U)
+#define CAN_CTRL1_LBUF_SHIFT (4U)
+/*! LBUF
+ * 0b1..Lowest number buffer is transmitted first
+ * 0b0..Buffer with highest priority is transmitted first
+ */
+#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK (0x20U)
+#define CAN_CTRL1_TSYN_SHIFT (5U)
+/*! TSYN
+ * 0b1..Timer Sync feature enabled
+ * 0b0..Timer Sync feature disabled
+ */
+#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK (0x40U)
+#define CAN_CTRL1_BOFFREC_SHIFT (6U)
+/*! BOFFREC
+ * 0b1..Automatic recovering from Bus Off state disabled
+ * 0b0..Automatic recovering from Bus Off state enabled, according to CAN Spec 2.0 part B
+ */
+#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK (0x80U)
+#define CAN_CTRL1_SMP_SHIFT (7U)
+/*! SMP
+ * 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and 2
+ * preceding samples, a majority rule is used
+ * 0b0..Just one sample is used to determine the bit value
+ */
+#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
+#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
+/*! RWRNMSK
+ * 0b1..Rx Warning Interrupt enabled
+ * 0b0..Rx Warning Interrupt disabled
+ */
+#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
+#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
+/*! TWRNMSK
+ * 0b1..Tx Warning Interrupt enabled
+ * 0b0..Tx Warning Interrupt disabled
+ */
+#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK (0x1000U)
+#define CAN_CTRL1_LPB_SHIFT (12U)
+/*! LPB
+ * 0b1..Loop Back enabled
+ * 0b0..Loop Back disabled
+ */
+#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
+#define CAN_CTRL1_ERRMSK_SHIFT (14U)
+/*! ERRMSK
+ * 0b1..Error interrupt enabled
+ * 0b0..Error interrupt disabled
+ */
+#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
+#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
+/*! BOFFMSK
+ * 0b1..Bus Off interrupt enabled
+ * 0b0..Bus Off interrupt disabled
+ */
+#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK (0x70000U)
+#define CAN_CTRL1_PSEG2_SHIFT (16U)
+#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK (0x380000U)
+#define CAN_CTRL1_PSEG1_SHIFT (19U)
+#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK (0xC00000U)
+#define CAN_CTRL1_RJW_SHIFT (22U)
+#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
+#define CAN_CTRL1_PRESDIV_SHIFT (24U)
+#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
+/*! @} */
+
+/*! @name TIMER - Free Running Timer Register */
+/*! @{ */
+#define CAN_TIMER_TIMER_MASK (0xFFFFU)
+#define CAN_TIMER_TIMER_SHIFT (0U)
+#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
+/*! @} */
+
+/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
+/*! @{ */
+#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
+#define CAN_RXMGMASK_MG_SHIFT (0U)
+/*! MG
+ * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked against the one received
+ * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
+ */
+#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
+/*! @} */
+
+/*! @name RX14MASK - Rx Buffer 14 Mask Register */
+/*! @{ */
+#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
+#define CAN_RX14MASK_RX14M_SHIFT (0U)
+/*! RX14M
+ * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
+ * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
+ */
+#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
+/*! @} */
+
+/*! @name RX15MASK - Rx Buffer 15 Mask Register */
+/*! @{ */
+#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
+#define CAN_RX15MASK_RX15M_SHIFT (0U)
+/*! RX15M
+ * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
+ * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
+ */
+#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
+/*! @} */
+
+/*! @name ECR - Error Counter Register */
+/*! @{ */
+#define CAN_ECR_TX_ERR_COUNTER_MASK (0xFFU)
+#define CAN_ECR_TX_ERR_COUNTER_SHIFT (0U)
+#define CAN_ECR_TX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TX_ERR_COUNTER_SHIFT)) & CAN_ECR_TX_ERR_COUNTER_MASK)
+#define CAN_ECR_RX_ERR_COUNTER_MASK (0xFF00U)
+#define CAN_ECR_RX_ERR_COUNTER_SHIFT (8U)
+#define CAN_ECR_RX_ERR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RX_ERR_COUNTER_SHIFT)) & CAN_ECR_RX_ERR_COUNTER_MASK)
+/*! @} */
+
+/*! @name ESR1 - Error and Status 1 Register */
+/*! @{ */
+#define CAN_ESR1_WAKINT_MASK (0x1U)
+#define CAN_ESR1_WAKINT_SHIFT (0U)
+/*! WAKINT
+ * 0b1..Indicates a recessive to dominant transition received on the CAN bus when the FLEXCAN module is in Stop Mode
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK (0x2U)
+#define CAN_ESR1_ERRINT_SHIFT (1U)
+/*! ERRINT
+ * 0b1..Indicates setting of any Error Bit in the Error and Status Register
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK (0x4U)
+#define CAN_ESR1_BOFFINT_SHIFT (2U)
+/*! BOFFINT
+ * 0b1..FLEXCAN module entered 'Bus Off' state
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK (0x8U)
+#define CAN_ESR1_RX_SHIFT (3U)
+/*! RX
+ * 0b1..FLEXCAN is transmitting a message
+ * 0b0..FLEXCAN is receiving a message
+ */
+#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK (0x30U)
+#define CAN_ESR1_FLTCONF_SHIFT (4U)
+/*! FLTCONF
+ * 0b00..Error Active
+ * 0b01..Error Passive
+ * 0b1x..Bus off
+ */
+#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK (0x40U)
+#define CAN_ESR1_TX_SHIFT (6U)
+/*! TX
+ * 0b1..FLEXCAN is transmitting a message
+ * 0b0..FLEXCAN is receiving a message
+ */
+#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK (0x80U)
+#define CAN_ESR1_IDLE_SHIFT (7U)
+/*! IDLE
+ * 0b1..CAN bus is now IDLE
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK (0x100U)
+#define CAN_ESR1_RXWRN_SHIFT (8U)
+/*! RXWRN
+ * 0b1..Rx_Err_Counter >= 96
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK (0x200U)
+#define CAN_ESR1_TXWRN_SHIFT (9U)
+/*! TXWRN
+ * 0b1..TX_Err_Counter >= 96
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK (0x400U)
+#define CAN_ESR1_STFERR_SHIFT (10U)
+/*! STFERR
+ * 0b1..A Stuffing Error occurred since last read of this register.
+ * 0b0..No such occurrence.
+ */
+#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK (0x800U)
+#define CAN_ESR1_FRMERR_SHIFT (11U)
+/*! FRMERR
+ * 0b1..A Form Error occurred since last read of this register
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK (0x1000U)
+#define CAN_ESR1_CRCERR_SHIFT (12U)
+/*! CRCERR
+ * 0b1..A CRC error occurred since last read of this register.
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK (0x2000U)
+#define CAN_ESR1_ACKERR_SHIFT (13U)
+/*! ACKERR
+ * 0b1..An ACK error occurred since last read of this register
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
+#define CAN_ESR1_BIT0ERR_SHIFT (14U)
+/*! BIT0ERR
+ * 0b1..At least one bit sent as dominant is received as recessive
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
+#define CAN_ESR1_BIT1ERR_SHIFT (15U)
+/*! BIT1ERR
+ * 0b1..At least one bit sent as recessive is received as dominant
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK (0x10000U)
+#define CAN_ESR1_RWRNINT_SHIFT (16U)
+/*! RWRNINT
+ * 0b1..The Rx error counter transition from < 96 to >= 96
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK (0x20000U)
+#define CAN_ESR1_TWRNINT_SHIFT (17U)
+/*! TWRNINT
+ * 0b1..The Tx error counter transition from < 96 to >= 96
+ * 0b0..No such occurrence
+ */
+#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK (0x40000U)
+#define CAN_ESR1_SYNCH_SHIFT (18U)
+/*! SYNCH
+ * 0b1..FlexCAN is synchronized to the CAN bus
+ * 0b0..FlexCAN is not synchronized to the CAN bus
+ */
+#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
+/*! @} */
+
+/*! @name IMASK2 - Interrupt Masks 2 Register */
+/*! @{ */
+#define CAN_IMASK2_BUFHM_MASK (0xFFFFFFFFU)
+#define CAN_IMASK2_BUFHM_SHIFT (0U)
+/*! BUFHM
+ * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
+ * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
+ */
+#define CAN_IMASK2_BUFHM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUFHM_SHIFT)) & CAN_IMASK2_BUFHM_MASK)
+/*! @} */
+
+/*! @name IMASK1 - Interrupt Masks 1 Register */
+/*! @{ */
+#define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
+#define CAN_IMASK1_BUFLM_SHIFT (0U)
+/*! BUFLM
+ * 0b00000000000000000000000000000001..The corresponding buffer Interrupt is enabled
+ * 0b00000000000000000000000000000000..The corresponding buffer Interrupt is disabled
+ */
+#define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
+/*! @} */
+
+/*! @name IFLAG2 - Interrupt Flags 2 Register */
+/*! @{ */
+#define CAN_IFLAG2_BUFHI_MASK (0xFFFFFFFFU)
+#define CAN_IFLAG2_BUFHI_SHIFT (0U)
+/*! BUFHI
+ * 0b00000000000000000000000000000001..The corresponding buffer has successfully completed transmission or reception
+ * 0b00000000000000000000000000000000..No such occurrence
+ */
+#define CAN_IFLAG2_BUFHI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUFHI_SHIFT)) & CAN_IFLAG2_BUFHI_MASK)
+/*! @} */
+
+/*! @name IFLAG1 - Interrupt Flags 1 Register */
+/*! @{ */
+#define CAN_IFLAG1_BUF4TO0I_MASK (0x1FU)
+#define CAN_IFLAG1_BUF4TO0I_SHIFT (0U)
+/*! BUF4TO0I
+ * 0b00001..Corresponding MB completed transmission/reception
+ * 0b00000..No such occurrence
+ */
+#define CAN_IFLAG1_BUF4TO0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO0I_SHIFT)) & CAN_IFLAG1_BUF4TO0I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK (0x20U)
+#define CAN_IFLAG1_BUF5I_SHIFT (5U)
+/*! BUF5I
+ * 0b1..MB5 completed transmission/reception or frames available in the FIFO
+ * 0b0..No such occurrence
+ */
+#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK (0x40U)
+#define CAN_IFLAG1_BUF6I_SHIFT (6U)
+/*! BUF6I
+ * 0b1..MB6 completed transmission/reception or FIFO almost full
+ * 0b0..No such occurrence
+ */
+#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK (0x80U)
+#define CAN_IFLAG1_BUF7I_SHIFT (7U)
+/*! BUF7I
+ * 0b1..MB7 completed transmission/reception or FIFO overflow
+ * 0b0..No such occurrence
+ */
+#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
+#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
+/*! BUF31TO8I
+ * 0b000000000000000000000001..The corresponding MB has successfully completed transmission or reception
+ * 0b000000000000000000000000..No such occurrence
+ */
+#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
+/*! @} */
+
+/*! @name CTRL2 - Control 2 Register */
+/*! @{ */
+#define CAN_CTRL2_EACEN_MASK (0x10000U)
+#define CAN_CTRL2_EACEN_SHIFT (16U)
+/*! EACEN
+ * 0b1..Enables the comparison of both Rx Mailbox filter's IDE and RTR bit with their corresponding bits within
+ * the incoming frame. Mask bits do apply.
+ * 0b0..Rx Mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
+ */
+#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK (0x20000U)
+#define CAN_CTRL2_RRS_SHIFT (17U)
+/*! RRS
+ * 0b1..Remote Request Frame is stored
+ * 0b0..Remote Response Frame is generated
+ */
+#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK (0x40000U)
+#define CAN_CTRL2_MRP_SHIFT (18U)
+/*! MRP
+ * 0b1..Matching starts from Mailboxes and continues on Rx FIFO
+ * 0b0..Matching starts from Rx FIFO and continues on Mailboxes
+ */
+#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK (0xF80000U)
+#define CAN_CTRL2_TASD_SHIFT (19U)
+#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK (0xF000000U)
+#define CAN_CTRL2_RFFN_SHIFT (24U)
+#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
+#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
+/*! WRMFRZ
+ * 0b1..Enable unrestricted write access to FlexCAN memory
+ * 0b0..Keep the write access restricted in some regions of FlexCAN memory
+ */
+#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
+/*! @} */
+
+/*! @name ESR2 - Error and Status 2 Register */
+/*! @{ */
+#define CAN_ESR2_IMB_MASK (0x2000U)
+#define CAN_ESR2_IMB_SHIFT (13U)
+/*! IMB
+ * 0b1..If ESR2[VPS] is asserted, there is at least one inactive Mailbox. LPTM content is the number of the first one.
+ * 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive Mailbox.
+ */
+#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK (0x4000U)
+#define CAN_ESR2_VPS_SHIFT (14U)
+/*! VPS
+ * 0b1..Contents of IMB and LPTM are valid
+ * 0b0..Contents of IMB and LPTM are invalid
+ */
+#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK (0x7F0000U)
+#define CAN_ESR2_LPTM_SHIFT (16U)
+#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
+/*! @} */
+
+/*! @name CRCR - CRC Register */
+/*! @{ */
+#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
+#define CAN_CRCR_TXCRC_SHIFT (0U)
+#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
+#define CAN_CRCR_MBCRC_SHIFT (16U)
+#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
+/*! @} */
+
+/*! @name RXFGMASK - Rx FIFO Global Mask Register */
+/*! @{ */
+#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
+#define CAN_RXFGMASK_FGM_SHIFT (0U)
+/*! FGM
+ * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
+ * 0b00000000000000000000000000000000..The corresponding bit in the filter is "don't care"
+ */
+#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
+/*! @} */
+
+/*! @name RXFIR - Rx FIFO Information Register */
+/*! @{ */
+#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
+#define CAN_RXFIR_IDHIT_SHIFT (0U)
+#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
+/*! @} */
+
+/*! @name DBG1 - Debug 1 register */
+/*! @{ */
+#define CAN_DBG1_CFSM_MASK (0x3FU)
+#define CAN_DBG1_CFSM_SHIFT (0U)
+/*! CFSM - CAN Finite State Machine
+ */
+#define CAN_DBG1_CFSM(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CFSM_SHIFT)) & CAN_DBG1_CFSM_MASK)
+#define CAN_DBG1_CBN_MASK (0x1F000000U)
+#define CAN_DBG1_CBN_SHIFT (24U)
+/*! CBN - CAN Bit Number
+ */
+#define CAN_DBG1_CBN(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG1_CBN_SHIFT)) & CAN_DBG1_CBN_MASK)
+/*! @} */
+
+/*! @name DBG2 - Debug 2 register */
+/*! @{ */
+#define CAN_DBG2_RMP_MASK (0x7FU)
+#define CAN_DBG2_RMP_SHIFT (0U)
+/*! RMP - Rx Matching Pointer
+ */
+#define CAN_DBG2_RMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_RMP_SHIFT)) & CAN_DBG2_RMP_MASK)
+#define CAN_DBG2_MPP_MASK (0x80U)
+#define CAN_DBG2_MPP_SHIFT (7U)
+/*! MPP - Matching Process in Progress
+ * 0b0..No matching process ongoing.
+ * 0b1..Matching process is in progress.
+ */
+#define CAN_DBG2_MPP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_MPP_SHIFT)) & CAN_DBG2_MPP_MASK)
+#define CAN_DBG2_TAP_MASK (0x7F00U)
+#define CAN_DBG2_TAP_SHIFT (8U)
+/*! TAP - Tx Arbitration Pointer
+ */
+#define CAN_DBG2_TAP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_TAP_SHIFT)) & CAN_DBG2_TAP_MASK)
+#define CAN_DBG2_APP_MASK (0x8000U)
+#define CAN_DBG2_APP_SHIFT (15U)
+/*! APP - Arbitration Process in Progress
+ * 0b0..No matching process ongoing.
+ * 0b1..Matching process is in progress.
+ */
+#define CAN_DBG2_APP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBG2_APP_SHIFT)) & CAN_DBG2_APP_MASK)
+/*! @} */
+
+/*! @name CS - Message Buffer 0 CS Register..Message Buffer 63 CS Register */
+/*! @{ */
+#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
+#define CAN_CS_TIME_STAMP_SHIFT (0U)
+/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
+ * Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
+ * appears on the CAN bus.
+ */
+#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK (0xF0000U)
+#define CAN_CS_DLC_SHIFT (16U)
+/*! DLC - Length of the data to be stored/transmitted.
+ */
+#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK (0x100000U)
+#define CAN_CS_RTR_SHIFT (20U)
+/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
+ */
+#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK (0x200000U)
+#define CAN_CS_IDE_SHIFT (21U)
+/*! IDE - ID Extended. One/zero for extended/standard format frame.
+ */
+#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK (0x400000U)
+#define CAN_CS_SRR_SHIFT (22U)
+/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
+ */
+#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK (0xF000000U)
+#define CAN_CS_CODE_SHIFT (24U)
+/*! CODE - Reserved
+ */
+#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
+/*! @} */
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT (64U)
+
+/*! @name ID - Message Buffer 0 ID Register..Message Buffer 63 ID Register */
+/*! @{ */
+#define CAN_ID_EXT_MASK (0x3FFFFU)
+#define CAN_ID_EXT_SHIFT (0U)
+/*! EXT - Contains extended (LOW word) identifier of message buffer.
+ */
+#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK (0x1FFC0000U)
+#define CAN_ID_STD_SHIFT (18U)
+/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
+ */
+#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK (0xE0000000U)
+#define CAN_ID_PRIO_SHIFT (29U)
+/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
+ * makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
+ * ID to define the transmission priority.
+ */
+#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
+/*! @} */
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT (64U)
+
+/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
+/*! @{ */
+#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
+#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
+/*! DATA_BYTE_3 - Data byte 3 of Rx/Tx frame.
+ */
+#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
+#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
+/*! DATA_BYTE_2 - Data byte 2 of Rx/Tx frame.
+ */
+#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
+#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
+/*! DATA_BYTE_1 - Data byte 1 of Rx/Tx frame.
+ */
+#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
+#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
+/*! DATA_BYTE_0 - Data byte 0 of Rx/Tx frame.
+ */
+#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
+/*! @} */
+
+/* The count of CAN_WORD0 */
+#define CAN_WORD0_COUNT (64U)
+
+/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
+/*! @{ */
+#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
+#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
+/*! DATA_BYTE_7 - Data byte 7 of Rx/Tx frame.
+ */
+#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
+#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
+/*! DATA_BYTE_6 - Data byte 6 of Rx/Tx frame.
+ */
+#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
+#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
+/*! DATA_BYTE_5 - Data byte 5 of Rx/Tx frame.
+ */
+#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
+#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
+/*! DATA_BYTE_4 - Data byte 4 of Rx/Tx frame.
+ */
+#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
+/*! @} */
+
+/* The count of CAN_WORD1 */
+#define CAN_WORD1_COUNT (64U)
+
+/*! @name RXIMR - Rx Individual Mask Registers */
+/*! @{ */
+#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
+#define CAN_RXIMR_MI_SHIFT (0U)
+/*! MI
+ * 0b00000000000000000000000000000001..The corresponding bit in the filter is checked
+ * 0b00000000000000000000000000000000..the corresponding bit in the filter is "don't care"
+ */
+#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
+/*! @} */
+
+/* The count of CAN_RXIMR */
+#define CAN_RXIMR_COUNT (64U)
+
+/*! @name GFWR - Glitch Filter Width Registers */
+/*! @{ */
+#define CAN_GFWR_GFWR_MASK (0xFFU)
+#define CAN_GFWR_GFWR_SHIFT (0U)
+#define CAN_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFWR_GFWR_SHIFT)) & CAN_GFWR_GFWR_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN1 base address */
+#define CAN1_BASE (0x401D0000u)
+/** Peripheral CAN1 base pointer */
+#define CAN1 ((CAN_Type *)CAN1_BASE)
+/** Peripheral CAN2 base address */
+#define CAN2_BASE (0x401D4000u)
+/** Peripheral CAN2 base pointer */
+#define CAN2 ((CAN_Type *)CAN2_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
+#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
+#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
+#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
+#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
+#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn }
+/* Backward compatibility */
+#define CAN_ECR_TXERRCNT_MASK CAN_ECR_TX_ERR_COUNTER_MASK
+#define CAN_ECR_TXERRCNT_SHIFT CAN_ECR_TX_ERR_COUNTER_SHIFT
+#define CAN_ECR_TXERRCNT(x) CAN_ECR_TX_ERR_COUNTER(x)
+#define CAN_ECR_RXERRCNT_MASK CAN_ECR_RX_ERR_COUNTER_MASK
+#define CAN_ECR_RXERRCNT_SHIFT CAN_ECR_RX_ERR_COUNTER_SHIFT
+#define CAN_ECR_RXERRCNT(x) CAN_ECR_RX_ERR_COUNTER(x)
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CCM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
+ * @{
+ */
+
+/** CCM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CCR; /**< CCM Control Register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __I uint32_t CSR; /**< CCM Status Register, offset: 0x8 */
+ __IO uint32_t CCSR; /**< CCM Clock Switcher Register, offset: 0xC */
+ __IO uint32_t CACRR; /**< CCM Arm Clock Root Register, offset: 0x10 */
+ __IO uint32_t CBCDR; /**< CCM Bus Clock Divider Register, offset: 0x14 */
+ __IO uint32_t CBCMR; /**< CCM Bus Clock Multiplexer Register, offset: 0x18 */
+ __IO uint32_t CSCMR1; /**< CCM Serial Clock Multiplexer Register 1, offset: 0x1C */
+ __IO uint32_t CSCMR2; /**< CCM Serial Clock Multiplexer Register 2, offset: 0x20 */
+ __IO uint32_t CSCDR1; /**< CCM Serial Clock Divider Register 1, offset: 0x24 */
+ __IO uint32_t CS1CDR; /**< CCM Clock Divider Register, offset: 0x28 */
+ __IO uint32_t CS2CDR; /**< CCM Clock Divider Register, offset: 0x2C */
+ __IO uint32_t CDCDR; /**< CCM D1 Clock Divider Register, offset: 0x30 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t CSCDR2; /**< CCM Serial Clock Divider Register 2, offset: 0x38 */
+ __IO uint32_t CSCDR3; /**< CCM Serial Clock Divider Register 3, offset: 0x3C */
+ uint8_t RESERVED_2[8];
+ __I uint32_t CDHIPR; /**< CCM Divider Handshake In-Process Register, offset: 0x48 */
+ uint8_t RESERVED_3[8];
+ __IO uint32_t CLPCR; /**< CCM Low Power Control Register, offset: 0x54 */
+ __IO uint32_t CISR; /**< CCM Interrupt Status Register, offset: 0x58 */
+ __IO uint32_t CIMR; /**< CCM Interrupt Mask Register, offset: 0x5C */
+ __IO uint32_t CCOSR; /**< CCM Clock Output Source Register, offset: 0x60 */
+ __IO uint32_t CGPR; /**< CCM General Purpose Register, offset: 0x64 */
+ __IO uint32_t CCGR0; /**< CCM Clock Gating Register 0, offset: 0x68 */
+ __IO uint32_t CCGR1; /**< CCM Clock Gating Register 1, offset: 0x6C */
+ __IO uint32_t CCGR2; /**< CCM Clock Gating Register 2, offset: 0x70 */
+ __IO uint32_t CCGR3; /**< CCM Clock Gating Register 3, offset: 0x74 */
+ __IO uint32_t CCGR4; /**< CCM Clock Gating Register 4, offset: 0x78 */
+ __IO uint32_t CCGR5; /**< CCM Clock Gating Register 5, offset: 0x7C */
+ __IO uint32_t CCGR6; /**< CCM Clock Gating Register 6, offset: 0x80 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t CMEOR; /**< CCM Module Enable Overide Register, offset: 0x88 */
+} CCM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CCM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CCM_Register_Masks CCM Register Masks
+ * @{
+ */
+
+/*! @name CCR - CCM Control Register */
+/*! @{ */
+#define CCM_CCR_OSCNT_MASK (0xFFU)
+#define CCM_CCR_OSCNT_SHIFT (0U)
+/*! OSCNT - Oscillator ready counter value. These bits define value of 32KHz counter, that serve as
+ * counter for oscillator lock time (count to n+1 ckil's). This is used for oscillator lock time.
+ * Current estimation is ~5ms. This counter will be used in ignition sequence and in wake from
+ * stop sequence if sbyos bit was defined, to notify that on chip oscillator output is ready for
+ * the dpll_ip to use and only then the gate in dpll_ip can be opened.
+ */
+#define CCM_CCR_OSCNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_OSCNT_SHIFT)) & CCM_CCR_OSCNT_MASK)
+#define CCM_CCR_COSC_EN_MASK (0x1000U)
+#define CCM_CCR_COSC_EN_SHIFT (12U)
+/*! COSC_EN
+ * 0b0..disable on chip oscillator
+ * 0b1..enable on chip oscillator
+ */
+#define CCM_CCR_COSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_COSC_EN_SHIFT)) & CCM_CCR_COSC_EN_MASK)
+#define CCM_CCR_REG_BYPASS_COUNT_MASK (0x7E00000U)
+#define CCM_CCR_REG_BYPASS_COUNT_SHIFT (21U)
+/*! REG_BYPASS_COUNT
+ * 0b000000..no delay
+ * 0b000001..1 CKIL clock period delay
+ * 0b111111..63 CKIL clock periods delay
+ */
+#define CCM_CCR_REG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_REG_BYPASS_COUNT_SHIFT)) & CCM_CCR_REG_BYPASS_COUNT_MASK)
+#define CCM_CCR_RBC_EN_MASK (0x8000000U)
+#define CCM_CCR_RBC_EN_SHIFT (27U)
+/*! RBC_EN
+ * 0b1..REG_BYPASS_COUNTER enabled.
+ * 0b0..REG_BYPASS_COUNTER disabled
+ */
+#define CCM_CCR_RBC_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCR_RBC_EN_SHIFT)) & CCM_CCR_RBC_EN_MASK)
+/*! @} */
+
+/*! @name CSR - CCM Status Register */
+/*! @{ */
+#define CCM_CSR_REF_EN_B_MASK (0x1U)
+#define CCM_CSR_REF_EN_B_SHIFT (0U)
+/*! REF_EN_B
+ * 0b0..value of CCM_REF_EN_B is '0'
+ * 0b1..value of CCM_REF_EN_B is '1'
+ */
+#define CCM_CSR_REF_EN_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_REF_EN_B_SHIFT)) & CCM_CSR_REF_EN_B_MASK)
+#define CCM_CSR_CAMP2_READY_MASK (0x8U)
+#define CCM_CSR_CAMP2_READY_SHIFT (3U)
+/*! CAMP2_READY
+ * 0b0..CAMP2 is not ready.
+ * 0b1..CAMP2 is ready.
+ */
+#define CCM_CSR_CAMP2_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_CAMP2_READY_SHIFT)) & CCM_CSR_CAMP2_READY_MASK)
+#define CCM_CSR_COSC_READY_MASK (0x20U)
+#define CCM_CSR_COSC_READY_SHIFT (5U)
+/*! COSC_READY
+ * 0b0..on board oscillator is not ready.
+ * 0b1..on board oscillator is ready.
+ */
+#define CCM_CSR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSR_COSC_READY_SHIFT)) & CCM_CSR_COSC_READY_MASK)
+/*! @} */
+
+/*! @name CCSR - CCM Clock Switcher Register */
+/*! @{ */
+#define CCM_CCSR_PLL3_SW_CLK_SEL_MASK (0x1U)
+#define CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT (0U)
+/*! PLL3_SW_CLK_SEL
+ * 0b0..pll3_main_clk
+ * 0b1..pll3 bypass clock
+ */
+#define CCM_CCSR_PLL3_SW_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCSR_PLL3_SW_CLK_SEL_SHIFT)) & CCM_CCSR_PLL3_SW_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name CACRR - CCM Arm Clock Root Register */
+/*! @{ */
+#define CCM_CACRR_ARM_PODF_MASK (0x7U)
+#define CCM_CACRR_ARM_PODF_SHIFT (0U)
+/*! ARM_PODF
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CACRR_ARM_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CACRR_ARM_PODF_SHIFT)) & CCM_CACRR_ARM_PODF_MASK)
+/*! @} */
+
+/*! @name CBCDR - CCM Bus Clock Divider Register */
+/*! @{ */
+#define CCM_CBCDR_SEMC_CLK_SEL_MASK (0x40U)
+#define CCM_CBCDR_SEMC_CLK_SEL_SHIFT (6U)
+/*! SEMC_CLK_SEL
+ * 0b0..Periph_clk output will be used as SEMC clock root
+ * 0b1..SEMC alternative clock will be used as SEMC clock root
+ */
+#define CCM_CBCDR_SEMC_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_CLK_SEL_MASK)
+#define CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK (0x80U)
+#define CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT (7U)
+/*! SEMC_ALT_CLK_SEL
+ * 0b0..PLL2 PFD2 will be selected as alternative clock for SEMC root clock
+ * 0b1..PLL3 PFD1 will be selected as alternative clock for SEMC root clock
+ */
+#define CCM_CBCDR_SEMC_ALT_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_ALT_CLK_SEL_SHIFT)) & CCM_CBCDR_SEMC_ALT_CLK_SEL_MASK)
+#define CCM_CBCDR_IPG_PODF_MASK (0x300U)
+#define CCM_CBCDR_IPG_PODF_SHIFT (8U)
+/*! IPG_PODF
+ * 0b00..divide by 1
+ * 0b01..divide by 2
+ * 0b10..divide by 3
+ * 0b11..divide by 4
+ */
+#define CCM_CBCDR_IPG_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_IPG_PODF_SHIFT)) & CCM_CBCDR_IPG_PODF_MASK)
+#define CCM_CBCDR_AHB_PODF_MASK (0x1C00U)
+#define CCM_CBCDR_AHB_PODF_SHIFT (10U)
+/*! AHB_PODF
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CBCDR_AHB_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_AHB_PODF_SHIFT)) & CCM_CBCDR_AHB_PODF_MASK)
+#define CCM_CBCDR_SEMC_PODF_MASK (0x70000U)
+#define CCM_CBCDR_SEMC_PODF_SHIFT (16U)
+/*! SEMC_PODF
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CBCDR_SEMC_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_SEMC_PODF_SHIFT)) & CCM_CBCDR_SEMC_PODF_MASK)
+#define CCM_CBCDR_PERIPH_CLK_SEL_MASK (0x2000000U)
+#define CCM_CBCDR_PERIPH_CLK_SEL_SHIFT (25U)
+/*! PERIPH_CLK_SEL
+ * 0b0..derive clock from pre_periph_clk_sel
+ * 0b1..derive clock from periph_clk2_clk_divided
+ */
+#define CCM_CBCDR_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCDR_PERIPH_CLK_SEL_MASK)
+#define CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x38000000U)
+#define CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT (27U)
+/*! PERIPH_CLK2_PODF
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CBCDR_PERIPH_CLK2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT)) & CCM_CBCDR_PERIPH_CLK2_PODF_MASK)
+/*! @} */
+
+/*! @name CBCMR - CCM Bus Clock Multiplexer Register */
+/*! @{ */
+#define CCM_CBCMR_LPSPI_CLK_SEL_MASK (0x30U)
+#define CCM_CBCMR_LPSPI_CLK_SEL_SHIFT (4U)
+/*! LPSPI_CLK_SEL
+ * 0b00..derive clock from PLL3 PFD1 clk
+ * 0b01..derive clock from PLL3 PFD0
+ * 0b10..derive clock from PLL2
+ * 0b11..derive clock from PLL2 PFD2
+ */
+#define CCM_CBCMR_LPSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_CLK_SEL_SHIFT)) & CCM_CBCMR_LPSPI_CLK_SEL_MASK)
+#define CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3000U)
+#define CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT (12U)
+/*! PERIPH_CLK2_SEL
+ * 0b00..derive clock from pll3_sw_clk
+ * 0b01..derive clock from osc_clk (pll1_ref_clk)
+ * 0b10..derive clock from pll2_bypass_clk
+ * 0b11..reserved
+ */
+#define CCM_CBCMR_PERIPH_CLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PERIPH_CLK2_SEL_SHIFT)) & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
+#define CCM_CBCMR_TRACE_CLK_SEL_MASK (0xC000U)
+#define CCM_CBCMR_TRACE_CLK_SEL_SHIFT (14U)
+/*! TRACE_CLK_SEL
+ * 0b00..derive clock from PLL2
+ * 0b01..derive clock from PLL2 PFD2
+ * 0b10..derive clock from PLL2 PFD0
+ * 0b11..derive clock from PLL2 PFD1
+ */
+#define CCM_CBCMR_TRACE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_TRACE_CLK_SEL_SHIFT)) & CCM_CBCMR_TRACE_CLK_SEL_MASK)
+#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0xC0000U)
+#define CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT (18U)
+/*! PRE_PERIPH_CLK_SEL
+ * 0b00..derive clock from PLL2
+ * 0b01..derive clock from PLL2 PFD2
+ * 0b10..derive clock from PLL2 PFD0
+ * 0b11..derive clock from divided PLL1
+ */
+#define CCM_CBCMR_PRE_PERIPH_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_PRE_PERIPH_CLK_SEL_SHIFT)) & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
+#define CCM_CBCMR_LCDIF_PODF_MASK (0x3800000U)
+#define CCM_CBCMR_LCDIF_PODF_SHIFT (23U)
+/*! LCDIF_PODF
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CBCMR_LCDIF_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LCDIF_PODF_SHIFT)) & CCM_CBCMR_LCDIF_PODF_MASK)
+#define CCM_CBCMR_LPSPI_PODF_MASK (0x1C000000U)
+#define CCM_CBCMR_LPSPI_PODF_SHIFT (26U)
+/*! LPSPI_PODF
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CBCMR_LPSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CBCMR_LPSPI_PODF_SHIFT)) & CCM_CBCMR_LPSPI_PODF_MASK)
+/*! @} */
+
+/*! @name CSCMR1 - CCM Serial Clock Multiplexer Register 1 */
+/*! @{ */
+#define CCM_CSCMR1_PERCLK_PODF_MASK (0x3FU)
+#define CCM_CSCMR1_PERCLK_PODF_SHIFT (0U)
+/*! PERCLK_PODF - Divider for perclk podf.
+ * 0b000000..Divide by 1
+ * 0b000001..Divide by 2
+ * 0b000010..Divide by 3
+ * 0b000011..Divide by 4
+ * 0b000100..Divide by 5
+ * 0b000101..Divide by 6
+ * 0b000110..Divide by 7
+ * 0b000111..Divide by 8
+ * 0b001000..Divide by 9
+ * 0b001001..Divide by 10
+ * 0b001010..Divide by 11
+ * 0b001011..Divide by 12
+ * 0b001100..Divide by 13
+ * 0b001101..Divide by 14
+ * 0b001110..Divide by 15
+ * 0b001111..Divide by 16
+ * 0b010000..Divide by 17
+ * 0b010001..Divide by 18
+ * 0b010010..Divide by 19
+ * 0b010011..Divide by 20
+ * 0b010100..Divide by 21
+ * 0b010101..Divide by 22
+ * 0b010110..Divide by 23
+ * 0b010111..Divide by 24
+ * 0b011000..Divide by 25
+ * 0b011001..Divide by 26
+ * 0b011010..Divide by 27
+ * 0b011011..Divide by 28
+ * 0b011100..Divide by 29
+ * 0b011101..Divide by 30
+ * 0b011110..Divide by 31
+ * 0b011111..Divide by 32
+ * 0b100000..Divide by 33
+ * 0b100001..Divide by 34
+ * 0b100010..Divide by 35
+ * 0b100011..Divide by 36
+ * 0b100100..Divide by 37
+ * 0b100101..Divide by 38
+ * 0b100110..Divide by 39
+ * 0b100111..Divide by 40
+ * 0b101000..Divide by 41
+ * 0b101001..Divide by 42
+ * 0b101010..Divide by 43
+ * 0b101011..Divide by 44
+ * 0b101100..Divide by 45
+ * 0b101101..Divide by 46
+ * 0b101110..Divide by 47
+ * 0b101111..Divide by 48
+ * 0b110000..Divide by 49
+ * 0b110001..Divide by 50
+ * 0b110010..Divide by 51
+ * 0b110011..Divide by 52
+ * 0b110100..Divide by 53
+ * 0b110101..Divide by 54
+ * 0b110110..Divide by 55
+ * 0b110111..Divide by 56
+ * 0b111000..Divide by 57
+ * 0b111001..Divide by 58
+ * 0b111010..Divide by 59
+ * 0b111011..Divide by 60
+ * 0b111100..Divide by 61
+ * 0b111101..Divide by 62
+ * 0b111110..Divide by 63
+ * 0b111111..Divide by 64
+ */
+#define CCM_CSCMR1_PERCLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_PODF_SHIFT)) & CCM_CSCMR1_PERCLK_PODF_MASK)
+#define CCM_CSCMR1_PERCLK_CLK_SEL_MASK (0x40U)
+#define CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT (6U)
+/*! PERCLK_CLK_SEL
+ * 0b0..derive clock from ipg clk root
+ * 0b1..derive clock from osc_clk
+ */
+#define CCM_CSCMR1_PERCLK_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_PERCLK_CLK_SEL_SHIFT)) & CCM_CSCMR1_PERCLK_CLK_SEL_MASK)
+#define CCM_CSCMR1_SAI1_CLK_SEL_MASK (0xC00U)
+#define CCM_CSCMR1_SAI1_CLK_SEL_SHIFT (10U)
+/*! SAI1_CLK_SEL
+ * 0b00..derive clock from PLL3 PFD2
+ * 0b01..derive clock from PLL5
+ * 0b10..derive clock from PLL4
+ * 0b11..Reserved
+ */
+#define CCM_CSCMR1_SAI1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI1_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI1_CLK_SEL_MASK)
+#define CCM_CSCMR1_SAI2_CLK_SEL_MASK (0x3000U)
+#define CCM_CSCMR1_SAI2_CLK_SEL_SHIFT (12U)
+/*! SAI2_CLK_SEL
+ * 0b00..derive clock from PLL3 PFD2
+ * 0b01..derive clock from PLL5
+ * 0b10..derive clock from PLL4
+ * 0b11..Reserved
+ */
+#define CCM_CSCMR1_SAI2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI2_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI2_CLK_SEL_MASK)
+#define CCM_CSCMR1_SAI3_CLK_SEL_MASK (0xC000U)
+#define CCM_CSCMR1_SAI3_CLK_SEL_SHIFT (14U)
+/*! SAI3_CLK_SEL
+ * 0b00..derive clock from PLL3 PFD2
+ * 0b01..derive clock from PLL5
+ * 0b10..derive clock from PLL4
+ * 0b11..Reserved
+ */
+#define CCM_CSCMR1_SAI3_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_SAI3_CLK_SEL_SHIFT)) & CCM_CSCMR1_SAI3_CLK_SEL_MASK)
+#define CCM_CSCMR1_USDHC1_CLK_SEL_MASK (0x10000U)
+#define CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT (16U)
+/*! USDHC1_CLK_SEL
+ * 0b0..derive clock from PLL2 PFD2
+ * 0b1..derive clock from PLL2 PFD0
+ */
+#define CCM_CSCMR1_USDHC1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC1_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC1_CLK_SEL_MASK)
+#define CCM_CSCMR1_USDHC2_CLK_SEL_MASK (0x20000U)
+#define CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT (17U)
+/*! USDHC2_CLK_SEL
+ * 0b0..derive clock from PLL2 PFD2
+ * 0b1..derive clock from PLL2 PFD0
+ */
+#define CCM_CSCMR1_USDHC2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_USDHC2_CLK_SEL_SHIFT)) & CCM_CSCMR1_USDHC2_CLK_SEL_MASK)
+#define CCM_CSCMR1_FLEXSPI_PODF_MASK (0x3800000U)
+#define CCM_CSCMR1_FLEXSPI_PODF_SHIFT (23U)
+/*! FLEXSPI_PODF
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CSCMR1_FLEXSPI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_PODF_SHIFT)) & CCM_CSCMR1_FLEXSPI_PODF_MASK)
+#define CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK (0x60000000U)
+#define CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT (29U)
+/*! FLEXSPI_CLK_SEL
+ * 0b00..derive clock from semc_clk_root_pre
+ * 0b01..derive clock from pll3_sw_clk
+ * 0b10..derive clock from PLL2 PFD2
+ * 0b11..derive clock from PLL3 PFD0
+ */
+#define CCM_CSCMR1_FLEXSPI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR1_FLEXSPI_CLK_SEL_SHIFT)) & CCM_CSCMR1_FLEXSPI_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name CSCMR2 - CCM Serial Clock Multiplexer Register 2 */
+/*! @{ */
+#define CCM_CSCMR2_CAN_CLK_PODF_MASK (0xFCU)
+#define CCM_CSCMR2_CAN_CLK_PODF_SHIFT (2U)
+/*! CAN_CLK_PODF - Divider for CAN clock podf.
+ * 0b000000..Divide by 1
+ * 0b000001..Divide by 2
+ * 0b000010..Divide by 3
+ * 0b000011..Divide by 4
+ * 0b000100..Divide by 5
+ * 0b000101..Divide by 6
+ * 0b000110..Divide by 7
+ * 0b000111..Divide by 8
+ * 0b001000..Divide by 9
+ * 0b001001..Divide by 10
+ * 0b001010..Divide by 11
+ * 0b001011..Divide by 12
+ * 0b001100..Divide by 13
+ * 0b001101..Divide by 14
+ * 0b001110..Divide by 15
+ * 0b001111..Divide by 16
+ * 0b010000..Divide by 17
+ * 0b010001..Divide by 18
+ * 0b010010..Divide by 19
+ * 0b010011..Divide by 20
+ * 0b010100..Divide by 21
+ * 0b010101..Divide by 22
+ * 0b010110..Divide by 23
+ * 0b010111..Divide by 24
+ * 0b011000..Divide by 25
+ * 0b011001..Divide by 26
+ * 0b011010..Divide by 27
+ * 0b011011..Divide by 28
+ * 0b011100..Divide by 29
+ * 0b011101..Divide by 30
+ * 0b011110..Divide by 31
+ * 0b011111..Divide by 32
+ * 0b100000..Divide by 33
+ * 0b100001..Divide by 34
+ * 0b100010..Divide by 35
+ * 0b100011..Divide by 36
+ * 0b100100..Divide by 37
+ * 0b100101..Divide by 38
+ * 0b100110..Divide by 39
+ * 0b100111..Divide by 40
+ * 0b101000..Divide by 41
+ * 0b101001..Divide by 42
+ * 0b101010..Divide by 43
+ * 0b101011..Divide by 44
+ * 0b101100..Divide by 45
+ * 0b101101..Divide by 46
+ * 0b101110..Divide by 47
+ * 0b101111..Divide by 48
+ * 0b110000..Divide by 49
+ * 0b110001..Divide by 50
+ * 0b110010..Divide by 51
+ * 0b110011..Divide by 52
+ * 0b110100..Divide by 53
+ * 0b110101..Divide by 54
+ * 0b110110..Divide by 55
+ * 0b110111..Divide by 56
+ * 0b111000..Divide by 57
+ * 0b111001..Divide by 58
+ * 0b111010..Divide by 59
+ * 0b111011..Divide by 60
+ * 0b111100..Divide by 61
+ * 0b111101..Divide by 62
+ * 0b111110..Divide by 63
+ * 0b111111..Divide by 64
+ */
+#define CCM_CSCMR2_CAN_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_PODF_SHIFT)) & CCM_CSCMR2_CAN_CLK_PODF_MASK)
+#define CCM_CSCMR2_CAN_CLK_SEL_MASK (0x300U)
+#define CCM_CSCMR2_CAN_CLK_SEL_SHIFT (8U)
+/*! CAN_CLK_SEL
+ * 0b00..derive clock from pll3_sw_clk divided clock (60M)
+ * 0b01..derive clock from osc_clk (24M)
+ * 0b10..derive clock from pll3_sw_clk divided clock (80M)
+ * 0b11..Disable FlexCAN clock
+ */
+#define CCM_CSCMR2_CAN_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_CAN_CLK_SEL_SHIFT)) & CCM_CSCMR2_CAN_CLK_SEL_MASK)
+#define CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK (0x180000U)
+#define CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT (19U)
+/*! FLEXIO2_CLK_SEL
+ * 0b00..derive clock from PLL4 divided clock
+ * 0b01..derive clock from PLL3 PFD2 clock
+ * 0b10..derive clock from PLL5 clock
+ * 0b11..derive clock from pll3_sw_clk
+ */
+#define CCM_CSCMR2_FLEXIO2_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCMR2_FLEXIO2_CLK_SEL_SHIFT)) & CCM_CSCMR2_FLEXIO2_CLK_SEL_MASK)
+/*! @} */
+
+/*! @name CSCDR1 - CCM Serial Clock Divider Register 1 */
+/*! @{ */
+#define CCM_CSCDR1_UART_CLK_PODF_MASK (0x3FU)
+#define CCM_CSCDR1_UART_CLK_PODF_SHIFT (0U)
+/*! UART_CLK_PODF - Divider for uart clock podf.
+ * 0b000000..Divide by 1
+ * 0b000001..Divide by 2
+ * 0b000010..Divide by 3
+ * 0b000011..Divide by 4
+ * 0b000100..Divide by 5
+ * 0b000101..Divide by 6
+ * 0b000110..Divide by 7
+ * 0b000111..Divide by 8
+ * 0b001000..Divide by 9
+ * 0b001001..Divide by 10
+ * 0b001010..Divide by 11
+ * 0b001011..Divide by 12
+ * 0b001100..Divide by 13
+ * 0b001101..Divide by 14
+ * 0b001110..Divide by 15
+ * 0b001111..Divide by 16
+ * 0b010000..Divide by 17
+ * 0b010001..Divide by 18
+ * 0b010010..Divide by 19
+ * 0b010011..Divide by 20
+ * 0b010100..Divide by 21
+ * 0b010101..Divide by 22
+ * 0b010110..Divide by 23
+ * 0b010111..Divide by 24
+ * 0b011000..Divide by 25
+ * 0b011001..Divide by 26
+ * 0b011010..Divide by 27
+ * 0b011011..Divide by 28
+ * 0b011100..Divide by 29
+ * 0b011101..Divide by 30
+ * 0b011110..Divide by 31
+ * 0b011111..Divide by 32
+ * 0b100000..Divide by 33
+ * 0b100001..Divide by 34
+ * 0b100010..Divide by 35
+ * 0b100011..Divide by 36
+ * 0b100100..Divide by 37
+ * 0b100101..Divide by 38
+ * 0b100110..Divide by 39
+ * 0b100111..Divide by 40
+ * 0b101000..Divide by 41
+ * 0b101001..Divide by 42
+ * 0b101010..Divide by 43
+ * 0b101011..Divide by 44
+ * 0b101100..Divide by 45
+ * 0b101101..Divide by 46
+ * 0b101110..Divide by 47
+ * 0b101111..Divide by 48
+ * 0b110000..Divide by 49
+ * 0b110001..Divide by 50
+ * 0b110010..Divide by 51
+ * 0b110011..Divide by 52
+ * 0b110100..Divide by 53
+ * 0b110101..Divide by 54
+ * 0b110110..Divide by 55
+ * 0b110111..Divide by 56
+ * 0b111000..Divide by 57
+ * 0b111001..Divide by 58
+ * 0b111010..Divide by 59
+ * 0b111011..Divide by 60
+ * 0b111100..Divide by 61
+ * 0b111101..Divide by 62
+ * 0b111110..Divide by 63
+ * 0b111111..Divide by 64
+ */
+#define CCM_CSCDR1_UART_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_PODF_SHIFT)) & CCM_CSCDR1_UART_CLK_PODF_MASK)
+#define CCM_CSCDR1_UART_CLK_SEL_MASK (0x40U)
+#define CCM_CSCDR1_UART_CLK_SEL_SHIFT (6U)
+/*! UART_CLK_SEL
+ * 0b0..derive clock from pll3_80m
+ * 0b1..derive clock from osc_clk
+ */
+#define CCM_CSCDR1_UART_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_UART_CLK_SEL_SHIFT)) & CCM_CSCDR1_UART_CLK_SEL_MASK)
+#define CCM_CSCDR1_USDHC1_PODF_MASK (0x3800U)
+#define CCM_CSCDR1_USDHC1_PODF_SHIFT (11U)
+/*! USDHC1_PODF
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CSCDR1_USDHC1_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC1_PODF_SHIFT)) & CCM_CSCDR1_USDHC1_PODF_MASK)
+#define CCM_CSCDR1_USDHC2_PODF_MASK (0x70000U)
+#define CCM_CSCDR1_USDHC2_PODF_SHIFT (16U)
+/*! USDHC2_PODF
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CSCDR1_USDHC2_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_USDHC2_PODF_SHIFT)) & CCM_CSCDR1_USDHC2_PODF_MASK)
+#define CCM_CSCDR1_TRACE_PODF_MASK (0x6000000U)
+#define CCM_CSCDR1_TRACE_PODF_SHIFT (25U)
+/*! TRACE_PODF
+ * 0b00..divide by 1
+ * 0b01..divide by 2
+ * 0b10..divide by 3
+ * 0b11..divide by 4
+ */
+#define CCM_CSCDR1_TRACE_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR1_TRACE_PODF_SHIFT)) & CCM_CSCDR1_TRACE_PODF_MASK)
+/*! @} */
+
+/*! @name CS1CDR - CCM Clock Divider Register */
+/*! @{ */
+#define CCM_CS1CDR_SAI1_CLK_PODF_MASK (0x3FU)
+#define CCM_CS1CDR_SAI1_CLK_PODF_SHIFT (0U)
+/*! SAI1_CLK_PODF - Divider for sai1 clock podf. The input clock to this divider should be lower
+ * than 300Mhz, the predivider can be used to achieve this.
+ * 0b000000..Divide by 1
+ * 0b000001..Divide by 2
+ * 0b000010..Divide by 3
+ * 0b000011..Divide by 4
+ * 0b000100..Divide by 5
+ * 0b000101..Divide by 6
+ * 0b000110..Divide by 7
+ * 0b000111..Divide by 8
+ * 0b001000..Divide by 9
+ * 0b001001..Divide by 10
+ * 0b001010..Divide by 11
+ * 0b001011..Divide by 12
+ * 0b001100..Divide by 13
+ * 0b001101..Divide by 14
+ * 0b001110..Divide by 15
+ * 0b001111..Divide by 16
+ * 0b010000..Divide by 17
+ * 0b010001..Divide by 18
+ * 0b010010..Divide by 19
+ * 0b010011..Divide by 20
+ * 0b010100..Divide by 21
+ * 0b010101..Divide by 22
+ * 0b010110..Divide by 23
+ * 0b010111..Divide by 24
+ * 0b011000..Divide by 25
+ * 0b011001..Divide by 26
+ * 0b011010..Divide by 27
+ * 0b011011..Divide by 28
+ * 0b011100..Divide by 29
+ * 0b011101..Divide by 30
+ * 0b011110..Divide by 31
+ * 0b011111..Divide by 32
+ * 0b100000..Divide by 33
+ * 0b100001..Divide by 34
+ * 0b100010..Divide by 35
+ * 0b100011..Divide by 36
+ * 0b100100..Divide by 37
+ * 0b100101..Divide by 38
+ * 0b100110..Divide by 39
+ * 0b100111..Divide by 40
+ * 0b101000..Divide by 41
+ * 0b101001..Divide by 42
+ * 0b101010..Divide by 43
+ * 0b101011..Divide by 44
+ * 0b101100..Divide by 45
+ * 0b101101..Divide by 46
+ * 0b101110..Divide by 47
+ * 0b101111..Divide by 48
+ * 0b110000..Divide by 49
+ * 0b110001..Divide by 50
+ * 0b110010..Divide by 51
+ * 0b110011..Divide by 52
+ * 0b110100..Divide by 53
+ * 0b110101..Divide by 54
+ * 0b110110..Divide by 55
+ * 0b110111..Divide by 56
+ * 0b111000..Divide by 57
+ * 0b111001..Divide by 58
+ * 0b111010..Divide by 59
+ * 0b111011..Divide by 60
+ * 0b111100..Divide by 61
+ * 0b111101..Divide by 62
+ * 0b111110..Divide by 63
+ * 0b111111..Divide by 64
+ */
+#define CCM_CS1CDR_SAI1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PODF_MASK)
+#define CCM_CS1CDR_SAI1_CLK_PRED_MASK (0x1C0U)
+#define CCM_CS1CDR_SAI1_CLK_PRED_SHIFT (6U)
+/*! SAI1_CLK_PRED
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CS1CDR_SAI1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI1_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI1_CLK_PRED_MASK)
+#define CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK (0xE00U)
+#define CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT (9U)
+/*! FLEXIO2_CLK_PRED
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CS1CDR_FLEXIO2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PRED_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PRED_MASK)
+#define CCM_CS1CDR_SAI3_CLK_PODF_MASK (0x3F0000U)
+#define CCM_CS1CDR_SAI3_CLK_PODF_SHIFT (16U)
+/*! SAI3_CLK_PODF - Divider for sai3 clock podf. The input clock to this divider should be lower
+ * than 300Mhz, the predivider can be used to achieve this.
+ * 0b000000..Divide by 1
+ * 0b000001..Divide by 2
+ * 0b000010..Divide by 3
+ * 0b000011..Divide by 4
+ * 0b000100..Divide by 5
+ * 0b000101..Divide by 6
+ * 0b000110..Divide by 7
+ * 0b000111..Divide by 8
+ * 0b001000..Divide by 9
+ * 0b001001..Divide by 10
+ * 0b001010..Divide by 11
+ * 0b001011..Divide by 12
+ * 0b001100..Divide by 13
+ * 0b001101..Divide by 14
+ * 0b001110..Divide by 15
+ * 0b001111..Divide by 16
+ * 0b010000..Divide by 17
+ * 0b010001..Divide by 18
+ * 0b010010..Divide by 19
+ * 0b010011..Divide by 20
+ * 0b010100..Divide by 21
+ * 0b010101..Divide by 22
+ * 0b010110..Divide by 23
+ * 0b010111..Divide by 24
+ * 0b011000..Divide by 25
+ * 0b011001..Divide by 26
+ * 0b011010..Divide by 27
+ * 0b011011..Divide by 28
+ * 0b011100..Divide by 29
+ * 0b011101..Divide by 30
+ * 0b011110..Divide by 31
+ * 0b011111..Divide by 32
+ * 0b100000..Divide by 33
+ * 0b100001..Divide by 34
+ * 0b100010..Divide by 35
+ * 0b100011..Divide by 36
+ * 0b100100..Divide by 37
+ * 0b100101..Divide by 38
+ * 0b100110..Divide by 39
+ * 0b100111..Divide by 40
+ * 0b101000..Divide by 41
+ * 0b101001..Divide by 42
+ * 0b101010..Divide by 43
+ * 0b101011..Divide by 44
+ * 0b101100..Divide by 45
+ * 0b101101..Divide by 46
+ * 0b101110..Divide by 47
+ * 0b101111..Divide by 48
+ * 0b110000..Divide by 49
+ * 0b110001..Divide by 50
+ * 0b110010..Divide by 51
+ * 0b110011..Divide by 52
+ * 0b110100..Divide by 53
+ * 0b110101..Divide by 54
+ * 0b110110..Divide by 55
+ * 0b110111..Divide by 56
+ * 0b111000..Divide by 57
+ * 0b111001..Divide by 58
+ * 0b111010..Divide by 59
+ * 0b111011..Divide by 60
+ * 0b111100..Divide by 61
+ * 0b111101..Divide by 62
+ * 0b111110..Divide by 63
+ * 0b111111..Divide by 64
+ */
+#define CCM_CS1CDR_SAI3_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PODF_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PODF_MASK)
+#define CCM_CS1CDR_SAI3_CLK_PRED_MASK (0x1C00000U)
+#define CCM_CS1CDR_SAI3_CLK_PRED_SHIFT (22U)
+/*! SAI3_CLK_PRED
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CS1CDR_SAI3_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_SAI3_CLK_PRED_SHIFT)) & CCM_CS1CDR_SAI3_CLK_PRED_MASK)
+#define CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK (0xE000000U)
+#define CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT (25U)
+/*! FLEXIO2_CLK_PODF - Divider for flexio2 clock. Divider should be updated when output clock is gated.
+ * 0b000..Divide by 1
+ * 0b001..Divide by 2
+ * 0b010..Divide by 3
+ * 0b011..Divide by 4
+ * 0b100..Divide by 5
+ * 0b101..Divide by 6
+ * 0b110..Divide by 7
+ * 0b111..Divide by 8
+ */
+#define CCM_CS1CDR_FLEXIO2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS1CDR_FLEXIO2_CLK_PODF_SHIFT)) & CCM_CS1CDR_FLEXIO2_CLK_PODF_MASK)
+/*! @} */
+
+/*! @name CS2CDR - CCM Clock Divider Register */
+/*! @{ */
+#define CCM_CS2CDR_SAI2_CLK_PODF_MASK (0x3FU)
+#define CCM_CS2CDR_SAI2_CLK_PODF_SHIFT (0U)
+/*! SAI2_CLK_PODF - Divider for sai2 clock podf. The input clock to this divider should be lower
+ * than 300Mhz, the predivider can be used to achieve this.
+ * 0b000000..Divide by 1
+ * 0b000001..Divide by 2
+ * 0b000010..Divide by 3
+ * 0b000011..Divide by 4
+ * 0b000100..Divide by 5
+ * 0b000101..Divide by 6
+ * 0b000110..Divide by 7
+ * 0b000111..Divide by 8
+ * 0b001000..Divide by 9
+ * 0b001001..Divide by 10
+ * 0b001010..Divide by 11
+ * 0b001011..Divide by 12
+ * 0b001100..Divide by 13
+ * 0b001101..Divide by 14
+ * 0b001110..Divide by 15
+ * 0b001111..Divide by 16
+ * 0b010000..Divide by 17
+ * 0b010001..Divide by 18
+ * 0b010010..Divide by 19
+ * 0b010011..Divide by 20
+ * 0b010100..Divide by 21
+ * 0b010101..Divide by 22
+ * 0b010110..Divide by 23
+ * 0b010111..Divide by 24
+ * 0b011000..Divide by 25
+ * 0b011001..Divide by 26
+ * 0b011010..Divide by 27
+ * 0b011011..Divide by 28
+ * 0b011100..Divide by 29
+ * 0b011101..Divide by 30
+ * 0b011110..Divide by 31
+ * 0b011111..Divide by 32
+ * 0b100000..Divide by 33
+ * 0b100001..Divide by 34
+ * 0b100010..Divide by 35
+ * 0b100011..Divide by 36
+ * 0b100100..Divide by 37
+ * 0b100101..Divide by 38
+ * 0b100110..Divide by 39
+ * 0b100111..Divide by 40
+ * 0b101000..Divide by 41
+ * 0b101001..Divide by 42
+ * 0b101010..Divide by 43
+ * 0b101011..Divide by 44
+ * 0b101100..Divide by 45
+ * 0b101101..Divide by 46
+ * 0b101110..Divide by 47
+ * 0b101111..Divide by 48
+ * 0b110000..Divide by 49
+ * 0b110001..Divide by 50
+ * 0b110010..Divide by 51
+ * 0b110011..Divide by 52
+ * 0b110100..Divide by 53
+ * 0b110101..Divide by 54
+ * 0b110110..Divide by 55
+ * 0b110111..Divide by 56
+ * 0b111000..Divide by 57
+ * 0b111001..Divide by 58
+ * 0b111010..Divide by 59
+ * 0b111011..Divide by 60
+ * 0b111100..Divide by 61
+ * 0b111101..Divide by 62
+ * 0b111110..Divide by 63
+ * 0b111111..Divide by 64
+ */
+#define CCM_CS2CDR_SAI2_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PODF_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PODF_MASK)
+#define CCM_CS2CDR_SAI2_CLK_PRED_MASK (0x1C0U)
+#define CCM_CS2CDR_SAI2_CLK_PRED_SHIFT (6U)
+/*! SAI2_CLK_PRED
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CS2CDR_SAI2_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CS2CDR_SAI2_CLK_PRED_SHIFT)) & CCM_CS2CDR_SAI2_CLK_PRED_MASK)
+/*! @} */
+
+/*! @name CDCDR - CCM D1 Clock Divider Register */
+/*! @{ */
+#define CCM_CDCDR_FLEXIO1_CLK_SEL_MASK (0x180U)
+#define CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT (7U)
+/*! FLEXIO1_CLK_SEL
+ * 0b00..derive clock from PLL4
+ * 0b01..derive clock from PLL3 PFD2
+ * 0b10..derive clock from PLL5
+ * 0b11..derive clock from pll3_sw_clk
+ */
+#define CCM_CDCDR_FLEXIO1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_SEL_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_SEL_MASK)
+#define CCM_CDCDR_FLEXIO1_CLK_PODF_MASK (0xE00U)
+#define CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT (9U)
+/*! FLEXIO1_CLK_PODF - Divider for flexio1 clock podf. Divider should be updated when output clock is gated.
+ * 0b000..Divide by 1
+ * 0b001..Divide by 2
+ * 0b010..Divide by 3
+ * 0b011..Divide by 4
+ * 0b100..Divide by 5
+ * 0b101..Divide by 6
+ * 0b110..Divide by 7
+ * 0b111..Divide by 8
+ */
+#define CCM_CDCDR_FLEXIO1_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PODF_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PODF_MASK)
+#define CCM_CDCDR_FLEXIO1_CLK_PRED_MASK (0x7000U)
+#define CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT (12U)
+/*! FLEXIO1_CLK_PRED - Divider for flexio1 clock pred. Divider should be updated when output clock is gated.
+ * 0b000..Divide by 1
+ * 0b001..Divide by 2
+ * 0b010..Divide by 3
+ * 0b011..Divide by 4
+ * 0b100..Divide by 5
+ * 0b101..Divide by 6
+ * 0b110..Divide by 7
+ * 0b111..Divide by 8
+ */
+#define CCM_CDCDR_FLEXIO1_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_FLEXIO1_CLK_PRED_SHIFT)) & CCM_CDCDR_FLEXIO1_CLK_PRED_MASK)
+#define CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x300000U)
+#define CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT (20U)
+/*! SPDIF0_CLK_SEL
+ * 0b00..derive clock from PLL4
+ * 0b01..derive clock from PLL3 PFD2
+ * 0b10..derive clock from PLL5
+ * 0b11..derive clock from pll3_sw_clk
+ */
+#define CCM_CDCDR_SPDIF0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_SEL_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_SEL_MASK)
+#define CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x1C00000U)
+#define CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT (22U)
+/*! SPDIF0_CLK_PODF - Divider for spdif0 clock podf. Divider should be updated when output clock is gated.
+ * 0b000..Divide by 1
+ * 0b001..Divide by 2
+ * 0b010..Divide by 3
+ * 0b011..Divide by 4
+ * 0b100..Divide by 5
+ * 0b101..Divide by 6
+ * 0b110..Divide by 7
+ * 0b111..Divide by 8
+ */
+#define CCM_CDCDR_SPDIF0_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PODF_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PODF_MASK)
+#define CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0xE000000U)
+#define CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT (25U)
+/*! SPDIF0_CLK_PRED - Divider for spdif0 clock pred. Divider should be updated when output clock is gated.
+ * 0b000..Divide by 1
+ * 0b001..Divide by 2
+ * 0b010..Divide by 3
+ * 0b011..Divide by 4
+ * 0b100..Divide by 5
+ * 0b101..Divide by 6
+ * 0b110..Divide by 7
+ * 0b111..Divide by 8
+ */
+#define CCM_CDCDR_SPDIF0_CLK_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDCDR_SPDIF0_CLK_PRED_SHIFT)) & CCM_CDCDR_SPDIF0_CLK_PRED_MASK)
+/*! @} */
+
+/*! @name CSCDR2 - CCM Serial Clock Divider Register 2 */
+/*! @{ */
+#define CCM_CSCDR2_LCDIF_PRED_MASK (0x7000U)
+#define CCM_CSCDR2_LCDIF_PRED_SHIFT (12U)
+/*! LCDIF_PRED
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CSCDR2_LCDIF_PRED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRED_SHIFT)) & CCM_CSCDR2_LCDIF_PRED_MASK)
+#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK (0x38000U)
+#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT (15U)
+/*! LCDIF_PRE_CLK_SEL
+ * 0b000..derive clock from PLL2
+ * 0b001..derive clock from PLL3 PFD3
+ * 0b010..derive clock from PLL5
+ * 0b011..derive clock from PLL2 PFD0
+ * 0b100..derive clock from PLL2 PFD1
+ * 0b101..derive clock from PLL3 PFD1
+ */
+#define CCM_CSCDR2_LCDIF_PRE_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LCDIF_PRE_CLK_SEL_SHIFT)) & CCM_CSCDR2_LCDIF_PRE_CLK_SEL_MASK)
+#define CCM_CSCDR2_LPI2C_CLK_SEL_MASK (0x40000U)
+#define CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT (18U)
+/*! LPI2C_CLK_SEL
+ * 0b0..derive clock from pll3_60m
+ * 0b1..derive clock from osc_clk
+ */
+#define CCM_CSCDR2_LPI2C_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_SEL_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_SEL_MASK)
+#define CCM_CSCDR2_LPI2C_CLK_PODF_MASK (0x1F80000U)
+#define CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT (19U)
+/*! LPI2C_CLK_PODF - Divider for lpi2c clock podf. Divider should be updated when output clock is
+ * gated. The input clock to this divider should be lower than 300Mhz, the predivider can be used
+ * to achieve this.
+ * 0b000000..Divide by 1
+ * 0b000001..Divide by 2
+ * 0b000010..Divide by 3
+ * 0b000011..Divide by 4
+ * 0b000100..Divide by 5
+ * 0b000101..Divide by 6
+ * 0b000110..Divide by 7
+ * 0b000111..Divide by 8
+ * 0b001000..Divide by 9
+ * 0b001001..Divide by 10
+ * 0b001010..Divide by 11
+ * 0b001011..Divide by 12
+ * 0b001100..Divide by 13
+ * 0b001101..Divide by 14
+ * 0b001110..Divide by 15
+ * 0b001111..Divide by 16
+ * 0b010000..Divide by 17
+ * 0b010001..Divide by 18
+ * 0b010010..Divide by 19
+ * 0b010011..Divide by 20
+ * 0b010100..Divide by 21
+ * 0b010101..Divide by 22
+ * 0b010110..Divide by 23
+ * 0b010111..Divide by 24
+ * 0b011000..Divide by 25
+ * 0b011001..Divide by 26
+ * 0b011010..Divide by 27
+ * 0b011011..Divide by 28
+ * 0b011100..Divide by 29
+ * 0b011101..Divide by 30
+ * 0b011110..Divide by 31
+ * 0b011111..Divide by 32
+ * 0b100000..Divide by 33
+ * 0b100001..Divide by 34
+ * 0b100010..Divide by 35
+ * 0b100011..Divide by 36
+ * 0b100100..Divide by 37
+ * 0b100101..Divide by 38
+ * 0b100110..Divide by 39
+ * 0b100111..Divide by 40
+ * 0b101000..Divide by 41
+ * 0b101001..Divide by 42
+ * 0b101010..Divide by 43
+ * 0b101011..Divide by 44
+ * 0b101100..Divide by 45
+ * 0b101101..Divide by 46
+ * 0b101110..Divide by 47
+ * 0b101111..Divide by 48
+ * 0b110000..Divide by 49
+ * 0b110001..Divide by 50
+ * 0b110010..Divide by 51
+ * 0b110011..Divide by 52
+ * 0b110100..Divide by 53
+ * 0b110101..Divide by 54
+ * 0b110110..Divide by 55
+ * 0b110111..Divide by 56
+ * 0b111000..Divide by 57
+ * 0b111001..Divide by 58
+ * 0b111010..Divide by 59
+ * 0b111011..Divide by 60
+ * 0b111100..Divide by 61
+ * 0b111101..Divide by 62
+ * 0b111110..Divide by 63
+ * 0b111111..Divide by 64
+ */
+#define CCM_CSCDR2_LPI2C_CLK_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR2_LPI2C_CLK_PODF_SHIFT)) & CCM_CSCDR2_LPI2C_CLK_PODF_MASK)
+/*! @} */
+
+/*! @name CSCDR3 - CCM Serial Clock Divider Register 3 */
+/*! @{ */
+#define CCM_CSCDR3_CSI_CLK_SEL_MASK (0x600U)
+#define CCM_CSCDR3_CSI_CLK_SEL_SHIFT (9U)
+/*! CSI_CLK_SEL
+ * 0b00..derive clock from osc_clk (24M)
+ * 0b01..derive clock from PLL2 PFD2
+ * 0b10..derive clock from pll3_120M
+ * 0b11..derive clock from PLL3 PFD1
+ */
+#define CCM_CSCDR3_CSI_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_CLK_SEL_SHIFT)) & CCM_CSCDR3_CSI_CLK_SEL_MASK)
+#define CCM_CSCDR3_CSI_PODF_MASK (0x3800U)
+#define CCM_CSCDR3_CSI_PODF_SHIFT (11U)
+/*! CSI_PODF
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CSCDR3_CSI_PODF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CSCDR3_CSI_PODF_SHIFT)) & CCM_CSCDR3_CSI_PODF_MASK)
+/*! @} */
+
+/*! @name CDHIPR - CCM Divider Handshake In-Process Register */
+/*! @{ */
+#define CCM_CDHIPR_SEMC_PODF_BUSY_MASK (0x1U)
+#define CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT (0U)
+/*! SEMC_PODF_BUSY
+ * 0b0..divider is not busy and its value represents the actual division.
+ * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
+ * value of the division factor, and after the handshake the written value of the semc_podf will be applied.
+ */
+#define CCM_CDHIPR_SEMC_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_SEMC_PODF_BUSY_SHIFT)) & CCM_CDHIPR_SEMC_PODF_BUSY_MASK)
+#define CCM_CDHIPR_AHB_PODF_BUSY_MASK (0x2U)
+#define CCM_CDHIPR_AHB_PODF_BUSY_SHIFT (1U)
+/*! AHB_PODF_BUSY
+ * 0b0..divider is not busy and its value represents the actual division.
+ * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
+ * value of the division factor, and after the handshake the written value of the ahb_podf will be applied.
+ */
+#define CCM_CDHIPR_AHB_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_AHB_PODF_BUSY_SHIFT)) & CCM_CDHIPR_AHB_PODF_BUSY_MASK)
+#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK (0x8U)
+#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT (3U)
+/*! PERIPH2_CLK_SEL_BUSY
+ * 0b0..mux is not busy and its value represents the actual division.
+ * 0b1..mux is busy with handshake process with module. The value read in the periph2_clk_sel represents the
+ * previous value of select, and after the handshake periph2_clk_sel value will be applied.
+ */
+#define CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY_MASK)
+#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK (0x20U)
+#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT (5U)
+/*! PERIPH_CLK_SEL_BUSY
+ * 0b0..mux is not busy and its value represents the actual division.
+ * 0b1..mux is busy with handshake process with module. The value read in the periph_clk_sel represents the
+ * previous value of select, and after the handshake periph_clk_sel value will be applied.
+ */
+#define CCM_CDHIPR_PERIPH_CLK_SEL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_SHIFT)) & CCM_CDHIPR_PERIPH_CLK_SEL_BUSY_MASK)
+#define CCM_CDHIPR_ARM_PODF_BUSY_MASK (0x10000U)
+#define CCM_CDHIPR_ARM_PODF_BUSY_SHIFT (16U)
+/*! ARM_PODF_BUSY
+ * 0b0..divider is not busy and its value represents the actual division.
+ * 0b1..divider is busy with handshake process with module. The value read in the divider represents the previous
+ * value of the division factor, and after the handshake the written value of the arm_podf will be applied.
+ */
+#define CCM_CDHIPR_ARM_PODF_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CDHIPR_ARM_PODF_BUSY_SHIFT)) & CCM_CDHIPR_ARM_PODF_BUSY_MASK)
+/*! @} */
+
+/*! @name CLPCR - CCM Low Power Control Register */
+/*! @{ */
+#define CCM_CLPCR_LPM_MASK (0x3U)
+#define CCM_CLPCR_LPM_SHIFT (0U)
+/*! LPM
+ * 0b00..Remain in run mode
+ * 0b01..Transfer to wait mode
+ * 0b10..Transfer to stop mode
+ * 0b11..Reserved
+ */
+#define CCM_CLPCR_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_LPM_SHIFT)) & CCM_CLPCR_LPM_MASK)
+#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK (0x20U)
+#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT (5U)
+/*! ARM_CLK_DIS_ON_LPM
+ * 0b0..ARM clock enabled on wait mode.
+ * 0b1..ARM clock disabled on wait mode. .
+ */
+#define CCM_CLPCR_ARM_CLK_DIS_ON_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_ARM_CLK_DIS_ON_LPM_SHIFT)) & CCM_CLPCR_ARM_CLK_DIS_ON_LPM_MASK)
+#define CCM_CLPCR_SBYOS_MASK (0x40U)
+#define CCM_CLPCR_SBYOS_SHIFT (6U)
+/*! SBYOS
+ * 0b0..On-chip oscillator will not be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will remain
+ * asserted - '0' and cosc_pwrdown will remain de asserted - '0')
+ * 0b1..On-chip oscillator will be powered down, after next entrance to STOP mode. (CCM_REF_EN_B will be
+ * deasserted - '1' and cosc_pwrdown will be asserted - '1'). When returning from STOP mode, external oscillator will
+ * be enabled again, on-chip oscillator will return to oscillator mode, and after oscnt count, CCM will
+ * continue with the exit from the STOP mode process.
+ */
+#define CCM_CLPCR_SBYOS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_SBYOS_SHIFT)) & CCM_CLPCR_SBYOS_MASK)
+#define CCM_CLPCR_DIS_REF_OSC_MASK (0x80U)
+#define CCM_CLPCR_DIS_REF_OSC_SHIFT (7U)
+/*! DIS_REF_OSC
+ * 0b0..external high frequency oscillator will be enabled, i.e. CCM_REF_EN_B = '0'.
+ * 0b1..external high frequency oscillator will be disabled, i.e. CCM_REF_EN_B = '1'
+ */
+#define CCM_CLPCR_DIS_REF_OSC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_DIS_REF_OSC_SHIFT)) & CCM_CLPCR_DIS_REF_OSC_MASK)
+#define CCM_CLPCR_VSTBY_MASK (0x100U)
+#define CCM_CLPCR_VSTBY_SHIFT (8U)
+/*! VSTBY
+ * 0b0..Voltage will not be changed to standby voltage after next entrance to STOP mode. ( PMIC_STBY_REQ will remain negated - '0')
+ * 0b1..Voltage will be requested to change to standby voltage after next entrance to stop mode. ( PMIC_STBY_REQ will be asserted - '1').
+ */
+#define CCM_CLPCR_VSTBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_VSTBY_SHIFT)) & CCM_CLPCR_VSTBY_MASK)
+#define CCM_CLPCR_STBY_COUNT_MASK (0x600U)
+#define CCM_CLPCR_STBY_COUNT_SHIFT (9U)
+/*! STBY_COUNT
+ * 0b00..CCM will wait (1*pmic_delay_scaler)+1 ckil clock cycles
+ * 0b01..CCM will wait (3*pmic_delay_scaler)+1 ckil clock cycles
+ * 0b10..CCM will wait (7*pmic_delay_scaler)+1 ckil clock cycles
+ * 0b11..CCM will wait (15*pmic_delay_scaler)+1 ckil clock cycles
+ */
+#define CCM_CLPCR_STBY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_STBY_COUNT_SHIFT)) & CCM_CLPCR_STBY_COUNT_MASK)
+#define CCM_CLPCR_COSC_PWRDOWN_MASK (0x800U)
+#define CCM_CLPCR_COSC_PWRDOWN_SHIFT (11U)
+/*! COSC_PWRDOWN
+ * 0b0..On chip oscillator will not be powered down, i.e. cosc_pwrdown = '0'.
+ * 0b1..On chip oscillator will be powered down, i.e. cosc_pwrdown = '1'.
+ */
+#define CCM_CLPCR_COSC_PWRDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_COSC_PWRDOWN_SHIFT)) & CCM_CLPCR_COSC_PWRDOWN_MASK)
+#define CCM_CLPCR_BYPASS_LPM_HS1_MASK (0x80000U)
+#define CCM_CLPCR_BYPASS_LPM_HS1_SHIFT (19U)
+#define CCM_CLPCR_BYPASS_LPM_HS1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS1_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS1_MASK)
+#define CCM_CLPCR_BYPASS_LPM_HS0_MASK (0x200000U)
+#define CCM_CLPCR_BYPASS_LPM_HS0_SHIFT (21U)
+#define CCM_CLPCR_BYPASS_LPM_HS0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_BYPASS_LPM_HS0_SHIFT)) & CCM_CLPCR_BYPASS_LPM_HS0_MASK)
+#define CCM_CLPCR_MASK_CORE0_WFI_MASK (0x400000U)
+#define CCM_CLPCR_MASK_CORE0_WFI_SHIFT (22U)
+/*! MASK_CORE0_WFI
+ * 0b0..WFI of core0 is not masked
+ * 0b1..WFI of core0 is masked
+ */
+#define CCM_CLPCR_MASK_CORE0_WFI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_CORE0_WFI_SHIFT)) & CCM_CLPCR_MASK_CORE0_WFI_MASK)
+#define CCM_CLPCR_MASK_SCU_IDLE_MASK (0x4000000U)
+#define CCM_CLPCR_MASK_SCU_IDLE_SHIFT (26U)
+/*! MASK_SCU_IDLE
+ * 0b1..SCU IDLE is masked
+ * 0b0..SCU IDLE is not masked
+ */
+#define CCM_CLPCR_MASK_SCU_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_SCU_IDLE_SHIFT)) & CCM_CLPCR_MASK_SCU_IDLE_MASK)
+#define CCM_CLPCR_MASK_L2CC_IDLE_MASK (0x8000000U)
+#define CCM_CLPCR_MASK_L2CC_IDLE_SHIFT (27U)
+/*! MASK_L2CC_IDLE
+ * 0b1..L2CC IDLE is masked
+ * 0b0..L2CC IDLE is not masked
+ */
+#define CCM_CLPCR_MASK_L2CC_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLPCR_MASK_L2CC_IDLE_SHIFT)) & CCM_CLPCR_MASK_L2CC_IDLE_MASK)
+/*! @} */
+
+/*! @name CISR - CCM Interrupt Status Register */
+/*! @{ */
+#define CCM_CISR_LRF_PLL_MASK (0x1U)
+#define CCM_CISR_LRF_PLL_SHIFT (0U)
+/*! LRF_PLL
+ * 0b0..interrupt is not generated due to lock ready of all enabled and not bypaseed PLLs
+ * 0b1..interrupt generated due to lock ready of all enabled and not bypaseed PLLs
+ */
+#define CCM_CISR_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_LRF_PLL_SHIFT)) & CCM_CISR_LRF_PLL_MASK)
+#define CCM_CISR_COSC_READY_MASK (0x40U)
+#define CCM_CISR_COSC_READY_SHIFT (6U)
+/*! COSC_READY
+ * 0b0..interrupt is not generated due to on board oscillator ready
+ * 0b1..interrupt generated due to on board oscillator ready
+ */
+#define CCM_CISR_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_COSC_READY_SHIFT)) & CCM_CISR_COSC_READY_MASK)
+#define CCM_CISR_SEMC_PODF_LOADED_MASK (0x20000U)
+#define CCM_CISR_SEMC_PODF_LOADED_SHIFT (17U)
+/*! SEMC_PODF_LOADED
+ * 0b0..interrupt is not generated due to frequency change of semc_podf
+ * 0b1..interrupt generated due to frequency change of semc_podf
+ */
+#define CCM_CISR_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_SEMC_PODF_LOADED_SHIFT)) & CCM_CISR_SEMC_PODF_LOADED_MASK)
+#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
+#define CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
+/*! PERIPH2_CLK_SEL_LOADED
+ * 0b0..interrupt is not generated due to frequency change of periph2_clk_sel
+ * 0b1..interrupt generated due to frequency change of periph2_clk_sel
+ */
+#define CCM_CISR_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH2_CLK_SEL_LOADED_MASK)
+#define CCM_CISR_AHB_PODF_LOADED_MASK (0x100000U)
+#define CCM_CISR_AHB_PODF_LOADED_SHIFT (20U)
+/*! AHB_PODF_LOADED
+ * 0b0..interrupt is not generated due to frequency change of ahb_podf
+ * 0b1..interrupt generated due to frequency change of ahb_podf
+ */
+#define CCM_CISR_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_AHB_PODF_LOADED_SHIFT)) & CCM_CISR_AHB_PODF_LOADED_MASK)
+#define CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
+#define CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
+/*! PERIPH_CLK_SEL_LOADED
+ * 0b0..interrupt is not generated due to update of periph_clk_sel.
+ * 0b1..interrupt generated due to update of periph_clk_sel.
+ */
+#define CCM_CISR_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CISR_PERIPH_CLK_SEL_LOADED_MASK)
+#define CCM_CISR_ARM_PODF_LOADED_MASK (0x4000000U)
+#define CCM_CISR_ARM_PODF_LOADED_SHIFT (26U)
+/*! ARM_PODF_LOADED
+ * 0b0..interrupt is not generated due to frequency change of arm_podf
+ * 0b1..interrupt generated due to frequency change of arm_podf
+ */
+#define CCM_CISR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CISR_ARM_PODF_LOADED_SHIFT)) & CCM_CISR_ARM_PODF_LOADED_MASK)
+/*! @} */
+
+/*! @name CIMR - CCM Interrupt Mask Register */
+/*! @{ */
+#define CCM_CIMR_MASK_LRF_PLL_MASK (0x1U)
+#define CCM_CIMR_MASK_LRF_PLL_SHIFT (0U)
+/*! MASK_LRF_PLL
+ * 0b0..don't mask interrupt due to lrf of PLLs - interrupt will be created
+ * 0b1..mask interrupt due to lrf of PLLs
+ */
+#define CCM_CIMR_MASK_LRF_PLL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_LRF_PLL_SHIFT)) & CCM_CIMR_MASK_LRF_PLL_MASK)
+#define CCM_CIMR_MASK_COSC_READY_MASK (0x40U)
+#define CCM_CIMR_MASK_COSC_READY_SHIFT (6U)
+/*! MASK_COSC_READY
+ * 0b0..don't mask interrupt due to on board oscillator ready - interrupt will be created
+ * 0b1..mask interrupt due to on board oscillator ready
+ */
+#define CCM_CIMR_MASK_COSC_READY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_COSC_READY_SHIFT)) & CCM_CIMR_MASK_COSC_READY_MASK)
+#define CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK (0x20000U)
+#define CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT (17U)
+/*! MASK_SEMC_PODF_LOADED
+ * 0b0..don't mask interrupt due to frequency change of semc_podf - interrupt will be created
+ * 0b1..mask interrupt due to frequency change of semc_podf
+ */
+#define CCM_CIMR_MASK_SEMC_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_SEMC_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_SEMC_PODF_LOADED_MASK)
+#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK (0x80000U)
+#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT (19U)
+/*! MASK_PERIPH2_CLK_SEL_LOADED
+ * 0b0..don't mask interrupt due to update of periph2_clk_sel - interrupt will be created
+ * 0b1..mask interrupt due to update of periph2_clk_sel
+ */
+#define CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED_MASK)
+#define CCM_CIMR_MASK_AHB_PODF_LOADED_MASK (0x100000U)
+#define CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT (20U)
+/*! MASK_AHB_PODF_LOADED
+ * 0b0..don't mask interrupt due to frequency change of ahb_podf - interrupt will be created
+ * 0b1..mask interrupt due to frequency change of ahb_podf
+ */
+#define CCM_CIMR_MASK_AHB_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_AHB_PODF_LOADED_SHIFT)) & CCM_CIMR_MASK_AHB_PODF_LOADED_MASK)
+#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK (0x400000U)
+#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT (22U)
+/*! MASK_PERIPH_CLK_SEL_LOADED
+ * 0b0..don't mask interrupt due to update of periph_clk_sel - interrupt will be created
+ * 0b1..mask interrupt due to update of periph_clk_sel
+ */
+#define CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_SHIFT)) & CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED_MASK)
+#define CCM_CIMR_ARM_PODF_LOADED_MASK (0x4000000U)
+#define CCM_CIMR_ARM_PODF_LOADED_SHIFT (26U)
+/*! ARM_PODF_LOADED
+ * 0b0..don't mask interrupt due to frequency change of arm_podf - interrupt will be created
+ * 0b1..mask interrupt due to frequency change of arm_podf
+ */
+#define CCM_CIMR_ARM_PODF_LOADED(x) (((uint32_t)(((uint32_t)(x)) << CCM_CIMR_ARM_PODF_LOADED_SHIFT)) & CCM_CIMR_ARM_PODF_LOADED_MASK)
+/*! @} */
+
+/*! @name CCOSR - CCM Clock Output Source Register */
+/*! @{ */
+#define CCM_CCOSR_CLKO1_SEL_MASK (0xFU)
+#define CCM_CCOSR_CLKO1_SEL_SHIFT (0U)
+/*! CLKO1_SEL
+ * 0b0000..USB1 PLL clock (divided by 2)
+ * 0b0001..SYS PLL clock (divided by 2)
+ * 0b0011..VIDEO PLL clock (divided by 2)
+ * 0b0101..semc_clk_root
+ * 0b0110..Reserved
+ * 0b1010..lcdif_pix_clk_root
+ * 0b1011..ahb_clk_root
+ * 0b1100..ipg_clk_root
+ * 0b1101..perclk_root
+ * 0b1110..ckil_sync_clk_root
+ * 0b1111..pll4_main_clk
+ */
+#define CCM_CCOSR_CLKO1_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_SEL_SHIFT)) & CCM_CCOSR_CLKO1_SEL_MASK)
+#define CCM_CCOSR_CLKO1_DIV_MASK (0x70U)
+#define CCM_CCOSR_CLKO1_DIV_SHIFT (4U)
+/*! CLKO1_DIV
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CCOSR_CLKO1_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_DIV_SHIFT)) & CCM_CCOSR_CLKO1_DIV_MASK)
+#define CCM_CCOSR_CLKO1_EN_MASK (0x80U)
+#define CCM_CCOSR_CLKO1_EN_SHIFT (7U)
+/*! CLKO1_EN
+ * 0b0..CCM_CLKO1 disabled.
+ * 0b1..CCM_CLKO1 enabled.
+ */
+#define CCM_CCOSR_CLKO1_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO1_EN_SHIFT)) & CCM_CCOSR_CLKO1_EN_MASK)
+#define CCM_CCOSR_CLK_OUT_SEL_MASK (0x100U)
+#define CCM_CCOSR_CLK_OUT_SEL_SHIFT (8U)
+/*! CLK_OUT_SEL
+ * 0b0..CCM_CLKO1 output drives CCM_CLKO1 clock
+ * 0b1..CCM_CLKO1 output drives CCM_CLKO2 clock
+ */
+#define CCM_CCOSR_CLK_OUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLK_OUT_SEL_SHIFT)) & CCM_CCOSR_CLK_OUT_SEL_MASK)
+#define CCM_CCOSR_CLKO2_SEL_MASK (0x1F0000U)
+#define CCM_CCOSR_CLKO2_SEL_SHIFT (16U)
+/*! CLKO2_SEL
+ * 0b00011..usdhc1_clk_root
+ * 0b00101..wrck_clk_root
+ * 0b00110..lpi2c_clk_root
+ * 0b01011..csi_clk_root
+ * 0b01110..osc_clk
+ * 0b10001..usdhc2_clk_root
+ * 0b10010..sai1_clk_root
+ * 0b10011..sai2_clk_root
+ * 0b10100..sai3_clk_root
+ * 0b10111..can_clk_root
+ * 0b11011..flexspi_clk_root
+ * 0b11100..uart_clk_root
+ * 0b11101..spdif0_clk_root
+ * 0b11111..Reserved
+ */
+#define CCM_CCOSR_CLKO2_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_SEL_SHIFT)) & CCM_CCOSR_CLKO2_SEL_MASK)
+#define CCM_CCOSR_CLKO2_DIV_MASK (0xE00000U)
+#define CCM_CCOSR_CLKO2_DIV_SHIFT (21U)
+/*! CLKO2_DIV
+ * 0b000..divide by 1
+ * 0b001..divide by 2
+ * 0b010..divide by 3
+ * 0b011..divide by 4
+ * 0b100..divide by 5
+ * 0b101..divide by 6
+ * 0b110..divide by 7
+ * 0b111..divide by 8
+ */
+#define CCM_CCOSR_CLKO2_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_DIV_SHIFT)) & CCM_CCOSR_CLKO2_DIV_MASK)
+#define CCM_CCOSR_CLKO2_EN_MASK (0x1000000U)
+#define CCM_CCOSR_CLKO2_EN_SHIFT (24U)
+/*! CLKO2_EN
+ * 0b0..CCM_CLKO2 disabled.
+ * 0b1..CCM_CLKO2 enabled.
+ */
+#define CCM_CCOSR_CLKO2_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCOSR_CLKO2_EN_SHIFT)) & CCM_CCOSR_CLKO2_EN_MASK)
+/*! @} */
+
+/*! @name CGPR - CCM General Purpose Register */
+/*! @{ */
+#define CCM_CGPR_PMIC_DELAY_SCALER_MASK (0x1U)
+#define CCM_CGPR_PMIC_DELAY_SCALER_SHIFT (0U)
+/*! PMIC_DELAY_SCALER
+ * 0b0..clock is not divided
+ * 0b1..clock is divided /8
+ */
+#define CCM_CGPR_PMIC_DELAY_SCALER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_PMIC_DELAY_SCALER_SHIFT)) & CCM_CGPR_PMIC_DELAY_SCALER_MASK)
+#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK (0x10U)
+#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT (4U)
+/*! EFUSE_PROG_SUPPLY_GATE
+ * 0b0..fuse programing supply voltage is gated off to the efuse module
+ * 0b1..allow fuse programing.
+ */
+#define CCM_CGPR_EFUSE_PROG_SUPPLY_GATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_SHIFT)) & CCM_CGPR_EFUSE_PROG_SUPPLY_GATE_MASK)
+#define CCM_CGPR_SYS_MEM_DS_CTRL_MASK (0xC000U)
+#define CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT (14U)
+/*! SYS_MEM_DS_CTRL
+ * 0b00..Disable memory DS mode always
+ * 0b01..Enable memory (outside ARM platform) DS mode when system STOP and PLL are disabled
+ * 0b1x..enable memory (outside ARM platform) DS mode when system is in STOP mode
+ */
+#define CCM_CGPR_SYS_MEM_DS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_SYS_MEM_DS_CTRL_SHIFT)) & CCM_CGPR_SYS_MEM_DS_CTRL_MASK)
+#define CCM_CGPR_FPL_MASK (0x10000U)
+#define CCM_CGPR_FPL_SHIFT (16U)
+/*! FPL - Fast PLL enable.
+ * 0b0..Engage PLL enable default way.
+ * 0b1..Engage PLL enable 3 CKIL clocks earlier at exiting low power mode (STOP). Should be used only if 24MHz OSC was active in low power mode.
+ */
+#define CCM_CGPR_FPL(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_FPL_SHIFT)) & CCM_CGPR_FPL_MASK)
+#define CCM_CGPR_INT_MEM_CLK_LPM_MASK (0x20000U)
+#define CCM_CGPR_INT_MEM_CLK_LPM_SHIFT (17U)
+/*! INT_MEM_CLK_LPM
+ * 0b0..Disable the clock to the ARM platform memories when entering Low Power Mode
+ * 0b1..Keep the clocks to the ARM platform memories enabled only if an interrupt is pending when entering Low
+ * Power Modes (WAIT and STOP without power gating)
+ */
+#define CCM_CGPR_INT_MEM_CLK_LPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_CGPR_INT_MEM_CLK_LPM_SHIFT)) & CCM_CGPR_INT_MEM_CLK_LPM_MASK)
+/*! @} */
+
+/*! @name CCGR0 - CCM Clock Gating Register 0 */
+/*! @{ */
+#define CCM_CCGR0_CG0_MASK (0x3U)
+#define CCM_CCGR0_CG0_SHIFT (0U)
+#define CCM_CCGR0_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG0_SHIFT)) & CCM_CCGR0_CG0_MASK)
+#define CCM_CCGR0_CG1_MASK (0xCU)
+#define CCM_CCGR0_CG1_SHIFT (2U)
+#define CCM_CCGR0_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG1_SHIFT)) & CCM_CCGR0_CG1_MASK)
+#define CCM_CCGR0_CG2_MASK (0x30U)
+#define CCM_CCGR0_CG2_SHIFT (4U)
+#define CCM_CCGR0_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG2_SHIFT)) & CCM_CCGR0_CG2_MASK)
+#define CCM_CCGR0_CG3_MASK (0xC0U)
+#define CCM_CCGR0_CG3_SHIFT (6U)
+#define CCM_CCGR0_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG3_SHIFT)) & CCM_CCGR0_CG3_MASK)
+#define CCM_CCGR0_CG4_MASK (0x300U)
+#define CCM_CCGR0_CG4_SHIFT (8U)
+#define CCM_CCGR0_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG4_SHIFT)) & CCM_CCGR0_CG4_MASK)
+#define CCM_CCGR0_CG5_MASK (0xC00U)
+#define CCM_CCGR0_CG5_SHIFT (10U)
+#define CCM_CCGR0_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG5_SHIFT)) & CCM_CCGR0_CG5_MASK)
+#define CCM_CCGR0_CG6_MASK (0x3000U)
+#define CCM_CCGR0_CG6_SHIFT (12U)
+#define CCM_CCGR0_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG6_SHIFT)) & CCM_CCGR0_CG6_MASK)
+#define CCM_CCGR0_CG7_MASK (0xC000U)
+#define CCM_CCGR0_CG7_SHIFT (14U)
+#define CCM_CCGR0_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG7_SHIFT)) & CCM_CCGR0_CG7_MASK)
+#define CCM_CCGR0_CG8_MASK (0x30000U)
+#define CCM_CCGR0_CG8_SHIFT (16U)
+#define CCM_CCGR0_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG8_SHIFT)) & CCM_CCGR0_CG8_MASK)
+#define CCM_CCGR0_CG9_MASK (0xC0000U)
+#define CCM_CCGR0_CG9_SHIFT (18U)
+#define CCM_CCGR0_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG9_SHIFT)) & CCM_CCGR0_CG9_MASK)
+#define CCM_CCGR0_CG10_MASK (0x300000U)
+#define CCM_CCGR0_CG10_SHIFT (20U)
+#define CCM_CCGR0_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG10_SHIFT)) & CCM_CCGR0_CG10_MASK)
+#define CCM_CCGR0_CG11_MASK (0xC00000U)
+#define CCM_CCGR0_CG11_SHIFT (22U)
+#define CCM_CCGR0_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG11_SHIFT)) & CCM_CCGR0_CG11_MASK)
+#define CCM_CCGR0_CG12_MASK (0x3000000U)
+#define CCM_CCGR0_CG12_SHIFT (24U)
+#define CCM_CCGR0_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG12_SHIFT)) & CCM_CCGR0_CG12_MASK)
+#define CCM_CCGR0_CG13_MASK (0xC000000U)
+#define CCM_CCGR0_CG13_SHIFT (26U)
+#define CCM_CCGR0_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG13_SHIFT)) & CCM_CCGR0_CG13_MASK)
+#define CCM_CCGR0_CG14_MASK (0x30000000U)
+#define CCM_CCGR0_CG14_SHIFT (28U)
+#define CCM_CCGR0_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG14_SHIFT)) & CCM_CCGR0_CG14_MASK)
+#define CCM_CCGR0_CG15_MASK (0xC0000000U)
+#define CCM_CCGR0_CG15_SHIFT (30U)
+#define CCM_CCGR0_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR0_CG15_SHIFT)) & CCM_CCGR0_CG15_MASK)
+/*! @} */
+
+/*! @name CCGR1 - CCM Clock Gating Register 1 */
+/*! @{ */
+#define CCM_CCGR1_CG0_MASK (0x3U)
+#define CCM_CCGR1_CG0_SHIFT (0U)
+#define CCM_CCGR1_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG0_SHIFT)) & CCM_CCGR1_CG0_MASK)
+#define CCM_CCGR1_CG1_MASK (0xCU)
+#define CCM_CCGR1_CG1_SHIFT (2U)
+#define CCM_CCGR1_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG1_SHIFT)) & CCM_CCGR1_CG1_MASK)
+#define CCM_CCGR1_CG2_MASK (0x30U)
+#define CCM_CCGR1_CG2_SHIFT (4U)
+#define CCM_CCGR1_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG2_SHIFT)) & CCM_CCGR1_CG2_MASK)
+#define CCM_CCGR1_CG3_MASK (0xC0U)
+#define CCM_CCGR1_CG3_SHIFT (6U)
+#define CCM_CCGR1_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG3_SHIFT)) & CCM_CCGR1_CG3_MASK)
+#define CCM_CCGR1_CG4_MASK (0x300U)
+#define CCM_CCGR1_CG4_SHIFT (8U)
+#define CCM_CCGR1_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG4_SHIFT)) & CCM_CCGR1_CG4_MASK)
+#define CCM_CCGR1_CG5_MASK (0xC00U)
+#define CCM_CCGR1_CG5_SHIFT (10U)
+#define CCM_CCGR1_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG5_SHIFT)) & CCM_CCGR1_CG5_MASK)
+#define CCM_CCGR1_CG6_MASK (0x3000U)
+#define CCM_CCGR1_CG6_SHIFT (12U)
+#define CCM_CCGR1_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG6_SHIFT)) & CCM_CCGR1_CG6_MASK)
+#define CCM_CCGR1_CG7_MASK (0xC000U)
+#define CCM_CCGR1_CG7_SHIFT (14U)
+#define CCM_CCGR1_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG7_SHIFT)) & CCM_CCGR1_CG7_MASK)
+#define CCM_CCGR1_CG8_MASK (0x30000U)
+#define CCM_CCGR1_CG8_SHIFT (16U)
+#define CCM_CCGR1_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG8_SHIFT)) & CCM_CCGR1_CG8_MASK)
+#define CCM_CCGR1_CG9_MASK (0xC0000U)
+#define CCM_CCGR1_CG9_SHIFT (18U)
+#define CCM_CCGR1_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG9_SHIFT)) & CCM_CCGR1_CG9_MASK)
+#define CCM_CCGR1_CG10_MASK (0x300000U)
+#define CCM_CCGR1_CG10_SHIFT (20U)
+#define CCM_CCGR1_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG10_SHIFT)) & CCM_CCGR1_CG10_MASK)
+#define CCM_CCGR1_CG11_MASK (0xC00000U)
+#define CCM_CCGR1_CG11_SHIFT (22U)
+#define CCM_CCGR1_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG11_SHIFT)) & CCM_CCGR1_CG11_MASK)
+#define CCM_CCGR1_CG12_MASK (0x3000000U)
+#define CCM_CCGR1_CG12_SHIFT (24U)
+#define CCM_CCGR1_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG12_SHIFT)) & CCM_CCGR1_CG12_MASK)
+#define CCM_CCGR1_CG13_MASK (0xC000000U)
+#define CCM_CCGR1_CG13_SHIFT (26U)
+#define CCM_CCGR1_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG13_SHIFT)) & CCM_CCGR1_CG13_MASK)
+#define CCM_CCGR1_CG14_MASK (0x30000000U)
+#define CCM_CCGR1_CG14_SHIFT (28U)
+#define CCM_CCGR1_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG14_SHIFT)) & CCM_CCGR1_CG14_MASK)
+#define CCM_CCGR1_CG15_MASK (0xC0000000U)
+#define CCM_CCGR1_CG15_SHIFT (30U)
+#define CCM_CCGR1_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR1_CG15_SHIFT)) & CCM_CCGR1_CG15_MASK)
+/*! @} */
+
+/*! @name CCGR2 - CCM Clock Gating Register 2 */
+/*! @{ */
+#define CCM_CCGR2_CG0_MASK (0x3U)
+#define CCM_CCGR2_CG0_SHIFT (0U)
+#define CCM_CCGR2_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG0_SHIFT)) & CCM_CCGR2_CG0_MASK)
+#define CCM_CCGR2_CG1_MASK (0xCU)
+#define CCM_CCGR2_CG1_SHIFT (2U)
+#define CCM_CCGR2_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG1_SHIFT)) & CCM_CCGR2_CG1_MASK)
+#define CCM_CCGR2_CG2_MASK (0x30U)
+#define CCM_CCGR2_CG2_SHIFT (4U)
+#define CCM_CCGR2_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG2_SHIFT)) & CCM_CCGR2_CG2_MASK)
+#define CCM_CCGR2_CG3_MASK (0xC0U)
+#define CCM_CCGR2_CG3_SHIFT (6U)
+#define CCM_CCGR2_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG3_SHIFT)) & CCM_CCGR2_CG3_MASK)
+#define CCM_CCGR2_CG4_MASK (0x300U)
+#define CCM_CCGR2_CG4_SHIFT (8U)
+#define CCM_CCGR2_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG4_SHIFT)) & CCM_CCGR2_CG4_MASK)
+#define CCM_CCGR2_CG5_MASK (0xC00U)
+#define CCM_CCGR2_CG5_SHIFT (10U)
+#define CCM_CCGR2_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG5_SHIFT)) & CCM_CCGR2_CG5_MASK)
+#define CCM_CCGR2_CG6_MASK (0x3000U)
+#define CCM_CCGR2_CG6_SHIFT (12U)
+#define CCM_CCGR2_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG6_SHIFT)) & CCM_CCGR2_CG6_MASK)
+#define CCM_CCGR2_CG7_MASK (0xC000U)
+#define CCM_CCGR2_CG7_SHIFT (14U)
+#define CCM_CCGR2_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG7_SHIFT)) & CCM_CCGR2_CG7_MASK)
+#define CCM_CCGR2_CG8_MASK (0x30000U)
+#define CCM_CCGR2_CG8_SHIFT (16U)
+#define CCM_CCGR2_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG8_SHIFT)) & CCM_CCGR2_CG8_MASK)
+#define CCM_CCGR2_CG9_MASK (0xC0000U)
+#define CCM_CCGR2_CG9_SHIFT (18U)
+#define CCM_CCGR2_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG9_SHIFT)) & CCM_CCGR2_CG9_MASK)
+#define CCM_CCGR2_CG10_MASK (0x300000U)
+#define CCM_CCGR2_CG10_SHIFT (20U)
+#define CCM_CCGR2_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG10_SHIFT)) & CCM_CCGR2_CG10_MASK)
+#define CCM_CCGR2_CG11_MASK (0xC00000U)
+#define CCM_CCGR2_CG11_SHIFT (22U)
+#define CCM_CCGR2_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG11_SHIFT)) & CCM_CCGR2_CG11_MASK)
+#define CCM_CCGR2_CG12_MASK (0x3000000U)
+#define CCM_CCGR2_CG12_SHIFT (24U)
+#define CCM_CCGR2_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG12_SHIFT)) & CCM_CCGR2_CG12_MASK)
+#define CCM_CCGR2_CG13_MASK (0xC000000U)
+#define CCM_CCGR2_CG13_SHIFT (26U)
+#define CCM_CCGR2_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG13_SHIFT)) & CCM_CCGR2_CG13_MASK)
+#define CCM_CCGR2_CG14_MASK (0x30000000U)
+#define CCM_CCGR2_CG14_SHIFT (28U)
+#define CCM_CCGR2_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG14_SHIFT)) & CCM_CCGR2_CG14_MASK)
+#define CCM_CCGR2_CG15_MASK (0xC0000000U)
+#define CCM_CCGR2_CG15_SHIFT (30U)
+#define CCM_CCGR2_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR2_CG15_SHIFT)) & CCM_CCGR2_CG15_MASK)
+/*! @} */
+
+/*! @name CCGR3 - CCM Clock Gating Register 3 */
+/*! @{ */
+#define CCM_CCGR3_CG0_MASK (0x3U)
+#define CCM_CCGR3_CG0_SHIFT (0U)
+#define CCM_CCGR3_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG0_SHIFT)) & CCM_CCGR3_CG0_MASK)
+#define CCM_CCGR3_CG1_MASK (0xCU)
+#define CCM_CCGR3_CG1_SHIFT (2U)
+#define CCM_CCGR3_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG1_SHIFT)) & CCM_CCGR3_CG1_MASK)
+#define CCM_CCGR3_CG2_MASK (0x30U)
+#define CCM_CCGR3_CG2_SHIFT (4U)
+#define CCM_CCGR3_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG2_SHIFT)) & CCM_CCGR3_CG2_MASK)
+#define CCM_CCGR3_CG3_MASK (0xC0U)
+#define CCM_CCGR3_CG3_SHIFT (6U)
+#define CCM_CCGR3_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG3_SHIFT)) & CCM_CCGR3_CG3_MASK)
+#define CCM_CCGR3_CG4_MASK (0x300U)
+#define CCM_CCGR3_CG4_SHIFT (8U)
+#define CCM_CCGR3_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG4_SHIFT)) & CCM_CCGR3_CG4_MASK)
+#define CCM_CCGR3_CG5_MASK (0xC00U)
+#define CCM_CCGR3_CG5_SHIFT (10U)
+#define CCM_CCGR3_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG5_SHIFT)) & CCM_CCGR3_CG5_MASK)
+#define CCM_CCGR3_CG6_MASK (0x3000U)
+#define CCM_CCGR3_CG6_SHIFT (12U)
+#define CCM_CCGR3_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG6_SHIFT)) & CCM_CCGR3_CG6_MASK)
+#define CCM_CCGR3_CG7_MASK (0xC000U)
+#define CCM_CCGR3_CG7_SHIFT (14U)
+#define CCM_CCGR3_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG7_SHIFT)) & CCM_CCGR3_CG7_MASK)
+#define CCM_CCGR3_CG8_MASK (0x30000U)
+#define CCM_CCGR3_CG8_SHIFT (16U)
+#define CCM_CCGR3_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG8_SHIFT)) & CCM_CCGR3_CG8_MASK)
+#define CCM_CCGR3_CG9_MASK (0xC0000U)
+#define CCM_CCGR3_CG9_SHIFT (18U)
+#define CCM_CCGR3_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG9_SHIFT)) & CCM_CCGR3_CG9_MASK)
+#define CCM_CCGR3_CG10_MASK (0x300000U)
+#define CCM_CCGR3_CG10_SHIFT (20U)
+#define CCM_CCGR3_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG10_SHIFT)) & CCM_CCGR3_CG10_MASK)
+#define CCM_CCGR3_CG11_MASK (0xC00000U)
+#define CCM_CCGR3_CG11_SHIFT (22U)
+#define CCM_CCGR3_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG11_SHIFT)) & CCM_CCGR3_CG11_MASK)
+#define CCM_CCGR3_CG12_MASK (0x3000000U)
+#define CCM_CCGR3_CG12_SHIFT (24U)
+#define CCM_CCGR3_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG12_SHIFT)) & CCM_CCGR3_CG12_MASK)
+#define CCM_CCGR3_CG13_MASK (0xC000000U)
+#define CCM_CCGR3_CG13_SHIFT (26U)
+#define CCM_CCGR3_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG13_SHIFT)) & CCM_CCGR3_CG13_MASK)
+#define CCM_CCGR3_CG14_MASK (0x30000000U)
+#define CCM_CCGR3_CG14_SHIFT (28U)
+#define CCM_CCGR3_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG14_SHIFT)) & CCM_CCGR3_CG14_MASK)
+#define CCM_CCGR3_CG15_MASK (0xC0000000U)
+#define CCM_CCGR3_CG15_SHIFT (30U)
+#define CCM_CCGR3_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR3_CG15_SHIFT)) & CCM_CCGR3_CG15_MASK)
+/*! @} */
+
+/*! @name CCGR4 - CCM Clock Gating Register 4 */
+/*! @{ */
+#define CCM_CCGR4_CG0_MASK (0x3U)
+#define CCM_CCGR4_CG0_SHIFT (0U)
+#define CCM_CCGR4_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG0_SHIFT)) & CCM_CCGR4_CG0_MASK)
+#define CCM_CCGR4_CG1_MASK (0xCU)
+#define CCM_CCGR4_CG1_SHIFT (2U)
+#define CCM_CCGR4_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG1_SHIFT)) & CCM_CCGR4_CG1_MASK)
+#define CCM_CCGR4_CG2_MASK (0x30U)
+#define CCM_CCGR4_CG2_SHIFT (4U)
+#define CCM_CCGR4_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG2_SHIFT)) & CCM_CCGR4_CG2_MASK)
+#define CCM_CCGR4_CG3_MASK (0xC0U)
+#define CCM_CCGR4_CG3_SHIFT (6U)
+#define CCM_CCGR4_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG3_SHIFT)) & CCM_CCGR4_CG3_MASK)
+#define CCM_CCGR4_CG4_MASK (0x300U)
+#define CCM_CCGR4_CG4_SHIFT (8U)
+#define CCM_CCGR4_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG4_SHIFT)) & CCM_CCGR4_CG4_MASK)
+#define CCM_CCGR4_CG5_MASK (0xC00U)
+#define CCM_CCGR4_CG5_SHIFT (10U)
+#define CCM_CCGR4_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG5_SHIFT)) & CCM_CCGR4_CG5_MASK)
+#define CCM_CCGR4_CG6_MASK (0x3000U)
+#define CCM_CCGR4_CG6_SHIFT (12U)
+#define CCM_CCGR4_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG6_SHIFT)) & CCM_CCGR4_CG6_MASK)
+#define CCM_CCGR4_CG7_MASK (0xC000U)
+#define CCM_CCGR4_CG7_SHIFT (14U)
+#define CCM_CCGR4_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG7_SHIFT)) & CCM_CCGR4_CG7_MASK)
+#define CCM_CCGR4_CG8_MASK (0x30000U)
+#define CCM_CCGR4_CG8_SHIFT (16U)
+#define CCM_CCGR4_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG8_SHIFT)) & CCM_CCGR4_CG8_MASK)
+#define CCM_CCGR4_CG9_MASK (0xC0000U)
+#define CCM_CCGR4_CG9_SHIFT (18U)
+#define CCM_CCGR4_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG9_SHIFT)) & CCM_CCGR4_CG9_MASK)
+#define CCM_CCGR4_CG10_MASK (0x300000U)
+#define CCM_CCGR4_CG10_SHIFT (20U)
+#define CCM_CCGR4_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG10_SHIFT)) & CCM_CCGR4_CG10_MASK)
+#define CCM_CCGR4_CG11_MASK (0xC00000U)
+#define CCM_CCGR4_CG11_SHIFT (22U)
+#define CCM_CCGR4_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG11_SHIFT)) & CCM_CCGR4_CG11_MASK)
+#define CCM_CCGR4_CG12_MASK (0x3000000U)
+#define CCM_CCGR4_CG12_SHIFT (24U)
+#define CCM_CCGR4_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG12_SHIFT)) & CCM_CCGR4_CG12_MASK)
+#define CCM_CCGR4_CG13_MASK (0xC000000U)
+#define CCM_CCGR4_CG13_SHIFT (26U)
+#define CCM_CCGR4_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG13_SHIFT)) & CCM_CCGR4_CG13_MASK)
+#define CCM_CCGR4_CG14_MASK (0x30000000U)
+#define CCM_CCGR4_CG14_SHIFT (28U)
+#define CCM_CCGR4_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG14_SHIFT)) & CCM_CCGR4_CG14_MASK)
+#define CCM_CCGR4_CG15_MASK (0xC0000000U)
+#define CCM_CCGR4_CG15_SHIFT (30U)
+#define CCM_CCGR4_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR4_CG15_SHIFT)) & CCM_CCGR4_CG15_MASK)
+/*! @} */
+
+/*! @name CCGR5 - CCM Clock Gating Register 5 */
+/*! @{ */
+#define CCM_CCGR5_CG0_MASK (0x3U)
+#define CCM_CCGR5_CG0_SHIFT (0U)
+#define CCM_CCGR5_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG0_SHIFT)) & CCM_CCGR5_CG0_MASK)
+#define CCM_CCGR5_CG1_MASK (0xCU)
+#define CCM_CCGR5_CG1_SHIFT (2U)
+#define CCM_CCGR5_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG1_SHIFT)) & CCM_CCGR5_CG1_MASK)
+#define CCM_CCGR5_CG2_MASK (0x30U)
+#define CCM_CCGR5_CG2_SHIFT (4U)
+#define CCM_CCGR5_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG2_SHIFT)) & CCM_CCGR5_CG2_MASK)
+#define CCM_CCGR5_CG3_MASK (0xC0U)
+#define CCM_CCGR5_CG3_SHIFT (6U)
+#define CCM_CCGR5_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG3_SHIFT)) & CCM_CCGR5_CG3_MASK)
+#define CCM_CCGR5_CG4_MASK (0x300U)
+#define CCM_CCGR5_CG4_SHIFT (8U)
+#define CCM_CCGR5_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG4_SHIFT)) & CCM_CCGR5_CG4_MASK)
+#define CCM_CCGR5_CG5_MASK (0xC00U)
+#define CCM_CCGR5_CG5_SHIFT (10U)
+#define CCM_CCGR5_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG5_SHIFT)) & CCM_CCGR5_CG5_MASK)
+#define CCM_CCGR5_CG6_MASK (0x3000U)
+#define CCM_CCGR5_CG6_SHIFT (12U)
+#define CCM_CCGR5_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG6_SHIFT)) & CCM_CCGR5_CG6_MASK)
+#define CCM_CCGR5_CG7_MASK (0xC000U)
+#define CCM_CCGR5_CG7_SHIFT (14U)
+#define CCM_CCGR5_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG7_SHIFT)) & CCM_CCGR5_CG7_MASK)
+#define CCM_CCGR5_CG8_MASK (0x30000U)
+#define CCM_CCGR5_CG8_SHIFT (16U)
+#define CCM_CCGR5_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG8_SHIFT)) & CCM_CCGR5_CG8_MASK)
+#define CCM_CCGR5_CG9_MASK (0xC0000U)
+#define CCM_CCGR5_CG9_SHIFT (18U)
+#define CCM_CCGR5_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG9_SHIFT)) & CCM_CCGR5_CG9_MASK)
+#define CCM_CCGR5_CG10_MASK (0x300000U)
+#define CCM_CCGR5_CG10_SHIFT (20U)
+#define CCM_CCGR5_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG10_SHIFT)) & CCM_CCGR5_CG10_MASK)
+#define CCM_CCGR5_CG11_MASK (0xC00000U)
+#define CCM_CCGR5_CG11_SHIFT (22U)
+#define CCM_CCGR5_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG11_SHIFT)) & CCM_CCGR5_CG11_MASK)
+#define CCM_CCGR5_CG12_MASK (0x3000000U)
+#define CCM_CCGR5_CG12_SHIFT (24U)
+#define CCM_CCGR5_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG12_SHIFT)) & CCM_CCGR5_CG12_MASK)
+#define CCM_CCGR5_CG13_MASK (0xC000000U)
+#define CCM_CCGR5_CG13_SHIFT (26U)
+#define CCM_CCGR5_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG13_SHIFT)) & CCM_CCGR5_CG13_MASK)
+#define CCM_CCGR5_CG14_MASK (0x30000000U)
+#define CCM_CCGR5_CG14_SHIFT (28U)
+#define CCM_CCGR5_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG14_SHIFT)) & CCM_CCGR5_CG14_MASK)
+#define CCM_CCGR5_CG15_MASK (0xC0000000U)
+#define CCM_CCGR5_CG15_SHIFT (30U)
+#define CCM_CCGR5_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR5_CG15_SHIFT)) & CCM_CCGR5_CG15_MASK)
+/*! @} */
+
+/*! @name CCGR6 - CCM Clock Gating Register 6 */
+/*! @{ */
+#define CCM_CCGR6_CG0_MASK (0x3U)
+#define CCM_CCGR6_CG0_SHIFT (0U)
+#define CCM_CCGR6_CG0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG0_SHIFT)) & CCM_CCGR6_CG0_MASK)
+#define CCM_CCGR6_CG1_MASK (0xCU)
+#define CCM_CCGR6_CG1_SHIFT (2U)
+#define CCM_CCGR6_CG1(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG1_SHIFT)) & CCM_CCGR6_CG1_MASK)
+#define CCM_CCGR6_CG2_MASK (0x30U)
+#define CCM_CCGR6_CG2_SHIFT (4U)
+#define CCM_CCGR6_CG2(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG2_SHIFT)) & CCM_CCGR6_CG2_MASK)
+#define CCM_CCGR6_CG3_MASK (0xC0U)
+#define CCM_CCGR6_CG3_SHIFT (6U)
+#define CCM_CCGR6_CG3(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG3_SHIFT)) & CCM_CCGR6_CG3_MASK)
+#define CCM_CCGR6_CG4_MASK (0x300U)
+#define CCM_CCGR6_CG4_SHIFT (8U)
+#define CCM_CCGR6_CG4(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG4_SHIFT)) & CCM_CCGR6_CG4_MASK)
+#define CCM_CCGR6_CG5_MASK (0xC00U)
+#define CCM_CCGR6_CG5_SHIFT (10U)
+#define CCM_CCGR6_CG5(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG5_SHIFT)) & CCM_CCGR6_CG5_MASK)
+#define CCM_CCGR6_CG6_MASK (0x3000U)
+#define CCM_CCGR6_CG6_SHIFT (12U)
+#define CCM_CCGR6_CG6(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG6_SHIFT)) & CCM_CCGR6_CG6_MASK)
+#define CCM_CCGR6_CG7_MASK (0xC000U)
+#define CCM_CCGR6_CG7_SHIFT (14U)
+#define CCM_CCGR6_CG7(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG7_SHIFT)) & CCM_CCGR6_CG7_MASK)
+#define CCM_CCGR6_CG8_MASK (0x30000U)
+#define CCM_CCGR6_CG8_SHIFT (16U)
+#define CCM_CCGR6_CG8(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG8_SHIFT)) & CCM_CCGR6_CG8_MASK)
+#define CCM_CCGR6_CG9_MASK (0xC0000U)
+#define CCM_CCGR6_CG9_SHIFT (18U)
+#define CCM_CCGR6_CG9(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG9_SHIFT)) & CCM_CCGR6_CG9_MASK)
+#define CCM_CCGR6_CG10_MASK (0x300000U)
+#define CCM_CCGR6_CG10_SHIFT (20U)
+#define CCM_CCGR6_CG10(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG10_SHIFT)) & CCM_CCGR6_CG10_MASK)
+#define CCM_CCGR6_CG11_MASK (0xC00000U)
+#define CCM_CCGR6_CG11_SHIFT (22U)
+#define CCM_CCGR6_CG11(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG11_SHIFT)) & CCM_CCGR6_CG11_MASK)
+#define CCM_CCGR6_CG12_MASK (0x3000000U)
+#define CCM_CCGR6_CG12_SHIFT (24U)
+#define CCM_CCGR6_CG12(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG12_SHIFT)) & CCM_CCGR6_CG12_MASK)
+#define CCM_CCGR6_CG13_MASK (0xC000000U)
+#define CCM_CCGR6_CG13_SHIFT (26U)
+#define CCM_CCGR6_CG13(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG13_SHIFT)) & CCM_CCGR6_CG13_MASK)
+#define CCM_CCGR6_CG14_MASK (0x30000000U)
+#define CCM_CCGR6_CG14_SHIFT (28U)
+#define CCM_CCGR6_CG14(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG14_SHIFT)) & CCM_CCGR6_CG14_MASK)
+#define CCM_CCGR6_CG15_MASK (0xC0000000U)
+#define CCM_CCGR6_CG15_SHIFT (30U)
+#define CCM_CCGR6_CG15(x) (((uint32_t)(((uint32_t)(x)) << CCM_CCGR6_CG15_SHIFT)) & CCM_CCGR6_CG15_MASK)
+/*! @} */
+
+/*! @name CMEOR - CCM Module Enable Overide Register */
+/*! @{ */
+#define CCM_CMEOR_MOD_EN_OV_GPT_MASK (0x20U)
+#define CCM_CMEOR_MOD_EN_OV_GPT_SHIFT (5U)
+/*! MOD_EN_OV_GPT
+ * 0b0..don't override module enable signal
+ * 0b1..override module enable signal
+ */
+#define CCM_CMEOR_MOD_EN_OV_GPT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_GPT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_GPT_MASK)
+#define CCM_CMEOR_MOD_EN_OV_PIT_MASK (0x40U)
+#define CCM_CMEOR_MOD_EN_OV_PIT_SHIFT (6U)
+/*! MOD_EN_OV_PIT
+ * 0b0..don't override module enable signal
+ * 0b1..override module enable signal
+ */
+#define CCM_CMEOR_MOD_EN_OV_PIT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_PIT_SHIFT)) & CCM_CMEOR_MOD_EN_OV_PIT_MASK)
+#define CCM_CMEOR_MOD_EN_USDHC_MASK (0x80U)
+#define CCM_CMEOR_MOD_EN_USDHC_SHIFT (7U)
+/*! MOD_EN_USDHC
+ * 0b0..don't override module enable signal
+ * 0b1..override module enable signal
+ */
+#define CCM_CMEOR_MOD_EN_USDHC(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_USDHC_SHIFT)) & CCM_CMEOR_MOD_EN_USDHC_MASK)
+#define CCM_CMEOR_MOD_EN_OV_TRNG_MASK (0x200U)
+#define CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT (9U)
+/*! MOD_EN_OV_TRNG
+ * 0b0..don't override module enable signal
+ * 0b1..override module enable signal
+ */
+#define CCM_CMEOR_MOD_EN_OV_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_TRNG_SHIFT)) & CCM_CMEOR_MOD_EN_OV_TRNG_MASK)
+#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK (0x10000000U)
+#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT (28U)
+/*! MOD_EN_OV_CAN2_CPI
+ * 0b0..don't override module enable signal
+ * 0b1..override module enable signal
+ */
+#define CCM_CMEOR_MOD_EN_OV_CAN2_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN2_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN2_CPI_MASK)
+#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK (0x40000000U)
+#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT (30U)
+/*! MOD_EN_OV_CAN1_CPI
+ * 0b0..don't overide module enable signal
+ * 0b1..overide module enable signal
+ */
+#define CCM_CMEOR_MOD_EN_OV_CAN1_CPI(x) (((uint32_t)(((uint32_t)(x)) << CCM_CMEOR_MOD_EN_OV_CAN1_CPI_SHIFT)) & CCM_CMEOR_MOD_EN_OV_CAN1_CPI_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CCM_Register_Masks */
+
+
+/* CCM - Peripheral instance base addresses */
+/** Peripheral CCM base address */
+#define CCM_BASE (0x400FC000u)
+/** Peripheral CCM base pointer */
+#define CCM ((CCM_Type *)CCM_BASE)
+/** Array initializer of CCM peripheral base addresses */
+#define CCM_BASE_ADDRS { CCM_BASE }
+/** Array initializer of CCM peripheral base pointers */
+#define CCM_BASE_PTRS { CCM }
+/** Interrupt vectors for the CCM peripheral type */
+#define CCM_IRQS { CCM_1_IRQn, CCM_2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CCM_ANALOG Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CCM_ANALOG_Peripheral_Access_Layer CCM_ANALOG Peripheral Access Layer
+ * @{
+ */
+
+/** CCM_ANALOG - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PLL_ARM; /**< Analog ARM PLL control Register, offset: 0x0 */
+ __IO uint32_t PLL_ARM_SET; /**< Analog ARM PLL control Register, offset: 0x4 */
+ __IO uint32_t PLL_ARM_CLR; /**< Analog ARM PLL control Register, offset: 0x8 */
+ __IO uint32_t PLL_ARM_TOG; /**< Analog ARM PLL control Register, offset: 0xC */
+ __IO uint32_t PLL_USB1; /**< Analog USB1 480MHz PLL Control Register, offset: 0x10 */
+ __IO uint32_t PLL_USB1_SET; /**< Analog USB1 480MHz PLL Control Register, offset: 0x14 */
+ __IO uint32_t PLL_USB1_CLR; /**< Analog USB1 480MHz PLL Control Register, offset: 0x18 */
+ __IO uint32_t PLL_USB1_TOG; /**< Analog USB1 480MHz PLL Control Register, offset: 0x1C */
+ __IO uint32_t PLL_USB2; /**< Analog USB2 480MHz PLL Control Register, offset: 0x20 */
+ __IO uint32_t PLL_USB2_SET; /**< Analog USB2 480MHz PLL Control Register, offset: 0x24 */
+ __IO uint32_t PLL_USB2_CLR; /**< Analog USB2 480MHz PLL Control Register, offset: 0x28 */
+ __IO uint32_t PLL_USB2_TOG; /**< Analog USB2 480MHz PLL Control Register, offset: 0x2C */
+ __IO uint32_t PLL_SYS; /**< Analog System PLL Control Register, offset: 0x30 */
+ __IO uint32_t PLL_SYS_SET; /**< Analog System PLL Control Register, offset: 0x34 */
+ __IO uint32_t PLL_SYS_CLR; /**< Analog System PLL Control Register, offset: 0x38 */
+ __IO uint32_t PLL_SYS_TOG; /**< Analog System PLL Control Register, offset: 0x3C */
+ __IO uint32_t PLL_SYS_SS; /**< 528MHz System PLL Spread Spectrum Register, offset: 0x40 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t PLL_SYS_NUM; /**< Numerator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x50 */
+ uint8_t RESERVED_1[12];
+ __IO uint32_t PLL_SYS_DENOM; /**< Denominator of 528MHz System PLL Fractional Loop Divider Register, offset: 0x60 */
+ uint8_t RESERVED_2[12];
+ __IO uint32_t PLL_AUDIO; /**< Analog Audio PLL control Register, offset: 0x70 */
+ __IO uint32_t PLL_AUDIO_SET; /**< Analog Audio PLL control Register, offset: 0x74 */
+ __IO uint32_t PLL_AUDIO_CLR; /**< Analog Audio PLL control Register, offset: 0x78 */
+ __IO uint32_t PLL_AUDIO_TOG; /**< Analog Audio PLL control Register, offset: 0x7C */
+ __IO uint32_t PLL_AUDIO_NUM; /**< Numerator of Audio PLL Fractional Loop Divider Register, offset: 0x80 */
+ uint8_t RESERVED_3[12];
+ __IO uint32_t PLL_AUDIO_DENOM; /**< Denominator of Audio PLL Fractional Loop Divider Register, offset: 0x90 */
+ uint8_t RESERVED_4[12];
+ __IO uint32_t PLL_VIDEO; /**< Analog Video PLL control Register, offset: 0xA0 */
+ __IO uint32_t PLL_VIDEO_SET; /**< Analog Video PLL control Register, offset: 0xA4 */
+ __IO uint32_t PLL_VIDEO_CLR; /**< Analog Video PLL control Register, offset: 0xA8 */
+ __IO uint32_t PLL_VIDEO_TOG; /**< Analog Video PLL control Register, offset: 0xAC */
+ __IO uint32_t PLL_VIDEO_NUM; /**< Numerator of Video PLL Fractional Loop Divider Register, offset: 0xB0 */
+ uint8_t RESERVED_5[12];
+ __IO uint32_t PLL_VIDEO_DENOM; /**< Denominator of Video PLL Fractional Loop Divider Register, offset: 0xC0 */
+ uint8_t RESERVED_6[28];
+ __IO uint32_t PLL_ENET; /**< Analog ENET PLL Control Register, offset: 0xE0 */
+ __IO uint32_t PLL_ENET_SET; /**< Analog ENET PLL Control Register, offset: 0xE4 */
+ __IO uint32_t PLL_ENET_CLR; /**< Analog ENET PLL Control Register, offset: 0xE8 */
+ __IO uint32_t PLL_ENET_TOG; /**< Analog ENET PLL Control Register, offset: 0xEC */
+ __IO uint32_t PFD_480; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF0 */
+ __IO uint32_t PFD_480_SET; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF4 */
+ __IO uint32_t PFD_480_CLR; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xF8 */
+ __IO uint32_t PFD_480_TOG; /**< 480MHz Clock (PLL3) Phase Fractional Divider Control Register, offset: 0xFC */
+ __IO uint32_t PFD_528; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x100 */
+ __IO uint32_t PFD_528_SET; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x104 */
+ __IO uint32_t PFD_528_CLR; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x108 */
+ __IO uint32_t PFD_528_TOG; /**< 528MHz Clock (PLL2) Phase Fractional Divider Control Register, offset: 0x10C */
+ uint8_t RESERVED_7[64];
+ __IO uint32_t MISC0; /**< Miscellaneous Register 0, offset: 0x150 */
+ __IO uint32_t MISC0_SET; /**< Miscellaneous Register 0, offset: 0x154 */
+ __IO uint32_t MISC0_CLR; /**< Miscellaneous Register 0, offset: 0x158 */
+ __IO uint32_t MISC0_TOG; /**< Miscellaneous Register 0, offset: 0x15C */
+ __IO uint32_t MISC1; /**< Miscellaneous Register 1, offset: 0x160 */
+ __IO uint32_t MISC1_SET; /**< Miscellaneous Register 1, offset: 0x164 */
+ __IO uint32_t MISC1_CLR; /**< Miscellaneous Register 1, offset: 0x168 */
+ __IO uint32_t MISC1_TOG; /**< Miscellaneous Register 1, offset: 0x16C */
+ __IO uint32_t MISC2; /**< Miscellaneous Register 2, offset: 0x170 */
+ __IO uint32_t MISC2_SET; /**< Miscellaneous Register 2, offset: 0x174 */
+ __IO uint32_t MISC2_CLR; /**< Miscellaneous Register 2, offset: 0x178 */
+ __IO uint32_t MISC2_TOG; /**< Miscellaneous Register 2, offset: 0x17C */
+} CCM_ANALOG_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CCM_ANALOG Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CCM_ANALOG_Register_Masks CCM_ANALOG Register Masks
+ * @{
+ */
+
+/*! @name PLL_ARM - Analog ARM PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_ARM_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_ARM_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_ARM_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_ARM_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_ARM_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_ARM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_ENABLE_MASK)
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_ARM_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_ARM_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_ARM_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_BYPASS_MASK)
+#define CCM_ANALOG_PLL_ARM_PLL_SEL_MASK (0x80000U)
+#define CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT (19U)
+#define CCM_ANALOG_PLL_ARM_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_PLL_SEL_MASK)
+#define CCM_ANALOG_PLL_ARM_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_ARM_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_ARM_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_ARM_SET - Analog ARM PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_ARM_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_ARM_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_ARM_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_ENABLE_MASK)
+#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_ARM_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_BYPASS_MASK)
+#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK (0x80000U)
+#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT (19U)
+#define CCM_ANALOG_PLL_ARM_SET_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_PLL_SEL_MASK)
+#define CCM_ANALOG_PLL_ARM_SET_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_ARM_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_SET_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_ARM_CLR - Analog ARM PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_ARM_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_ARM_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_ENABLE_MASK)
+#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_ARM_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_BYPASS_MASK)
+#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK (0x80000U)
+#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT (19U)
+#define CCM_ANALOG_PLL_ARM_CLR_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_PLL_SEL_MASK)
+#define CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_ARM_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_CLR_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_ARM_TOG - Analog ARM PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_ARM_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_ARM_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_ENABLE_MASK)
+#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_ARM_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_BYPASS_MASK)
+#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK (0x80000U)
+#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT (19U)
+#define CCM_ANALOG_PLL_ARM_TOG_PLL_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_PLL_SEL_MASK)
+#define CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_ARM_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ARM_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ARM_TOG_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_USB1 - Analog USB1 480MHz PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK (0x2U)
+#define CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT (1U)
+#define CCM_ANALOG_PLL_USB1_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK (0x40U)
+#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT (6U)
+/*! EN_USB_CLKS
+ * 0b0..PLL outputs for USBPHYn off.
+ * 0b1..PLL outputs for USBPHYn on.
+ */
+#define CCM_ANALOG_PLL_USB1_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK)
+#define CCM_ANALOG_PLL_USB1_POWER_MASK (0x1000U)
+#define CCM_ANALOG_PLL_USB1_POWER_SHIFT (12U)
+#define CCM_ANALOG_PLL_USB1_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_POWER_MASK)
+#define CCM_ANALOG_PLL_USB1_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_USB1_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_USB1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_ENABLE_MASK)
+#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ */
+#define CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_USB1_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_USB1_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_USB1_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_BYPASS_MASK)
+#define CCM_ANALOG_PLL_USB1_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_USB1_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_USB1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_USB1_SET - Analog USB1 480MHz PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK (0x2U)
+#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT (1U)
+#define CCM_ANALOG_PLL_USB1_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK (0x40U)
+#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT (6U)
+/*! EN_USB_CLKS
+ * 0b0..PLL outputs for USBPHYn off.
+ * 0b1..PLL outputs for USBPHYn on.
+ */
+#define CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_EN_USB_CLKS_MASK)
+#define CCM_ANALOG_PLL_USB1_SET_POWER_MASK (0x1000U)
+#define CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT (12U)
+#define CCM_ANALOG_PLL_USB1_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_POWER_MASK)
+#define CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_USB1_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_ENABLE_MASK)
+#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ */
+#define CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_USB1_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_BYPASS_MASK)
+#define CCM_ANALOG_PLL_USB1_SET_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_USB1_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_SET_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_USB1_CLR - Analog USB1 480MHz PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK (0x2U)
+#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT (1U)
+#define CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK (0x40U)
+#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT (6U)
+/*! EN_USB_CLKS
+ * 0b0..PLL outputs for USBPHYn off.
+ * 0b1..PLL outputs for USBPHYn on.
+ */
+#define CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_EN_USB_CLKS_MASK)
+#define CCM_ANALOG_PLL_USB1_CLR_POWER_MASK (0x1000U)
+#define CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT (12U)
+#define CCM_ANALOG_PLL_USB1_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_POWER_MASK)
+#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_USB1_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_ENABLE_MASK)
+#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ */
+#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_USB1_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_BYPASS_MASK)
+#define CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_USB1_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_CLR_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_USB1_TOG - Analog USB1 480MHz PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK (0x2U)
+#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT (1U)
+#define CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK (0x40U)
+#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT (6U)
+/*! EN_USB_CLKS
+ * 0b0..PLL outputs for USBPHYn off.
+ * 0b1..PLL outputs for USBPHYn on.
+ */
+#define CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_EN_USB_CLKS_MASK)
+#define CCM_ANALOG_PLL_USB1_TOG_POWER_MASK (0x1000U)
+#define CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT (12U)
+#define CCM_ANALOG_PLL_USB1_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_POWER_MASK)
+#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_USB1_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_ENABLE_MASK)
+#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ */
+#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_USB1_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_BYPASS_MASK)
+#define CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_USB1_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB1_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB1_TOG_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_USB2 - Analog USB2 480MHz PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK (0x2U)
+#define CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT (1U)
+#define CCM_ANALOG_PLL_USB2_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK (0x40U)
+#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT (6U)
+#define CCM_ANALOG_PLL_USB2_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_EN_USB_CLKS_MASK)
+#define CCM_ANALOG_PLL_USB2_POWER_MASK (0x1000U)
+#define CCM_ANALOG_PLL_USB2_POWER_SHIFT (12U)
+#define CCM_ANALOG_PLL_USB2_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_POWER_MASK)
+#define CCM_ANALOG_PLL_USB2_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_USB2_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_USB2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_ENABLE_MASK)
+#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_USB2_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_USB2_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_USB2_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_BYPASS_MASK)
+#define CCM_ANALOG_PLL_USB2_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_USB2_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_USB2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_USB2_SET - Analog USB2 480MHz PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK (0x2U)
+#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT (1U)
+#define CCM_ANALOG_PLL_USB2_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK (0x40U)
+#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT (6U)
+#define CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_EN_USB_CLKS_MASK)
+#define CCM_ANALOG_PLL_USB2_SET_POWER_MASK (0x1000U)
+#define CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT (12U)
+#define CCM_ANALOG_PLL_USB2_SET_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_POWER_MASK)
+#define CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_USB2_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_ENABLE_MASK)
+#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_USB2_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_BYPASS_MASK)
+#define CCM_ANALOG_PLL_USB2_SET_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_USB2_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_SET_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_USB2_CLR - Analog USB2 480MHz PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK (0x2U)
+#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT (1U)
+#define CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK (0x40U)
+#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT (6U)
+#define CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_EN_USB_CLKS_MASK)
+#define CCM_ANALOG_PLL_USB2_CLR_POWER_MASK (0x1000U)
+#define CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT (12U)
+#define CCM_ANALOG_PLL_USB2_CLR_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_POWER_MASK)
+#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_USB2_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_ENABLE_MASK)
+#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_USB2_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_BYPASS_MASK)
+#define CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_USB2_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_CLR_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_USB2_TOG - Analog USB2 480MHz PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK (0x2U)
+#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT (1U)
+#define CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK (0x40U)
+#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT (6U)
+#define CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_EN_USB_CLKS_MASK)
+#define CCM_ANALOG_PLL_USB2_TOG_POWER_MASK (0x1000U)
+#define CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT (12U)
+#define CCM_ANALOG_PLL_USB2_TOG_POWER(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_POWER_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_POWER_MASK)
+#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_USB2_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_ENABLE_MASK)
+#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_USB2_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_BYPASS_MASK)
+#define CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_USB2_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_USB2_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_USB2_TOG_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SYS - Analog System PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK (0x1U)
+#define CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_SYS_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_SYS_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_SYS_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_SYS_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_SYS_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_SYS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_ENABLE_MASK)
+#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ */
+#define CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_SYS_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_SYS_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_SYS_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_BYPASS_MASK)
+#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_SYS_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_SYS_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_SYS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SYS_SET - Analog System PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK (0x1U)
+#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_SYS_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_SYS_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_SYS_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_ENABLE_MASK)
+#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ */
+#define CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_SYS_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_BYPASS_MASK)
+#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_SYS_SET_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_SYS_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_SET_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SYS_CLR - Analog System PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK (0x1U)
+#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_SYS_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_SYS_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_ENABLE_MASK)
+#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ */
+#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_SYS_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_BYPASS_MASK)
+#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_SYS_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_CLR_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SYS_TOG - Analog System PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK (0x1U)
+#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_SYS_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_SYS_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_ENABLE_MASK)
+#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ */
+#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_SYS_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_BYPASS_MASK)
+#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_SYS_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_SYS_TOG_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_SYS_SS - 528MHz System PLL Spread Spectrum Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_SYS_SS_STEP_MASK (0x7FFFU)
+#define CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT (0U)
+#define CCM_ANALOG_PLL_SYS_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STEP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STEP_MASK)
+#define CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK (0x8000U)
+#define CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT (15U)
+/*! ENABLE - Enable bit
+ * 0b0..Spread spectrum modulation disabled
+ * 0b1..Soread spectrum modulation enabled
+ */
+#define CCM_ANALOG_PLL_SYS_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_ENABLE_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_ENABLE_MASK)
+#define CCM_ANALOG_PLL_SYS_SS_STOP_MASK (0xFFFF0000U)
+#define CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT (16U)
+#define CCM_ANALOG_PLL_SYS_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_SS_STOP_SHIFT)) & CCM_ANALOG_PLL_SYS_SS_STOP_MASK)
+/*! @} */
+
+/*! @name PLL_SYS_NUM - Numerator of 528MHz System PLL Fractional Loop Divider Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_SYS_NUM_A_MASK (0x3FFFFFFFU)
+#define CCM_ANALOG_PLL_SYS_NUM_A_SHIFT (0U)
+#define CCM_ANALOG_PLL_SYS_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_NUM_A_SHIFT)) & CCM_ANALOG_PLL_SYS_NUM_A_MASK)
+/*! @} */
+
+/*! @name PLL_SYS_DENOM - Denominator of 528MHz System PLL Fractional Loop Divider Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_SYS_DENOM_B_MASK (0x3FFFFFFFU)
+#define CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT (0U)
+#define CCM_ANALOG_PLL_SYS_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_SYS_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_SYS_DENOM_B_MASK)
+/*! @} */
+
+/*! @name PLL_AUDIO - Analog Audio PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_AUDIO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_AUDIO_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_AUDIO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_ENABLE_MASK)
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_AUDIO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_BYPASS_MASK)
+#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK (0x180000U)
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ * 0b00..Divide by 4.
+ * 0b01..Divide by 2.
+ * 0b10..Divide by 1.
+ * 0b11..Reserved
+ */
+#define CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_POST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_AUDIO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_AUDIO_SET - Analog Audio PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_AUDIO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_ENABLE_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_AUDIO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_BYPASS_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK (0x180000U)
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ * 0b00..Divide by 4.
+ * 0b01..Divide by 2.
+ * 0b10..Divide by 1.
+ * 0b11..Reserved
+ */
+#define CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_POST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_AUDIO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_SET_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_AUDIO_CLR - Analog Audio PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_ENABLE_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_BYPASS_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK (0x180000U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ * 0b00..Divide by 4.
+ * 0b01..Divide by 2.
+ * 0b10..Divide by 1.
+ * 0b11..Reserved
+ */
+#define CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_POST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_AUDIO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_CLR_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_AUDIO_TOG - Analog Audio PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_ENABLE_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_BYPASS_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK (0x180000U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ * 0b00..Divide by 4.
+ * 0b01..Divide by 2.
+ * 0b10..Divide by 1.
+ * 0b11..Reserved
+ */
+#define CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_POST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_AUDIO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_AUDIO_TOG_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_AUDIO_NUM - Numerator of Audio PLL Fractional Loop Divider Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_MASK (0x3FFFFFFFU)
+#define CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT (0U)
+#define CCM_ANALOG_PLL_AUDIO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_AUDIO_NUM_A_MASK)
+/*! @} */
+
+/*! @name PLL_AUDIO_DENOM - Denominator of Audio PLL Fractional Loop Divider Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK (0x3FFFFFFFU)
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT (0U)
+#define CCM_ANALOG_PLL_AUDIO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_AUDIO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_AUDIO_DENOM_B_MASK)
+/*! @} */
+
+/*! @name PLL_VIDEO - Analog Video PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_VIDEO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_VIDEO_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_VIDEO_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_VIDEO_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_ENABLE_MASK)
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_VIDEO_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_BYPASS_MASK)
+#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK (0x180000U)
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ * 0b00..Divide by 4.
+ * 0b01..Divide by 2.
+ * 0b10..Divide by 1.
+ * 0b11..Reserved
+ */
+#define CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_VIDEO_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_VIDEO_SET - Analog Video PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_VIDEO_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_ENABLE_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_VIDEO_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_BYPASS_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK (0x180000U)
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ * 0b00..Divide by 4.
+ * 0b01..Divide by 2.
+ * 0b10..Divide by 1.
+ * 0b11..Reserved
+ */
+#define CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_POST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_VIDEO_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_SET_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_VIDEO_CLR - Analog Video PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_ENABLE_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_BYPASS_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK (0x180000U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ * 0b00..Divide by 4.
+ * 0b01..Divide by 2.
+ * 0b10..Divide by 1.
+ * 0b11..Reserved
+ */
+#define CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_POST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_VIDEO_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_CLR_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_VIDEO_TOG - Analog Video PLL control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK (0x7FU)
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_ENABLE_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_BYPASS_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK (0x180000U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT (19U)
+/*! POST_DIV_SELECT
+ * 0b00..Divide by 4.
+ * 0b01..Divide by 2.
+ * 0b10..Divide by 1.
+ * 0b11..Reserved
+ */
+#define CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_POST_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_VIDEO_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_VIDEO_TOG_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_VIDEO_NUM - Numerator of Video PLL Fractional Loop Divider Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_VIDEO_NUM_A_MASK (0x3FFFFFFFU)
+#define CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT (0U)
+#define CCM_ANALOG_PLL_VIDEO_NUM_A(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_NUM_A_SHIFT)) & CCM_ANALOG_PLL_VIDEO_NUM_A_MASK)
+/*! @} */
+
+/*! @name PLL_VIDEO_DENOM - Denominator of Video PLL Fractional Loop Divider Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK (0x3FFFFFFFU)
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT (0U)
+#define CCM_ANALOG_PLL_VIDEO_DENOM_B(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_VIDEO_DENOM_B_SHIFT)) & CCM_ANALOG_PLL_VIDEO_DENOM_B_MASK)
+/*! @} */
+
+/*! @name PLL_ENET - Analog ENET PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK (0x3U)
+#define CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_ENET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_ENET_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_ENET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_ENET_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_ENET_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_ENET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_ENABLE_MASK)
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_ENET_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_ENET_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_ENET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_BYPASS_MASK)
+#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK (0x200000U)
+#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT (21U)
+#define CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_MASK)
+#define CCM_ANALOG_PLL_ENET_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_ENET_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_ENET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_ENET_SET - Analog ENET PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK (0x3U)
+#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_ENET_SET_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_ENET_SET_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_ENET_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENABLE_MASK)
+#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_ENET_SET_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_BYPASS_MASK)
+#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK (0x200000U)
+#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT (21U)
+#define CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_ENET_25M_REF_EN_MASK)
+#define CCM_ANALOG_PLL_ENET_SET_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_ENET_SET_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_SET_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_SET_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_ENET_CLR - Analog ENET PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK (0x3U)
+#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_ENET_CLR_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_ENET_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENABLE_MASK)
+#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_ENET_CLR_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_BYPASS_MASK)
+#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK (0x200000U)
+#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT (21U)
+#define CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_ENET_25M_REF_EN_MASK)
+#define CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_ENET_CLR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_CLR_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_CLR_LOCK_MASK)
+/*! @} */
+
+/*! @name PLL_ENET_TOG - Analog ENET PLL Control Register */
+/*! @{ */
+#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK (0x3U)
+#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT (0U)
+#define CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_DIV_SELECT_MASK)
+#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK (0x1000U)
+#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT (12U)
+#define CCM_ANALOG_PLL_ENET_TOG_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_POWERDOWN_MASK)
+#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK (0x2000U)
+#define CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT (13U)
+#define CCM_ANALOG_PLL_ENET_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENABLE_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENABLE_MASK)
+#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK (0xC000U)
+#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT (14U)
+/*! BYPASS_CLK_SRC
+ * 0b00..Select the 24MHz oscillator as source.
+ * 0b01..Select the CLK1_N / CLK1_P as source.
+ * 0b10..Reserved1
+ * 0b11..Reserved2
+ */
+#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_CLK_SRC_MASK)
+#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK (0x10000U)
+#define CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT (16U)
+#define CCM_ANALOG_PLL_ENET_TOG_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_BYPASS_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_BYPASS_MASK)
+#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK (0x40000U)
+#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT (18U)
+#define CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_PFD_OFFSET_EN_MASK)
+#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK (0x200000U)
+#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT (21U)
+#define CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_ENET_25M_REF_EN_MASK)
+#define CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK (0x80000000U)
+#define CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT (31U)
+#define CCM_ANALOG_PLL_ENET_TOG_LOCK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PLL_ENET_TOG_LOCK_SHIFT)) & CCM_ANALOG_PLL_ENET_TOG_LOCK_MASK)
+/*! @} */
+
+/*! @name PFD_480 - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
+/*! @{ */
+#define CCM_ANALOG_PFD_480_PFD0_FRAC_MASK (0x3FU)
+#define CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT (0U)
+#define CCM_ANALOG_PFD_480_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_PFD0_STABLE_MASK (0x40U)
+#define CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT (6U)
+#define CCM_ANALOG_PFD_480_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK (0x80U)
+#define CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT (7U)
+#define CCM_ANALOG_PFD_480_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD0_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_PFD1_FRAC_MASK (0x3F00U)
+#define CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT (8U)
+#define CCM_ANALOG_PFD_480_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_PFD1_STABLE_MASK (0x4000U)
+#define CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT (14U)
+#define CCM_ANALOG_PFD_480_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK (0x8000U)
+#define CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT (15U)
+#define CCM_ANALOG_PFD_480_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD1_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_PFD2_FRAC_MASK (0x3F0000U)
+#define CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT (16U)
+#define CCM_ANALOG_PFD_480_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_PFD2_STABLE_MASK (0x400000U)
+#define CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT (22U)
+#define CCM_ANALOG_PFD_480_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK (0x800000U)
+#define CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT (23U)
+#define CCM_ANALOG_PFD_480_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD2_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_PFD3_FRAC_MASK (0x3F000000U)
+#define CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT (24U)
+#define CCM_ANALOG_PFD_480_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_PFD3_STABLE_MASK (0x40000000U)
+#define CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT (30U)
+#define CCM_ANALOG_PFD_480_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK (0x80000000U)
+#define CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT (31U)
+#define CCM_ANALOG_PFD_480_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_PFD3_CLKGATE_MASK)
+/*! @} */
+
+/*! @name PFD_480_SET - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
+/*! @{ */
+#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK (0x3FU)
+#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT (0U)
+#define CCM_ANALOG_PFD_480_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK (0x40U)
+#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT (6U)
+#define CCM_ANALOG_PFD_480_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK (0x80U)
+#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT (7U)
+#define CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD0_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK (0x3F00U)
+#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT (8U)
+#define CCM_ANALOG_PFD_480_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK (0x4000U)
+#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT (14U)
+#define CCM_ANALOG_PFD_480_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK (0x8000U)
+#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT (15U)
+#define CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD1_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK (0x3F0000U)
+#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT (16U)
+#define CCM_ANALOG_PFD_480_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK (0x400000U)
+#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT (22U)
+#define CCM_ANALOG_PFD_480_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK (0x800000U)
+#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT (23U)
+#define CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD2_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK (0x3F000000U)
+#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT (24U)
+#define CCM_ANALOG_PFD_480_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK (0x40000000U)
+#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT (30U)
+#define CCM_ANALOG_PFD_480_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK (0x80000000U)
+#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT (31U)
+#define CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_SET_PFD3_CLKGATE_MASK)
+/*! @} */
+
+/*! @name PFD_480_CLR - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
+/*! @{ */
+#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK (0x3FU)
+#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT (0U)
+#define CCM_ANALOG_PFD_480_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK (0x40U)
+#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT (6U)
+#define CCM_ANALOG_PFD_480_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK (0x80U)
+#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT (7U)
+#define CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD0_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK (0x3F00U)
+#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT (8U)
+#define CCM_ANALOG_PFD_480_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK (0x4000U)
+#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT (14U)
+#define CCM_ANALOG_PFD_480_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK (0x8000U)
+#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT (15U)
+#define CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD1_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK (0x3F0000U)
+#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT (16U)
+#define CCM_ANALOG_PFD_480_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK (0x400000U)
+#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT (22U)
+#define CCM_ANALOG_PFD_480_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK (0x800000U)
+#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT (23U)
+#define CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD2_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK (0x3F000000U)
+#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT (24U)
+#define CCM_ANALOG_PFD_480_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK (0x40000000U)
+#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT (30U)
+#define CCM_ANALOG_PFD_480_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK (0x80000000U)
+#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT (31U)
+#define CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_CLR_PFD3_CLKGATE_MASK)
+/*! @} */
+
+/*! @name PFD_480_TOG - 480MHz Clock (PLL3) Phase Fractional Divider Control Register */
+/*! @{ */
+#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK (0x3FU)
+#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT (0U)
+#define CCM_ANALOG_PFD_480_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK (0x40U)
+#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT (6U)
+#define CCM_ANALOG_PFD_480_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK (0x80U)
+#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT (7U)
+#define CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD0_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK (0x3F00U)
+#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT (8U)
+#define CCM_ANALOG_PFD_480_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK (0x4000U)
+#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT (14U)
+#define CCM_ANALOG_PFD_480_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK (0x8000U)
+#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT (15U)
+#define CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD1_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK (0x3F0000U)
+#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT (16U)
+#define CCM_ANALOG_PFD_480_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK (0x400000U)
+#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT (22U)
+#define CCM_ANALOG_PFD_480_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK (0x800000U)
+#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT (23U)
+#define CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD2_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK (0x3F000000U)
+#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT (24U)
+#define CCM_ANALOG_PFD_480_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_FRAC_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK (0x40000000U)
+#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT (30U)
+#define CCM_ANALOG_PFD_480_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_STABLE_MASK)
+#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK (0x80000000U)
+#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT (31U)
+#define CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_480_TOG_PFD3_CLKGATE_MASK)
+/*! @} */
+
+/*! @name PFD_528 - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
+/*! @{ */
+#define CCM_ANALOG_PFD_528_PFD0_FRAC_MASK (0x3FU)
+#define CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT (0U)
+#define CCM_ANALOG_PFD_528_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_PFD0_STABLE_MASK (0x40U)
+#define CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT (6U)
+#define CCM_ANALOG_PFD_528_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK (0x80U)
+#define CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT (7U)
+#define CCM_ANALOG_PFD_528_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD0_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_PFD1_FRAC_MASK (0x3F00U)
+#define CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT (8U)
+#define CCM_ANALOG_PFD_528_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_PFD1_STABLE_MASK (0x4000U)
+#define CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT (14U)
+#define CCM_ANALOG_PFD_528_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK (0x8000U)
+#define CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT (15U)
+#define CCM_ANALOG_PFD_528_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD1_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_PFD2_FRAC_MASK (0x3F0000U)
+#define CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT (16U)
+#define CCM_ANALOG_PFD_528_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_PFD2_STABLE_MASK (0x400000U)
+#define CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT (22U)
+#define CCM_ANALOG_PFD_528_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK (0x800000U)
+#define CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT (23U)
+#define CCM_ANALOG_PFD_528_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD2_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_PFD3_FRAC_MASK (0x3F000000U)
+#define CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT (24U)
+#define CCM_ANALOG_PFD_528_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_PFD3_STABLE_MASK (0x40000000U)
+#define CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT (30U)
+#define CCM_ANALOG_PFD_528_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK (0x80000000U)
+#define CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT (31U)
+#define CCM_ANALOG_PFD_528_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_PFD3_CLKGATE_MASK)
+/*! @} */
+
+/*! @name PFD_528_SET - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
+/*! @{ */
+#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK (0x3FU)
+#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT (0U)
+#define CCM_ANALOG_PFD_528_SET_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK (0x40U)
+#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT (6U)
+#define CCM_ANALOG_PFD_528_SET_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK (0x80U)
+#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT (7U)
+#define CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD0_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK (0x3F00U)
+#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT (8U)
+#define CCM_ANALOG_PFD_528_SET_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK (0x4000U)
+#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT (14U)
+#define CCM_ANALOG_PFD_528_SET_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK (0x8000U)
+#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT (15U)
+#define CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD1_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK (0x3F0000U)
+#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT (16U)
+#define CCM_ANALOG_PFD_528_SET_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK (0x400000U)
+#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT (22U)
+#define CCM_ANALOG_PFD_528_SET_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK (0x800000U)
+#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT (23U)
+#define CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD2_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK (0x3F000000U)
+#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT (24U)
+#define CCM_ANALOG_PFD_528_SET_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK (0x40000000U)
+#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT (30U)
+#define CCM_ANALOG_PFD_528_SET_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK (0x80000000U)
+#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT (31U)
+#define CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_SET_PFD3_CLKGATE_MASK)
+/*! @} */
+
+/*! @name PFD_528_CLR - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
+/*! @{ */
+#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK (0x3FU)
+#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT (0U)
+#define CCM_ANALOG_PFD_528_CLR_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK (0x40U)
+#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT (6U)
+#define CCM_ANALOG_PFD_528_CLR_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK (0x80U)
+#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT (7U)
+#define CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD0_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK (0x3F00U)
+#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT (8U)
+#define CCM_ANALOG_PFD_528_CLR_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK (0x4000U)
+#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT (14U)
+#define CCM_ANALOG_PFD_528_CLR_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK (0x8000U)
+#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT (15U)
+#define CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD1_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK (0x3F0000U)
+#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT (16U)
+#define CCM_ANALOG_PFD_528_CLR_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK (0x400000U)
+#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT (22U)
+#define CCM_ANALOG_PFD_528_CLR_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK (0x800000U)
+#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT (23U)
+#define CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD2_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK (0x3F000000U)
+#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT (24U)
+#define CCM_ANALOG_PFD_528_CLR_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK (0x40000000U)
+#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT (30U)
+#define CCM_ANALOG_PFD_528_CLR_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK (0x80000000U)
+#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT (31U)
+#define CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_CLR_PFD3_CLKGATE_MASK)
+/*! @} */
+
+/*! @name PFD_528_TOG - 528MHz Clock (PLL2) Phase Fractional Divider Control Register */
+/*! @{ */
+#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK (0x3FU)
+#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT (0U)
+#define CCM_ANALOG_PFD_528_TOG_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK (0x40U)
+#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT (6U)
+#define CCM_ANALOG_PFD_528_TOG_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK (0x80U)
+#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT (7U)
+#define CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD0_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK (0x3F00U)
+#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT (8U)
+#define CCM_ANALOG_PFD_528_TOG_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK (0x4000U)
+#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT (14U)
+#define CCM_ANALOG_PFD_528_TOG_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK (0x8000U)
+#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT (15U)
+#define CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD1_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK (0x3F0000U)
+#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT (16U)
+#define CCM_ANALOG_PFD_528_TOG_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK (0x400000U)
+#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT (22U)
+#define CCM_ANALOG_PFD_528_TOG_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK (0x800000U)
+#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT (23U)
+#define CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD2_CLKGATE_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK (0x3F000000U)
+#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT (24U)
+#define CCM_ANALOG_PFD_528_TOG_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_FRAC_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK (0x40000000U)
+#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT (30U)
+#define CCM_ANALOG_PFD_528_TOG_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_STABLE_MASK)
+#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK (0x80000000U)
+#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT (31U)
+#define CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_SHIFT)) & CCM_ANALOG_PFD_528_TOG_PFD3_CLKGATE_MASK)
+/*! @} */
+
+/*! @name MISC0 - Miscellaneous Register 0 */
+/*! @{ */
+#define CCM_ANALOG_MISC0_REFTOP_PWD_MASK (0x1U)
+#define CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT (0U)
+#define CCM_ANALOG_MISC0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_PWD_MASK)
+#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK (0x8U)
+#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ * 0b0..Uses coarse bias currents for startup
+ * 0b1..Uses bandgap-based bias currents for best performance.
+ */
+#define CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_SELFBIASOFF_MASK)
+#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK (0x70U)
+#define CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT (4U)
+/*! REFTOP_VBGADJ
+ * 0b000..Nominal VBG
+ * 0b001..VBG+0.78%
+ * 0b010..VBG+1.56%
+ * 0b011..VBG+2.34%
+ * 0b100..VBG-0.78%
+ * 0b101..VBG-1.56%
+ * 0b110..VBG-2.34%
+ * 0b111..VBG-3.12%
+ */
+#define CCM_ANALOG_MISC0_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGADJ_MASK)
+#define CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK (0x80U)
+#define CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT (7U)
+#define CCM_ANALOG_MISC0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_REFTOP_VBGUP_MASK)
+#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK (0xC00U)
+#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT (10U)
+/*! STOP_MODE_CONFIG
+ * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
+#define CCM_ANALOG_MISC0_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_STOP_MODE_CONFIG_MASK)
+#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK (0x1000U)
+#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT (12U)
+/*! DISCON_HIGH_SNVS
+ * 0b0..Turn on the switch
+ * 0b1..Turn off the switch
+ */
+#define CCM_ANALOG_MISC0_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_DISCON_HIGH_SNVS_MASK)
+#define CCM_ANALOG_MISC0_OSC_I_MASK (0x6000U)
+#define CCM_ANALOG_MISC0_OSC_I_SHIFT (13U)
+/*! OSC_I
+ * 0b00..Nominal
+ * 0b01..Decrease current by 12.5%
+ * 0b10..Decrease current by 25.0%
+ * 0b11..Decrease current by 37.5%
+ */
+#define CCM_ANALOG_MISC0_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_OSC_I_MASK)
+#define CCM_ANALOG_MISC0_OSC_XTALOK_MASK (0x8000U)
+#define CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT (15U)
+#define CCM_ANALOG_MISC0_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_MASK)
+#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK (0x10000U)
+#define CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT (16U)
+#define CCM_ANALOG_MISC0_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_OSC_XTALOK_EN_MASK)
+#define CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK (0x2000000U)
+#define CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT (25U)
+/*! CLKGATE_CTRL
+ * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ * 0b1..Prevent the logic from ever gating off the clock.
+ */
+#define CCM_ANALOG_MISC0_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_CTRL_MASK)
+#define CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK (0x1C000000U)
+#define CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT (26U)
+/*! CLKGATE_DELAY
+ * 0b000..0.5ms
+ * 0b001..1.0ms
+ * 0b010..2.0ms
+ * 0b011..3.0ms
+ * 0b100..4.0ms
+ * 0b101..5.0ms
+ * 0b110..6.0ms
+ * 0b111..7.0ms
+ */
+#define CCM_ANALOG_MISC0_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLKGATE_DELAY_MASK)
+#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK (0x20000000U)
+#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT (29U)
+/*! RTC_XTAL_SOURCE
+ * 0b0..Internal ring oscillator
+ * 0b1..RTC_XTAL
+ */
+#define CCM_ANALOG_MISC0_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_RTC_XTAL_SOURCE_MASK)
+#define CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK (0x40000000U)
+#define CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT (30U)
+#define CCM_ANALOG_MISC0_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_XTAL_24M_PWD_MASK)
+/*! @} */
+
+/*! @name MISC0_SET - Miscellaneous Register 0 */
+/*! @{ */
+#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK (0x1U)
+#define CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT (0U)
+#define CCM_ANALOG_MISC0_SET_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_PWD_MASK)
+#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK (0x8U)
+#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ * 0b0..Uses coarse bias currents for startup
+ * 0b1..Uses bandgap-based bias currents for best performance.
+ */
+#define CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_SELFBIASOFF_MASK)
+#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK (0x70U)
+#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT (4U)
+/*! REFTOP_VBGADJ
+ * 0b000..Nominal VBG
+ * 0b001..VBG+0.78%
+ * 0b010..VBG+1.56%
+ * 0b011..VBG+2.34%
+ * 0b100..VBG-0.78%
+ * 0b101..VBG-1.56%
+ * 0b110..VBG-2.34%
+ * 0b111..VBG-3.12%
+ */
+#define CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGADJ_MASK)
+#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK (0x80U)
+#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT (7U)
+#define CCM_ANALOG_MISC0_SET_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_SET_REFTOP_VBGUP_MASK)
+#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK (0xC00U)
+#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT (10U)
+/*! STOP_MODE_CONFIG
+ * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
+#define CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_SET_STOP_MODE_CONFIG_MASK)
+#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK (0x1000U)
+#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT (12U)
+/*! DISCON_HIGH_SNVS
+ * 0b0..Turn on the switch
+ * 0b1..Turn off the switch
+ */
+#define CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_SET_DISCON_HIGH_SNVS_MASK)
+#define CCM_ANALOG_MISC0_SET_OSC_I_MASK (0x6000U)
+#define CCM_ANALOG_MISC0_SET_OSC_I_SHIFT (13U)
+/*! OSC_I
+ * 0b00..Nominal
+ * 0b01..Decrease current by 12.5%
+ * 0b10..Decrease current by 25.0%
+ * 0b11..Decrease current by 37.5%
+ */
+#define CCM_ANALOG_MISC0_SET_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_I_MASK)
+#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK (0x8000U)
+#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT (15U)
+#define CCM_ANALOG_MISC0_SET_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_MASK)
+#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK (0x10000U)
+#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT (16U)
+#define CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_SET_OSC_XTALOK_EN_MASK)
+#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK (0x2000000U)
+#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT (25U)
+/*! CLKGATE_CTRL
+ * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ * 0b1..Prevent the logic from ever gating off the clock.
+ */
+#define CCM_ANALOG_MISC0_SET_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_CTRL_MASK)
+#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK (0x1C000000U)
+#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT (26U)
+/*! CLKGATE_DELAY
+ * 0b000..0.5ms
+ * 0b001..1.0ms
+ * 0b010..2.0ms
+ * 0b011..3.0ms
+ * 0b100..4.0ms
+ * 0b101..5.0ms
+ * 0b110..6.0ms
+ * 0b111..7.0ms
+ */
+#define CCM_ANALOG_MISC0_SET_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_SET_CLKGATE_DELAY_MASK)
+#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK (0x20000000U)
+#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT (29U)
+/*! RTC_XTAL_SOURCE
+ * 0b0..Internal ring oscillator
+ * 0b1..RTC_XTAL
+ */
+#define CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_SET_RTC_XTAL_SOURCE_MASK)
+#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK (0x40000000U)
+#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT (30U)
+#define CCM_ANALOG_MISC0_SET_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_SET_XTAL_24M_PWD_MASK)
+/*! @} */
+
+/*! @name MISC0_CLR - Miscellaneous Register 0 */
+/*! @{ */
+#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK (0x1U)
+#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT (0U)
+#define CCM_ANALOG_MISC0_CLR_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_PWD_MASK)
+#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK (0x8U)
+#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ * 0b0..Uses coarse bias currents for startup
+ * 0b1..Uses bandgap-based bias currents for best performance.
+ */
+#define CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_SELFBIASOFF_MASK)
+#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK (0x70U)
+#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT (4U)
+/*! REFTOP_VBGADJ
+ * 0b000..Nominal VBG
+ * 0b001..VBG+0.78%
+ * 0b010..VBG+1.56%
+ * 0b011..VBG+2.34%
+ * 0b100..VBG-0.78%
+ * 0b101..VBG-1.56%
+ * 0b110..VBG-2.34%
+ * 0b111..VBG-3.12%
+ */
+#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGADJ_MASK)
+#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK (0x80U)
+#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT (7U)
+#define CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_CLR_REFTOP_VBGUP_MASK)
+#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK (0xC00U)
+#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT (10U)
+/*! STOP_MODE_CONFIG
+ * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
+#define CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_CLR_STOP_MODE_CONFIG_MASK)
+#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK (0x1000U)
+#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT (12U)
+/*! DISCON_HIGH_SNVS
+ * 0b0..Turn on the switch
+ * 0b1..Turn off the switch
+ */
+#define CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_CLR_DISCON_HIGH_SNVS_MASK)
+#define CCM_ANALOG_MISC0_CLR_OSC_I_MASK (0x6000U)
+#define CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT (13U)
+/*! OSC_I
+ * 0b00..Nominal
+ * 0b01..Decrease current by 12.5%
+ * 0b10..Decrease current by 25.0%
+ * 0b11..Decrease current by 37.5%
+ */
+#define CCM_ANALOG_MISC0_CLR_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_I_MASK)
+#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK (0x8000U)
+#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT (15U)
+#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_MASK)
+#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK (0x10000U)
+#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT (16U)
+#define CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_CLR_OSC_XTALOK_EN_MASK)
+#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK (0x2000000U)
+#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT (25U)
+/*! CLKGATE_CTRL
+ * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ * 0b1..Prevent the logic from ever gating off the clock.
+ */
+#define CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_CTRL_MASK)
+#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK (0x1C000000U)
+#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT (26U)
+/*! CLKGATE_DELAY
+ * 0b000..0.5ms
+ * 0b001..1.0ms
+ * 0b010..2.0ms
+ * 0b011..3.0ms
+ * 0b100..4.0ms
+ * 0b101..5.0ms
+ * 0b110..6.0ms
+ * 0b111..7.0ms
+ */
+#define CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_CLR_CLKGATE_DELAY_MASK)
+#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK (0x20000000U)
+#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT (29U)
+/*! RTC_XTAL_SOURCE
+ * 0b0..Internal ring oscillator
+ * 0b1..RTC_XTAL
+ */
+#define CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_CLR_RTC_XTAL_SOURCE_MASK)
+#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK (0x40000000U)
+#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT (30U)
+#define CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_CLR_XTAL_24M_PWD_MASK)
+/*! @} */
+
+/*! @name MISC0_TOG - Miscellaneous Register 0 */
+/*! @{ */
+#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK (0x1U)
+#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT (0U)
+#define CCM_ANALOG_MISC0_TOG_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_PWD_MASK)
+#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK (0x8U)
+#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT (3U)
+/*! REFTOP_SELFBIASOFF
+ * 0b0..Uses coarse bias currents for startup
+ * 0b1..Uses bandgap-based bias currents for best performance.
+ */
+#define CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_SELFBIASOFF_MASK)
+#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK (0x70U)
+#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT (4U)
+/*! REFTOP_VBGADJ
+ * 0b000..Nominal VBG
+ * 0b001..VBG+0.78%
+ * 0b010..VBG+1.56%
+ * 0b011..VBG+2.34%
+ * 0b100..VBG-0.78%
+ * 0b101..VBG-1.56%
+ * 0b110..VBG-2.34%
+ * 0b111..VBG-3.12%
+ */
+#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGADJ_MASK)
+#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK (0x80U)
+#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT (7U)
+#define CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_SHIFT)) & CCM_ANALOG_MISC0_TOG_REFTOP_VBGUP_MASK)
+#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK (0xC00U)
+#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT (10U)
+/*! STOP_MODE_CONFIG
+ * 0b00..All analog except rtc powered down on stop mode assertion. XtalOsc=on, RCOsc=off;
+ * 0b01..Certain analog functions such as certain regulators left up. XtalOsc=on, RCOsc=off;
+ * 0b10..XtalOsc=off, RCOsc=on, Old BG=on, New BG=off.
+ * 0b11..XtalOsc=off, RCOsc=on, Old BG=off, New BG=on.
+ */
+#define CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_SHIFT)) & CCM_ANALOG_MISC0_TOG_STOP_MODE_CONFIG_MASK)
+#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK (0x1000U)
+#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT (12U)
+/*! DISCON_HIGH_SNVS
+ * 0b0..Turn on the switch
+ * 0b1..Turn off the switch
+ */
+#define CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_SHIFT)) & CCM_ANALOG_MISC0_TOG_DISCON_HIGH_SNVS_MASK)
+#define CCM_ANALOG_MISC0_TOG_OSC_I_MASK (0x6000U)
+#define CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT (13U)
+/*! OSC_I
+ * 0b00..Nominal
+ * 0b01..Decrease current by 12.5%
+ * 0b10..Decrease current by 25.0%
+ * 0b11..Decrease current by 37.5%
+ */
+#define CCM_ANALOG_MISC0_TOG_OSC_I(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_I_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_I_MASK)
+#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK (0x8000U)
+#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT (15U)
+#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_MASK)
+#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK (0x10000U)
+#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT (16U)
+#define CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_SHIFT)) & CCM_ANALOG_MISC0_TOG_OSC_XTALOK_EN_MASK)
+#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK (0x2000000U)
+#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT (25U)
+/*! CLKGATE_CTRL
+ * 0b0..Allow the logic to automatically gate the clock when the XTAL is powered down.
+ * 0b1..Prevent the logic from ever gating off the clock.
+ */
+#define CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_CTRL_MASK)
+#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK (0x1C000000U)
+#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT (26U)
+/*! CLKGATE_DELAY
+ * 0b000..0.5ms
+ * 0b001..1.0ms
+ * 0b010..2.0ms
+ * 0b011..3.0ms
+ * 0b100..4.0ms
+ * 0b101..5.0ms
+ * 0b110..6.0ms
+ * 0b111..7.0ms
+ */
+#define CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_SHIFT)) & CCM_ANALOG_MISC0_TOG_CLKGATE_DELAY_MASK)
+#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK (0x20000000U)
+#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT (29U)
+/*! RTC_XTAL_SOURCE
+ * 0b0..Internal ring oscillator
+ * 0b1..RTC_XTAL
+ */
+#define CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_SHIFT)) & CCM_ANALOG_MISC0_TOG_RTC_XTAL_SOURCE_MASK)
+#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK (0x40000000U)
+#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT (30U)
+#define CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_SHIFT)) & CCM_ANALOG_MISC0_TOG_XTAL_24M_PWD_MASK)
+/*! @} */
+
+/*! @name MISC1 - Miscellaneous Register 1 */
+/*! @{ */
+#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK (0x1FU)
+#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT (0U)
+/*! LVDS1_CLK_SEL
+ * 0b00000..Arm PLL
+ * 0b00001..System PLL
+ * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ * 0b00110..Audio PLL
+ * 0b00111..Video PLL
+ * 0b01001..ethernet ref clock (ENET_PLL)
+ * 0b01100..USB1 PLL clock
+ * 0b01101..USB2 PLL clock
+ * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ * 0b10010..xtal (24M)
+ */
+#define CCM_ANALOG_MISC1_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK (0x400U)
+#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT (10U)
+#define CCM_ANALOG_MISC1_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_OBEN_MASK)
+#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK (0x1000U)
+#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT (12U)
+#define CCM_ANALOG_MISC1_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_LVDSCLK1_IBEN_MASK)
+#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK (0x10000U)
+#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT (16U)
+#define CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_480_AUTOGATE_EN_MASK)
+#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK (0x20000U)
+#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT (17U)
+#define CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_PFD_528_AUTOGATE_EN_MASK)
+#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK (0x8000000U)
+#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT (27U)
+#define CCM_ANALOG_MISC1_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPPANIC_MASK)
+#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK (0x10000000U)
+#define CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT (28U)
+#define CCM_ANALOG_MISC1_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPLOW_MASK)
+#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK (0x20000000U)
+#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT (29U)
+#define CCM_ANALOG_MISC1_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_IRQ_TEMPHIGH_MASK)
+#define CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK (0x40000000U)
+#define CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT (30U)
+#define CCM_ANALOG_MISC1_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_ANA_BO_MASK)
+#define CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK (0x80000000U)
+#define CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT (31U)
+#define CCM_ANALOG_MISC1_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_IRQ_DIG_BO_MASK)
+/*! @} */
+
+/*! @name MISC1_SET - Miscellaneous Register 1 */
+/*! @{ */
+#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK (0x1FU)
+#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT (0U)
+/*! LVDS1_CLK_SEL
+ * 0b00000..Arm PLL
+ * 0b00001..System PLL
+ * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ * 0b00110..Audio PLL
+ * 0b00111..Video PLL
+ * 0b01001..ethernet ref clock (ENET_PLL)
+ * 0b01100..USB1 PLL clock
+ * 0b01101..USB2 PLL clock
+ * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ * 0b10010..xtal (24M)
+ */
+#define CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK (0x400U)
+#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT (10U)
+#define CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_OBEN_MASK)
+#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK (0x1000U)
+#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT (12U)
+#define CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_SET_LVDSCLK1_IBEN_MASK)
+#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK (0x10000U)
+#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT (16U)
+#define CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_480_AUTOGATE_EN_MASK)
+#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK (0x20000U)
+#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT (17U)
+#define CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_SET_PFD_528_AUTOGATE_EN_MASK)
+#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK (0x8000000U)
+#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT (27U)
+#define CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPPANIC_MASK)
+#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK (0x10000000U)
+#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT (28U)
+#define CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPLOW_MASK)
+#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK (0x20000000U)
+#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT (29U)
+#define CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_TEMPHIGH_MASK)
+#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK (0x40000000U)
+#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT (30U)
+#define CCM_ANALOG_MISC1_SET_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_ANA_BO_MASK)
+#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK (0x80000000U)
+#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT (31U)
+#define CCM_ANALOG_MISC1_SET_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_SET_IRQ_DIG_BO_MASK)
+/*! @} */
+
+/*! @name MISC1_CLR - Miscellaneous Register 1 */
+/*! @{ */
+#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK (0x1FU)
+#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT (0U)
+/*! LVDS1_CLK_SEL
+ * 0b00000..Arm PLL
+ * 0b00001..System PLL
+ * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ * 0b00110..Audio PLL
+ * 0b00111..Video PLL
+ * 0b01001..ethernet ref clock (ENET_PLL)
+ * 0b01100..USB1 PLL clock
+ * 0b01101..USB2 PLL clock
+ * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ * 0b10010..xtal (24M)
+ */
+#define CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK (0x400U)
+#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT (10U)
+#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_OBEN_MASK)
+#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK (0x1000U)
+#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT (12U)
+#define CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_CLR_LVDSCLK1_IBEN_MASK)
+#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK (0x10000U)
+#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT (16U)
+#define CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_480_AUTOGATE_EN_MASK)
+#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK (0x20000U)
+#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT (17U)
+#define CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_CLR_PFD_528_AUTOGATE_EN_MASK)
+#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK (0x8000000U)
+#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT (27U)
+#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPPANIC_MASK)
+#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK (0x10000000U)
+#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT (28U)
+#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPLOW_MASK)
+#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK (0x20000000U)
+#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT (29U)
+#define CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_TEMPHIGH_MASK)
+#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK (0x40000000U)
+#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT (30U)
+#define CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_ANA_BO_MASK)
+#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK (0x80000000U)
+#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT (31U)
+#define CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_CLR_IRQ_DIG_BO_MASK)
+/*! @} */
+
+/*! @name MISC1_TOG - Miscellaneous Register 1 */
+/*! @{ */
+#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK (0x1FU)
+#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT (0U)
+/*! LVDS1_CLK_SEL
+ * 0b00000..Arm PLL
+ * 0b00001..System PLL
+ * 0b00010..ref_pfd4_clk == pll2_pfd0_clk
+ * 0b00011..ref_pfd5_clk == pll2_pfd1_clk
+ * 0b00100..ref_pfd6_clk == pll2_pfd2_clk
+ * 0b00101..ref_pfd7_clk == pll2_pfd3_clk
+ * 0b00110..Audio PLL
+ * 0b00111..Video PLL
+ * 0b01001..ethernet ref clock (ENET_PLL)
+ * 0b01100..USB1 PLL clock
+ * 0b01101..USB2 PLL clock
+ * 0b01110..ref_pfd0_clk == pll3_pfd0_clk
+ * 0b01111..ref_pfd1_clk == pll3_pfd1_clk
+ * 0b10000..ref_pfd2_clk == pll3_pfd2_clk
+ * 0b10001..ref_pfd3_clk == pll3_pfd3_clk
+ * 0b10010..xtal (24M)
+ */
+#define CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDS1_CLK_SEL_MASK)
+#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK (0x400U)
+#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT (10U)
+#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_OBEN_MASK)
+#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK (0x1000U)
+#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT (12U)
+#define CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_SHIFT)) & CCM_ANALOG_MISC1_TOG_LVDSCLK1_IBEN_MASK)
+#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK (0x10000U)
+#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT (16U)
+#define CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_480_AUTOGATE_EN_MASK)
+#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK (0x20000U)
+#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT (17U)
+#define CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_SHIFT)) & CCM_ANALOG_MISC1_TOG_PFD_528_AUTOGATE_EN_MASK)
+#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK (0x8000000U)
+#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT (27U)
+#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPPANIC_MASK)
+#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK (0x10000000U)
+#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT (28U)
+#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPLOW_MASK)
+#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK (0x20000000U)
+#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT (29U)
+#define CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_TEMPHIGH_MASK)
+#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK (0x40000000U)
+#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT (30U)
+#define CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_ANA_BO_MASK)
+#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK (0x80000000U)
+#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT (31U)
+#define CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_SHIFT)) & CCM_ANALOG_MISC1_TOG_IRQ_DIG_BO_MASK)
+/*! @} */
+
+/*! @name MISC2 - Miscellaneous Register 2 */
+/*! @{ */
+#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK (0x7U)
+#define CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT (0U)
+/*! REG0_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK (0x8U)
+#define CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT (3U)
+/*! REG0_BO_STATUS
+ * 0b1..Brownout, supply is below target minus brownout offset.
+ */
+#define CCM_ANALOG_MISC2_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG0_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK (0x20U)
+#define CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT (5U)
+#define CCM_ANALOG_MISC2_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG0_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_REG0_OK_MASK (0x40U)
+#define CCM_ANALOG_MISC2_REG0_OK_SHIFT (6U)
+#define CCM_ANALOG_MISC2_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_REG0_OK_MASK)
+#define CCM_ANALOG_MISC2_PLL3_disable_MASK (0x80U)
+#define CCM_ANALOG_MISC2_PLL3_disable_SHIFT (7U)
+/*! PLL3_disable
+ * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
+ * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
+ */
+#define CCM_ANALOG_MISC2_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_PLL3_disable_MASK)
+#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK (0x700U)
+#define CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT (8U)
+/*! REG1_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK (0x800U)
+#define CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT (11U)
+/*! REG1_BO_STATUS
+ * 0b1..Brownout, supply is below target minus brownout offset.
+ */
+#define CCM_ANALOG_MISC2_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG1_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK (0x2000U)
+#define CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT (13U)
+#define CCM_ANALOG_MISC2_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG1_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_REG1_OK_MASK (0x4000U)
+#define CCM_ANALOG_MISC2_REG1_OK_SHIFT (14U)
+#define CCM_ANALOG_MISC2_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_REG1_OK_MASK)
+#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK (0x8000U)
+#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT (15U)
+/*! AUDIO_DIV_LSB
+ * 0b0..divide by 1 (Default)
+ * 0b1..divide by 2
+ */
+#define CCM_ANALOG_MISC2_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK)
+#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK (0x70000U)
+#define CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT (16U)
+/*! REG2_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK (0x80000U)
+#define CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT (19U)
+#define CCM_ANALOG_MISC2_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_REG2_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK (0x200000U)
+#define CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT (21U)
+#define CCM_ANALOG_MISC2_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_REG2_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_REG2_OK_MASK (0x400000U)
+#define CCM_ANALOG_MISC2_REG2_OK_SHIFT (22U)
+#define CCM_ANALOG_MISC2_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_REG2_OK_MASK)
+#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK (0x800000U)
+#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT (23U)
+/*! AUDIO_DIV_MSB
+ * 0b0..divide by 1 (Default)
+ * 0b1..divide by 2
+ */
+#define CCM_ANALOG_MISC2_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK)
+#define CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK (0x3000000U)
+#define CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT (24U)
+/*! REG0_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG0_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK (0xC000000U)
+#define CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT (26U)
+/*! REG1_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG1_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK (0x30000000U)
+#define CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT (28U)
+/*! REG2_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_REG2_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_VIDEO_DIV_MASK (0xC0000000U)
+#define CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT (30U)
+/*! VIDEO_DIV
+ * 0b00..divide by 1 (Default)
+ * 0b01..divide by 2
+ * 0b10..divide by 1
+ * 0b11..divide by 4
+ */
+#define CCM_ANALOG_MISC2_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_VIDEO_DIV_MASK)
+/*! @} */
+
+/*! @name MISC2_SET - Miscellaneous Register 2 */
+/*! @{ */
+#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK (0x7U)
+#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT (0U)
+/*! REG0_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK (0x8U)
+#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT (3U)
+/*! REG0_BO_STATUS
+ * 0b1..Brownout, supply is below target minus brownout offset.
+ */
+#define CCM_ANALOG_MISC2_SET_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK (0x20U)
+#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT (5U)
+#define CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_SET_REG0_OK_MASK (0x40U)
+#define CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT (6U)
+#define CCM_ANALOG_MISC2_SET_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_OK_MASK)
+#define CCM_ANALOG_MISC2_SET_PLL3_disable_MASK (0x80U)
+#define CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT (7U)
+/*! PLL3_disable
+ * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
+ * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
+ */
+#define CCM_ANALOG_MISC2_SET_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_SET_PLL3_disable_MASK)
+#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK (0x700U)
+#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT (8U)
+/*! REG1_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK (0x800U)
+#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT (11U)
+/*! REG1_BO_STATUS
+ * 0b1..Brownout, supply is below target minus brownout offset.
+ */
+#define CCM_ANALOG_MISC2_SET_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK (0x2000U)
+#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT (13U)
+#define CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_SET_REG1_OK_MASK (0x4000U)
+#define CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT (14U)
+#define CCM_ANALOG_MISC2_SET_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_OK_MASK)
+#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK (0x8000U)
+#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT (15U)
+/*! AUDIO_DIV_LSB
+ * 0b0..divide by 1 (Default)
+ * 0b1..divide by 2
+ */
+#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_LSB_MASK)
+#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK (0x70000U)
+#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT (16U)
+/*! REG2_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK (0x80000U)
+#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT (19U)
+#define CCM_ANALOG_MISC2_SET_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK (0x200000U)
+#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT (21U)
+#define CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_SET_REG2_OK_MASK (0x400000U)
+#define CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT (22U)
+#define CCM_ANALOG_MISC2_SET_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_OK_MASK)
+#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK (0x800000U)
+#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT (23U)
+/*! AUDIO_DIV_MSB
+ * 0b0..divide by 1 (Default)
+ * 0b1..divide by 2
+ */
+#define CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_SET_AUDIO_DIV_MSB_MASK)
+#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK (0x3000000U)
+#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT (24U)
+/*! REG0_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_SET_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG0_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK (0xC000000U)
+#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT (26U)
+/*! REG1_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_SET_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG1_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK (0x30000000U)
+#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT (28U)
+/*! REG2_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_SET_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_SET_REG2_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK (0xC0000000U)
+#define CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT (30U)
+/*! VIDEO_DIV
+ * 0b00..divide by 1 (Default)
+ * 0b01..divide by 2
+ * 0b10..divide by 1
+ * 0b11..divide by 4
+ */
+#define CCM_ANALOG_MISC2_SET_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_SET_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_SET_VIDEO_DIV_MASK)
+/*! @} */
+
+/*! @name MISC2_CLR - Miscellaneous Register 2 */
+/*! @{ */
+#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK (0x7U)
+#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT (0U)
+/*! REG0_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK (0x8U)
+#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT (3U)
+/*! REG0_BO_STATUS
+ * 0b1..Brownout, supply is below target minus brownout offset.
+ */
+#define CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK (0x20U)
+#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT (5U)
+#define CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG0_OK_MASK (0x40U)
+#define CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT (6U)
+#define CCM_ANALOG_MISC2_CLR_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_OK_MASK)
+#define CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK (0x80U)
+#define CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT (7U)
+/*! PLL3_disable
+ * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
+ * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
+ */
+#define CCM_ANALOG_MISC2_CLR_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_CLR_PLL3_disable_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK (0x700U)
+#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT (8U)
+/*! REG1_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK (0x800U)
+#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT (11U)
+/*! REG1_BO_STATUS
+ * 0b1..Brownout, supply is below target minus brownout offset.
+ */
+#define CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK (0x2000U)
+#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT (13U)
+#define CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG1_OK_MASK (0x4000U)
+#define CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT (14U)
+#define CCM_ANALOG_MISC2_CLR_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_OK_MASK)
+#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK (0x8000U)
+#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT (15U)
+/*! AUDIO_DIV_LSB
+ * 0b0..divide by 1 (Default)
+ * 0b1..divide by 2
+ */
+#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_LSB_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK (0x70000U)
+#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT (16U)
+/*! REG2_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK (0x80000U)
+#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT (19U)
+#define CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK (0x200000U)
+#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT (21U)
+#define CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG2_OK_MASK (0x400000U)
+#define CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT (22U)
+#define CCM_ANALOG_MISC2_CLR_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_OK_MASK)
+#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK (0x800000U)
+#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT (23U)
+/*! AUDIO_DIV_MSB
+ * 0b0..divide by 1 (Default)
+ * 0b1..divide by 2
+ */
+#define CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_CLR_AUDIO_DIV_MSB_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK (0x3000000U)
+#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT (24U)
+/*! REG0_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG0_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK (0xC000000U)
+#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT (26U)
+/*! REG1_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG1_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK (0x30000000U)
+#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT (28U)
+/*! REG2_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_CLR_REG2_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK (0xC0000000U)
+#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT (30U)
+/*! VIDEO_DIV
+ * 0b00..divide by 1 (Default)
+ * 0b01..divide by 2
+ * 0b10..divide by 1
+ * 0b11..divide by 4
+ */
+#define CCM_ANALOG_MISC2_CLR_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_CLR_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_CLR_VIDEO_DIV_MASK)
+/*! @} */
+
+/*! @name MISC2_TOG - Miscellaneous Register 2 */
+/*! @{ */
+#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK (0x7U)
+#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT (0U)
+/*! REG0_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK (0x8U)
+#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT (3U)
+/*! REG0_BO_STATUS
+ * 0b1..Brownout, supply is below target minus brownout offset.
+ */
+#define CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK (0x20U)
+#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT (5U)
+#define CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG0_OK_MASK (0x40U)
+#define CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT (6U)
+#define CCM_ANALOG_MISC2_TOG_REG0_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_OK_MASK)
+#define CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK (0x80U)
+#define CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT (7U)
+/*! PLL3_disable
+ * 0b0..PLL3 is being used by peripherals and is enabled when SoC is not in any low power mode
+ * 0b1..PLL3 can be disabled when the SoC is not in any low power mode
+ */
+#define CCM_ANALOG_MISC2_TOG_PLL3_disable(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_PLL3_disable_SHIFT)) & CCM_ANALOG_MISC2_TOG_PLL3_disable_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK (0x700U)
+#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT (8U)
+/*! REG1_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK (0x800U)
+#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT (11U)
+/*! REG1_BO_STATUS
+ * 0b1..Brownout, supply is below target minus brownout offset.
+ */
+#define CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK (0x2000U)
+#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT (13U)
+#define CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG1_OK_MASK (0x4000U)
+#define CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT (14U)
+#define CCM_ANALOG_MISC2_TOG_REG1_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_OK_MASK)
+#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK (0x8000U)
+#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT (15U)
+/*! AUDIO_DIV_LSB
+ * 0b0..divide by 1 (Default)
+ * 0b1..divide by 2
+ */
+#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_LSB_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK (0x70000U)
+#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT (16U)
+/*! REG2_BO_OFFSET
+ * 0b100..Brownout offset = 0.100V
+ * 0b111..Brownout offset = 0.175V
+ */
+#define CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_OFFSET_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK (0x80000U)
+#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT (19U)
+#define CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_BO_STATUS_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK (0x200000U)
+#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT (21U)
+#define CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_ENABLE_BO_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG2_OK_MASK (0x400000U)
+#define CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT (22U)
+#define CCM_ANALOG_MISC2_TOG_REG2_OK(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_OK_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_OK_MASK)
+#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK (0x800000U)
+#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT (23U)
+/*! AUDIO_DIV_MSB
+ * 0b0..divide by 1 (Default)
+ * 0b1..divide by 2
+ */
+#define CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_SHIFT)) & CCM_ANALOG_MISC2_TOG_AUDIO_DIV_MSB_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK (0x3000000U)
+#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT (24U)
+/*! REG0_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG0_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK (0xC000000U)
+#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT (26U)
+/*! REG1_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG1_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK (0x30000000U)
+#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT (28U)
+/*! REG2_STEP_TIME
+ * 0b00..64
+ * 0b01..128
+ * 0b10..256
+ * 0b11..512
+ */
+#define CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_SHIFT)) & CCM_ANALOG_MISC2_TOG_REG2_STEP_TIME_MASK)
+#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK (0xC0000000U)
+#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT (30U)
+/*! VIDEO_DIV
+ * 0b00..divide by 1 (Default)
+ * 0b01..divide by 2
+ * 0b10..divide by 1
+ * 0b11..divide by 4
+ */
+#define CCM_ANALOG_MISC2_TOG_VIDEO_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_ANALOG_MISC2_TOG_VIDEO_DIV_SHIFT)) & CCM_ANALOG_MISC2_TOG_VIDEO_DIV_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CCM_ANALOG_Register_Masks */
+
+
+/* CCM_ANALOG - Peripheral instance base addresses */
+/** Peripheral CCM_ANALOG base address */
+#define CCM_ANALOG_BASE (0x400D8000u)
+/** Peripheral CCM_ANALOG base pointer */
+#define CCM_ANALOG ((CCM_ANALOG_Type *)CCM_ANALOG_BASE)
+/** Array initializer of CCM_ANALOG peripheral base addresses */
+#define CCM_ANALOG_BASE_ADDRS { CCM_ANALOG_BASE }
+/** Array initializer of CCM_ANALOG peripheral base pointers */
+#define CCM_ANALOG_BASE_PTRS { CCM_ANALOG }
+
+/*!
+ * @}
+ */ /* end of group CCM_ANALOG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CMP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
+ __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
+ __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
+ __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
+ __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
+ __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CMP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/*! @name CR0 - CMP Control Register 0 */
+/*! @{ */
+#define CMP_CR0_HYSTCTR_MASK (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT (0U)
+/*! HYSTCTR - Comparator hard block hysteresis control
+ * 0b00..Level 0
+ * 0b01..Level 1
+ * 0b10..Level 2
+ * 0b11..Level 3
+ */
+#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT (4U)
+/*! FILTER_CNT - Filter Sample Count
+ * 0b000..Filter is disabled. If SE = 1, then COUT is a logic 0. This is not a legal state, and is not recommended. If SE = 0, COUT = COUTA.
+ * 0b001..One sample must agree. The comparator output is simply sampled.
+ * 0b010..2 consecutive samples must agree.
+ * 0b011..3 consecutive samples must agree.
+ * 0b100..4 consecutive samples must agree.
+ * 0b101..5 consecutive samples must agree.
+ * 0b110..6 consecutive samples must agree.
+ * 0b111..7 consecutive samples must agree.
+ */
+#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+/*! @} */
+
+/*! @name CR1 - CMP Control Register 1 */
+/*! @{ */
+#define CMP_CR1_EN_MASK (0x1U)
+#define CMP_CR1_EN_SHIFT (0U)
+/*! EN - Comparator Module Enable
+ * 0b0..Analog Comparator is disabled.
+ * 0b1..Analog Comparator is enabled.
+ */
+#define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK (0x2U)
+#define CMP_CR1_OPE_SHIFT (1U)
+/*! OPE - Comparator Output Pin Enable
+ * 0b0..CMPO is not available on the associated CMPO output pin. If the comparator does not own the pin, this field has no effect.
+ * 0b1..CMPO is available on the associated CMPO output pin. The comparator output (CMPO) is driven out on the
+ * associated CMPO output pin if the comparator owns the pin. If the comparator does not own the field, this
+ * bit has no effect.
+ */
+#define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK (0x4U)
+#define CMP_CR1_COS_SHIFT (2U)
+/*! COS - Comparator Output Select
+ * 0b0..Set the filtered comparator output (CMPO) to equal COUT.
+ * 0b1..Set the unfiltered comparator output (CMPO) to equal COUTA.
+ */
+#define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK (0x8U)
+#define CMP_CR1_INV_SHIFT (3U)
+/*! INV - Comparator INVERT
+ * 0b0..Does not invert the comparator output.
+ * 0b1..Inverts the comparator output.
+ */
+#define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK (0x10U)
+#define CMP_CR1_PMODE_SHIFT (4U)
+/*! PMODE - Power Mode Select
+ * 0b0..Low-Speed (LS) Comparison mode selected. In this mode, CMP has slower output propagation delay and lower current consumption.
+ * 0b1..High-Speed (HS) Comparison mode selected. In this mode, CMP has faster output propagation delay and higher current consumption.
+ */
+#define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_WE_MASK (0x40U)
+#define CMP_CR1_WE_SHIFT (6U)
+/*! WE - Windowing Enable
+ * 0b0..Windowing mode is not selected.
+ * 0b1..Windowing mode is selected.
+ */
+#define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK (0x80U)
+#define CMP_CR1_SE_SHIFT (7U)
+/*! SE - Sample Enable
+ * 0b0..Sampling mode is not selected.
+ * 0b1..Sampling mode is selected.
+ */
+#define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+/*! @} */
+
+/*! @name FPR - CMP Filter Period Register */
+/*! @{ */
+#define CMP_FPR_FILT_PER_MASK (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT (0U)
+/*! FILT_PER - Filter Sample Period
+ */
+#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+/*! @} */
+
+/*! @name SCR - CMP Status and Control Register */
+/*! @{ */
+#define CMP_SCR_COUT_MASK (0x1U)
+#define CMP_SCR_COUT_SHIFT (0U)
+/*! COUT - Analog Comparator Output
+ */
+#define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK (0x2U)
+#define CMP_SCR_CFF_SHIFT (1U)
+/*! CFF - Analog Comparator Flag Falling
+ * 0b0..Falling-edge on COUT has not been detected.
+ * 0b1..Falling-edge on COUT has occurred.
+ */
+#define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK (0x4U)
+#define CMP_SCR_CFR_SHIFT (2U)
+/*! CFR - Analog Comparator Flag Rising
+ * 0b0..Rising-edge on COUT has not been detected.
+ * 0b1..Rising-edge on COUT has occurred.
+ */
+#define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK (0x8U)
+#define CMP_SCR_IEF_SHIFT (3U)
+/*! IEF - Comparator Interrupt Enable Falling
+ * 0b0..Interrupt is disabled.
+ * 0b1..Interrupt is enabled.
+ */
+#define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK (0x10U)
+#define CMP_SCR_IER_SHIFT (4U)
+/*! IER - Comparator Interrupt Enable Rising
+ * 0b0..Interrupt is disabled.
+ * 0b1..Interrupt is enabled.
+ */
+#define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK (0x40U)
+#define CMP_SCR_DMAEN_SHIFT (6U)
+/*! DMAEN - DMA Enable Control
+ * 0b0..DMA is disabled.
+ * 0b1..DMA is enabled.
+ */
+#define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+/*! @} */
+
+/*! @name DACCR - DAC Control Register */
+/*! @{ */
+#define CMP_DACCR_VOSEL_MASK (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT (0U)
+/*! VOSEL - DAC Output Voltage Select
+ */
+#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT (6U)
+/*! VRSEL - Supply Voltage Reference Source Select
+ * 0b0..Vin1 is selected as resistor ladder network supply reference.
+ * 0b1..Vin2 is selected as resistor ladder network supply reference.
+ */
+#define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK (0x80U)
+#define CMP_DACCR_DACEN_SHIFT (7U)
+/*! DACEN - DAC Enable
+ * 0b0..DAC is disabled.
+ * 0b1..DAC is enabled.
+ */
+#define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+/*! @} */
+
+/*! @name MUXCR - MUX Control Register */
+/*! @{ */
+#define CMP_MUXCR_MSEL_MASK (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT (0U)
+/*! MSEL - Minus Input Mux Control
+ * 0b000..IN0
+ * 0b001..IN1
+ * 0b010..IN2
+ * 0b011..IN3
+ * 0b100..IN4
+ * 0b101..IN5
+ * 0b110..IN6
+ * 0b111..IN7
+ */
+#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT (3U)
+/*! PSEL - Plus Input Mux Control
+ * 0b000..IN0
+ * 0b001..IN1
+ * 0b010..IN2
+ * 0b011..IN3
+ * 0b100..IN4
+ * 0b101..IN5
+ * 0b110..IN6
+ * 0b111..IN7
+ */
+#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP1 base address */
+#define CMP1_BASE (0x40094000u)
+/** Peripheral CMP1 base pointer */
+#define CMP1 ((CMP_Type *)CMP1_BASE)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE (0x40094008u)
+/** Peripheral CMP2 base pointer */
+#define CMP2 ((CMP_Type *)CMP2_BASE)
+/** Peripheral CMP3 base address */
+#define CMP3_BASE (0x40094010u)
+/** Peripheral CMP3 base pointer */
+#define CMP3 ((CMP_Type *)CMP3_BASE)
+/** Peripheral CMP4 base address */
+#define CMP4_BASE (0x40094018u)
+/** Peripheral CMP4 base pointer */
+#define CMP4 ((CMP_Type *)CMP4_BASE)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CSI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
+ * @{
+ */
+
+/** CSI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSICR1; /**< CSI Control Register 1, offset: 0x0 */
+ __IO uint32_t CSICR2; /**< CSI Control Register 2, offset: 0x4 */
+ __IO uint32_t CSICR3; /**< CSI Control Register 3, offset: 0x8 */
+ __I uint32_t CSISTATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */
+ __I uint32_t CSIRFIFO; /**< CSI RX FIFO Register, offset: 0x10 */
+ __IO uint32_t CSIRXCNT; /**< CSI RX Count Register, offset: 0x14 */
+ __IO uint32_t CSISR; /**< CSI Status Register, offset: 0x18 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CSIDMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
+ __IO uint32_t CSIDMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
+ __IO uint32_t CSIDMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
+ __IO uint32_t CSIDMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
+ __IO uint32_t CSIFBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
+ __IO uint32_t CSIIMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t CSICR18; /**< CSI Control Register 18, offset: 0x48 */
+ __IO uint32_t CSICR19; /**< CSI Control Register 19, offset: 0x4C */
+} CSI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CSI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CSI_Register_Masks CSI Register Masks
+ * @{
+ */
+
+/*! @name CSICR1 - CSI Control Register 1 */
+/*! @{ */
+#define CSI_CSICR1_PIXEL_BIT_MASK (0x1U)
+#define CSI_CSICR1_PIXEL_BIT_SHIFT (0U)
+/*! PIXEL_BIT
+ * 0b0..8-bit data for each pixel
+ * 0b1..10-bit data for each pixel
+ */
+#define CSI_CSICR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PIXEL_BIT_SHIFT)) & CSI_CSICR1_PIXEL_BIT_MASK)
+#define CSI_CSICR1_REDGE_MASK (0x2U)
+#define CSI_CSICR1_REDGE_SHIFT (1U)
+/*! REDGE
+ * 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
+ * 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
+ */
+#define CSI_CSICR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_REDGE_SHIFT)) & CSI_CSICR1_REDGE_MASK)
+#define CSI_CSICR1_INV_PCLK_MASK (0x4U)
+#define CSI_CSICR1_INV_PCLK_SHIFT (2U)
+/*! INV_PCLK
+ * 0b0..CSI_PIXCLK is directly applied to internal circuitry
+ * 0b1..CSI_PIXCLK is inverted before applied to internal circuitry
+ */
+#define CSI_CSICR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_PCLK_SHIFT)) & CSI_CSICR1_INV_PCLK_MASK)
+#define CSI_CSICR1_INV_DATA_MASK (0x8U)
+#define CSI_CSICR1_INV_DATA_SHIFT (3U)
+/*! INV_DATA
+ * 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
+ * 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
+ */
+#define CSI_CSICR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_INV_DATA_SHIFT)) & CSI_CSICR1_INV_DATA_MASK)
+#define CSI_CSICR1_GCLK_MODE_MASK (0x10U)
+#define CSI_CSICR1_GCLK_MODE_SHIFT (4U)
+/*! GCLK_MODE
+ * 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
+ * 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
+ */
+#define CSI_CSICR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_GCLK_MODE_SHIFT)) & CSI_CSICR1_GCLK_MODE_MASK)
+#define CSI_CSICR1_CLR_RXFIFO_MASK (0x20U)
+#define CSI_CSICR1_CLR_RXFIFO_SHIFT (5U)
+#define CSI_CSICR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_RXFIFO_SHIFT)) & CSI_CSICR1_CLR_RXFIFO_MASK)
+#define CSI_CSICR1_CLR_STATFIFO_MASK (0x40U)
+#define CSI_CSICR1_CLR_STATFIFO_SHIFT (6U)
+#define CSI_CSICR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CLR_STATFIFO_SHIFT)) & CSI_CSICR1_CLR_STATFIFO_MASK)
+#define CSI_CSICR1_PACK_DIR_MASK (0x80U)
+#define CSI_CSICR1_PACK_DIR_SHIFT (7U)
+/*! PACK_DIR
+ * 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For
+ * stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
+ * 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For
+ * stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
+ */
+#define CSI_CSICR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PACK_DIR_SHIFT)) & CSI_CSICR1_PACK_DIR_MASK)
+#define CSI_CSICR1_FCC_MASK (0x100U)
+#define CSI_CSICR1_FCC_SHIFT (8U)
+/*! FCC
+ * 0b0..Asynchronous FIFO clear is selected.
+ * 0b1..Synchronous FIFO clear is selected.
+ */
+#define CSI_CSICR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FCC_SHIFT)) & CSI_CSICR1_FCC_MASK)
+#define CSI_CSICR1_CCIR_EN_MASK (0x400U)
+#define CSI_CSICR1_CCIR_EN_SHIFT (10U)
+/*! CCIR_EN
+ * 0b0..Traditional interface is selected. Timing interface logic is used to latch data.
+ * 0b1..CCIR656 interface is selected.
+ */
+#define CSI_CSICR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_EN_SHIFT)) & CSI_CSICR1_CCIR_EN_MASK)
+#define CSI_CSICR1_HSYNC_POL_MASK (0x800U)
+#define CSI_CSICR1_HSYNC_POL_SHIFT (11U)
+/*! HSYNC_POL
+ * 0b0..HSYNC is active low
+ * 0b1..HSYNC is active high
+ */
+#define CSI_CSICR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_HSYNC_POL_SHIFT)) & CSI_CSICR1_HSYNC_POL_MASK)
+#define CSI_CSICR1_SOF_INTEN_MASK (0x10000U)
+#define CSI_CSICR1_SOF_INTEN_SHIFT (16U)
+/*! SOF_INTEN
+ * 0b0..SOF interrupt disable
+ * 0b1..SOF interrupt enable
+ */
+#define CSI_CSICR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_INTEN_SHIFT)) & CSI_CSICR1_SOF_INTEN_MASK)
+#define CSI_CSICR1_SOF_POL_MASK (0x20000U)
+#define CSI_CSICR1_SOF_POL_SHIFT (17U)
+/*! SOF_POL
+ * 0b0..SOF interrupt is generated on SOF falling edge
+ * 0b1..SOF interrupt is generated on SOF rising edge
+ */
+#define CSI_CSICR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SOF_POL_SHIFT)) & CSI_CSICR1_SOF_POL_MASK)
+#define CSI_CSICR1_RXFF_INTEN_MASK (0x40000U)
+#define CSI_CSICR1_RXFF_INTEN_SHIFT (18U)
+/*! RXFF_INTEN
+ * 0b0..RxFIFO full interrupt disable
+ * 0b1..RxFIFO full interrupt enable
+ */
+#define CSI_CSICR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RXFF_INTEN_SHIFT)) & CSI_CSICR1_RXFF_INTEN_MASK)
+#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
+#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
+/*! FB1_DMA_DONE_INTEN
+ * 0b0..Frame Buffer1 DMA Transfer Done interrupt disable
+ * 0b1..Frame Buffer1 DMA Transfer Done interrupt enable
+ */
+#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK)
+#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
+#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
+/*! FB2_DMA_DONE_INTEN
+ * 0b0..Frame Buffer2 DMA Transfer Done interrupt disable
+ * 0b1..Frame Buffer2 DMA Transfer Done interrupt enable
+ */
+#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK)
+#define CSI_CSICR1_STATFF_INTEN_MASK (0x200000U)
+#define CSI_CSICR1_STATFF_INTEN_SHIFT (21U)
+/*! STATFF_INTEN
+ * 0b0..STATFIFO full interrupt disable
+ * 0b1..STATFIFO full interrupt enable
+ */
+#define CSI_CSICR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_STATFF_INTEN_SHIFT)) & CSI_CSICR1_STATFF_INTEN_MASK)
+#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
+#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
+/*! SFF_DMA_DONE_INTEN
+ * 0b0..STATFIFO DMA Transfer Done interrupt disable
+ * 0b1..STATFIFO DMA Transfer Done interrupt enable
+ */
+#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK)
+#define CSI_CSICR1_RF_OR_INTEN_MASK (0x1000000U)
+#define CSI_CSICR1_RF_OR_INTEN_SHIFT (24U)
+/*! RF_OR_INTEN
+ * 0b0..RxFIFO overrun interrupt is disabled
+ * 0b1..RxFIFO overrun interrupt is enabled
+ */
+#define CSI_CSICR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_RF_OR_INTEN_SHIFT)) & CSI_CSICR1_RF_OR_INTEN_MASK)
+#define CSI_CSICR1_SF_OR_INTEN_MASK (0x2000000U)
+#define CSI_CSICR1_SF_OR_INTEN_SHIFT (25U)
+/*! SF_OR_INTEN
+ * 0b0..STATFIFO overrun interrupt is disabled
+ * 0b1..STATFIFO overrun interrupt is enabled
+ */
+#define CSI_CSICR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SF_OR_INTEN_SHIFT)) & CSI_CSICR1_SF_OR_INTEN_MASK)
+#define CSI_CSICR1_COF_INT_EN_MASK (0x4000000U)
+#define CSI_CSICR1_COF_INT_EN_SHIFT (26U)
+/*! COF_INT_EN
+ * 0b0..COF interrupt is disabled
+ * 0b1..COF interrupt is enabled
+ */
+#define CSI_CSICR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_COF_INT_EN_SHIFT)) & CSI_CSICR1_COF_INT_EN_MASK)
+#define CSI_CSICR1_CCIR_MODE_MASK (0x8000000U)
+#define CSI_CSICR1_CCIR_MODE_SHIFT (27U)
+/*! CCIR_MODE
+ * 0b0..Progressive mode is selected
+ * 0b1..Interlace mode is selected
+ */
+#define CSI_CSICR1_CCIR_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_CCIR_MODE_SHIFT)) & CSI_CSICR1_CCIR_MODE_MASK)
+#define CSI_CSICR1_PrP_IF_EN_MASK (0x10000000U)
+#define CSI_CSICR1_PrP_IF_EN_SHIFT (28U)
+/*! PrP_IF_EN
+ * 0b0..CSI to PrP bus is disabled
+ * 0b1..CSI to PrP bus is enabled
+ */
+#define CSI_CSICR1_PrP_IF_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_PrP_IF_EN_SHIFT)) & CSI_CSICR1_PrP_IF_EN_MASK)
+#define CSI_CSICR1_EOF_INT_EN_MASK (0x20000000U)
+#define CSI_CSICR1_EOF_INT_EN_SHIFT (29U)
+/*! EOF_INT_EN
+ * 0b0..EOF interrupt is disabled.
+ * 0b1..EOF interrupt is generated when RX count value is reached.
+ */
+#define CSI_CSICR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EOF_INT_EN_SHIFT)) & CSI_CSICR1_EOF_INT_EN_MASK)
+#define CSI_CSICR1_EXT_VSYNC_MASK (0x40000000U)
+#define CSI_CSICR1_EXT_VSYNC_SHIFT (30U)
+/*! EXT_VSYNC
+ * 0b0..Internal VSYNC mode
+ * 0b1..External VSYNC mode
+ */
+#define CSI_CSICR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_EXT_VSYNC_SHIFT)) & CSI_CSICR1_EXT_VSYNC_MASK)
+#define CSI_CSICR1_SWAP16_EN_MASK (0x80000000U)
+#define CSI_CSICR1_SWAP16_EN_SHIFT (31U)
+/*! SWAP16_EN
+ * 0b0..Disable swapping
+ * 0b1..Enable swapping
+ */
+#define CSI_CSICR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR1_SWAP16_EN_SHIFT)) & CSI_CSICR1_SWAP16_EN_MASK)
+/*! @} */
+
+/*! @name CSICR2 - CSI Control Register 2 */
+/*! @{ */
+#define CSI_CSICR2_HSC_MASK (0xFFU)
+#define CSI_CSICR2_HSC_SHIFT (0U)
+#define CSI_CSICR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_HSC_SHIFT)) & CSI_CSICR2_HSC_MASK)
+#define CSI_CSICR2_VSC_MASK (0xFF00U)
+#define CSI_CSICR2_VSC_SHIFT (8U)
+#define CSI_CSICR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_VSC_SHIFT)) & CSI_CSICR2_VSC_MASK)
+#define CSI_CSICR2_LVRM_MASK (0x70000U)
+#define CSI_CSICR2_LVRM_SHIFT (16U)
+/*! LVRM
+ * 0b000..512 x 384
+ * 0b001..448 x 336
+ * 0b010..384 x 288
+ * 0b011..384 x 256
+ * 0b100..320 x 240
+ * 0b101..288 x 216
+ * 0b110..400 x 300
+ */
+#define CSI_CSICR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_LVRM_SHIFT)) & CSI_CSICR2_LVRM_MASK)
+#define CSI_CSICR2_BTS_MASK (0x180000U)
+#define CSI_CSICR2_BTS_SHIFT (19U)
+/*! BTS
+ * 0b00..GR
+ * 0b01..RG
+ * 0b10..BG
+ * 0b11..GB
+ */
+#define CSI_CSICR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_BTS_SHIFT)) & CSI_CSICR2_BTS_MASK)
+#define CSI_CSICR2_SCE_MASK (0x800000U)
+#define CSI_CSICR2_SCE_SHIFT (23U)
+/*! SCE
+ * 0b0..Skip count disable
+ * 0b1..Skip count enable
+ */
+#define CSI_CSICR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_SCE_SHIFT)) & CSI_CSICR2_SCE_MASK)
+#define CSI_CSICR2_AFS_MASK (0x3000000U)
+#define CSI_CSICR2_AFS_SHIFT (24U)
+/*! AFS
+ * 0b00..Abs Diff on consecutive green pixels
+ * 0b01..Abs Diff on every third green pixels
+ * 0b1x..Abs Diff on every four green pixels
+ */
+#define CSI_CSICR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_AFS_SHIFT)) & CSI_CSICR2_AFS_MASK)
+#define CSI_CSICR2_DRM_MASK (0x4000000U)
+#define CSI_CSICR2_DRM_SHIFT (26U)
+/*! DRM
+ * 0b0..Stats grid of 8 x 6
+ * 0b1..Stats grid of 8 x 12
+ */
+#define CSI_CSICR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DRM_SHIFT)) & CSI_CSICR2_DRM_MASK)
+#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
+#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
+/*! DMA_BURST_TYPE_SFF
+ * 0bx0..INCR8
+ * 0b01..INCR4
+ * 0b11..INCR16
+ */
+#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK)
+#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
+#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
+/*! DMA_BURST_TYPE_RFF
+ * 0bx0..INCR8
+ * 0b01..INCR4
+ * 0b11..INCR16
+ */
+#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK)
+/*! @} */
+
+/*! @name CSICR3 - CSI Control Register 3 */
+/*! @{ */
+#define CSI_CSICR3_ECC_AUTO_EN_MASK (0x1U)
+#define CSI_CSICR3_ECC_AUTO_EN_SHIFT (0U)
+/*! ECC_AUTO_EN
+ * 0b0..Auto Error correction is disabled.
+ * 0b1..Auto Error correction is enabled.
+ */
+#define CSI_CSICR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_AUTO_EN_SHIFT)) & CSI_CSICR3_ECC_AUTO_EN_MASK)
+#define CSI_CSICR3_ECC_INT_EN_MASK (0x2U)
+#define CSI_CSICR3_ECC_INT_EN_SHIFT (1U)
+/*! ECC_INT_EN
+ * 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
+ * 0b1..Interrupt is generated when error is detected.
+ */
+#define CSI_CSICR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ECC_INT_EN_SHIFT)) & CSI_CSICR3_ECC_INT_EN_MASK)
+#define CSI_CSICR3_ZERO_PACK_EN_MASK (0x4U)
+#define CSI_CSICR3_ZERO_PACK_EN_SHIFT (2U)
+/*! ZERO_PACK_EN
+ * 0b0..Zero packing disabled
+ * 0b1..Zero packing enabled
+ */
+#define CSI_CSICR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_ZERO_PACK_EN_SHIFT)) & CSI_CSICR3_ZERO_PACK_EN_MASK)
+#define CSI_CSICR3_TWO_8BIT_SENSOR_MASK (0x8U)
+#define CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT (3U)
+/*! TWO_8BIT_SENSOR
+ * 0b0..Only one sensor is connected.
+ * 0b1..Two 8-bit sensors are connected or one 16-bit sensor is connected.
+ */
+#define CSI_CSICR3_TWO_8BIT_SENSOR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_TWO_8BIT_SENSOR_SHIFT)) & CSI_CSICR3_TWO_8BIT_SENSOR_MASK)
+#define CSI_CSICR3_RxFF_LEVEL_MASK (0x70U)
+#define CSI_CSICR3_RxFF_LEVEL_SHIFT (4U)
+/*! RxFF_LEVEL
+ * 0b000..4 Double words
+ * 0b001..8 Double words
+ * 0b010..16 Double words
+ * 0b011..24 Double words
+ * 0b100..32 Double words
+ * 0b101..48 Double words
+ * 0b110..64 Double words
+ * 0b111..96 Double words
+ */
+#define CSI_CSICR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_RxFF_LEVEL_SHIFT)) & CSI_CSICR3_RxFF_LEVEL_MASK)
+#define CSI_CSICR3_HRESP_ERR_EN_MASK (0x80U)
+#define CSI_CSICR3_HRESP_ERR_EN_SHIFT (7U)
+/*! HRESP_ERR_EN
+ * 0b0..Disable hresponse error interrupt
+ * 0b1..Enable hresponse error interrupt
+ */
+#define CSI_CSICR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_HRESP_ERR_EN_SHIFT)) & CSI_CSICR3_HRESP_ERR_EN_MASK)
+#define CSI_CSICR3_STATFF_LEVEL_MASK (0x700U)
+#define CSI_CSICR3_STATFF_LEVEL_SHIFT (8U)
+/*! STATFF_LEVEL
+ * 0b000..4 Double words
+ * 0b001..8 Double words
+ * 0b010..12 Double words
+ * 0b011..16 Double words
+ * 0b100..24 Double words
+ * 0b101..32 Double words
+ * 0b110..48 Double words
+ * 0b111..64 Double words
+ */
+#define CSI_CSICR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_STATFF_LEVEL_SHIFT)) & CSI_CSICR3_STATFF_LEVEL_MASK)
+#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK (0x800U)
+#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT (11U)
+/*! DMA_REQ_EN_SFF
+ * 0b0..Disable the dma request
+ * 0b1..Enable the dma request
+ */
+#define CSI_CSICR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_SFF_MASK)
+#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK (0x1000U)
+#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT (12U)
+/*! DMA_REQ_EN_RFF
+ * 0b0..Disable the dma request
+ * 0b1..Enable the dma request
+ */
+#define CSI_CSICR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CSICR3_DMA_REQ_EN_RFF_MASK)
+#define CSI_CSICR3_DMA_REFLASH_SFF_MASK (0x2000U)
+#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT (13U)
+/*! DMA_REFLASH_SFF
+ * 0b0..No reflashing
+ * 0b1..Reflash the embedded DMA controller
+ */
+#define CSI_CSICR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_SFF_MASK)
+#define CSI_CSICR3_DMA_REFLASH_RFF_MASK (0x4000U)
+#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT (14U)
+/*! DMA_REFLASH_RFF
+ * 0b0..No reflashing
+ * 0b1..Reflash the embedded DMA controller
+ */
+#define CSI_CSICR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CSICR3_DMA_REFLASH_RFF_MASK)
+#define CSI_CSICR3_FRMCNT_RST_MASK (0x8000U)
+#define CSI_CSICR3_FRMCNT_RST_SHIFT (15U)
+/*! FRMCNT_RST
+ * 0b0..Do not reset
+ * 0b1..Reset frame counter immediately
+ */
+#define CSI_CSICR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_RST_SHIFT)) & CSI_CSICR3_FRMCNT_RST_MASK)
+#define CSI_CSICR3_FRMCNT_MASK (0xFFFF0000U)
+#define CSI_CSICR3_FRMCNT_SHIFT (16U)
+#define CSI_CSICR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR3_FRMCNT_SHIFT)) & CSI_CSICR3_FRMCNT_MASK)
+/*! @} */
+
+/*! @name CSISTATFIFO - CSI Statistic FIFO Register */
+/*! @{ */
+#define CSI_CSISTATFIFO_STAT_MASK (0xFFFFFFFFU)
+#define CSI_CSISTATFIFO_STAT_SHIFT (0U)
+#define CSI_CSISTATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISTATFIFO_STAT_SHIFT)) & CSI_CSISTATFIFO_STAT_MASK)
+/*! @} */
+
+/*! @name CSIRFIFO - CSI RX FIFO Register */
+/*! @{ */
+#define CSI_CSIRFIFO_IMAGE_MASK (0xFFFFFFFFU)
+#define CSI_CSIRFIFO_IMAGE_SHIFT (0U)
+#define CSI_CSIRFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRFIFO_IMAGE_SHIFT)) & CSI_CSIRFIFO_IMAGE_MASK)
+/*! @} */
+
+/*! @name CSIRXCNT - CSI RX Count Register */
+/*! @{ */
+#define CSI_CSIRXCNT_RXCNT_MASK (0x3FFFFFU)
+#define CSI_CSIRXCNT_RXCNT_SHIFT (0U)
+#define CSI_CSIRXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIRXCNT_RXCNT_SHIFT)) & CSI_CSIRXCNT_RXCNT_MASK)
+/*! @} */
+
+/*! @name CSISR - CSI Status Register */
+/*! @{ */
+#define CSI_CSISR_DRDY_MASK (0x1U)
+#define CSI_CSISR_DRDY_SHIFT (0U)
+/*! DRDY
+ * 0b0..No data (word) is ready
+ * 0b1..At least 1 datum (word) is ready in RXFIFO.
+ */
+#define CSI_CSISR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DRDY_SHIFT)) & CSI_CSISR_DRDY_MASK)
+#define CSI_CSISR_ECC_INT_MASK (0x2U)
+#define CSI_CSISR_ECC_INT_SHIFT (1U)
+/*! ECC_INT
+ * 0b0..No error detected
+ * 0b1..Error is detected in CCIR coding
+ */
+#define CSI_CSISR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_ECC_INT_SHIFT)) & CSI_CSISR_ECC_INT_MASK)
+#define CSI_CSISR_HRESP_ERR_INT_MASK (0x80U)
+#define CSI_CSISR_HRESP_ERR_INT_SHIFT (7U)
+/*! HRESP_ERR_INT
+ * 0b0..No hresponse error.
+ * 0b1..Hresponse error is detected.
+ */
+#define CSI_CSISR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_HRESP_ERR_INT_SHIFT)) & CSI_CSISR_HRESP_ERR_INT_MASK)
+#define CSI_CSISR_COF_INT_MASK (0x2000U)
+#define CSI_CSISR_COF_INT_SHIFT (13U)
+/*! COF_INT
+ * 0b0..Video field has no change.
+ * 0b1..Change of video field is detected.
+ */
+#define CSI_CSISR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_COF_INT_SHIFT)) & CSI_CSISR_COF_INT_MASK)
+#define CSI_CSISR_F1_INT_MASK (0x4000U)
+#define CSI_CSISR_F1_INT_SHIFT (14U)
+/*! F1_INT
+ * 0b0..Field 1 of video is not detected.
+ * 0b1..Field 1 of video is about to start.
+ */
+#define CSI_CSISR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F1_INT_SHIFT)) & CSI_CSISR_F1_INT_MASK)
+#define CSI_CSISR_F2_INT_MASK (0x8000U)
+#define CSI_CSISR_F2_INT_SHIFT (15U)
+/*! F2_INT
+ * 0b0..Field 2 of video is not detected
+ * 0b1..Field 2 of video is about to start
+ */
+#define CSI_CSISR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_F2_INT_SHIFT)) & CSI_CSISR_F2_INT_MASK)
+#define CSI_CSISR_SOF_INT_MASK (0x10000U)
+#define CSI_CSISR_SOF_INT_SHIFT (16U)
+/*! SOF_INT
+ * 0b0..SOF is not detected.
+ * 0b1..SOF is detected.
+ */
+#define CSI_CSISR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SOF_INT_SHIFT)) & CSI_CSISR_SOF_INT_MASK)
+#define CSI_CSISR_EOF_INT_MASK (0x20000U)
+#define CSI_CSISR_EOF_INT_SHIFT (17U)
+/*! EOF_INT
+ * 0b0..EOF is not detected.
+ * 0b1..EOF is detected.
+ */
+#define CSI_CSISR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_EOF_INT_SHIFT)) & CSI_CSISR_EOF_INT_MASK)
+#define CSI_CSISR_RxFF_INT_MASK (0x40000U)
+#define CSI_CSISR_RxFF_INT_SHIFT (18U)
+/*! RxFF_INT
+ * 0b0..RxFIFO is not full.
+ * 0b1..RxFIFO is full.
+ */
+#define CSI_CSISR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RxFF_INT_SHIFT)) & CSI_CSISR_RxFF_INT_MASK)
+#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK (0x80000U)
+#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT (19U)
+/*! DMA_TSF_DONE_FB1
+ * 0b0..DMA transfer is not completed.
+ * 0b1..DMA transfer is completed.
+ */
+#define CSI_CSISR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB1_MASK)
+#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK (0x100000U)
+#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT (20U)
+/*! DMA_TSF_DONE_FB2
+ * 0b0..DMA transfer is not completed.
+ * 0b1..DMA transfer is completed.
+ */
+#define CSI_CSISR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_FB2_MASK)
+#define CSI_CSISR_STATFF_INT_MASK (0x200000U)
+#define CSI_CSISR_STATFF_INT_SHIFT (21U)
+/*! STATFF_INT
+ * 0b0..STATFIFO is not full.
+ * 0b1..STATFIFO is full.
+ */
+#define CSI_CSISR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_STATFF_INT_SHIFT)) & CSI_CSISR_STATFF_INT_MASK)
+#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK (0x400000U)
+#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT (22U)
+/*! DMA_TSF_DONE_SFF
+ * 0b0..DMA transfer is not completed.
+ * 0b1..DMA transfer is completed.
+ */
+#define CSI_CSISR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_CSISR_DMA_TSF_DONE_SFF_MASK)
+#define CSI_CSISR_RF_OR_INT_MASK (0x1000000U)
+#define CSI_CSISR_RF_OR_INT_SHIFT (24U)
+/*! RF_OR_INT
+ * 0b0..RXFIFO has not overflowed.
+ * 0b1..RXFIFO has overflowed.
+ */
+#define CSI_CSISR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_RF_OR_INT_SHIFT)) & CSI_CSISR_RF_OR_INT_MASK)
+#define CSI_CSISR_SF_OR_INT_MASK (0x2000000U)
+#define CSI_CSISR_SF_OR_INT_SHIFT (25U)
+/*! SF_OR_INT
+ * 0b0..STATFIFO has not overflowed.
+ * 0b1..STATFIFO has overflowed.
+ */
+#define CSI_CSISR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_SF_OR_INT_SHIFT)) & CSI_CSISR_SF_OR_INT_MASK)
+#define CSI_CSISR_DMA_FIELD1_DONE_MASK (0x4000000U)
+#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT (26U)
+#define CSI_CSISR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD1_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD1_DONE_MASK)
+#define CSI_CSISR_DMA_FIELD0_DONE_MASK (0x8000000U)
+#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT (27U)
+#define CSI_CSISR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_DMA_FIELD0_DONE_SHIFT)) & CSI_CSISR_DMA_FIELD0_DONE_MASK)
+#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
+#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
+#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK)
+/*! @} */
+
+/*! @name CSIDMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
+/*! @{ */
+#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
+#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
+#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
+/*! @} */
+
+/*! @name CSIDMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
+/*! @{ */
+#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
+#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
+#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
+/*! @} */
+
+/*! @name CSIDMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
+/*! @{ */
+#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
+#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
+#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK)
+/*! @} */
+
+/*! @name CSIDMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
+/*! @{ */
+#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
+#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
+#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK)
+/*! @} */
+
+/*! @name CSIFBUF_PARA - CSI Frame Buffer Parameter Register */
+/*! @{ */
+#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
+#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT (0U)
+#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK)
+#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
+#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
+#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK)
+/*! @} */
+
+/*! @name CSIIMAG_PARA - CSI Image Parameter Register */
+/*! @{ */
+#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
+#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
+#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK)
+#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
+#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
+#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK)
+/*! @} */
+
+/*! @name CSICR18 - CSI Control Register 18 */
+/*! @{ */
+#define CSI_CSICR18_DEINTERLACE_EN_MASK (0x4U)
+#define CSI_CSICR18_DEINTERLACE_EN_SHIFT (2U)
+/*! DEINTERLACE_EN
+ * 0b0..Deinterlace disabled
+ * 0b1..Deinterlace enabled
+ */
+#define CSI_CSICR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DEINTERLACE_EN_SHIFT)) & CSI_CSICR18_DEINTERLACE_EN_MASK)
+#define CSI_CSICR18_PARALLEL24_EN_MASK (0x8U)
+#define CSI_CSICR18_PARALLEL24_EN_SHIFT (3U)
+#define CSI_CSICR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_PARALLEL24_EN_SHIFT)) & CSI_CSICR18_PARALLEL24_EN_MASK)
+#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK (0x10U)
+#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT (4U)
+#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_EN_MASK)
+#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
+#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
+/*! BASEADDR_SWITCH_SEL
+ * 0b0..Switching base address at the edge of the vsync
+ * 0b1..Switching base address at the edge of the first data of each frame
+ */
+#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK)
+#define CSI_CSICR18_FIELD0_DONE_IE_MASK (0x40U)
+#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT (6U)
+/*! FIELD0_DONE_IE
+ * 0b0..Interrupt disabled
+ * 0b1..Interrupt enabled
+ */
+#define CSI_CSICR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_FIELD0_DONE_IE_SHIFT)) & CSI_CSICR18_FIELD0_DONE_IE_MASK)
+#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
+#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
+/*! DMA_FIELD1_DONE_IE
+ * 0b0..Interrupt disabled
+ * 0b1..Interrupt enabled
+ */
+#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK)
+#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK (0x100U)
+#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT (8U)
+/*! LAST_DMA_REQ_SEL
+ * 0b0..fifo_full_level
+ * 0b1..hburst_length
+ */
+#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CSICR18_LAST_DMA_REQ_SEL_MASK)
+#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
+#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
+#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK)
+#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK (0x400U)
+#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT (10U)
+/*! RGB888A_FORMAT_SEL
+ * 0b0..{8'h0, data[23:0]}
+ * 0b1..{data[23:0], 8'h0}
+ */
+#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CSICR18_RGB888A_FORMAT_SEL_MASK)
+#define CSI_CSICR18_AHB_HPROT_MASK (0xF000U)
+#define CSI_CSICR18_AHB_HPROT_SHIFT (12U)
+#define CSI_CSICR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_AHB_HPROT_SHIFT)) & CSI_CSICR18_AHB_HPROT_MASK)
+#define CSI_CSICR18_MASK_OPTION_MASK (0xC0000U)
+#define CSI_CSICR18_MASK_OPTION_SHIFT (18U)
+/*! MASK_OPTION
+ * 0b00..Writing to memory from first completely frame, when using this option, the CSI_ENABLE should be 1.
+ * 0b01..Writing to memory when CSI_ENABLE is 1.
+ * 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
+ * 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
+ */
+#define CSI_CSICR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_MASK_OPTION_SHIFT)) & CSI_CSICR18_MASK_OPTION_MASK)
+#define CSI_CSICR18_CSI_ENABLE_MASK (0x80000000U)
+#define CSI_CSICR18_CSI_ENABLE_SHIFT (31U)
+#define CSI_CSICR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR18_CSI_ENABLE_SHIFT)) & CSI_CSICR18_CSI_ENABLE_MASK)
+/*! @} */
+
+/*! @name CSICR19 - CSI Control Register 19 */
+/*! @{ */
+#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
+#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
+#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CSI_Register_Masks */
+
+
+/* CSI - Peripheral instance base addresses */
+/** Peripheral CSI base address */
+#define CSI_BASE (0x402BC000u)
+/** Peripheral CSI base pointer */
+#define CSI ((CSI_Type *)CSI_BASE)
+/** Array initializer of CSI peripheral base addresses */
+#define CSI_BASE_ADDRS { CSI_BASE }
+/** Array initializer of CSI peripheral base pointers */
+#define CSI_BASE_PTRS { CSI }
+/** Interrupt vectors for the CSI peripheral type */
+#define CSI_IRQS { CSI_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CSU Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CSU_Peripheral_Access_Layer CSU Peripheral Access Layer
+ * @{
+ */
+
+/** CSU - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CSL[32]; /**< Config security level register, array offset: 0x0, array step: 0x4 */
+ uint8_t RESERVED_0[384];
+ __IO uint32_t HP0; /**< HP0 register, offset: 0x200 */
+ uint8_t RESERVED_1[20];
+ __IO uint32_t SA; /**< Secure access register, offset: 0x218 */
+ uint8_t RESERVED_2[316];
+ __IO uint32_t HPCONTROL0; /**< HPCONTROL0 register, offset: 0x358 */
+} CSU_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CSU Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CSU_Register_Masks CSU Register Masks
+ * @{
+ */
+
+/*! @name CSL - Config security level register */
+/*! @{ */
+#define CSU_CSL_SUR_S2_MASK (0x1U)
+#define CSU_CSL_SUR_S2_SHIFT (0U)
+/*! SUR_S2
+ * 0b0..The secure user read access is disabled for the second slave.
+ * 0b1..The secure user read access is enabled for the second slave.
+ */
+#define CSU_CSL_SUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S2_SHIFT)) & CSU_CSL_SUR_S2_MASK)
+#define CSU_CSL_SSR_S2_MASK (0x2U)
+#define CSU_CSL_SSR_S2_SHIFT (1U)
+/*! SSR_S2
+ * 0b0..The secure supervisor read access is disabled for the second slave.
+ * 0b1..The secure supervisor read access is enabled for the second slave.
+ */
+#define CSU_CSL_SSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S2_SHIFT)) & CSU_CSL_SSR_S2_MASK)
+#define CSU_CSL_NUR_S2_MASK (0x4U)
+#define CSU_CSL_NUR_S2_SHIFT (2U)
+/*! NUR_S2
+ * 0b0..The non-secure user read access is disabled for the second slave.
+ * 0b1..The non-secure user read access is enabled for the second slave.
+ */
+#define CSU_CSL_NUR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S2_SHIFT)) & CSU_CSL_NUR_S2_MASK)
+#define CSU_CSL_NSR_S2_MASK (0x8U)
+#define CSU_CSL_NSR_S2_SHIFT (3U)
+/*! NSR_S2
+ * 0b0..The non-secure supervisor read access is disabled for the second slave.
+ * 0b1..The non-secure supervisor read access is enabled for the second slave.
+ */
+#define CSU_CSL_NSR_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S2_SHIFT)) & CSU_CSL_NSR_S2_MASK)
+#define CSU_CSL_SUW_S2_MASK (0x10U)
+#define CSU_CSL_SUW_S2_SHIFT (4U)
+/*! SUW_S2
+ * 0b0..The secure user write access is disabled for the second slave.
+ * 0b1..The secure user write access is enabled for the second slave.
+ */
+#define CSU_CSL_SUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S2_SHIFT)) & CSU_CSL_SUW_S2_MASK)
+#define CSU_CSL_SSW_S2_MASK (0x20U)
+#define CSU_CSL_SSW_S2_SHIFT (5U)
+/*! SSW_S2
+ * 0b0..The secure supervisor write access is disabled for the second slave.
+ * 0b1..The secure supervisor write access is enabled for the second slave.
+ */
+#define CSU_CSL_SSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S2_SHIFT)) & CSU_CSL_SSW_S2_MASK)
+#define CSU_CSL_NUW_S2_MASK (0x40U)
+#define CSU_CSL_NUW_S2_SHIFT (6U)
+/*! NUW_S2
+ * 0b0..The non-secure user write access is disabled for the second slave.
+ * 0b1..The non-secure user write access is enabled for the second slave.
+ */
+#define CSU_CSL_NUW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S2_SHIFT)) & CSU_CSL_NUW_S2_MASK)
+#define CSU_CSL_NSW_S2_MASK (0x80U)
+#define CSU_CSL_NSW_S2_SHIFT (7U)
+/*! NSW_S2
+ * 0b0..The non-secure supervisor write access is disabled for the second slave.
+ * 0b1..The non-secure supervisor write access is enabled for the second slave.
+ */
+#define CSU_CSL_NSW_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S2_SHIFT)) & CSU_CSL_NSW_S2_MASK)
+#define CSU_CSL_LOCK_S2_MASK (0x100U)
+#define CSU_CSL_LOCK_S2_SHIFT (8U)
+/*! LOCK_S2
+ * 0b0..Not locked. Bits 7-0 can be written by the software.
+ * 0b1..Bits 7-0 are locked and cannot be written by the software
+ */
+#define CSU_CSL_LOCK_S2(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S2_SHIFT)) & CSU_CSL_LOCK_S2_MASK)
+#define CSU_CSL_SUR_S1_MASK (0x10000U)
+#define CSU_CSL_SUR_S1_SHIFT (16U)
+/*! SUR_S1
+ * 0b0..The secure user read access is disabled for the first slave.
+ * 0b1..The secure user read access is enabled for the first slave.
+ */
+#define CSU_CSL_SUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUR_S1_SHIFT)) & CSU_CSL_SUR_S1_MASK)
+#define CSU_CSL_SSR_S1_MASK (0x20000U)
+#define CSU_CSL_SSR_S1_SHIFT (17U)
+/*! SSR_S1
+ * 0b0..The secure supervisor read access is disabled for the first slave.
+ * 0b1..The secure supervisor read access is enabled for the first slave.
+ */
+#define CSU_CSL_SSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSR_S1_SHIFT)) & CSU_CSL_SSR_S1_MASK)
+#define CSU_CSL_NUR_S1_MASK (0x40000U)
+#define CSU_CSL_NUR_S1_SHIFT (18U)
+/*! NUR_S1
+ * 0b0..The non-secure user read access is disabled for the first slave.
+ * 0b1..The non-secure user read access is enabled for the first slave.
+ */
+#define CSU_CSL_NUR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUR_S1_SHIFT)) & CSU_CSL_NUR_S1_MASK)
+#define CSU_CSL_NSR_S1_MASK (0x80000U)
+#define CSU_CSL_NSR_S1_SHIFT (19U)
+/*! NSR_S1
+ * 0b0..The non-secure supervisor read access is disabled for the first slave.
+ * 0b1..The non-secure supervisor read access is enabled for the first slave.
+ */
+#define CSU_CSL_NSR_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSR_S1_SHIFT)) & CSU_CSL_NSR_S1_MASK)
+#define CSU_CSL_SUW_S1_MASK (0x100000U)
+#define CSU_CSL_SUW_S1_SHIFT (20U)
+/*! SUW_S1
+ * 0b0..The secure user write access is disabled for the first slave.
+ * 0b1..The secure user write access is enabled for the first slave.
+ */
+#define CSU_CSL_SUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SUW_S1_SHIFT)) & CSU_CSL_SUW_S1_MASK)
+#define CSU_CSL_SSW_S1_MASK (0x200000U)
+#define CSU_CSL_SSW_S1_SHIFT (21U)
+/*! SSW_S1
+ * 0b0..The secure supervisor write access is disabled for the first slave.
+ * 0b1..The secure supervisor write access is enabled for the first slave.
+ */
+#define CSU_CSL_SSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_SSW_S1_SHIFT)) & CSU_CSL_SSW_S1_MASK)
+#define CSU_CSL_NUW_S1_MASK (0x400000U)
+#define CSU_CSL_NUW_S1_SHIFT (22U)
+/*! NUW_S1
+ * 0b0..The non-secure user write access is disabled for the first slave.
+ * 0b1..The non-secure user write access is enabled for the first slave.
+ */
+#define CSU_CSL_NUW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NUW_S1_SHIFT)) & CSU_CSL_NUW_S1_MASK)
+#define CSU_CSL_NSW_S1_MASK (0x800000U)
+#define CSU_CSL_NSW_S1_SHIFT (23U)
+/*! NSW_S1
+ * 0b0..The non-secure supervisor write access is disabled for the first slave.
+ * 0b1..The non-secure supervisor write access is enabled for the first slave
+ */
+#define CSU_CSL_NSW_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_NSW_S1_SHIFT)) & CSU_CSL_NSW_S1_MASK)
+#define CSU_CSL_LOCK_S1_MASK (0x1000000U)
+#define CSU_CSL_LOCK_S1_SHIFT (24U)
+/*! LOCK_S1
+ * 0b0..Not locked. The bits 16-23 can be written by the software.
+ * 0b1..The bits 16-23 are locked and can't be written by the software.
+ */
+#define CSU_CSL_LOCK_S1(x) (((uint32_t)(((uint32_t)(x)) << CSU_CSL_LOCK_S1_SHIFT)) & CSU_CSL_LOCK_S1_MASK)
+/*! @} */
+
+/* The count of CSU_CSL */
+#define CSU_CSL_COUNT (32U)
+
+/*! @name HP0 - HP0 register */
+/*! @{ */
+#define CSU_HP0_HP_DMA_MASK (0x4U)
+#define CSU_HP0_HP_DMA_SHIFT (2U)
+/*! HP_DMA
+ * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
+#define CSU_HP0_HP_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DMA_SHIFT)) & CSU_HP0_HP_DMA_MASK)
+#define CSU_HP0_L_DMA_MASK (0x8U)
+#define CSU_HP0_L_DMA_SHIFT (3U)
+/*! L_DMA
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HP0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DMA_SHIFT)) & CSU_HP0_L_DMA_MASK)
+#define CSU_HP0_HP_LCDIF_MASK (0x10U)
+#define CSU_HP0_HP_LCDIF_SHIFT (4U)
+/*! HP_LCDIF
+ * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
+#define CSU_HP0_HP_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_LCDIF_SHIFT)) & CSU_HP0_HP_LCDIF_MASK)
+#define CSU_HP0_L_LCDIF_MASK (0x20U)
+#define CSU_HP0_L_LCDIF_SHIFT (5U)
+/*! L_LCDIF
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HP0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_LCDIF_SHIFT)) & CSU_HP0_L_LCDIF_MASK)
+#define CSU_HP0_HP_CSI_MASK (0x40U)
+#define CSU_HP0_HP_CSI_SHIFT (6U)
+/*! HP_CSI
+ * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
+#define CSU_HP0_HP_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_CSI_SHIFT)) & CSU_HP0_HP_CSI_MASK)
+#define CSU_HP0_L_CSI_MASK (0x80U)
+#define CSU_HP0_L_CSI_SHIFT (7U)
+/*! L_CSI
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HP0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_CSI_SHIFT)) & CSU_HP0_L_CSI_MASK)
+#define CSU_HP0_HP_PXP_MASK (0x100U)
+#define CSU_HP0_HP_PXP_SHIFT (8U)
+/*! HP_PXP
+ * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
+#define CSU_HP0_HP_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_PXP_SHIFT)) & CSU_HP0_HP_PXP_MASK)
+#define CSU_HP0_L_PXP_MASK (0x200U)
+#define CSU_HP0_L_PXP_SHIFT (9U)
+/*! L_PXP
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HP0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_PXP_SHIFT)) & CSU_HP0_L_PXP_MASK)
+#define CSU_HP0_HP_DCP_MASK (0x400U)
+#define CSU_HP0_HP_DCP_SHIFT (10U)
+/*! HP_DCP
+ * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
+#define CSU_HP0_HP_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_DCP_SHIFT)) & CSU_HP0_HP_DCP_MASK)
+#define CSU_HP0_L_DCP_MASK (0x800U)
+#define CSU_HP0_L_DCP_SHIFT (11U)
+/*! L_DCP
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit cannot be written by the software.
+ */
+#define CSU_HP0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_DCP_SHIFT)) & CSU_HP0_L_DCP_MASK)
+#define CSU_HP0_HP_ENET_MASK (0x4000U)
+#define CSU_HP0_HP_ENET_SHIFT (14U)
+/*! HP_ENET
+ * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
+#define CSU_HP0_HP_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_ENET_SHIFT)) & CSU_HP0_HP_ENET_MASK)
+#define CSU_HP0_L_ENET_MASK (0x8000U)
+#define CSU_HP0_L_ENET_SHIFT (15U)
+/*! L_ENET
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HP0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_ENET_SHIFT)) & CSU_HP0_L_ENET_MASK)
+#define CSU_HP0_HP_USDHC1_MASK (0x10000U)
+#define CSU_HP0_HP_USDHC1_SHIFT (16U)
+/*! HP_USDHC1
+ * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
+#define CSU_HP0_HP_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC1_SHIFT)) & CSU_HP0_HP_USDHC1_MASK)
+#define CSU_HP0_L_USDHC1_MASK (0x20000U)
+#define CSU_HP0_L_USDHC1_SHIFT (17U)
+/*! L_USDHC1
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HP0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC1_SHIFT)) & CSU_HP0_L_USDHC1_MASK)
+#define CSU_HP0_HP_USDHC2_MASK (0x40000U)
+#define CSU_HP0_HP_USDHC2_SHIFT (18U)
+/*! HP_USDHC2
+ * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
+#define CSU_HP0_HP_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USDHC2_SHIFT)) & CSU_HP0_HP_USDHC2_MASK)
+#define CSU_HP0_L_USDHC2_MASK (0x80000U)
+#define CSU_HP0_L_USDHC2_SHIFT (19U)
+/*! L_USDHC2
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HP0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USDHC2_SHIFT)) & CSU_HP0_L_USDHC2_MASK)
+#define CSU_HP0_HP_TPSMP_MASK (0x100000U)
+#define CSU_HP0_HP_TPSMP_SHIFT (20U)
+/*! HP_TPSMP
+ * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
+#define CSU_HP0_HP_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_TPSMP_SHIFT)) & CSU_HP0_HP_TPSMP_MASK)
+#define CSU_HP0_L_TPSMP_MASK (0x200000U)
+#define CSU_HP0_L_TPSMP_SHIFT (21U)
+/*! L_TPSMP
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HP0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_TPSMP_SHIFT)) & CSU_HP0_L_TPSMP_MASK)
+#define CSU_HP0_HP_USB_MASK (0x400000U)
+#define CSU_HP0_HP_USB_SHIFT (22U)
+/*! HP_USB
+ * 0b0..The hprot1 input signal value is routed to the csu_hprot1 output for the corresponding master.
+ * 0b1..The HP register bit is routed to the csu_hprot1 output for the corresponding master.
+ */
+#define CSU_HP0_HP_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_HP_USB_SHIFT)) & CSU_HP0_HP_USB_MASK)
+#define CSU_HP0_L_USB_MASK (0x800000U)
+#define CSU_HP0_L_USB_SHIFT (23U)
+/*! L_USB
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HP0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HP0_L_USB_SHIFT)) & CSU_HP0_L_USB_MASK)
+/*! @} */
+
+/*! @name SA - Secure access register */
+/*! @{ */
+#define CSU_SA_NSA_DMA_MASK (0x4U)
+#define CSU_SA_NSA_DMA_SHIFT (2U)
+/*! NSA_DMA - Non-secure access policy indicator bit
+ * 0b0..Secure access for the corresponding type-1 master
+ * 0b1..Non-secure access for the corresponding type-1 master
+ */
+#define CSU_SA_NSA_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DMA_SHIFT)) & CSU_SA_NSA_DMA_MASK)
+#define CSU_SA_L_DMA_MASK (0x8U)
+#define CSU_SA_L_DMA_SHIFT (3U)
+/*! L_DMA
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_SA_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DMA_SHIFT)) & CSU_SA_L_DMA_MASK)
+#define CSU_SA_NSA_LCDIF_MASK (0x10U)
+#define CSU_SA_NSA_LCDIF_SHIFT (4U)
+/*! NSA_LCDIF - Non-secure access policy indicator bit
+ * 0b0..Secure access for the corresponding type-1 master
+ * 0b1..Non-secure access for the corresponding type-1 master
+ */
+#define CSU_SA_NSA_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_LCDIF_SHIFT)) & CSU_SA_NSA_LCDIF_MASK)
+#define CSU_SA_L_LCDIF_MASK (0x20U)
+#define CSU_SA_L_LCDIF_SHIFT (5U)
+/*! L_LCDIF
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_SA_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_LCDIF_SHIFT)) & CSU_SA_L_LCDIF_MASK)
+#define CSU_SA_NSA_CSI_MASK (0x40U)
+#define CSU_SA_NSA_CSI_SHIFT (6U)
+/*! NSA_CSI - Non-secure access policy indicator bit
+ * 0b0..Secure access for the corresponding type-1 master
+ * 0b1..Non-secure access for the corresponding type-1 master
+ */
+#define CSU_SA_NSA_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_CSI_SHIFT)) & CSU_SA_NSA_CSI_MASK)
+#define CSU_SA_L_CSI_MASK (0x80U)
+#define CSU_SA_L_CSI_SHIFT (7U)
+/*! L_CSI
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_SA_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_CSI_SHIFT)) & CSU_SA_L_CSI_MASK)
+#define CSU_SA_NSA_PXP_MASK (0x100U)
+#define CSU_SA_NSA_PXP_SHIFT (8U)
+/*! NSA_PXP - Non-Secure Access Policy indicator bit
+ * 0b0..Secure access for the corresponding type-1 master
+ * 0b1..Non-secure access for the corresponding type-1 master
+ */
+#define CSU_SA_NSA_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_PXP_SHIFT)) & CSU_SA_NSA_PXP_MASK)
+#define CSU_SA_L_PXP_MASK (0x200U)
+#define CSU_SA_L_PXP_SHIFT (9U)
+/*! L_PXP
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_SA_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_PXP_SHIFT)) & CSU_SA_L_PXP_MASK)
+#define CSU_SA_NSA_DCP_MASK (0x400U)
+#define CSU_SA_NSA_DCP_SHIFT (10U)
+/*! NSA_DCP - Non-secure access policy indicator bit
+ * 0b0..Secure access for the corresponding type-1 master
+ * 0b1..Non-secure access for the corresponding type-1 master
+ */
+#define CSU_SA_NSA_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_DCP_SHIFT)) & CSU_SA_NSA_DCP_MASK)
+#define CSU_SA_L_DCP_MASK (0x800U)
+#define CSU_SA_L_DCP_SHIFT (11U)
+/*! L_DCP
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_SA_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_DCP_SHIFT)) & CSU_SA_L_DCP_MASK)
+#define CSU_SA_NSA_ENET_MASK (0x4000U)
+#define CSU_SA_NSA_ENET_SHIFT (14U)
+/*! NSA_ENET - Non-secure access policy indicator bit
+ * 0b0..Secure access for the corresponding type-1 master
+ * 0b1..Non-secure access for the corresponding type-1 master
+ */
+#define CSU_SA_NSA_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_ENET_SHIFT)) & CSU_SA_NSA_ENET_MASK)
+#define CSU_SA_L_ENET_MASK (0x8000U)
+#define CSU_SA_L_ENET_SHIFT (15U)
+/*! L_ENET
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_SA_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_ENET_SHIFT)) & CSU_SA_L_ENET_MASK)
+#define CSU_SA_NSA_USDHC1_MASK (0x10000U)
+#define CSU_SA_NSA_USDHC1_SHIFT (16U)
+/*! NSA_USDHC1 - Non-secure access policy indicator bit
+ * 0b0..Secure access for the corresponding type-1 master
+ * 0b1..Non-secure access for the corresponding type-1 master
+ */
+#define CSU_SA_NSA_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC1_SHIFT)) & CSU_SA_NSA_USDHC1_MASK)
+#define CSU_SA_L_USDHC1_MASK (0x20000U)
+#define CSU_SA_L_USDHC1_SHIFT (17U)
+/*! L_USDHC1
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_SA_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC1_SHIFT)) & CSU_SA_L_USDHC1_MASK)
+#define CSU_SA_NSA_USDHC2_MASK (0x40000U)
+#define CSU_SA_NSA_USDHC2_SHIFT (18U)
+/*! NSA_USDHC2 - Non-secure access policy indicator bit
+ * 0b0..Secure access for the corresponding type-1 master
+ * 0b1..Non-secure access for the corresponding type-1 master
+ */
+#define CSU_SA_NSA_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USDHC2_SHIFT)) & CSU_SA_NSA_USDHC2_MASK)
+#define CSU_SA_L_USDHC2_MASK (0x80000U)
+#define CSU_SA_L_USDHC2_SHIFT (19U)
+/*! L_USDHC2
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_SA_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USDHC2_SHIFT)) & CSU_SA_L_USDHC2_MASK)
+#define CSU_SA_NSA_TPSMP_MASK (0x100000U)
+#define CSU_SA_NSA_TPSMP_SHIFT (20U)
+/*! NSA_TPSMP - Non-secure access policy indicator bit
+ * 0b0..Secure access for the corresponding type-1 master
+ * 0b1..Non-secure access for the corresponding type-1 master
+ */
+#define CSU_SA_NSA_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_TPSMP_SHIFT)) & CSU_SA_NSA_TPSMP_MASK)
+#define CSU_SA_L_TPSMP_MASK (0x200000U)
+#define CSU_SA_L_TPSMP_SHIFT (21U)
+/*! L_TPSMP
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_SA_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_TPSMP_SHIFT)) & CSU_SA_L_TPSMP_MASK)
+#define CSU_SA_NSA_USB_MASK (0x400000U)
+#define CSU_SA_NSA_USB_SHIFT (22U)
+/*! NSA_USB - Non-secure access policy indicator bit
+ * 0b0..Secure access for the corresponding type-1 master
+ * 0b1..Non-secure access for the corresponding type-1 master
+ */
+#define CSU_SA_NSA_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_NSA_USB_SHIFT)) & CSU_SA_NSA_USB_MASK)
+#define CSU_SA_L_USB_MASK (0x800000U)
+#define CSU_SA_L_USB_SHIFT (23U)
+/*! L_USB
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_SA_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_SA_L_USB_SHIFT)) & CSU_SA_L_USB_MASK)
+/*! @} */
+
+/*! @name HPCONTROL0 - HPCONTROL0 register */
+/*! @{ */
+#define CSU_HPCONTROL0_HPC_DMA_MASK (0x4U)
+#define CSU_HPCONTROL0_HPC_DMA_SHIFT (2U)
+/*! HPC_DMA
+ * 0b0..User mode for the corresponding master
+ * 0b1..Supervisor mode for the corresponding master
+ */
+#define CSU_HPCONTROL0_HPC_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DMA_SHIFT)) & CSU_HPCONTROL0_HPC_DMA_MASK)
+#define CSU_HPCONTROL0_L_DMA_MASK (0x8U)
+#define CSU_HPCONTROL0_L_DMA_SHIFT (3U)
+/*! L_DMA
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HPCONTROL0_L_DMA(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DMA_SHIFT)) & CSU_HPCONTROL0_L_DMA_MASK)
+#define CSU_HPCONTROL0_HPC_LCDIF_MASK (0x10U)
+#define CSU_HPCONTROL0_HPC_LCDIF_SHIFT (4U)
+/*! HPC_LCDIF
+ * 0b0..User mode for the corresponding master
+ * 0b1..Supervisor mode for the corresponding master
+ */
+#define CSU_HPCONTROL0_HPC_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_LCDIF_SHIFT)) & CSU_HPCONTROL0_HPC_LCDIF_MASK)
+#define CSU_HPCONTROL0_L_LCDIF_MASK (0x20U)
+#define CSU_HPCONTROL0_L_LCDIF_SHIFT (5U)
+/*! L_LCDIF
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HPCONTROL0_L_LCDIF(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_LCDIF_SHIFT)) & CSU_HPCONTROL0_L_LCDIF_MASK)
+#define CSU_HPCONTROL0_HPC_CSI_MASK (0x40U)
+#define CSU_HPCONTROL0_HPC_CSI_SHIFT (6U)
+/*! HPC_CSI
+ * 0b0..User mode for the corresponding master
+ * 0b1..Supervisor mode for the corresponding master
+ */
+#define CSU_HPCONTROL0_HPC_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_CSI_SHIFT)) & CSU_HPCONTROL0_HPC_CSI_MASK)
+#define CSU_HPCONTROL0_L_CSI_MASK (0x80U)
+#define CSU_HPCONTROL0_L_CSI_SHIFT (7U)
+/*! L_CSI
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HPCONTROL0_L_CSI(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_CSI_SHIFT)) & CSU_HPCONTROL0_L_CSI_MASK)
+#define CSU_HPCONTROL0_HPC_PXP_MASK (0x100U)
+#define CSU_HPCONTROL0_HPC_PXP_SHIFT (8U)
+/*! HPC_PXP
+ * 0b0..User mode for the corresponding master
+ * 0b1..Supervisor mode for the corresponding master
+ */
+#define CSU_HPCONTROL0_HPC_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_PXP_SHIFT)) & CSU_HPCONTROL0_HPC_PXP_MASK)
+#define CSU_HPCONTROL0_L_PXP_MASK (0x200U)
+#define CSU_HPCONTROL0_L_PXP_SHIFT (9U)
+/*! L_PXP
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HPCONTROL0_L_PXP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_PXP_SHIFT)) & CSU_HPCONTROL0_L_PXP_MASK)
+#define CSU_HPCONTROL0_HPC_DCP_MASK (0x400U)
+#define CSU_HPCONTROL0_HPC_DCP_SHIFT (10U)
+/*! HPC_DCP
+ * 0b0..User mode for the corresponding master
+ * 0b1..Supervisor mode for the corresponding master
+ */
+#define CSU_HPCONTROL0_HPC_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_DCP_SHIFT)) & CSU_HPCONTROL0_HPC_DCP_MASK)
+#define CSU_HPCONTROL0_L_DCP_MASK (0x800U)
+#define CSU_HPCONTROL0_L_DCP_SHIFT (11U)
+/*! L_DCP
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HPCONTROL0_L_DCP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_DCP_SHIFT)) & CSU_HPCONTROL0_L_DCP_MASK)
+#define CSU_HPCONTROL0_HPC_ENET_MASK (0x4000U)
+#define CSU_HPCONTROL0_HPC_ENET_SHIFT (14U)
+/*! HPC_ENET
+ * 0b0..User mode for the corresponding master
+ * 0b1..Supervisor mode for the corresponding master
+ */
+#define CSU_HPCONTROL0_HPC_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_ENET_SHIFT)) & CSU_HPCONTROL0_HPC_ENET_MASK)
+#define CSU_HPCONTROL0_L_ENET_MASK (0x8000U)
+#define CSU_HPCONTROL0_L_ENET_SHIFT (15U)
+/*! L_ENET
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HPCONTROL0_L_ENET(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_ENET_SHIFT)) & CSU_HPCONTROL0_L_ENET_MASK)
+#define CSU_HPCONTROL0_HPC_USDHC1_MASK (0x10000U)
+#define CSU_HPCONTROL0_HPC_USDHC1_SHIFT (16U)
+/*! HPC_USDHC1
+ * 0b0..User mode for the corresponding master
+ * 0b1..Supervisor mode for the corresponding master
+ */
+#define CSU_HPCONTROL0_HPC_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC1_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC1_MASK)
+#define CSU_HPCONTROL0_L_USDHC1_MASK (0x20000U)
+#define CSU_HPCONTROL0_L_USDHC1_SHIFT (17U)
+/*! L_USDHC1
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HPCONTROL0_L_USDHC1(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC1_SHIFT)) & CSU_HPCONTROL0_L_USDHC1_MASK)
+#define CSU_HPCONTROL0_HPC_USDHC2_MASK (0x40000U)
+#define CSU_HPCONTROL0_HPC_USDHC2_SHIFT (18U)
+/*! HPC_USDHC2
+ * 0b0..User mode for the corresponding master
+ * 0b1..Supervisor mode for the corresponding master
+ */
+#define CSU_HPCONTROL0_HPC_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USDHC2_SHIFT)) & CSU_HPCONTROL0_HPC_USDHC2_MASK)
+#define CSU_HPCONTROL0_L_USDHC2_MASK (0x80000U)
+#define CSU_HPCONTROL0_L_USDHC2_SHIFT (19U)
+/*! L_USDHC2
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HPCONTROL0_L_USDHC2(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USDHC2_SHIFT)) & CSU_HPCONTROL0_L_USDHC2_MASK)
+#define CSU_HPCONTROL0_HPC_TPSMP_MASK (0x100000U)
+#define CSU_HPCONTROL0_HPC_TPSMP_SHIFT (20U)
+/*! HPC_TPSMP
+ * 0b0..User mode for the corresponding master
+ * 0b1..Supervisor mode for the corresponding master
+ */
+#define CSU_HPCONTROL0_HPC_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_TPSMP_SHIFT)) & CSU_HPCONTROL0_HPC_TPSMP_MASK)
+#define CSU_HPCONTROL0_L_TPSMP_MASK (0x200000U)
+#define CSU_HPCONTROL0_L_TPSMP_SHIFT (21U)
+/*! L_TPSMP
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HPCONTROL0_L_TPSMP(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_TPSMP_SHIFT)) & CSU_HPCONTROL0_L_TPSMP_MASK)
+#define CSU_HPCONTROL0_HPC_USB_MASK (0x400000U)
+#define CSU_HPCONTROL0_HPC_USB_SHIFT (22U)
+/*! HPC_USB
+ * 0b0..User mode for the corresponding master
+ * 0b1..Supervisor mode for the corresponding master
+ */
+#define CSU_HPCONTROL0_HPC_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_HPC_USB_SHIFT)) & CSU_HPCONTROL0_HPC_USB_MASK)
+#define CSU_HPCONTROL0_L_USB_MASK (0x800000U)
+#define CSU_HPCONTROL0_L_USB_SHIFT (23U)
+/*! L_USB
+ * 0b0..No lock-the adjacent (next lower) bit can be written by the software.
+ * 0b1..Lock-the adjacent (next lower) bit can't be written by the software.
+ */
+#define CSU_HPCONTROL0_L_USB(x) (((uint32_t)(((uint32_t)(x)) << CSU_HPCONTROL0_L_USB_SHIFT)) & CSU_HPCONTROL0_L_USB_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group CSU_Register_Masks */
+
+
+/* CSU - Peripheral instance base addresses */
+/** Peripheral CSU base address */
+#define CSU_BASE (0x400DC000u)
+/** Peripheral CSU base pointer */
+#define CSU ((CSU_Type *)CSU_BASE)
+/** Array initializer of CSU peripheral base addresses */
+#define CSU_BASE_ADDRS { CSU_BASE }
+/** Array initializer of CSU peripheral base pointers */
+#define CSU_BASE_PTRS { CSU }
+
+/*!
+ * @}
+ */ /* end of group CSU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DCDC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
+ * @{
+ */
+
+/** DCDC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t REG0; /**< DCDC Register 0, offset: 0x0 */
+ __IO uint32_t REG1; /**< DCDC Register 1, offset: 0x4 */
+ __IO uint32_t REG2; /**< DCDC Register 2, offset: 0x8 */
+ __IO uint32_t REG3; /**< DCDC Register 3, offset: 0xC */
+} DCDC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DCDC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DCDC_Register_Masks DCDC Register Masks
+ * @{
+ */
+
+/*! @name REG0 - DCDC Register 0 */
+/*! @{ */
+#define DCDC_REG0_PWD_ZCD_MASK (0x1U)
+#define DCDC_REG0_PWD_ZCD_SHIFT (0U)
+#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
+#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
+#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
+#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
+#define DCDC_REG0_SEL_CLK_MASK (0x4U)
+#define DCDC_REG0_SEL_CLK_SHIFT (2U)
+#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
+#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
+#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
+#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
+#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
+#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
+#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
+#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
+#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
+#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
+#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
+#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
+#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
+#define DCDC_REG0_OVERCUR_TRIG_ADJ_MASK (0x600U)
+#define DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT (9U)
+#define DCDC_REG0_OVERCUR_TRIG_ADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_OVERCUR_TRIG_ADJ_SHIFT)) & DCDC_REG0_OVERCUR_TRIG_ADJ_MASK)
+#define DCDC_REG0_PWD_CMP_BATT_DET_MASK (0x800U)
+#define DCDC_REG0_PWD_CMP_BATT_DET_SHIFT (11U)
+#define DCDC_REG0_PWD_CMP_BATT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_BATT_DET_SHIFT)) & DCDC_REG0_PWD_CMP_BATT_DET_MASK)
+#define DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK (0xF000U)
+#define DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT (12U)
+#define DCDC_REG0_ADJ_POSLIMIT_BUCK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_ADJ_POSLIMIT_BUCK_SHIFT)) & DCDC_REG0_ADJ_POSLIMIT_BUCK_MASK)
+#define DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK (0x10000U)
+#define DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT (16U)
+#define DCDC_REG0_EN_LP_OVERLOAD_SNS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_EN_LP_OVERLOAD_SNS_SHIFT)) & DCDC_REG0_EN_LP_OVERLOAD_SNS_MASK)
+#define DCDC_REG0_PWD_HIGH_VOLT_DET_MASK (0x20000U)
+#define DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT (17U)
+#define DCDC_REG0_PWD_HIGH_VOLT_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VOLT_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VOLT_DET_MASK)
+#define DCDC_REG0_LP_OVERLOAD_THRSH_MASK (0xC0000U)
+#define DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT (18U)
+#define DCDC_REG0_LP_OVERLOAD_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_THRSH_SHIFT)) & DCDC_REG0_LP_OVERLOAD_THRSH_MASK)
+#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK (0x100000U)
+#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT (20U)
+#define DCDC_REG0_LP_OVERLOAD_FREQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_OVERLOAD_FREQ_SEL_SHIFT)) & DCDC_REG0_LP_OVERLOAD_FREQ_SEL_MASK)
+#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
+#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
+#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
+#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
+#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
+#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
+#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
+#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
+#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
+#define DCDC_REG0_CURRENT_ALERT_RESET_MASK (0x10000000U)
+#define DCDC_REG0_CURRENT_ALERT_RESET_SHIFT (28U)
+#define DCDC_REG0_CURRENT_ALERT_RESET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CURRENT_ALERT_RESET_SHIFT)) & DCDC_REG0_CURRENT_ALERT_RESET_MASK)
+#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
+#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
+#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
+#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
+#define DCDC_REG0_STS_DC_OK_SHIFT (31U)
+#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
+/*! @} */
+
+/*! @name REG1 - DCDC Register 1 */
+/*! @{ */
+#define DCDC_REG1_REG_FBK_SEL_MASK (0x180U)
+#define DCDC_REG1_REG_FBK_SEL_SHIFT (7U)
+#define DCDC_REG1_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_FBK_SEL_SHIFT)) & DCDC_REG1_REG_FBK_SEL_MASK)
+#define DCDC_REG1_REG_RLOAD_SW_MASK (0x200U)
+#define DCDC_REG1_REG_RLOAD_SW_SHIFT (9U)
+#define DCDC_REG1_REG_RLOAD_SW(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_REG_RLOAD_SW_SHIFT)) & DCDC_REG1_REG_RLOAD_SW_MASK)
+#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x3000U)
+#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (12U)
+#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
+#define DCDC_REG1_LOOPCTRL_HST_THRESH_MASK (0x200000U)
+#define DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT (21U)
+#define DCDC_REG1_LOOPCTRL_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_HST_THRESH_MASK)
+#define DCDC_REG1_LOOPCTRL_EN_HYST_MASK (0x800000U)
+#define DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT (23U)
+#define DCDC_REG1_LOOPCTRL_EN_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_HYST_MASK)
+#define DCDC_REG1_VBG_TRIM_MASK (0x1F000000U)
+#define DCDC_REG1_VBG_TRIM_SHIFT (24U)
+#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
+/*! @} */
+
+/*! @name REG2 - DCDC Register 2 */
+/*! @{ */
+#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
+#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
+#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
+#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
+#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
+#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
+#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
+#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
+#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
+#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
+#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
+#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
+#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
+#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
+#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
+#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
+#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
+#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
+#define DCDC_REG2_DISABLE_PULSE_SKIP_MASK (0x8000000U)
+#define DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT (27U)
+#define DCDC_REG2_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG2_DISABLE_PULSE_SKIP_MASK)
+#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
+#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
+#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
+/*! @} */
+
+/*! @name REG3 - DCDC Register 3 */
+/*! @{ */
+#define DCDC_REG3_TRG_MASK (0x1FU)
+#define DCDC_REG3_TRG_SHIFT (0U)
+#define DCDC_REG3_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TRG_SHIFT)) & DCDC_REG3_TRG_MASK)
+#define DCDC_REG3_TARGET_LP_MASK (0x700U)
+#define DCDC_REG3_TARGET_LP_SHIFT (8U)
+#define DCDC_REG3_TARGET_LP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_TARGET_LP_SHIFT)) & DCDC_REG3_TARGET_LP_MASK)
+#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
+#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
+#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
+#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
+#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
+#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
+#define DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK (0x10000000U)
+#define DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT (28U)
+#define DCDC_REG3_MISC_DISABLEFET_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DISABLEFET_LOGIC_SHIFT)) & DCDC_REG3_MISC_DISABLEFET_LOGIC_MASK)
+#define DCDC_REG3_DISABLE_STEP_MASK (0x40000000U)
+#define DCDC_REG3_DISABLE_STEP_SHIFT (30U)
+#define DCDC_REG3_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_STEP_SHIFT)) & DCDC_REG3_DISABLE_STEP_MASK)
+/*! @} */
+
+
+/*!
+ * @}
+ */ /* end of group DCDC_Register_Masks */
+
+
+/* DCDC - Peripheral instance base addresses */
+/** Peripheral DCDC base address */
+#define DCDC_BASE (0x40080000u)
+/** Peripheral DCDC base pointer */
+#define DCDC ((DCDC_Type *)DCDC_BASE)
+/** Array initializer of DCDC peripheral base addresses */
+#define DCDC_BASE_ADDRS { DCDC_BASE }
+/** Array initializer of DCDC peripheral base pointers */
+#define DCDC_BASE_PTRS { DCDC }
+/** Interrupt vectors for the DCDC peripheral type */
+#define DCDC_IRQS { DCDC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DCDC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DCP Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DCP_Peripheral_Access_Layer DCP Peripheral Access Layer
+ * @{
+ */
+
+/** DCP - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< DCP control register 0, offset: 0x0 */
+ __IO uint32_t CTRL_SET; /**< DCP control register 0, offset: 0x4 */
+ __IO uint32_t CTRL_CLR; /**< DCP control register 0, offset: 0x8 */
+ __IO uint32_t CTRL_TOG; /**< DCP control register 0, offset: 0xC */
+ __IO uint32_t STAT; /**< DCP status register, offset: 0x10 */
+ __IO uint32_t STAT_SET; /**< DCP status register, offset: 0x14 */
+ __IO uint32_t STAT_CLR; /**< DCP status register, offset: 0x18 */
+ __IO uint32_t STAT_TOG; /**< DCP status register, offset: 0x1C */
+ __IO uint32_t CHANNELCTRL; /**< DCP channel control register, offset: 0x20 */
+ __IO uint32_t CHANNELCTRL_SET; /**< DCP channel control register, offset: 0x24 */
+ __IO uint32_t CHANNELCTRL_CLR; /**< DCP channel control register, offset: 0x28 */
+ __IO uint32_t CHANNELCTRL_TOG; /**< DCP channel control register, offset: 0x2C */
+ __IO uint32_t CAPABILITY0; /**< DCP capability 0 register, offset: 0x30 */
+ uint8_t RESERVED_0[12];
+ __I uint32_t CAPABILITY1; /**< DCP capability 1 register, offset: 0x40 */
+ uint8_t RESERVED_1[12];
+ __IO uint32_t CONTEXT; /**< DCP context buffer pointer, offset: 0x50 */
+ uint8_t RESERVED_2[12];
+ __IO uint32_t KEY; /**< DCP key index, offset: 0x60 */
+ uint8_t RESERVED_3[12];
+ __IO uint32_t KEYDATA; /**< DCP key data, offset: 0x70 */
+ uint8_t RESERVED_4[12];
+ __I uint32_t PACKET0; /**< DCP work packet 0 status register, offset: 0x80 */
+ uint8_t RESERVED_5[12];
+ __I uint32_t PACKET1; /**< DCP work packet 1 status register, offset: 0x90 */
+ uint8_t RESERVED_6[12];
+ __I uint32_t PACKET2; /**< DCP work packet 2 status register, offset: 0xA0 */
+ uint8_t RESERVED_7[12];
+ __I uint32_t PACKET3; /**< DCP work packet 3 status register, offset: 0xB0 */
+ uint8_t RESERVED_8[12];
+ __I uint32_t PACKET4; /**< DCP work packet 4 status register, offset: 0xC0 */
+ uint8_t RESERVED_9[12];
+ __I uint32_t PACKET5; /**< DCP work packet 5 status register, offset: 0xD0 */
+ uint8_t RESERVED_10[12];
+ __I uint32_t PACKET6; /**< DCP work packet 6 status register, offset: 0xE0 */
+ uint8_t RESERVED_11[28];
+ __IO uint32_t CH0CMDPTR; /**< DCP channel 0 command pointer address register, offset: 0x100 */
+ uint8_t RESERVED_12[12];
+ __IO uint32_t CH0SEMA; /**< DCP channel 0 semaphore register, offset: 0x110 */
+ uint8_t RESERVED_13[12];
+ __IO uint32_t CH0STAT; /**< DCP channel 0 status register, offset: 0x120 */
+ __IO uint32_t CH0STAT_SET; /**< DCP channel 0 status register, offset: 0x124 */
+ __IO uint32_t CH0STAT_CLR; /**< DCP channel 0 status register, offset: 0x128 */
+ __IO uint32_t CH0STAT_TOG; /**< DCP channel 0 status register, offset: 0x12C */
+ __IO uint32_t CH0OPTS; /**< DCP channel 0 options register, offset: 0x130 */
+ __IO uint32_t CH0OPTS_SET; /**< DCP channel 0 options register, offset: 0x134 */
+ __IO uint32_t CH0OPTS_CLR; /**< DCP channel 0 options register, offset: 0x138 */
+ __IO uint32_t CH0OPTS_TOG; /**< DCP channel 0 options register, offset: 0x13C */
+ __IO uint32_t CH1CMDPTR; /**< DCP channel 1 command pointer address register, offset: 0x140 */
+ uint8_t RESERVED_14[12];
+ __IO uint32_t CH1SEMA; /**< DCP channel 1 semaphore register, offset: 0x150 */
+ uint8_t RESERVED_15[12];
+ __IO uint32_t CH1STAT; /**< DCP channel 1 status register, offset: 0x160 */
+ __IO uint32_t CH1STAT_SET; /**< DCP channel 1 status register, offset: 0x164 */
+ __IO uint32_t CH1STAT_CLR; /**< DCP channel 1 status register, offset: 0x168 */
+ __IO uint32_t CH1STAT_TOG; /**< DCP channel 1 status register, offset: 0x16C */
+ __IO uint32_t CH1OPTS; /**< DCP channel 1 options register, offset: 0x170 */
+ __IO uint32_t CH1OPTS_SET; /**< DCP channel 1 options register, offset: 0x174 */
+ __IO uint32_t CH1OPTS_CLR; /**< DCP channel 1 options register, offset: 0x178 */
+ __IO uint32_t CH1OPTS_TOG; /**< DCP channel 1 options register, offset: 0x17C */
+ __IO uint32_t CH2CMDPTR; /**< DCP channel 2 command pointer address register, offset: 0x180 */
+ uint8_t RESERVED_16[12];
+ __IO uint32_t CH2SEMA; /**< DCP channel 2 semaphore register, offset: 0x190 */
+ uint8_t RESERVED_17[12];
+ __IO uint32_t CH2STAT; /**< DCP channel 2 status register, offset: 0x1A0 */
+ __IO uint32_t CH2STAT_SET; /**< DCP channel 2 status register, offset: 0x1A4 */
+ __IO uint32_t CH2STAT_CLR; /**< DCP channel 2 status register, offset: 0x1A8 */
+ __IO uint32_t CH2STAT_TOG; /**< DCP channel 2 status register, offset: 0x1AC */
+ __IO uint32_t CH2OPTS; /**< DCP channel 2 options register, offset: 0x1B0 */
+ __IO uint32_t CH2OPTS_SET; /**< DCP channel 2 options register, offset: 0x1B4 */
+ __IO uint32_t CH2OPTS_CLR; /**< DCP channel 2 options register, offset: 0x1B8 */
+ __IO uint32_t CH2OPTS_TOG; /**< DCP channel 2 options register, offset: 0x1BC */
+ __IO uint32_t CH3CMDPTR; /**< DCP channel 3 command pointer address register, offset: 0x1C0 */
+ uint8_t RESERVED_18[12];
+ __IO uint32_t CH3SEMA; /**< DCP channel 3 semaphore register, offset: 0x1D0 */
+ uint8_t RESERVED_19[12];
+ __IO uint32_t CH3STAT; /**< DCP channel 3 status register, offset: 0x1E0 */
+ __IO uint32_t CH3STAT_SET; /**< DCP channel 3 status register, offset: 0x1E4 */
+ __IO uint32_t CH3STAT_CLR; /**< DCP channel 3 status register, offset: 0x1E8 */
+ __IO uint32_t CH3STAT_TOG; /**< DCP channel 3 status register, offset: 0x1EC */
+ __IO uint32_t CH3OPTS; /**< DCP channel 3 options register, offset: 0x1F0 */
+ __IO uint32_t CH3OPTS_SET; /**< DCP channel 3 options register, offset: 0x1F4 */
+ __IO uint32_t CH3OPTS_CLR; /**< DCP channel 3 options register, offset: 0x1F8 */
+ __IO uint32_t CH3OPTS_TOG; /**< DCP channel 3 options register, offset: 0x1FC */
+ uint8_t RESERVED_20[512];
+ __IO uint32_t DBGSELECT; /**< DCP debug select register, offset: 0x400 */
+ uint8_t RESERVED_21[12];
+ __I uint32_t DBGDATA; /**< DCP debug data register, offset: 0x410 */
+ uint8_t RESERVED_22[12];
+ __IO uint32_t PAGETABLE; /**< DCP page table register, offset: 0x420 */
+ uint8_t RESERVED_23[12];
+ __I uint32_t VERSION; /**< DCP version register, offset: 0x430 */
+} DCP_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DCP Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DCP_Register_Masks DCP Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DCP control register 0 */
+/*! @{ */
+#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
+#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
+/*! CHANNEL_INTERRUPT_ENABLE
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CTRL_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CHANNEL_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
+#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
+#define DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_RSVD_CSC_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
+#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
+#define DCP_CTRL_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_SWITCHING_MASK)
+#define DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
+#define DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT (22U)
+#define DCP_CTRL_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_ENABLE_CONTEXT_CACHING_MASK)
+#define DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
+#define DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT (23U)
+#define DCP_CTRL_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_GATHER_RESIDUAL_WRITES_MASK)
+#define DCP_CTRL_PRESENT_SHA_MASK (0x10000000U)
+#define DCP_CTRL_PRESENT_SHA_SHIFT (28U)
+/*! PRESENT_SHA
+ * 0b1..Present
+ * 0b0..Absent
+ */
+#define DCP_CTRL_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_SHA_SHIFT)) & DCP_CTRL_PRESENT_SHA_MASK)
+#define DCP_CTRL_PRESENT_CRYPTO_MASK (0x20000000U)
+#define DCP_CTRL_PRESENT_CRYPTO_SHIFT (29U)
+/*! PRESENT_CRYPTO
+ * 0b1..Present
+ * 0b0..Absent
+ */
+#define DCP_CTRL_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_PRESENT_CRYPTO_MASK)
+#define DCP_CTRL_CLKGATE_MASK (0x40000000U)
+#define DCP_CTRL_CLKGATE_SHIFT (30U)
+#define DCP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLKGATE_SHIFT)) & DCP_CTRL_CLKGATE_MASK)
+#define DCP_CTRL_SFTRST_MASK (0x80000000U)
+#define DCP_CTRL_SFTRST_SHIFT (31U)
+#define DCP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SFTRST_SHIFT)) & DCP_CTRL_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_SET - DCP control register 0 */
+/*! @{ */
+#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
+#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
+/*! CHANNEL_INTERRUPT_ENABLE
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_CHANNEL_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
+#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
+#define DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_SET_RSVD_CSC_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_SWITCHING_MASK)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT (22U)
+#define DCP_CTRL_SET_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_SET_ENABLE_CONTEXT_CACHING_MASK)
+#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
+#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT (23U)
+#define DCP_CTRL_SET_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_SET_GATHER_RESIDUAL_WRITES_MASK)
+#define DCP_CTRL_SET_PRESENT_SHA_MASK (0x10000000U)
+#define DCP_CTRL_SET_PRESENT_SHA_SHIFT (28U)
+/*! PRESENT_SHA
+ * 0b1..Present
+ * 0b0..Absent
+ */
+#define DCP_CTRL_SET_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_SHA_SHIFT)) & DCP_CTRL_SET_PRESENT_SHA_MASK)
+#define DCP_CTRL_SET_PRESENT_CRYPTO_MASK (0x20000000U)
+#define DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT (29U)
+/*! PRESENT_CRYPTO
+ * 0b1..Present
+ * 0b0..Absent
+ */
+#define DCP_CTRL_SET_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_SET_PRESENT_CRYPTO_MASK)
+#define DCP_CTRL_SET_CLKGATE_MASK (0x40000000U)
+#define DCP_CTRL_SET_CLKGATE_SHIFT (30U)
+#define DCP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_CLKGATE_SHIFT)) & DCP_CTRL_SET_CLKGATE_MASK)
+#define DCP_CTRL_SET_SFTRST_MASK (0x80000000U)
+#define DCP_CTRL_SET_SFTRST_SHIFT (31U)
+#define DCP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_SET_SFTRST_SHIFT)) & DCP_CTRL_SET_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_CLR - DCP control register 0 */
+/*! @{ */
+#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
+#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
+/*! CHANNEL_INTERRUPT_ENABLE
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_CHANNEL_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
+#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
+#define DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_CLR_RSVD_CSC_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_SWITCHING_MASK)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT (22U)
+#define DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_CLR_ENABLE_CONTEXT_CACHING_MASK)
+#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
+#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT (23U)
+#define DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_CLR_GATHER_RESIDUAL_WRITES_MASK)
+#define DCP_CTRL_CLR_PRESENT_SHA_MASK (0x10000000U)
+#define DCP_CTRL_CLR_PRESENT_SHA_SHIFT (28U)
+/*! PRESENT_SHA
+ * 0b1..Present
+ * 0b0..Absent
+ */
+#define DCP_CTRL_CLR_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_SHA_SHIFT)) & DCP_CTRL_CLR_PRESENT_SHA_MASK)
+#define DCP_CTRL_CLR_PRESENT_CRYPTO_MASK (0x20000000U)
+#define DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT (29U)
+/*! PRESENT_CRYPTO
+ * 0b1..Present
+ * 0b0..Absent
+ */
+#define DCP_CTRL_CLR_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_CLR_PRESENT_CRYPTO_MASK)
+#define DCP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
+#define DCP_CTRL_CLR_CLKGATE_SHIFT (30U)
+#define DCP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_CLKGATE_SHIFT)) & DCP_CTRL_CLR_CLKGATE_MASK)
+#define DCP_CTRL_CLR_SFTRST_MASK (0x80000000U)
+#define DCP_CTRL_CLR_SFTRST_SHIFT (31U)
+#define DCP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_CLR_SFTRST_SHIFT)) & DCP_CTRL_CLR_SFTRST_MASK)
+/*! @} */
+
+/*! @name CTRL_TOG - DCP control register 0 */
+/*! @{ */
+#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK (0xFFU)
+#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT (0U)
+/*! CHANNEL_INTERRUPT_ENABLE
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_CHANNEL_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK (0x100U)
+#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT (8U)
+#define DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_SHIFT)) & DCP_CTRL_TOG_RSVD_CSC_INTERRUPT_ENABLE_MASK)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK (0x200000U)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT (21U)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_SWITCHING_MASK)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK (0x400000U)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT (22U)
+#define DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_SHIFT)) & DCP_CTRL_TOG_ENABLE_CONTEXT_CACHING_MASK)
+#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK (0x800000U)
+#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT (23U)
+#define DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_SHIFT)) & DCP_CTRL_TOG_GATHER_RESIDUAL_WRITES_MASK)
+#define DCP_CTRL_TOG_PRESENT_SHA_MASK (0x10000000U)
+#define DCP_CTRL_TOG_PRESENT_SHA_SHIFT (28U)
+/*! PRESENT_SHA
+ * 0b1..Present
+ * 0b0..Absent
+ */
+#define DCP_CTRL_TOG_PRESENT_SHA(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_SHA_SHIFT)) & DCP_CTRL_TOG_PRESENT_SHA_MASK)
+#define DCP_CTRL_TOG_PRESENT_CRYPTO_MASK (0x20000000U)
+#define DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT (29U)
+/*! PRESENT_CRYPTO
+ * 0b1..Present
+ * 0b0..Absent
+ */
+#define DCP_CTRL_TOG_PRESENT_CRYPTO(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_PRESENT_CRYPTO_SHIFT)) & DCP_CTRL_TOG_PRESENT_CRYPTO_MASK)
+#define DCP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
+#define DCP_CTRL_TOG_CLKGATE_SHIFT (30U)
+#define DCP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_CLKGATE_SHIFT)) & DCP_CTRL_TOG_CLKGATE_MASK)
+#define DCP_CTRL_TOG_SFTRST_MASK (0x80000000U)
+#define DCP_CTRL_TOG_SFTRST_SHIFT (31U)
+#define DCP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CTRL_TOG_SFTRST_SHIFT)) & DCP_CTRL_TOG_SFTRST_MASK)
+/*! @} */
+
+/*! @name STAT - DCP status register */
+/*! @{ */
+#define DCP_STAT_IRQ_MASK (0xFU)
+#define DCP_STAT_IRQ_SHIFT (0U)
+#define DCP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_IRQ_SHIFT)) & DCP_STAT_IRQ_MASK)
+#define DCP_STAT_RSVD_IRQ_MASK (0x100U)
+#define DCP_STAT_RSVD_IRQ_SHIFT (8U)
+#define DCP_STAT_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_RSVD_IRQ_SHIFT)) & DCP_STAT_RSVD_IRQ_MASK)
+#define DCP_STAT_READY_CHANNELS_MASK (0xFF0000U)
+#define DCP_STAT_READY_CHANNELS_SHIFT (16U)
+/*! READY_CHANNELS
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_STAT_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_READY_CHANNELS_SHIFT)) & DCP_STAT_READY_CHANNELS_MASK)
+#define DCP_STAT_CUR_CHANNEL_MASK (0xF000000U)
+#define DCP_STAT_CUR_CHANNEL_SHIFT (24U)
+/*! CUR_CHANNEL
+ * 0b0000..None
+ * 0b0001..CH0
+ * 0b0010..CH1
+ * 0b0011..CH2
+ * 0b0100..CH3
+ */
+#define DCP_STAT_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CUR_CHANNEL_SHIFT)) & DCP_STAT_CUR_CHANNEL_MASK)
+#define DCP_STAT_OTP_KEY_READY_MASK (0x10000000U)
+#define DCP_STAT_OTP_KEY_READY_SHIFT (28U)
+#define DCP_STAT_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_OTP_KEY_READY_SHIFT)) & DCP_STAT_OTP_KEY_READY_MASK)
+/*! @} */
+
+/*! @name STAT_SET - DCP status register */
+/*! @{ */
+#define DCP_STAT_SET_IRQ_MASK (0xFU)
+#define DCP_STAT_SET_IRQ_SHIFT (0U)
+#define DCP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_IRQ_SHIFT)) & DCP_STAT_SET_IRQ_MASK)
+#define DCP_STAT_SET_RSVD_IRQ_MASK (0x100U)
+#define DCP_STAT_SET_RSVD_IRQ_SHIFT (8U)
+#define DCP_STAT_SET_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_RSVD_IRQ_SHIFT)) & DCP_STAT_SET_RSVD_IRQ_MASK)
+#define DCP_STAT_SET_READY_CHANNELS_MASK (0xFF0000U)
+#define DCP_STAT_SET_READY_CHANNELS_SHIFT (16U)
+/*! READY_CHANNELS
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_STAT_SET_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_READY_CHANNELS_SHIFT)) & DCP_STAT_SET_READY_CHANNELS_MASK)
+#define DCP_STAT_SET_CUR_CHANNEL_MASK (0xF000000U)
+#define DCP_STAT_SET_CUR_CHANNEL_SHIFT (24U)
+/*! CUR_CHANNEL
+ * 0b0000..None
+ * 0b0001..CH0
+ * 0b0010..CH1
+ * 0b0011..CH2
+ * 0b0100..CH3
+ */
+#define DCP_STAT_SET_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_CUR_CHANNEL_SHIFT)) & DCP_STAT_SET_CUR_CHANNEL_MASK)
+#define DCP_STAT_SET_OTP_KEY_READY_MASK (0x10000000U)
+#define DCP_STAT_SET_OTP_KEY_READY_SHIFT (28U)
+#define DCP_STAT_SET_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_SET_OTP_KEY_READY_SHIFT)) & DCP_STAT_SET_OTP_KEY_READY_MASK)
+/*! @} */
+
+/*! @name STAT_CLR - DCP status register */
+/*! @{ */
+#define DCP_STAT_CLR_IRQ_MASK (0xFU)
+#define DCP_STAT_CLR_IRQ_SHIFT (0U)
+#define DCP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_IRQ_SHIFT)) & DCP_STAT_CLR_IRQ_MASK)
+#define DCP_STAT_CLR_RSVD_IRQ_MASK (0x100U)
+#define DCP_STAT_CLR_RSVD_IRQ_SHIFT (8U)
+#define DCP_STAT_CLR_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_RSVD_IRQ_SHIFT)) & DCP_STAT_CLR_RSVD_IRQ_MASK)
+#define DCP_STAT_CLR_READY_CHANNELS_MASK (0xFF0000U)
+#define DCP_STAT_CLR_READY_CHANNELS_SHIFT (16U)
+/*! READY_CHANNELS
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_STAT_CLR_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_READY_CHANNELS_SHIFT)) & DCP_STAT_CLR_READY_CHANNELS_MASK)
+#define DCP_STAT_CLR_CUR_CHANNEL_MASK (0xF000000U)
+#define DCP_STAT_CLR_CUR_CHANNEL_SHIFT (24U)
+/*! CUR_CHANNEL
+ * 0b0000..None
+ * 0b0001..CH0
+ * 0b0010..CH1
+ * 0b0011..CH2
+ * 0b0100..CH3
+ */
+#define DCP_STAT_CLR_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_CUR_CHANNEL_SHIFT)) & DCP_STAT_CLR_CUR_CHANNEL_MASK)
+#define DCP_STAT_CLR_OTP_KEY_READY_MASK (0x10000000U)
+#define DCP_STAT_CLR_OTP_KEY_READY_SHIFT (28U)
+#define DCP_STAT_CLR_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_CLR_OTP_KEY_READY_SHIFT)) & DCP_STAT_CLR_OTP_KEY_READY_MASK)
+/*! @} */
+
+/*! @name STAT_TOG - DCP status register */
+/*! @{ */
+#define DCP_STAT_TOG_IRQ_MASK (0xFU)
+#define DCP_STAT_TOG_IRQ_SHIFT (0U)
+#define DCP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_IRQ_SHIFT)) & DCP_STAT_TOG_IRQ_MASK)
+#define DCP_STAT_TOG_RSVD_IRQ_MASK (0x100U)
+#define DCP_STAT_TOG_RSVD_IRQ_SHIFT (8U)
+#define DCP_STAT_TOG_RSVD_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_RSVD_IRQ_SHIFT)) & DCP_STAT_TOG_RSVD_IRQ_MASK)
+#define DCP_STAT_TOG_READY_CHANNELS_MASK (0xFF0000U)
+#define DCP_STAT_TOG_READY_CHANNELS_SHIFT (16U)
+/*! READY_CHANNELS
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_STAT_TOG_READY_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_READY_CHANNELS_SHIFT)) & DCP_STAT_TOG_READY_CHANNELS_MASK)
+#define DCP_STAT_TOG_CUR_CHANNEL_MASK (0xF000000U)
+#define DCP_STAT_TOG_CUR_CHANNEL_SHIFT (24U)
+/*! CUR_CHANNEL
+ * 0b0000..None
+ * 0b0001..CH0
+ * 0b0010..CH1
+ * 0b0011..CH2
+ * 0b0100..CH3
+ */
+#define DCP_STAT_TOG_CUR_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_CUR_CHANNEL_SHIFT)) & DCP_STAT_TOG_CUR_CHANNEL_MASK)
+#define DCP_STAT_TOG_OTP_KEY_READY_MASK (0x10000000U)
+#define DCP_STAT_TOG_OTP_KEY_READY_SHIFT (28U)
+#define DCP_STAT_TOG_OTP_KEY_READY(x) (((uint32_t)(((uint32_t)(x)) << DCP_STAT_TOG_OTP_KEY_READY_SHIFT)) & DCP_STAT_TOG_OTP_KEY_READY_MASK)
+/*! @} */
+
+/*! @name CHANNELCTRL - DCP channel control register */
+/*! @{ */
+#define DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK (0xFFU)
+#define DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT (0U)
+/*! ENABLE_CHANNEL
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_ENABLE_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
+#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
+/*! HIGH_PRIORITY_CHANNEL
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_HIGH_PRIORITY_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK (0x10000U)
+#define DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT (16U)
+#define DCP_CHANNELCTRL_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CH0_IRQ_MERGED_MASK)
+#define DCP_CHANNELCTRL_RSVD_MASK (0xFFFE0000U)
+#define DCP_CHANNELCTRL_RSVD_SHIFT (17U)
+#define DCP_CHANNELCTRL_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_RSVD_SHIFT)) & DCP_CHANNELCTRL_RSVD_MASK)
+/*! @} */
+
+/*! @name CHANNELCTRL_SET - DCP channel control register */
+/*! @{ */
+#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK (0xFFU)
+#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT (0U)
+/*! ENABLE_CHANNEL
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_SET_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_ENABLE_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
+#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
+/*! HIGH_PRIORITY_CHANNEL
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_SET_HIGH_PRIORITY_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK (0x10000U)
+#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT (16U)
+#define DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_SET_CH0_IRQ_MERGED_MASK)
+#define DCP_CHANNELCTRL_SET_RSVD_MASK (0xFFFE0000U)
+#define DCP_CHANNELCTRL_SET_RSVD_SHIFT (17U)
+#define DCP_CHANNELCTRL_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_SET_RSVD_SHIFT)) & DCP_CHANNELCTRL_SET_RSVD_MASK)
+/*! @} */
+
+/*! @name CHANNELCTRL_CLR - DCP channel control register */
+/*! @{ */
+#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK (0xFFU)
+#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT (0U)
+/*! ENABLE_CHANNEL
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_ENABLE_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
+#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
+/*! HIGH_PRIORITY_CHANNEL
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_CLR_HIGH_PRIORITY_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK (0x10000U)
+#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT (16U)
+#define DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_CLR_CH0_IRQ_MERGED_MASK)
+#define DCP_CHANNELCTRL_CLR_RSVD_MASK (0xFFFE0000U)
+#define DCP_CHANNELCTRL_CLR_RSVD_SHIFT (17U)
+#define DCP_CHANNELCTRL_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_CLR_RSVD_SHIFT)) & DCP_CHANNELCTRL_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name CHANNELCTRL_TOG - DCP channel control register */
+/*! @{ */
+#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK (0xFFU)
+#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT (0U)
+/*! ENABLE_CHANNEL
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_ENABLE_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK (0xFF00U)
+#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT (8U)
+/*! HIGH_PRIORITY_CHANNEL
+ * 0b00000001..CH0
+ * 0b00000010..CH1
+ * 0b00000100..CH2
+ * 0b00001000..CH3
+ */
+#define DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_SHIFT)) & DCP_CHANNELCTRL_TOG_HIGH_PRIORITY_CHANNEL_MASK)
+#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK (0x10000U)
+#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT (16U)
+#define DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_SHIFT)) & DCP_CHANNELCTRL_TOG_CH0_IRQ_MERGED_MASK)
+#define DCP_CHANNELCTRL_TOG_RSVD_MASK (0xFFFE0000U)
+#define DCP_CHANNELCTRL_TOG_RSVD_SHIFT (17U)
+#define DCP_CHANNELCTRL_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CHANNELCTRL_TOG_RSVD_SHIFT)) & DCP_CHANNELCTRL_TOG_RSVD_MASK)
+/*! @} */
+
+/*! @name CAPABILITY0 - DCP capability 0 register */
+/*! @{ */
+#define DCP_CAPABILITY0_NUM_KEYS_MASK (0xFFU)
+#define DCP_CAPABILITY0_NUM_KEYS_SHIFT (0U)
+#define DCP_CAPABILITY0_NUM_KEYS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_KEYS_SHIFT)) & DCP_CAPABILITY0_NUM_KEYS_MASK)
+#define DCP_CAPABILITY0_NUM_CHANNELS_MASK (0xF00U)
+#define DCP_CAPABILITY0_NUM_CHANNELS_SHIFT (8U)
+#define DCP_CAPABILITY0_NUM_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_NUM_CHANNELS_SHIFT)) & DCP_CAPABILITY0_NUM_CHANNELS_MASK)
+#define DCP_CAPABILITY0_RSVD_MASK (0x1FFFF000U)
+#define DCP_CAPABILITY0_RSVD_SHIFT (12U)
+#define DCP_CAPABILITY0_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_RSVD_SHIFT)) & DCP_CAPABILITY0_RSVD_MASK)
+#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK (0x20000000U)
+#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT (29U)
+#define DCP_CAPABILITY0_DISABLE_UNIQUE_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_SHIFT)) & DCP_CAPABILITY0_DISABLE_UNIQUE_KEY_MASK)
+#define DCP_CAPABILITY0_DISABLE_DECRYPT_MASK (0x80000000U)
+#define DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT (31U)
+#define DCP_CAPABILITY0_DISABLE_DECRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY0_DISABLE_DECRYPT_SHIFT)) & DCP_CAPABILITY0_DISABLE_DECRYPT_MASK)
+/*! @} */
+
+/*! @name CAPABILITY1 - DCP capability 1 register */
+/*! @{ */
+#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK (0xFFFFU)
+#define DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT (0U)
+/*! CIPHER_ALGORITHMS
+ * 0b0000000000000001..AES128
+ */
+#define DCP_CAPABILITY1_CIPHER_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_CIPHER_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_CIPHER_ALGORITHMS_MASK)
+#define DCP_CAPABILITY1_HASH_ALGORITHMS_MASK (0xFFFF0000U)
+#define DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT (16U)
+/*! HASH_ALGORITHMS
+ * 0b0000000000000001..SHA1
+ * 0b0000000000000010..CRC32
+ * 0b0000000000000100..SHA256
+ */
+#define DCP_CAPABILITY1_HASH_ALGORITHMS(x) (((uint32_t)(((uint32_t)(x)) << DCP_CAPABILITY1_HASH_ALGORITHMS_SHIFT)) & DCP_CAPABILITY1_HASH_ALGORITHMS_MASK)
+/*! @} */
+
+/*! @name CONTEXT - DCP context buffer pointer */
+/*! @{ */
+#define DCP_CONTEXT_ADDR_MASK (0xFFFFFFFFU)
+#define DCP_CONTEXT_ADDR_SHIFT (0U)
+#define DCP_CONTEXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CONTEXT_ADDR_SHIFT)) & DCP_CONTEXT_ADDR_MASK)
+/*! @} */
+
+/*! @name KEY - DCP key index */
+/*! @{ */
+#define DCP_KEY_SUBWORD_MASK (0x3U)
+#define DCP_KEY_SUBWORD_SHIFT (0U)
+#define DCP_KEY_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_SUBWORD_SHIFT)) & DCP_KEY_SUBWORD_MASK)
+#define DCP_KEY_RSVD_SUBWORD_MASK (0xCU)
+#define DCP_KEY_RSVD_SUBWORD_SHIFT (2U)
+#define DCP_KEY_RSVD_SUBWORD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SUBWORD_SHIFT)) & DCP_KEY_RSVD_SUBWORD_MASK)
+#define DCP_KEY_INDEX_MASK (0x30U)
+#define DCP_KEY_INDEX_SHIFT (4U)
+#define DCP_KEY_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_INDEX_SHIFT)) & DCP_KEY_INDEX_MASK)
+#define DCP_KEY_RSVD_INDEX_MASK (0xC0U)
+#define DCP_KEY_RSVD_INDEX_SHIFT (6U)
+#define DCP_KEY_RSVD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_INDEX_SHIFT)) & DCP_KEY_RSVD_INDEX_MASK)
+#define DCP_KEY_RSVD_MASK (0xFFFFFF00U)
+#define DCP_KEY_RSVD_SHIFT (8U)
+#define DCP_KEY_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEY_RSVD_SHIFT)) & DCP_KEY_RSVD_MASK)
+/*! @} */
+
+/*! @name KEYDATA - DCP key data */
+/*! @{ */
+#define DCP_KEYDATA_DATA_MASK (0xFFFFFFFFU)
+#define DCP_KEYDATA_DATA_SHIFT (0U)
+#define DCP_KEYDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DCP_KEYDATA_DATA_SHIFT)) & DCP_KEYDATA_DATA_MASK)
+/*! @} */
+
+/*! @name PACKET0 - DCP work packet 0 status register */
+/*! @{ */
+#define DCP_PACKET0_ADDR_MASK (0xFFFFFFFFU)
+#define DCP_PACKET0_ADDR_SHIFT (0U)
+#define DCP_PACKET0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET0_ADDR_SHIFT)) & DCP_PACKET0_ADDR_MASK)
+/*! @} */
+
+/*! @name PACKET1 - DCP work packet 1 status register */
+/*! @{ */
+#define DCP_PACKET1_INTERRUPT_MASK (0x1U)
+#define DCP_PACKET1_INTERRUPT_SHIFT (0U)
+#define DCP_PACKET1_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INTERRUPT_SHIFT)) & DCP_PACKET1_INTERRUPT_MASK)
+#define DCP_PACKET1_DECR_SEMAPHORE_MASK (0x2U)
+#define DCP_PACKET1_DECR_SEMAPHORE_SHIFT (1U)
+#define DCP_PACKET1_DECR_SEMAPHORE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_DECR_SEMAPHORE_SHIFT)) & DCP_PACKET1_DECR_SEMAPHORE_MASK)
+#define DCP_PACKET1_CHAIN_MASK (0x4U)
+#define DCP_PACKET1_CHAIN_SHIFT (2U)
+#define DCP_PACKET1_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_SHIFT)) & DCP_PACKET1_CHAIN_MASK)
+#define DCP_PACKET1_CHAIN_CONTIGUOUS_MASK (0x8U)
+#define DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT (3U)
+#define DCP_PACKET1_CHAIN_CONTIGUOUS(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHAIN_CONTIGUOUS_SHIFT)) & DCP_PACKET1_CHAIN_CONTIGUOUS_MASK)
+#define DCP_PACKET1_ENABLE_MEMCOPY_MASK (0x10U)
+#define DCP_PACKET1_ENABLE_MEMCOPY_SHIFT (4U)
+#define DCP_PACKET1_ENABLE_MEMCOPY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_MEMCOPY_SHIFT)) & DCP_PACKET1_ENABLE_MEMCOPY_MASK)
+#define DCP_PACKET1_ENABLE_CIPHER_MASK (0x20U)
+#define DCP_PACKET1_ENABLE_CIPHER_SHIFT (5U)
+#define DCP_PACKET1_ENABLE_CIPHER(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_CIPHER_SHIFT)) & DCP_PACKET1_ENABLE_CIPHER_MASK)
+#define DCP_PACKET1_ENABLE_HASH_MASK (0x40U)
+#define DCP_PACKET1_ENABLE_HASH_SHIFT (6U)
+#define DCP_PACKET1_ENABLE_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_HASH_SHIFT)) & DCP_PACKET1_ENABLE_HASH_MASK)
+#define DCP_PACKET1_ENABLE_BLIT_MASK (0x80U)
+#define DCP_PACKET1_ENABLE_BLIT_SHIFT (7U)
+#define DCP_PACKET1_ENABLE_BLIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_ENABLE_BLIT_SHIFT)) & DCP_PACKET1_ENABLE_BLIT_MASK)
+#define DCP_PACKET1_CIPHER_ENCRYPT_MASK (0x100U)
+#define DCP_PACKET1_CIPHER_ENCRYPT_SHIFT (8U)
+/*! CIPHER_ENCRYPT
+ * 0b1..ENCRYPT
+ * 0b0..DECRYPT
+ */
+#define DCP_PACKET1_CIPHER_ENCRYPT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_ENCRYPT_SHIFT)) & DCP_PACKET1_CIPHER_ENCRYPT_MASK)
+#define DCP_PACKET1_CIPHER_INIT_MASK (0x200U)
+#define DCP_PACKET1_CIPHER_INIT_SHIFT (9U)
+#define DCP_PACKET1_CIPHER_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CIPHER_INIT_SHIFT)) & DCP_PACKET1_CIPHER_INIT_MASK)
+#define DCP_PACKET1_OTP_KEY_MASK (0x400U)
+#define DCP_PACKET1_OTP_KEY_SHIFT (10U)
+#define DCP_PACKET1_OTP_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OTP_KEY_SHIFT)) & DCP_PACKET1_OTP_KEY_MASK)
+#define DCP_PACKET1_PAYLOAD_KEY_MASK (0x800U)
+#define DCP_PACKET1_PAYLOAD_KEY_SHIFT (11U)
+#define DCP_PACKET1_PAYLOAD_KEY(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_PAYLOAD_KEY_SHIFT)) & DCP_PACKET1_PAYLOAD_KEY_MASK)
+#define DCP_PACKET1_HASH_INIT_MASK (0x1000U)
+#define DCP_PACKET1_HASH_INIT_SHIFT (12U)
+#define DCP_PACKET1_HASH_INIT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_INIT_SHIFT)) & DCP_PACKET1_HASH_INIT_MASK)
+#define DCP_PACKET1_HASH_TERM_MASK (0x2000U)
+#define DCP_PACKET1_HASH_TERM_SHIFT (13U)
+#define DCP_PACKET1_HASH_TERM(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_TERM_SHIFT)) & DCP_PACKET1_HASH_TERM_MASK)
+#define DCP_PACKET1_CHECK_HASH_MASK (0x4000U)
+#define DCP_PACKET1_CHECK_HASH_SHIFT (14U)
+#define DCP_PACKET1_CHECK_HASH(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CHECK_HASH_SHIFT)) & DCP_PACKET1_CHECK_HASH_MASK)
+#define DCP_PACKET1_HASH_OUTPUT_MASK (0x8000U)
+#define DCP_PACKET1_HASH_OUTPUT_SHIFT (15U)
+/*! HASH_OUTPUT
+ * 0b0..INPUT
+ * 0b1..OUTPUT
+ */
+#define DCP_PACKET1_HASH_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_HASH_OUTPUT_SHIFT)) & DCP_PACKET1_HASH_OUTPUT_MASK)
+#define DCP_PACKET1_CONSTANT_FILL_MASK (0x10000U)
+#define DCP_PACKET1_CONSTANT_FILL_SHIFT (16U)
+#define DCP_PACKET1_CONSTANT_FILL(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_CONSTANT_FILL_SHIFT)) & DCP_PACKET1_CONSTANT_FILL_MASK)
+#define DCP_PACKET1_TEST_SEMA_IRQ_MASK (0x20000U)
+#define DCP_PACKET1_TEST_SEMA_IRQ_SHIFT (17U)
+#define DCP_PACKET1_TEST_SEMA_IRQ(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TEST_SEMA_IRQ_SHIFT)) & DCP_PACKET1_TEST_SEMA_IRQ_MASK)
+#define DCP_PACKET1_KEY_BYTESWAP_MASK (0x40000U)
+#define DCP_PACKET1_KEY_BYTESWAP_SHIFT (18U)
+#define DCP_PACKET1_KEY_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_BYTESWAP_SHIFT)) & DCP_PACKET1_KEY_BYTESWAP_MASK)
+#define DCP_PACKET1_KEY_WORDSWAP_MASK (0x80000U)
+#define DCP_PACKET1_KEY_WORDSWAP_SHIFT (19U)
+#define DCP_PACKET1_KEY_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_KEY_WORDSWAP_SHIFT)) & DCP_PACKET1_KEY_WORDSWAP_MASK)
+#define DCP_PACKET1_INPUT_BYTESWAP_MASK (0x100000U)
+#define DCP_PACKET1_INPUT_BYTESWAP_SHIFT (20U)
+#define DCP_PACKET1_INPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_INPUT_BYTESWAP_MASK)
+#define DCP_PACKET1_INPUT_WORDSWAP_MASK (0x200000U)
+#define DCP_PACKET1_INPUT_WORDSWAP_SHIFT (21U)
+#define DCP_PACKET1_INPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_INPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_INPUT_WORDSWAP_MASK)
+#define DCP_PACKET1_OUTPUT_BYTESWAP_MASK (0x400000U)
+#define DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT (22U)
+#define DCP_PACKET1_OUTPUT_BYTESWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_BYTESWAP_SHIFT)) & DCP_PACKET1_OUTPUT_BYTESWAP_MASK)
+#define DCP_PACKET1_OUTPUT_WORDSWAP_MASK (0x800000U)
+#define DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT (23U)
+#define DCP_PACKET1_OUTPUT_WORDSWAP(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_OUTPUT_WORDSWAP_SHIFT)) & DCP_PACKET1_OUTPUT_WORDSWAP_MASK)
+#define DCP_PACKET1_TAG_MASK (0xFF000000U)
+#define DCP_PACKET1_TAG_SHIFT (24U)
+#define DCP_PACKET1_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET1_TAG_SHIFT)) & DCP_PACKET1_TAG_MASK)
+/*! @} */
+
+/*! @name PACKET2 - DCP work packet 2 status register */
+/*! @{ */
+#define DCP_PACKET2_CIPHER_SELECT_MASK (0xFU)
+#define DCP_PACKET2_CIPHER_SELECT_SHIFT (0U)
+/*! CIPHER_SELECT
+ * 0b0000..AES128
+ */
+#define DCP_PACKET2_CIPHER_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_SELECT_SHIFT)) & DCP_PACKET2_CIPHER_SELECT_MASK)
+#define DCP_PACKET2_CIPHER_MODE_MASK (0xF0U)
+#define DCP_PACKET2_CIPHER_MODE_SHIFT (4U)
+/*! CIPHER_MODE
+ * 0b0000..ECB
+ * 0b0001..CBC
+ */
+#define DCP_PACKET2_CIPHER_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_MODE_SHIFT)) & DCP_PACKET2_CIPHER_MODE_MASK)
+#define DCP_PACKET2_KEY_SELECT_MASK (0xFF00U)
+#define DCP_PACKET2_KEY_SELECT_SHIFT (8U)
+/*! KEY_SELECT
+ * 0b00000000..KEY0
+ * 0b00000001..KEY1
+ * 0b00000010..KEY2
+ * 0b00000011..KEY3
+ * 0b11111110..UNIQUE_KEY
+ * 0b11111111..OTP_KEY
+ */
+#define DCP_PACKET2_KEY_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_KEY_SELECT_SHIFT)) & DCP_PACKET2_KEY_SELECT_MASK)
+#define DCP_PACKET2_HASH_SELECT_MASK (0xF0000U)
+#define DCP_PACKET2_HASH_SELECT_SHIFT (16U)
+/*! HASH_SELECT
+ * 0b0000..SHA1
+ * 0b0001..CRC32
+ * 0b0010..SHA256
+ */
+#define DCP_PACKET2_HASH_SELECT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_HASH_SELECT_SHIFT)) & DCP_PACKET2_HASH_SELECT_MASK)
+#define DCP_PACKET2_RSVD_MASK (0xF00000U)
+#define DCP_PACKET2_RSVD_SHIFT (20U)
+#define DCP_PACKET2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_RSVD_SHIFT)) & DCP_PACKET2_RSVD_MASK)
+#define DCP_PACKET2_CIPHER_CFG_MASK (0xFF000000U)
+#define DCP_PACKET2_CIPHER_CFG_SHIFT (24U)
+#define DCP_PACKET2_CIPHER_CFG(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET2_CIPHER_CFG_SHIFT)) & DCP_PACKET2_CIPHER_CFG_MASK)
+/*! @} */
+
+/*! @name PACKET3 - DCP work packet 3 status register */
+/*! @{ */
+#define DCP_PACKET3_ADDR_MASK (0xFFFFFFFFU)
+#define DCP_PACKET3_ADDR_SHIFT (0U)
+#define DCP_PACKET3_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET3_ADDR_SHIFT)) & DCP_PACKET3_ADDR_MASK)
+/*! @} */
+
+/*! @name PACKET4 - DCP work packet 4 status register */
+/*! @{ */
+#define DCP_PACKET4_ADDR_MASK (0xFFFFFFFFU)
+#define DCP_PACKET4_ADDR_SHIFT (0U)
+#define DCP_PACKET4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET4_ADDR_SHIFT)) & DCP_PACKET4_ADDR_MASK)
+/*! @} */
+
+/*! @name PACKET5 - DCP work packet 5 status register */
+/*! @{ */
+#define DCP_PACKET5_COUNT_MASK (0xFFFFFFFFU)
+#define DCP_PACKET5_COUNT_SHIFT (0U)
+#define DCP_PACKET5_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET5_COUNT_SHIFT)) & DCP_PACKET5_COUNT_MASK)
+/*! @} */
+
+/*! @name PACKET6 - DCP work packet 6 status register */
+/*! @{ */
+#define DCP_PACKET6_ADDR_MASK (0xFFFFFFFFU)
+#define DCP_PACKET6_ADDR_SHIFT (0U)
+#define DCP_PACKET6_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_PACKET6_ADDR_SHIFT)) & DCP_PACKET6_ADDR_MASK)
+/*! @} */
+
+/*! @name CH0CMDPTR - DCP channel 0 command pointer address register */
+/*! @{ */
+#define DCP_CH0CMDPTR_ADDR_MASK (0xFFFFFFFFU)
+#define DCP_CH0CMDPTR_ADDR_SHIFT (0U)
+#define DCP_CH0CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0CMDPTR_ADDR_SHIFT)) & DCP_CH0CMDPTR_ADDR_MASK)
+/*! @} */
+
+/*! @name CH0SEMA - DCP channel 0 semaphore register */
+/*! @{ */
+#define DCP_CH0SEMA_INCREMENT_MASK (0xFFU)
+#define DCP_CH0SEMA_INCREMENT_SHIFT (0U)
+#define DCP_CH0SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_INCREMENT_SHIFT)) & DCP_CH0SEMA_INCREMENT_MASK)
+#define DCP_CH0SEMA_VALUE_MASK (0xFF0000U)
+#define DCP_CH0SEMA_VALUE_SHIFT (16U)
+#define DCP_CH0SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0SEMA_VALUE_SHIFT)) & DCP_CH0SEMA_VALUE_MASK)
+/*! @} */
+
+/*! @name CH0STAT - DCP channel 0 status register */
+/*! @{ */
+#define DCP_CH0STAT_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH0STAT_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH0STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_RSVD_COMPLETE_MASK)
+#define DCP_CH0STAT_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH0STAT_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH0STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_HASH_MISMATCH_MASK)
+#define DCP_CH0STAT_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH0STAT_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH0STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_ERROR_SETUP_MASK)
+#define DCP_CH0STAT_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH0STAT_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH0STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_ERROR_PACKET_MASK)
+#define DCP_CH0STAT_ERROR_SRC_MASK (0x10U)
+#define DCP_CH0STAT_ERROR_SRC_SHIFT (4U)
+#define DCP_CH0STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_SRC_SHIFT)) & DCP_CH0STAT_ERROR_SRC_MASK)
+#define DCP_CH0STAT_ERROR_DST_MASK (0x20U)
+#define DCP_CH0STAT_ERROR_DST_SHIFT (5U)
+#define DCP_CH0STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_DST_SHIFT)) & DCP_CH0STAT_ERROR_DST_MASK)
+#define DCP_CH0STAT_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH0STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_ERROR_PAGEFAULT_MASK)
+#define DCP_CH0STAT_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH0STAT_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error signalled because the next pointer is 0x00000000
+ * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
+ * 0b00000011..Error signalled because an error is reported reading/writing the context buffer
+ * 0b00000100..Error signalled because an error is reported reading/writing the payload
+ * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
+ */
+#define DCP_CH0STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_ERROR_CODE_SHIFT)) & DCP_CH0STAT_ERROR_CODE_MASK)
+#define DCP_CH0STAT_TAG_MASK (0xFF000000U)
+#define DCP_CH0STAT_TAG_SHIFT (24U)
+#define DCP_CH0STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TAG_SHIFT)) & DCP_CH0STAT_TAG_MASK)
+/*! @} */
+
+/*! @name CH0STAT_SET - DCP channel 0 status register */
+/*! @{ */
+#define DCP_CH0STAT_SET_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH0STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_SET_RSVD_COMPLETE_MASK)
+#define DCP_CH0STAT_SET_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH0STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_SET_HASH_MISMATCH_MASK)
+#define DCP_CH0STAT_SET_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH0STAT_SET_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH0STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_SET_ERROR_SETUP_MASK)
+#define DCP_CH0STAT_SET_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH0STAT_SET_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH0STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_SET_ERROR_PACKET_MASK)
+#define DCP_CH0STAT_SET_ERROR_SRC_MASK (0x10U)
+#define DCP_CH0STAT_SET_ERROR_SRC_SHIFT (4U)
+#define DCP_CH0STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH0STAT_SET_ERROR_SRC_MASK)
+#define DCP_CH0STAT_SET_ERROR_DST_MASK (0x20U)
+#define DCP_CH0STAT_SET_ERROR_DST_SHIFT (5U)
+#define DCP_CH0STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_DST_SHIFT)) & DCP_CH0STAT_SET_ERROR_DST_MASK)
+#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH0STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_SET_ERROR_PAGEFAULT_MASK)
+#define DCP_CH0STAT_SET_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH0STAT_SET_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error signalled because the next pointer is 0x00000000
+ * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
+ * 0b00000011..Error signalled because an error is reported reading/writing the context buffer
+ * 0b00000100..Error signalled because an error is reported reading/writing the payload
+ * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
+ */
+#define DCP_CH0STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH0STAT_SET_ERROR_CODE_MASK)
+#define DCP_CH0STAT_SET_TAG_MASK (0xFF000000U)
+#define DCP_CH0STAT_SET_TAG_SHIFT (24U)
+#define DCP_CH0STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_SET_TAG_SHIFT)) & DCP_CH0STAT_SET_TAG_MASK)
+/*! @} */
+
+/*! @name CH0STAT_CLR - DCP channel 0 status register */
+/*! @{ */
+#define DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH0STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_CLR_RSVD_COMPLETE_MASK)
+#define DCP_CH0STAT_CLR_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH0STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_CLR_HASH_MISMATCH_MASK)
+#define DCP_CH0STAT_CLR_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH0STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SETUP_MASK)
+#define DCP_CH0STAT_CLR_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH0STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PACKET_MASK)
+#define DCP_CH0STAT_CLR_ERROR_SRC_MASK (0x10U)
+#define DCP_CH0STAT_CLR_ERROR_SRC_SHIFT (4U)
+#define DCP_CH0STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH0STAT_CLR_ERROR_SRC_MASK)
+#define DCP_CH0STAT_CLR_ERROR_DST_MASK (0x20U)
+#define DCP_CH0STAT_CLR_ERROR_DST_SHIFT (5U)
+#define DCP_CH0STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH0STAT_CLR_ERROR_DST_MASK)
+#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH0STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_CLR_ERROR_PAGEFAULT_MASK)
+#define DCP_CH0STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH0STAT_CLR_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error signalled because the next pointer is 0x00000000
+ * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
+ * 0b00000011..Error signalled because an error is reported reading/writing the context buffer
+ * 0b00000100..Error signalled because an error is reported reading/writing the payload
+ * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
+ */
+#define DCP_CH0STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH0STAT_CLR_ERROR_CODE_MASK)
+#define DCP_CH0STAT_CLR_TAG_MASK (0xFF000000U)
+#define DCP_CH0STAT_CLR_TAG_SHIFT (24U)
+#define DCP_CH0STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_CLR_TAG_SHIFT)) & DCP_CH0STAT_CLR_TAG_MASK)
+/*! @} */
+
+/*! @name CH0STAT_TOG - DCP channel 0 status register */
+/*! @{ */
+#define DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH0STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH0STAT_TOG_RSVD_COMPLETE_MASK)
+#define DCP_CH0STAT_TOG_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH0STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH0STAT_TOG_HASH_MISMATCH_MASK)
+#define DCP_CH0STAT_TOG_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH0STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SETUP_MASK)
+#define DCP_CH0STAT_TOG_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH0STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PACKET_MASK)
+#define DCP_CH0STAT_TOG_ERROR_SRC_MASK (0x10U)
+#define DCP_CH0STAT_TOG_ERROR_SRC_SHIFT (4U)
+#define DCP_CH0STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH0STAT_TOG_ERROR_SRC_MASK)
+#define DCP_CH0STAT_TOG_ERROR_DST_MASK (0x20U)
+#define DCP_CH0STAT_TOG_ERROR_DST_SHIFT (5U)
+#define DCP_CH0STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH0STAT_TOG_ERROR_DST_MASK)
+#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH0STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH0STAT_TOG_ERROR_PAGEFAULT_MASK)
+#define DCP_CH0STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH0STAT_TOG_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error signalled because the next pointer is 0x00000000
+ * 0b00000010..Error signalled because the semaphore is non-zero and neither chain bit is set
+ * 0b00000011..Error signalled because an error is reported reading/writing the context buffer
+ * 0b00000100..Error signalled because an error is reported reading/writing the payload
+ * 0b00000101..Error signalled because the control packet specifies an invalid mode select (for instance, blit + hash)
+ */
+#define DCP_CH0STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH0STAT_TOG_ERROR_CODE_MASK)
+#define DCP_CH0STAT_TOG_TAG_MASK (0xFF000000U)
+#define DCP_CH0STAT_TOG_TAG_SHIFT (24U)
+#define DCP_CH0STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0STAT_TOG_TAG_SHIFT)) & DCP_CH0STAT_TOG_TAG_MASK)
+/*! @} */
+
+/*! @name CH0OPTS - DCP channel 0 options register */
+/*! @{ */
+#define DCP_CH0OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH0OPTS_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH0OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_RECOVERY_TIMER_MASK)
+#define DCP_CH0OPTS_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH0OPTS_RSVD_SHIFT (16U)
+#define DCP_CH0OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_RSVD_SHIFT)) & DCP_CH0OPTS_RSVD_MASK)
+/*! @} */
+
+/*! @name CH0OPTS_SET - DCP channel 0 options register */
+/*! @{ */
+#define DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH0OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_SET_RECOVERY_TIMER_MASK)
+#define DCP_CH0OPTS_SET_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH0OPTS_SET_RSVD_SHIFT (16U)
+#define DCP_CH0OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_SET_RSVD_SHIFT)) & DCP_CH0OPTS_SET_RSVD_MASK)
+/*! @} */
+
+/*! @name CH0OPTS_CLR - DCP channel 0 options register */
+/*! @{ */
+#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH0OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_CLR_RECOVERY_TIMER_MASK)
+#define DCP_CH0OPTS_CLR_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH0OPTS_CLR_RSVD_SHIFT (16U)
+#define DCP_CH0OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_CLR_RSVD_SHIFT)) & DCP_CH0OPTS_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name CH0OPTS_TOG - DCP channel 0 options register */
+/*! @{ */
+#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH0OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH0OPTS_TOG_RECOVERY_TIMER_MASK)
+#define DCP_CH0OPTS_TOG_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH0OPTS_TOG_RSVD_SHIFT (16U)
+#define DCP_CH0OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH0OPTS_TOG_RSVD_SHIFT)) & DCP_CH0OPTS_TOG_RSVD_MASK)
+/*! @} */
+
+/*! @name CH1CMDPTR - DCP channel 1 command pointer address register */
+/*! @{ */
+#define DCP_CH1CMDPTR_ADDR_MASK (0xFFFFFFFFU)
+#define DCP_CH1CMDPTR_ADDR_SHIFT (0U)
+#define DCP_CH1CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1CMDPTR_ADDR_SHIFT)) & DCP_CH1CMDPTR_ADDR_MASK)
+/*! @} */
+
+/*! @name CH1SEMA - DCP channel 1 semaphore register */
+/*! @{ */
+#define DCP_CH1SEMA_INCREMENT_MASK (0xFFU)
+#define DCP_CH1SEMA_INCREMENT_SHIFT (0U)
+#define DCP_CH1SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_INCREMENT_SHIFT)) & DCP_CH1SEMA_INCREMENT_MASK)
+#define DCP_CH1SEMA_VALUE_MASK (0xFF0000U)
+#define DCP_CH1SEMA_VALUE_SHIFT (16U)
+#define DCP_CH1SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1SEMA_VALUE_SHIFT)) & DCP_CH1SEMA_VALUE_MASK)
+/*! @} */
+
+/*! @name CH1STAT - DCP channel 1 status register */
+/*! @{ */
+#define DCP_CH1STAT_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH1STAT_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH1STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_RSVD_COMPLETE_MASK)
+#define DCP_CH1STAT_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH1STAT_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH1STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_HASH_MISMATCH_MASK)
+#define DCP_CH1STAT_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH1STAT_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH1STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_ERROR_SETUP_MASK)
+#define DCP_CH1STAT_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH1STAT_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH1STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_ERROR_PACKET_MASK)
+#define DCP_CH1STAT_ERROR_SRC_MASK (0x10U)
+#define DCP_CH1STAT_ERROR_SRC_SHIFT (4U)
+#define DCP_CH1STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_SRC_SHIFT)) & DCP_CH1STAT_ERROR_SRC_MASK)
+#define DCP_CH1STAT_ERROR_DST_MASK (0x20U)
+#define DCP_CH1STAT_ERROR_DST_SHIFT (5U)
+#define DCP_CH1STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_DST_SHIFT)) & DCP_CH1STAT_ERROR_DST_MASK)
+#define DCP_CH1STAT_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH1STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_ERROR_PAGEFAULT_MASK)
+#define DCP_CH1STAT_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH1STAT_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error is signalled because the next pointer is 0x00000000.
+ * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
+ * 0b00000100..Error is signalled because an error was reported when reading/writing the payload.
+ * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
+#define DCP_CH1STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_ERROR_CODE_SHIFT)) & DCP_CH1STAT_ERROR_CODE_MASK)
+#define DCP_CH1STAT_TAG_MASK (0xFF000000U)
+#define DCP_CH1STAT_TAG_SHIFT (24U)
+#define DCP_CH1STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TAG_SHIFT)) & DCP_CH1STAT_TAG_MASK)
+/*! @} */
+
+/*! @name CH1STAT_SET - DCP channel 1 status register */
+/*! @{ */
+#define DCP_CH1STAT_SET_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH1STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_SET_RSVD_COMPLETE_MASK)
+#define DCP_CH1STAT_SET_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH1STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_SET_HASH_MISMATCH_MASK)
+#define DCP_CH1STAT_SET_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH1STAT_SET_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH1STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_SET_ERROR_SETUP_MASK)
+#define DCP_CH1STAT_SET_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH1STAT_SET_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH1STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_SET_ERROR_PACKET_MASK)
+#define DCP_CH1STAT_SET_ERROR_SRC_MASK (0x10U)
+#define DCP_CH1STAT_SET_ERROR_SRC_SHIFT (4U)
+#define DCP_CH1STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH1STAT_SET_ERROR_SRC_MASK)
+#define DCP_CH1STAT_SET_ERROR_DST_MASK (0x20U)
+#define DCP_CH1STAT_SET_ERROR_DST_SHIFT (5U)
+#define DCP_CH1STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_DST_SHIFT)) & DCP_CH1STAT_SET_ERROR_DST_MASK)
+#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH1STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_SET_ERROR_PAGEFAULT_MASK)
+#define DCP_CH1STAT_SET_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH1STAT_SET_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error is signalled because the next pointer is 0x00000000.
+ * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
+ * 0b00000100..Error is signalled because an error was reported when reading/writing the payload.
+ * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
+#define DCP_CH1STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH1STAT_SET_ERROR_CODE_MASK)
+#define DCP_CH1STAT_SET_TAG_MASK (0xFF000000U)
+#define DCP_CH1STAT_SET_TAG_SHIFT (24U)
+#define DCP_CH1STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_SET_TAG_SHIFT)) & DCP_CH1STAT_SET_TAG_MASK)
+/*! @} */
+
+/*! @name CH1STAT_CLR - DCP channel 1 status register */
+/*! @{ */
+#define DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH1STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_CLR_RSVD_COMPLETE_MASK)
+#define DCP_CH1STAT_CLR_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH1STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_CLR_HASH_MISMATCH_MASK)
+#define DCP_CH1STAT_CLR_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH1STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SETUP_MASK)
+#define DCP_CH1STAT_CLR_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH1STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PACKET_MASK)
+#define DCP_CH1STAT_CLR_ERROR_SRC_MASK (0x10U)
+#define DCP_CH1STAT_CLR_ERROR_SRC_SHIFT (4U)
+#define DCP_CH1STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH1STAT_CLR_ERROR_SRC_MASK)
+#define DCP_CH1STAT_CLR_ERROR_DST_MASK (0x20U)
+#define DCP_CH1STAT_CLR_ERROR_DST_SHIFT (5U)
+#define DCP_CH1STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH1STAT_CLR_ERROR_DST_MASK)
+#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH1STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_CLR_ERROR_PAGEFAULT_MASK)
+#define DCP_CH1STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH1STAT_CLR_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error is signalled because the next pointer is 0x00000000.
+ * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
+ * 0b00000100..Error is signalled because an error was reported when reading/writing the payload.
+ * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
+#define DCP_CH1STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH1STAT_CLR_ERROR_CODE_MASK)
+#define DCP_CH1STAT_CLR_TAG_MASK (0xFF000000U)
+#define DCP_CH1STAT_CLR_TAG_SHIFT (24U)
+#define DCP_CH1STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_CLR_TAG_SHIFT)) & DCP_CH1STAT_CLR_TAG_MASK)
+/*! @} */
+
+/*! @name CH1STAT_TOG - DCP channel 1 status register */
+/*! @{ */
+#define DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH1STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH1STAT_TOG_RSVD_COMPLETE_MASK)
+#define DCP_CH1STAT_TOG_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH1STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH1STAT_TOG_HASH_MISMATCH_MASK)
+#define DCP_CH1STAT_TOG_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH1STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SETUP_MASK)
+#define DCP_CH1STAT_TOG_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH1STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PACKET_MASK)
+#define DCP_CH1STAT_TOG_ERROR_SRC_MASK (0x10U)
+#define DCP_CH1STAT_TOG_ERROR_SRC_SHIFT (4U)
+#define DCP_CH1STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH1STAT_TOG_ERROR_SRC_MASK)
+#define DCP_CH1STAT_TOG_ERROR_DST_MASK (0x20U)
+#define DCP_CH1STAT_TOG_ERROR_DST_SHIFT (5U)
+#define DCP_CH1STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH1STAT_TOG_ERROR_DST_MASK)
+#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH1STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH1STAT_TOG_ERROR_PAGEFAULT_MASK)
+#define DCP_CH1STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH1STAT_TOG_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error is signalled because the next pointer is 0x00000000.
+ * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ * 0b00000011..Error is signalled because an error was reported when reading/writing the context buffer.
+ * 0b00000100..Error is signalled because an error was reported when reading/writing the payload.
+ * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for example, blit + hash).
+ */
+#define DCP_CH1STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH1STAT_TOG_ERROR_CODE_MASK)
+#define DCP_CH1STAT_TOG_TAG_MASK (0xFF000000U)
+#define DCP_CH1STAT_TOG_TAG_SHIFT (24U)
+#define DCP_CH1STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1STAT_TOG_TAG_SHIFT)) & DCP_CH1STAT_TOG_TAG_MASK)
+/*! @} */
+
+/*! @name CH1OPTS - DCP channel 1 options register */
+/*! @{ */
+#define DCP_CH1OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH1OPTS_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH1OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_RECOVERY_TIMER_MASK)
+#define DCP_CH1OPTS_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH1OPTS_RSVD_SHIFT (16U)
+#define DCP_CH1OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_RSVD_SHIFT)) & DCP_CH1OPTS_RSVD_MASK)
+/*! @} */
+
+/*! @name CH1OPTS_SET - DCP channel 1 options register */
+/*! @{ */
+#define DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH1OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_SET_RECOVERY_TIMER_MASK)
+#define DCP_CH1OPTS_SET_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH1OPTS_SET_RSVD_SHIFT (16U)
+#define DCP_CH1OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_SET_RSVD_SHIFT)) & DCP_CH1OPTS_SET_RSVD_MASK)
+/*! @} */
+
+/*! @name CH1OPTS_CLR - DCP channel 1 options register */
+/*! @{ */
+#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH1OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_CLR_RECOVERY_TIMER_MASK)
+#define DCP_CH1OPTS_CLR_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH1OPTS_CLR_RSVD_SHIFT (16U)
+#define DCP_CH1OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_CLR_RSVD_SHIFT)) & DCP_CH1OPTS_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name CH1OPTS_TOG - DCP channel 1 options register */
+/*! @{ */
+#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH1OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH1OPTS_TOG_RECOVERY_TIMER_MASK)
+#define DCP_CH1OPTS_TOG_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH1OPTS_TOG_RSVD_SHIFT (16U)
+#define DCP_CH1OPTS_TOG_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH1OPTS_TOG_RSVD_SHIFT)) & DCP_CH1OPTS_TOG_RSVD_MASK)
+/*! @} */
+
+/*! @name CH2CMDPTR - DCP channel 2 command pointer address register */
+/*! @{ */
+#define DCP_CH2CMDPTR_ADDR_MASK (0xFFFFFFFFU)
+#define DCP_CH2CMDPTR_ADDR_SHIFT (0U)
+#define DCP_CH2CMDPTR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2CMDPTR_ADDR_SHIFT)) & DCP_CH2CMDPTR_ADDR_MASK)
+/*! @} */
+
+/*! @name CH2SEMA - DCP channel 2 semaphore register */
+/*! @{ */
+#define DCP_CH2SEMA_INCREMENT_MASK (0xFFU)
+#define DCP_CH2SEMA_INCREMENT_SHIFT (0U)
+#define DCP_CH2SEMA_INCREMENT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_INCREMENT_SHIFT)) & DCP_CH2SEMA_INCREMENT_MASK)
+#define DCP_CH2SEMA_VALUE_MASK (0xFF0000U)
+#define DCP_CH2SEMA_VALUE_SHIFT (16U)
+#define DCP_CH2SEMA_VALUE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2SEMA_VALUE_SHIFT)) & DCP_CH2SEMA_VALUE_MASK)
+/*! @} */
+
+/*! @name CH2STAT - DCP channel 2 status register */
+/*! @{ */
+#define DCP_CH2STAT_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH2STAT_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH2STAT_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_RSVD_COMPLETE_MASK)
+#define DCP_CH2STAT_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH2STAT_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH2STAT_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_HASH_MISMATCH_MASK)
+#define DCP_CH2STAT_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH2STAT_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH2STAT_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_ERROR_SETUP_MASK)
+#define DCP_CH2STAT_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH2STAT_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH2STAT_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_ERROR_PACKET_MASK)
+#define DCP_CH2STAT_ERROR_SRC_MASK (0x10U)
+#define DCP_CH2STAT_ERROR_SRC_SHIFT (4U)
+#define DCP_CH2STAT_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_SRC_SHIFT)) & DCP_CH2STAT_ERROR_SRC_MASK)
+#define DCP_CH2STAT_ERROR_DST_MASK (0x20U)
+#define DCP_CH2STAT_ERROR_DST_SHIFT (5U)
+#define DCP_CH2STAT_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_DST_SHIFT)) & DCP_CH2STAT_ERROR_DST_MASK)
+#define DCP_CH2STAT_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH2STAT_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_ERROR_PAGEFAULT_MASK)
+#define DCP_CH2STAT_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH2STAT_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error is signalled because the next pointer is 0x00000000.
+ * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
+ */
+#define DCP_CH2STAT_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_ERROR_CODE_SHIFT)) & DCP_CH2STAT_ERROR_CODE_MASK)
+#define DCP_CH2STAT_TAG_MASK (0xFF000000U)
+#define DCP_CH2STAT_TAG_SHIFT (24U)
+#define DCP_CH2STAT_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TAG_SHIFT)) & DCP_CH2STAT_TAG_MASK)
+/*! @} */
+
+/*! @name CH2STAT_SET - DCP channel 2 status register */
+/*! @{ */
+#define DCP_CH2STAT_SET_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH2STAT_SET_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_SET_RSVD_COMPLETE_MASK)
+#define DCP_CH2STAT_SET_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH2STAT_SET_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_SET_HASH_MISMATCH_MASK)
+#define DCP_CH2STAT_SET_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH2STAT_SET_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH2STAT_SET_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_SET_ERROR_SETUP_MASK)
+#define DCP_CH2STAT_SET_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH2STAT_SET_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH2STAT_SET_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_SET_ERROR_PACKET_MASK)
+#define DCP_CH2STAT_SET_ERROR_SRC_MASK (0x10U)
+#define DCP_CH2STAT_SET_ERROR_SRC_SHIFT (4U)
+#define DCP_CH2STAT_SET_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_SRC_SHIFT)) & DCP_CH2STAT_SET_ERROR_SRC_MASK)
+#define DCP_CH2STAT_SET_ERROR_DST_MASK (0x20U)
+#define DCP_CH2STAT_SET_ERROR_DST_SHIFT (5U)
+#define DCP_CH2STAT_SET_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_DST_SHIFT)) & DCP_CH2STAT_SET_ERROR_DST_MASK)
+#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH2STAT_SET_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_SET_ERROR_PAGEFAULT_MASK)
+#define DCP_CH2STAT_SET_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH2STAT_SET_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error is signalled because the next pointer is 0x00000000.
+ * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
+ */
+#define DCP_CH2STAT_SET_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_ERROR_CODE_SHIFT)) & DCP_CH2STAT_SET_ERROR_CODE_MASK)
+#define DCP_CH2STAT_SET_TAG_MASK (0xFF000000U)
+#define DCP_CH2STAT_SET_TAG_SHIFT (24U)
+#define DCP_CH2STAT_SET_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_SET_TAG_SHIFT)) & DCP_CH2STAT_SET_TAG_MASK)
+/*! @} */
+
+/*! @name CH2STAT_CLR - DCP channel 2 status register */
+/*! @{ */
+#define DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH2STAT_CLR_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_CLR_RSVD_COMPLETE_MASK)
+#define DCP_CH2STAT_CLR_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH2STAT_CLR_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_CLR_HASH_MISMATCH_MASK)
+#define DCP_CH2STAT_CLR_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH2STAT_CLR_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SETUP_MASK)
+#define DCP_CH2STAT_CLR_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH2STAT_CLR_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PACKET_MASK)
+#define DCP_CH2STAT_CLR_ERROR_SRC_MASK (0x10U)
+#define DCP_CH2STAT_CLR_ERROR_SRC_SHIFT (4U)
+#define DCP_CH2STAT_CLR_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_SRC_SHIFT)) & DCP_CH2STAT_CLR_ERROR_SRC_MASK)
+#define DCP_CH2STAT_CLR_ERROR_DST_MASK (0x20U)
+#define DCP_CH2STAT_CLR_ERROR_DST_SHIFT (5U)
+#define DCP_CH2STAT_CLR_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_DST_SHIFT)) & DCP_CH2STAT_CLR_ERROR_DST_MASK)
+#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH2STAT_CLR_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_CLR_ERROR_PAGEFAULT_MASK)
+#define DCP_CH2STAT_CLR_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH2STAT_CLR_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error is signalled because the next pointer is 0x00000000.
+ * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
+ */
+#define DCP_CH2STAT_CLR_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_ERROR_CODE_SHIFT)) & DCP_CH2STAT_CLR_ERROR_CODE_MASK)
+#define DCP_CH2STAT_CLR_TAG_MASK (0xFF000000U)
+#define DCP_CH2STAT_CLR_TAG_SHIFT (24U)
+#define DCP_CH2STAT_CLR_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_CLR_TAG_SHIFT)) & DCP_CH2STAT_CLR_TAG_MASK)
+/*! @} */
+
+/*! @name CH2STAT_TOG - DCP channel 2 status register */
+/*! @{ */
+#define DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK (0x1U)
+#define DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT (0U)
+#define DCP_CH2STAT_TOG_RSVD_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_RSVD_COMPLETE_SHIFT)) & DCP_CH2STAT_TOG_RSVD_COMPLETE_MASK)
+#define DCP_CH2STAT_TOG_HASH_MISMATCH_MASK (0x2U)
+#define DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT (1U)
+#define DCP_CH2STAT_TOG_HASH_MISMATCH(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_HASH_MISMATCH_SHIFT)) & DCP_CH2STAT_TOG_HASH_MISMATCH_MASK)
+#define DCP_CH2STAT_TOG_ERROR_SETUP_MASK (0x4U)
+#define DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT (2U)
+#define DCP_CH2STAT_TOG_ERROR_SETUP(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SETUP_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SETUP_MASK)
+#define DCP_CH2STAT_TOG_ERROR_PACKET_MASK (0x8U)
+#define DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT (3U)
+#define DCP_CH2STAT_TOG_ERROR_PACKET(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PACKET_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PACKET_MASK)
+#define DCP_CH2STAT_TOG_ERROR_SRC_MASK (0x10U)
+#define DCP_CH2STAT_TOG_ERROR_SRC_SHIFT (4U)
+#define DCP_CH2STAT_TOG_ERROR_SRC(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_SRC_SHIFT)) & DCP_CH2STAT_TOG_ERROR_SRC_MASK)
+#define DCP_CH2STAT_TOG_ERROR_DST_MASK (0x20U)
+#define DCP_CH2STAT_TOG_ERROR_DST_SHIFT (5U)
+#define DCP_CH2STAT_TOG_ERROR_DST(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_DST_SHIFT)) & DCP_CH2STAT_TOG_ERROR_DST_MASK)
+#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK (0x40U)
+#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT (6U)
+#define DCP_CH2STAT_TOG_ERROR_PAGEFAULT(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_PAGEFAULT_SHIFT)) & DCP_CH2STAT_TOG_ERROR_PAGEFAULT_MASK)
+#define DCP_CH2STAT_TOG_ERROR_CODE_MASK (0xFF0000U)
+#define DCP_CH2STAT_TOG_ERROR_CODE_SHIFT (16U)
+/*! ERROR_CODE
+ * 0b00000001..Error is signalled because the next pointer is 0x00000000.
+ * 0b00000010..Error is signalled because the semaphore is of a non-zero value and neither of the chain bits is set.
+ * 0b00000011..Error is signalled because an error was reported while reading/writing the context buffer.
+ * 0b00000100..Error is signalled because an error was reported while reading/writing the payload.
+ * 0b00000101..Error is signalled because the control packet specifies an invalid mode select (for instance, blit + hash).
+ */
+#define DCP_CH2STAT_TOG_ERROR_CODE(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_ERROR_CODE_SHIFT)) & DCP_CH2STAT_TOG_ERROR_CODE_MASK)
+#define DCP_CH2STAT_TOG_TAG_MASK (0xFF000000U)
+#define DCP_CH2STAT_TOG_TAG_SHIFT (24U)
+#define DCP_CH2STAT_TOG_TAG(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2STAT_TOG_TAG_SHIFT)) & DCP_CH2STAT_TOG_TAG_MASK)
+/*! @} */
+
+/*! @name CH2OPTS - DCP channel 2 options register */
+/*! @{ */
+#define DCP_CH2OPTS_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH2OPTS_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH2OPTS_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_RECOVERY_TIMER_MASK)
+#define DCP_CH2OPTS_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH2OPTS_RSVD_SHIFT (16U)
+#define DCP_CH2OPTS_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_RSVD_SHIFT)) & DCP_CH2OPTS_RSVD_MASK)
+/*! @} */
+
+/*! @name CH2OPTS_SET - DCP channel 2 options register */
+/*! @{ */
+#define DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH2OPTS_SET_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_SET_RECOVERY_TIMER_MASK)
+#define DCP_CH2OPTS_SET_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH2OPTS_SET_RSVD_SHIFT (16U)
+#define DCP_CH2OPTS_SET_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_SET_RSVD_SHIFT)) & DCP_CH2OPTS_SET_RSVD_MASK)
+/*! @} */
+
+/*! @name CH2OPTS_CLR - DCP channel 2 options register */
+/*! @{ */
+#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH2OPTS_CLR_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_CLR_RECOVERY_TIMER_MASK)
+#define DCP_CH2OPTS_CLR_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH2OPTS_CLR_RSVD_SHIFT (16U)
+#define DCP_CH2OPTS_CLR_RSVD(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_CLR_RSVD_SHIFT)) & DCP_CH2OPTS_CLR_RSVD_MASK)
+/*! @} */
+
+/*! @name CH2OPTS_TOG - DCP channel 2 options register */
+/*! @{ */
+#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK (0xFFFFU)
+#define DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT (0U)
+#define DCP_CH2OPTS_TOG_RECOVERY_TIMER(x) (((uint32_t)(((uint32_t)(x)) << DCP_CH2OPTS_TOG_RECOVERY_TIMER_SHIFT)) & DCP_CH2OPTS_TOG_RECOVERY_TIMER_MASK)
+#define DCP_CH2OPTS_TOG_RSVD_MASK (0xFFFF0000U)
+#define DCP_CH2OPT