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authorChris Johns <chrisj@rtems.org>2017-12-23 18:18:56 +1100
committerSebastian Huber <sebastian.huber@embedded-brains.de>2018-01-25 08:45:26 +0100
commit2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 (patch)
tree44759efe9374f13200a97e96d91bd9a2b7e5ce2a /bsps/arm/atsam/include/libchip/include/spi.h
parentMAINTAINERS: Add myself to Write After Approval. (diff)
downloadrtems-2afb22b7e1ebcbe40373ff7e0efae7d207c655a9.tar.bz2
Remove make preinstall
A speciality of the RTEMS build system was the make preinstall step. It copied header files from arbitrary locations into the build tree. The header files were included via the -Bsome/build/tree/path GCC command line option. This has at least seven problems: * The make preinstall step itself needs time and disk space. * Errors in header files show up in the build tree copy. This makes it hard for editors to open the right file to fix the error. * There is no clear relationship between source and build tree header files. This makes an audit of the build process difficult. * The visibility of all header files in the build tree makes it difficult to enforce API barriers. For example it is discouraged to use BSP-specifics in the cpukit. * An introduction of a new build system is difficult. * Include paths specified by the -B option are system headers. This may suppress warnings. * The parallel build had sporadic failures on some hosts. This patch removes the make preinstall step. All installed header files are moved to dedicated include directories in the source tree. Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc, etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g. erc32, imx, qoriq, etc. The new cpukit include directories are: * cpukit/include * cpukit/score/cpu/@RTEMS_CPU@/include * cpukit/libnetworking The new BSP include directories are: * bsps/include * bsps/@RTEMS_CPU@/include * bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include There are build tree include directories for generated files. The include directory order favours the most general header file, e.g. it is not possible to override general header files via the include path order. The "bootstrap -p" option was removed. The new "bootstrap -H" option should be used to regenerate the "headers.am" files. Update #3254.
Diffstat (limited to 'bsps/arm/atsam/include/libchip/include/spi.h')
-rw-r--r--bsps/arm/atsam/include/libchip/include/spi.h116
1 files changed, 116 insertions, 0 deletions
diff --git a/bsps/arm/atsam/include/libchip/include/spi.h b/bsps/arm/atsam/include/libchip/include/spi.h
new file mode 100644
index 0000000000..0d888fbdfa
--- /dev/null
+++ b/bsps/arm/atsam/include/libchip/include/spi.h
@@ -0,0 +1,116 @@
+/* ---------------------------------------------------------------------------- */
+/* Atmel Microcontroller Software Support */
+/* SAM Software Package License */
+/* ---------------------------------------------------------------------------- */
+/* Copyright (c) 2015, Atmel Corporation */
+/* */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following condition is met: */
+/* */
+/* - Redistributions of source code must retain the above copyright notice, */
+/* this list of conditions and the disclaimer below. */
+/* */
+/* Atmel's name may not be used to endorse or promote products derived from */
+/* this software without specific prior written permission. */
+/* */
+/* DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR */
+/* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
+/* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE */
+/* DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, */
+/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT */
+/* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, */
+/* OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
+/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING */
+/* NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ---------------------------------------------------------------------------- */
+
+/**
+ * \file
+ *
+ * Interface for Serial Peripheral Interface (SPI) controller.
+ *
+ */
+
+#ifndef _SPI_
+#define _SPI_
+
+/*----------------------------------------------------------------------------
+ * Headers
+ *----------------------------------------------------------------------------*/
+
+#include "chip.h"
+
+/*----------------------------------------------------------------------------
+ * Macros
+ *----------------------------------------------------------------------------*/
+
+/**
+ *
+ * Here are several macros which should be used when configuring a SPI
+ * peripheral.
+ *
+ * \section spi_configuration_macros SPI Configuration Macros
+ * - \ref SPI_PCS
+ * - \ref SPI_SCBR
+ * - \ref SPI_DLYBS
+ * - \ref SPI_DLYBCT
+ */
+
+/** Calculate the PCS field value given the chip select NPCS value */
+#define SPI_PCS(npcs) SPI_MR_PCS((~(1 << npcs) & 0xF))
+
+/** Calculates the value of the CSR SCBR field given the baudrate and MCK. */
+#define SPI_SCBR(baudrate, masterClock) \
+ SPI_CSR_SCBR((uint32_t)(masterClock / baudrate))
+
+/** Calculates the value of the CSR DLYBS field given the desired delay (in ns) */
+#define SPI_DLYBS(delay, masterClock) \
+ SPI_CSR_DLYBS((uint32_t) (((masterClock / 1000000) * delay) / 1000)+1)
+
+/** Calculates the value of the CSR DLYBCT field given the desired delay (in ns) */
+#define SPI_DLYBCT(delay, masterClock) \
+ SPI_CSR_DLYBCT ((uint32_t) (((masterClock / 1000000) * delay) / 32000)+1)
+
+/*------------------------------------------------------------------------------ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*----------------------------------------------------------------------------
+ * Exported functions
+ *----------------------------------------------------------------------------*/
+
+extern void SPI_Enable(Spi *spi);
+extern void SPI_Disable(Spi *spi);
+
+extern void SPI_EnableIt(Spi *spi, uint32_t dwSources);
+extern void SPI_DisableIt(Spi *spi, uint32_t dwSources);
+
+extern void SPI_Configure(Spi *spi, uint32_t dwId, uint32_t dwConfiguration);
+extern void SPI_SetMode(Spi *spi, uint32_t dwConfiguration);
+
+extern void SPI_ChipSelect(Spi *spi, uint8_t cS);
+extern void SPI_ReleaseCS(Spi *spi);
+
+extern void SPI_ConfigureNPCS(Spi *spi, uint32_t dwNpcs,
+ uint32_t dwConfiguration);
+extern void SPI_ConfigureCSMode(Spi *spi, uint32_t dwNpcs,
+ uint32_t bReleaseOnLast);
+
+extern uint32_t SPI_Read(Spi *spi);
+extern void SPI_Write(Spi *spi, uint32_t dwNpcs, uint16_t wData);
+extern void SPI_WriteLast(Spi *spi, uint32_t dwNpcs, uint16_t wData);
+
+extern uint32_t SPI_GetStatus(Spi *spi);
+extern uint32_t SPI_IsFinished(Spi *pSpi);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* #ifndef _SPI_ */
+