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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-01-23 15:48:48 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2023-01-24 09:56:53 +0100 |
| commit | d36070fec8758a745a0b33f1ffa9f8192fceec51 (patch) | |
| tree | 1fc77b95d0588a6288dae6f2869fce3443a88221 /bsps/arm/altera-cyclone-v | |
| parent | cpuuse: Use standard wording and group name (diff) | |
| download | rtems-d36070fec8758a745a0b33f1ffa9f8192fceec51.tar.bz2 | |
intr: Add Interrupt Manager implementation group
The shared BSP interrupt controller support code actually implements
parts of the Interrupt Manager.
Update #3706.
Diffstat (limited to 'bsps/arm/altera-cyclone-v')
| -rw-r--r-- | bsps/arm/altera-cyclone-v/include/bsp/irq.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/irq.h b/bsps/arm/altera-cyclone-v/include/bsp/irq.h index 15d05ec632..d06bfa92f0 100644 --- a/bsps/arm/altera-cyclone-v/include/bsp/irq.h +++ b/bsps/arm/altera-cyclone-v/include/bsp/irq.h @@ -52,7 +52,7 @@ extern "C" { * * @ingroup RTEMSBSPsARMCycV * - * @ingroup bsp_interrupt + * @ingroup RTEMSImplClassicIntr * * @brief Intel Cyclone V Interrupt Support. * |