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author | Chris Johns <chrisj@rtems.org> | 2017-12-23 18:18:56 +1100 |
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committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-01-25 08:45:26 +0100 |
commit | 2afb22b7e1ebcbe40373ff7e0efae7d207c655a9 (patch) | |
tree | 44759efe9374f13200a97e96d91bd9a2b7e5ce2a /bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h | |
parent | MAINTAINERS: Add myself to Write After Approval. (diff) | |
download | rtems-2afb22b7e1ebcbe40373ff7e0efae7d207c655a9.tar.bz2 |
Remove make preinstall
A speciality of the RTEMS build system was the make preinstall step. It
copied header files from arbitrary locations into the build tree. The
header files were included via the -Bsome/build/tree/path GCC command
line option.
This has at least seven problems:
* The make preinstall step itself needs time and disk space.
* Errors in header files show up in the build tree copy. This makes it
hard for editors to open the right file to fix the error.
* There is no clear relationship between source and build tree header
files. This makes an audit of the build process difficult.
* The visibility of all header files in the build tree makes it
difficult to enforce API barriers. For example it is discouraged to
use BSP-specifics in the cpukit.
* An introduction of a new build system is difficult.
* Include paths specified by the -B option are system headers. This
may suppress warnings.
* The parallel build had sporadic failures on some hosts.
This patch removes the make preinstall step. All installed header
files are moved to dedicated include directories in the source tree.
Let @RTEMS_CPU@ be the target architecture, e.g. arm, powerpc, sparc,
etc. Let @RTEMS_BSP_FAMILIY@ be a BSP family base directory, e.g.
erc32, imx, qoriq, etc.
The new cpukit include directories are:
* cpukit/include
* cpukit/score/cpu/@RTEMS_CPU@/include
* cpukit/libnetworking
The new BSP include directories are:
* bsps/include
* bsps/@RTEMS_CPU@/include
* bsps/@RTEMS_CPU@/@RTEMS_BSP_FAMILIY@/include
There are build tree include directories for generated files.
The include directory order favours the most general header file, e.g.
it is not possible to override general header files via the include path
order.
The "bootstrap -p" option was removed. The new "bootstrap -H" option
should be used to regenerate the "headers.am" files.
Update #3254.
Diffstat (limited to 'bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h')
-rw-r--r-- | bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h | 114 |
1 files changed, 114 insertions, 0 deletions
diff --git a/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h new file mode 100644 index 0000000000..a43608e9f3 --- /dev/null +++ b/bsps/arm/altera-cyclone-v/include/bsp/alt_clock_group.h @@ -0,0 +1,114 @@ +/****************************************************************************** + * + * Copyright 2013 Altera Corporation. All Rights Reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are met: + * + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * + * 3. The name of the author may not be used to endorse or promote products + * derived from this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDER "AS IS" AND ANY EXPRESS OR + * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE, ARE DISCLAIMED. IN NO + * EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT + * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING + * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY + * OF SUCH DAMAGE. + * + ******************************************************************************/ + +/*! + * \file + * + * Contains the definition of an opaque data structure that contains raw + * configuration information for a clock group. + */ + +#ifndef __ALT_CLK_GRP_H__ +#define __ALT_CLK_GRP_H__ + +#include "hwlib.h" +#include "socal/alt_clkmgr.h" + +#ifdef __cplusplus +extern "C" +{ +#endif /* __cplusplus */ + +/*! + * This type definition enumerates the clock groups + */ +typedef enum ALT_CLK_GRP_e +{ + ALT_MAIN_PLL_CLK_GRP, /*!< Main PLL clock group */ + + ALT_PERIPH_PLL_CLK_GRP, /*!< Peripheral PLL clock group */ + + ALT_SDRAM_PLL_CLK_GRP /*!< SDRAM PLL clock group */ + +} ALT_CLK_GRP_t; + +/*! + * This type definition defines an opaque data structure for holding the + * configuration settings for a complete clock group. + */ +typedef struct ALT_CLK_GROUP_RAW_CFG_s +{ + uint32_t verid; /*!< SoC FPGA version identifier. This field + * encapsulates the silicon identifier and + * version information associated with this + * clock group configuration. It is used to + * assert that this clock group configuration + * is valid for this device. */ + + uint32_t siliid2; /*!< Reserved register - reserved for future + * device IDs or capability flags. */ + + ALT_CLK_GRP_t clkgrpsel; /*!< Clock group union discriminator. */ + + /*! + * This union holds the register values for configuration of the set of + * possible clock groups on the SoC FPGA. The \e clkgrpsel discriminator + * identifies the valid clock group union data member. + */ + union ALT_CLK_GROUP_RAW_CFG_u + { + /*! Clock group configuration for Main PLL group. */ + union + { + ALT_CLKMGR_MAINPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_MAINPLL_raw_t raw; /*!< Raw access. */ + } mainpllgrp; + + /*! Clock group configuration for Peripheral PLL group. */ + union + { + ALT_CLKMGR_PERPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_PERPLL_raw_t raw; /*!< Raw access. */ + } perpllgrp; + + /*! Clock group configuration for SDRAM PLL group. */ + union + { + ALT_CLKMGR_SDRPLL_t fld; /*!< Field access. */ + ALT_CLKMGR_SDRPLL_raw_t raw; /*!< Raw access. */ + } sdrpllgrp; + + } clkgrp; +} ALT_CLK_GROUP_RAW_CFG_t; + +#ifdef __cplusplus +} +#endif /* __cplusplus */ +#endif /* __ALT_CLK_GRP_H__ */ |