diff options
| author | Kinsey Moore <kinsey.moore@oarcorp.com> | 2022-07-14 18:10:45 -0500 |
|---|---|---|
| committer | Joel Sherrill <joel@rtems.org> | 2022-07-21 12:26:35 -0500 |
| commit | 10ef7087f62bb83b36e8d9fc98e89e8f81d33fb9 (patch) | |
| tree | 44c96108608c504b8c31b46da15394f9e1e55790 /bsps/aarch64/shared | |
| parent | Support _REENT_THREAD_LOCAL Newlib configuration (diff) | |
| download | rtems-10ef7087f62bb83b36e8d9fc98e89e8f81d33fb9.tar.bz2 | |
aarch64: Use page table level 0
This alters the AArch64 page table generation and mapping code and MMU
configuration to use page table level 0 in addition to levels 1, 2, and
3. This allows the mapping of up to 48 bits of memory space and is the
maximum that can be mapped without relying on additional processor
extensions. Mappings are restricted based on the number of physical
address bits that the CPU supports.
Diffstat (limited to 'bsps/aarch64/shared')
| -rw-r--r-- | bsps/aarch64/shared/mmu/vmsav8-64.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/bsps/aarch64/shared/mmu/vmsav8-64.c b/bsps/aarch64/shared/mmu/vmsav8-64.c index 9caa91c414..190a05f7d5 100644 --- a/bsps/aarch64/shared/mmu/vmsav8-64.c +++ b/bsps/aarch64/shared/mmu/vmsav8-64.c @@ -47,6 +47,11 @@ rtems_status_code aarch64_mmu_map( ) { rtems_status_code sc; + uint64_t max_mappable = 1LLU << aarch64_mmu_get_cpu_pa_bits(); + + if ( addr >= max_mappable || (addr + size) > max_mappable ) { + return RTEMS_INVALID_ADDRESS; + } aarch64_mmu_disable(); sc = aarch64_mmu_map_block( @@ -54,7 +59,7 @@ rtems_status_code aarch64_mmu_map( 0x0, addr, size, - 0, + -1, flags ); _AARCH64_Data_synchronization_barrier(); |