From 8714684129e69b6bec7ca56b4e4243854208a976 Mon Sep 17 00:00:00 2001 From: Pavel Pisa Date: Tue, 4 Oct 2016 23:30:22 +0200 Subject: score/arm: Correct logic to select 64 byte cache line maximum size for Cortex-A. The use of actual cache line max bytes and minimum required alignment in architecture but not-BSP dependent code could be problematic because there exists even ARM instruction set implementations with 128 byte line length and real maximum can be quite problematic to say. But actually supported ARM BSPs should be OK with these values. --- cpukit/score/cpu/arm/rtems/score/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h index 9fe28c4a3f..4cdca73838 100644 --- a/cpukit/score/cpu/arm/rtems/score/cpu.h +++ b/cpukit/score/cpu/arm/rtems/score/cpu.h @@ -146,9 +146,9 @@ #define CPU_STACK_GROWS_UP FALSE #if defined(ARM_MULTILIB_CACHE_LINE_MAX_64) - #define CPU_CACHE_LINE_BYTES 32 -#else #define CPU_CACHE_LINE_BYTES 64 +#else + #define CPU_CACHE_LINE_BYTES 32 #endif #define CPU_STRUCTURE_ALIGNMENT RTEMS_ALIGNED( CPU_CACHE_LINE_BYTES ) -- cgit v1.2.3