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authorChris Johns <chrisj@rtems.org>2013-12-10 13:41:16 +1100
committerChris Johns <chrisj@rtems.org>2013-12-10 13:41:16 +1100
commit6e4255d9a5b32fcf4e665eb908a2091f327ab1d3 (patch)
tree3439cd3acbe7d58ee5a5d4a138175f213bc85797
parent37df7150802a147b30716189ce4024757dd9d77f (diff)
downloadrtems-6e4255d9a5b32fcf4e665eb908a2091f327ab1d3.tar.bz2
arm/xilinx__zynq: Support application based clock freq.
Provide a weak call to a clock freq routine to allow the application to supply the freq defined in the Xilinx generated source. Add code to calculate the baud rate.
-rw-r--r--c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c112
1 files changed, 110 insertions, 2 deletions
diff --git a/c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c b/c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c
index 1ac7352161..cf47f04ed2 100644
--- a/c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c
+++ b/c/src/lib/libbsp/arm/xilinx-zynq/console/zynq-uart.c
@@ -25,10 +25,100 @@ static volatile zynq_uart *zynq_uart_get_regs(int minor)
return (volatile zynq_uart *) ct->ulCtrlPort1;
}
+/*
+ * Make weak and let the user override.
+ */
+uint32_t zynq_uart_input_clock(void) __attribute__ ((weak));
+
+uint32_t zynq_uart_input_clock(void)
+{
+ return 100000000UL;
+}
+
+static int zynq_cal_baud_rate(uint32_t baudrate,
+ uint32_t* brgr,
+ uint32_t* bauddiv,
+ uint32_t modereg)
+{
+ uint32_t brgr_value; /* Calculated value for baud rate generator */
+ uint32_t calcbaudrate; /* Calculated baud rate */
+ uint32_t bauderror; /* Diff between calculated and requested baud rate */
+ uint32_t best_error = 0xFFFFFFFF;
+ uint32_t percenterror;
+ uint32_t bdiv;
+ uint32_t inputclk = zynq_uart_input_clock();
+
+ /*
+ * Make sure the baud rate is not impossilby large.
+ * Fastest possible baud rate is Input Clock / 2.
+ */
+ if ((baudrate * 2) > inputclk) {
+ return -1;
+ }
+ /*
+ * Check whether the input clock is divided by 8
+ */
+ if(modereg & ZYNQ_UART_MODE_CLKS) {
+ inputclk = inputclk / 8;
+ }
+
+ /*
+ * Determine the Baud divider. It can be 4to 254.
+ * Loop through all possible combinations
+ */
+ for (bdiv = 4; bdiv < 255; bdiv++) {
+
+ /*
+ * Calculate the value for BRGR register
+ */
+ brgr_value = inputclk / (baudrate * (bdiv + 1));
+
+ /*
+ * Calculate the baud rate from the BRGR value
+ */
+ calcbaudrate = inputclk/ (brgr_value * (bdiv + 1));
+
+ /*
+ * Avoid unsigned integer underflow
+ */
+ if (baudrate > calcbaudrate) {
+ bauderror = baudrate - calcbaudrate;
+ }
+ else {
+ bauderror = calcbaudrate - baudrate;
+ }
+
+ /*
+ * Find the calculated baud rate closest to requested baud rate.
+ */
+ if (best_error > bauderror) {
+ *brgr = brgr_value;
+ *bauddiv = bdiv;
+ best_error = bauderror;
+ }
+ }
+
+ /*
+ * Make sure the best error is not too large.
+ */
+ percenterror = (best_error * 100) / baudrate;
+#define XUARTPS_MAX_BAUD_ERROR_RATE 3 /* max % error allowed */
+ if (XUARTPS_MAX_BAUD_ERROR_RATE < percenterror) {
+ return -1;
+ }
+
+ return 0;
+}
+
static void zynq_uart_initialize(int minor)
{
volatile zynq_uart *regs = zynq_uart_get_regs(minor);
+ uint32_t brgr = 0x3e;
+ uint32_t bauddiv = 0x6;
+ zynq_cal_baud_rate(115200, &brgr, &bauddiv, regs->mode);
+
+ regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
regs->control = ZYNQ_UART_CONTROL_RXDIS
| ZYNQ_UART_CONTROL_TXDIS
| ZYNQ_UART_CONTROL_RXRES
@@ -36,8 +126,8 @@ static void zynq_uart_initialize(int minor)
regs->mode = ZYNQ_UART_MODE_CHMODE(ZYNQ_UART_MODE_CHMODE_NORMAL)
| ZYNQ_UART_MODE_PAR(ZYNQ_UART_MODE_PAR_NONE)
| ZYNQ_UART_MODE_CHRL(ZYNQ_UART_MODE_CHRL_8);
- regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(0x3e);
- regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(0x6);
+ regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
+ regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
regs->rx_fifo_trg_lvl = ZYNQ_UART_RX_FIFO_TRG_LVL_RTRIG(0);
regs->rx_timeout = ZYNQ_UART_RX_TIMEOUT_RTO(0);
regs->control = ZYNQ_UART_CONTROL_RXEN
@@ -102,7 +192,25 @@ static ssize_t zynq_uart_write_support_polled(
static int zynq_uart_set_attribues(int minor, const struct termios *term)
{
+#if 0
+ volatile zynq_uart *regs = zynq_uart_get_regs(minor);
+ uint32_t brgr = 0;
+ uint32_t bauddiv = 0;
+ int rc;
+
+ rc = zynq_cal_baud_rate(115200, &brgr, &bauddiv, regs->mode);
+ if (rc != 0)
+ return rc;
+
+ regs->control &= ~(ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN);
+ regs->baud_rate_gen = ZYNQ_UART_BAUD_RATE_GEN_CD(brgr);
+ regs->baud_rate_div = ZYNQ_UART_BAUD_RATE_DIV_BDIV(bauddiv);
+ regs->control |= ZYNQ_UART_CONTROL_RXEN | ZYNQ_UART_CONTROL_TXEN;
+
+ return 0;
+#else
return -1;
+#endif
}
const console_fns zynq_uart_fns = {