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/**
* @file
*
* @brief LM32 CPU Dependent Source
*/
/*
* COPYRIGHT (c) 1989-1999.
* On-Line Applications Research Corporation (OAR).
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rtems.org/license/LICENSE.
*
* Jukka Pietarinen <jukka.pietarinen@mrf.fi>, 2008,
* Micro-Research Finland Oy
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/score/cpuimpl.h>
#include <rtems/score/isr.h>
/* _CPU_Initialize
*
* This routine performs processor dependent initialization.
*
* INPUT PARAMETERS: NONE
*
* LM32 Specific Information:
*
* XXX document implementation including references if appropriate
*/
void _CPU_Initialize(void)
{
/*
* If there is not an easy way to initialize the FP context
* during Context_Initialize, then it is usually easier to
* save an "uninitialized" FP context here and copy it to
* the task's during Context_Initialize.
*/
/* FP context initialization support goes here */
}
void _CPU_Fatal_halt( uint32_t source, CPU_Uint32ptr error )
{
ISR_Level level;
_CPU_ISR_Disable( level );
(void) level;
while ( true ) {
/* Do nothing */
}
}
uint32_t _CPU_ISR_Get_level( void )
{
/*
* This routine returns the current interrupt level.
*/
return 0;
}
void _CPU_ISR_install_vector(
uint32_t vector,
CPU_ISR_handler new_handler,
CPU_ISR_handler *old_handler
)
{
*old_handler = _ISR_Vector_table[ vector ];
/*
* We put the actual user ISR address in '_ISR_vector_table'. This will
* be used by the _ISR_Handler so the user gets control.
*/
_ISR_Vector_table[ vector ] = new_handler;
}
/*
* _CPU_Thread_Idle_body
*
* NOTES:
*
* 1. This is the same as the regular CPU independent algorithm.
*
* 2. If you implement this using a "halt", "idle", or "shutdown"
* instruction, then don't forget to put it in an infinite loop.
*
* 3. Be warned. Some processors with onboard DMA have been known
* to stop the DMA if the CPU were put in IDLE mode. This might
* also be a problem with other on-chip peripherals. So use this
* hook with caution.
*
* LM32 Specific Information:
*
* XXX document implementation including references if appropriate
*/
void *_CPU_Thread_Idle_body( uintptr_t ignored )
{
for( ; ; ) {
/* The LM32 softcore itself hasn't any HLT instruction. But the
* LM32 qemu target interprets this nop instruction as HLT.
*/
__asm__ volatile("and r0, r0, r0");
}
}
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