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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-01-20 11:04:39 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-01-21 15:00:21 +0100 |
| commit | 5071600b2172b5d37c1f5608f1c623143c651058 (patch) | |
| tree | c22af1661c5e43e3a0355ffb0b67b2d04899c002 /rtemsbsd/include/machine | |
| parent | zy7_slcr: Import from FreeBSD (diff) | |
| download | rtems-libbsd-5071600b2172b5d37c1f5608f1c623143c651058.tar.bz2 | |
Add Xilinx Zynq BSP support
Diffstat (limited to 'rtemsbsd/include/machine')
| -rw-r--r-- | rtemsbsd/include/machine/rtems-bsd-cache.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/rtemsbsd/include/machine/rtems-bsd-cache.h b/rtemsbsd/include/machine/rtems-bsd-cache.h index 77cc0794..838f730b 100644 --- a/rtemsbsd/include/machine/rtems-bsd-cache.h +++ b/rtemsbsd/include/machine/rtems-bsd-cache.h @@ -27,6 +27,9 @@ #if defined(LIBBSP_ARM_LPC24XX_BSP_H) /* No cache */ +#elif defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) + /* With cache, no coherency support in hardware */ + #define CPU_DATA_CACHE_ALIGNMENT 32 #elif defined(LIBBSP_ARM_LPC32XX_BSP_H) /* With cache, no coherency support in hardware */ #include <libcpu/cache.h> |