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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-03-26 15:39:18 +0100 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2015-04-01 09:15:30 +0200 |
| commit | aee6864330998a6952c4a4dad6a5395089df1613 (patch) | |
| tree | 9393a51dd919c0ef7be5f9997e04a72262706980 /rtemsbsd/include/machine/rtems-bsd-cache.h | |
| parent | if_dwc: Checksum offload (diff) | |
| download | rtems-libbsd-aee6864330998a6952c4a4dad6a5395089df1613.tar.bz2 | |
if_dwc: Add Altera Cyclone V support
Diffstat (limited to 'rtemsbsd/include/machine/rtems-bsd-cache.h')
| -rw-r--r-- | rtemsbsd/include/machine/rtems-bsd-cache.h | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/rtemsbsd/include/machine/rtems-bsd-cache.h b/rtemsbsd/include/machine/rtems-bsd-cache.h index e809eaae..b8c4ce7e 100644 --- a/rtemsbsd/include/machine/rtems-bsd-cache.h +++ b/rtemsbsd/include/machine/rtems-bsd-cache.h @@ -44,7 +44,8 @@ #if defined(LIBBSP_ARM_LPC24XX_BSP_H) /* No cache */ -#elif defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) +#elif defined(LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H) || \ + defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) /* With cache, no coherency support in hardware */ #define CPU_DATA_CACHE_ALIGNMENT 32 #elif defined(LIBBSP_ARM_LPC32XX_BSP_H) |