From aee6864330998a6952c4a4dad6a5395089df1613 Mon Sep 17 00:00:00 2001 From: Sebastian Huber Date: Thu, 26 Mar 2015 15:39:18 +0100 Subject: if_dwc: Add Altera Cyclone V support --- rtemsbsd/include/machine/rtems-bsd-cache.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'rtemsbsd/include/machine/rtems-bsd-cache.h') diff --git a/rtemsbsd/include/machine/rtems-bsd-cache.h b/rtemsbsd/include/machine/rtems-bsd-cache.h index e809eaae..b8c4ce7e 100644 --- a/rtemsbsd/include/machine/rtems-bsd-cache.h +++ b/rtemsbsd/include/machine/rtems-bsd-cache.h @@ -44,7 +44,8 @@ #if defined(LIBBSP_ARM_LPC24XX_BSP_H) /* No cache */ -#elif defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) +#elif defined(LIBBSP_ARM_ALTERA_CYCLONE_V_BSP_H) || \ + defined(LIBBSP_ARM_XILINX_ZYNQ_BSP_H) /* With cache, no coherency support in hardware */ #define CPU_DATA_CACHE_ALIGNMENT 32 #elif defined(LIBBSP_ARM_LPC32XX_BSP_H) -- cgit v1.2.3