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authorJoel Sherrill <joel@rtems.org>2018-08-09 08:42:28 -0500
committerJoel Sherrill <joel@rtems.org>2018-08-09 08:42:28 -0500
commit135b90cb1be69a5dadb062b734e4c739bba385a2 (patch)
treec45174411f75c937a6d2a8be470be1f8cc8711fb /cpu-supplement
parent806806cdcf7ecd98bdcbd07378106e40376fc0ae (diff)
downloadrtems-docs-135b90cb1be69a5dadb062b734e4c739bba385a2.tar.bz2
Fix SPARC_SWTRAP_IRQDIS typo
close #3493.
Diffstat (limited to 'cpu-supplement')
-rw-r--r--cpu-supplement/sparc.rst2
1 files changed, 1 insertions, 1 deletions
diff --git a/cpu-supplement/sparc.rst b/cpu-supplement/sparc.rst
index e0f5240..57b6062 100644
--- a/cpu-supplement/sparc.rst
+++ b/cpu-supplement/sparc.rst
@@ -641,7 +641,7 @@ as non-maskable interrupts.
Interrupts are disabled or enabled by performing a system call to the Operating
System reserved software traps 9 (SPARC_SWTRAP_IRQDIS) or 10
-(SPARC_SWTRAP_IRQDIS). The trap is generated by the software trap (Ticc)
+(SPARC_SWTRAP_IRQEN). The trap is generated by the software trap (Ticc)
instruction or indirectly by calling sparc_disable_interrupts() or
sparc_enable_interrupts() functions. Disabling interrupts return the previous
interrupt level (on trap entry) in register G1 and sets PSR.PIL to 15 to