Fix C formatting with indent

1 files changed, 1217 insertions, 1043 deletions

diff --git a/erc32.c b/erc32.c
index 190941e..3a7899d 100644
--- a/erc32.c
+++ b/erc32.c
@@ -131,77 +131,78 @@
 
 /* MEC registers */
 
-static char     fname[256];
-static uint32   mec_ssa[2];	/* Write protection start address */
-static uint32   mec_sea[2];	/* Write protection end address */
-static uint32   mec_wpr[2];	/* Write protection control fields */
-static uint32   mec_sfsr;
-static uint32   mec_ffar;
-static uint32   mec_ipr;
-static uint32   mec_imr;
-static uint32   mec_isr;
-static uint32   mec_icr;
-static uint32   mec_ifr;
-static uint32   mec_mcr;	/* MEC control register */
-static uint32   mec_memcfg;	/* Memory control register */
-static uint32   mec_wcr;	/* MEC waitstate register */
-static uint32   mec_iocr;	/* MEC IO control register */
-static uint32   posted_irq;
-static uint32   mec_ersr;	/* MEC error and status register */
-static uint32   mec_tcr;	/* MEC test comtrol register */
-
-static uint32   rtc_counter;
-static uint32   rtc_reload;
-static uint32   rtc_scaler;
-static uint32   rtc_scaler_start;
-static uint32   rtc_enabled;
-static uint32   rtc_cr;
-static uint32   rtc_se;
-
-static uint32   gpt_counter;
-static uint32   gpt_reload;
-static uint32   gpt_scaler;
-static uint32   gpt_scaler_start;
-static uint32   gpt_enabled;
-static uint32   gpt_cr;
-static uint32   gpt_se;
-
-static uint32   wdog_scaler;
-static uint32   wdog_counter;
-static uint32   wdog_rst_delay;
-static uint32   wdog_rston;
-
-enum wdog_type {
-    init, disabled, enabled, stopped
+static char fname[256];
+static uint32 mec_ssa[2];	/* Write protection start address */
+static uint32 mec_sea[2];	/* Write protection end address */
+static uint32 mec_wpr[2];	/* Write protection control fields */
+static uint32 mec_sfsr;
+static uint32 mec_ffar;
+static uint32 mec_ipr;
+static uint32 mec_imr;
+static uint32 mec_isr;
+static uint32 mec_icr;
+static uint32 mec_ifr;
+static uint32 mec_mcr;		/* MEC control register */
+static uint32 mec_memcfg;	/* Memory control register */
+static uint32 mec_wcr;		/* MEC waitstate register */
+static uint32 mec_iocr;		/* MEC IO control register */
+static uint32 posted_irq;
+static uint32 mec_ersr;		/* MEC error and status register */
+static uint32 mec_tcr;		/* MEC test comtrol register */
+
+static uint32 rtc_counter;
+static uint32 rtc_reload;
+static uint32 rtc_scaler;
+static uint32 rtc_scaler_start;
+static uint32 rtc_enabled;
+static uint32 rtc_cr;
+static uint32 rtc_se;
+
+static uint32 gpt_counter;
+static uint32 gpt_reload;
+static uint32 gpt_scaler;
+static uint32 gpt_scaler_start;
+static uint32 gpt_enabled;
+static uint32 gpt_cr;
+static uint32 gpt_se;
+
+static uint32 wdog_scaler;
+static uint32 wdog_counter;
+static uint32 wdog_rst_delay;
+static uint32 wdog_rston;
+
+enum wdog_type
+{
+  init, disabled, enabled, stopped
 };
 
 static enum wdog_type wdog_status;
 
 /* Memory support variables */
 
-static uint32   mem_ramr_ws;	/* RAM read waitstates */
-static uint32   mem_ramw_ws;	/* RAM write waitstates */
-static uint32   mem_romr_ws;	/* ROM read waitstates */
-static uint32   mem_romw_ws;	/* ROM write waitstates */
-static uint32	mem_ramstart;	/* RAM start */
-static uint32	mem_ramend;	/* RAM end */
-static uint32	mem_rammask;	/* RAM address mask */
-static uint32   mem_ramsz;	/* RAM size */
-static uint32   mem_romsz;	/* ROM size */
-static uint32   mem_accprot;	/* RAM write protection enabled */
-static uint32   mem_blockprot;	/* RAM block write protection enabled */
+static uint32 mem_ramr_ws;	/* RAM read waitstates */
+static uint32 mem_ramw_ws;	/* RAM write waitstates */
+static uint32 mem_romr_ws;	/* ROM read waitstates */
+static uint32 mem_romw_ws;	/* ROM write waitstates */
+static uint32 mem_ramstart;	/* RAM start */
+static uint32 mem_ramend;	/* RAM end */
+static uint32 mem_rammask;	/* RAM address mask */
+static uint32 mem_ramsz;	/* RAM size */
+static uint32 mem_romsz;	/* ROM size */
+static uint32 mem_accprot;	/* RAM write protection enabled */
+static uint32 mem_blockprot;	/* RAM block write protection enabled */
 
 /* UART support variables */
 
-static int32    fd1, fd2;	/* file descriptor for input file */
-static int32    Ucontrol;	/* UART status register */
+static int32 fd1, fd2;		/* file descriptor for input file */
+static int32 Ucontrol;		/* UART status register */
 static unsigned char aq[UARTBUF], bq[UARTBUF];
-static int32    anum, aind = 0;
-static int32    bnum, bind = 0;
-static char     wbufa[UARTBUF], wbufb[UARTBUF];
+static int32 anum, aind = 0;
+static int32 bnum, bind = 0;
+static char wbufa[UARTBUF], wbufb[UARTBUF];
 static unsigned wnuma;
 static unsigned wnumb;
-static FILE    *f1in, *f1out, *f2in, *f2out;
+static FILE *f1in, *f1out, *f2in, *f2out;
 #ifdef HAVE_TERMIOS_H
 static struct termios ioc1, ioc2, iocold1, iocold2;
 #endif
@@ -209,669 +210,726 @@ static struct termios ioc1, ioc2, iocold1, iocold2;
 #define O_NONBLOCK 0
 #endif
 
-static int      f1open = 0, f2open = 0;
+static int f1open = 0, f2open = 0;
 
-static char     uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
-static uint32   uart_stat_reg;
-static uint32   uarta_data, uartb_data;
+static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
+static uint32 uart_stat_reg;
+static uint32 uarta_data, uartb_data;
 
 /* Forward declarations */
 
-static void	decode_ersr (void);
-static void	mecparerror (void);
-static void	decode_memcfg (void);
-static void	decode_wcr (void);
-static void	decode_mcr (void);
-static void	close_port (void);
-static void	mec_reset (void);
-static void	mec_intack (int32 level);
-static void	chk_irq (void);
-static void	mec_irq (int32 level);
-static void	set_sfsr (uint32 fault, uint32 addr,
-			  uint32 asi, uint32 read);
-static int32	mec_read (uint32 addr, uint32 asi, uint32 *data);
-static int	mec_write (uint32 addr, uint32 data);
-static void	port_init (void);
-static uint32	read_uart (uint32 addr);
-static void	write_uart (uint32 addr, uint32 data);
-static void	flush_uart (void);
-static void	uarta_tx (void);
-static void	uartb_tx (void);
-static void	uart_rx (int32 arg);
-static void	uart_intr (int32 arg);
-static void	uart_irq_start (void);
-static void	wdog_intr (int32 arg);
-static void	wdog_start (void);
-static void	rtc_intr (int32 arg);
-static void	rtc_start (void);
-static uint32	rtc_counter_read (void);
-static void	rtc_scaler_set (uint32 val);
-static void	rtc_reload_set (uint32 val);
-static void	gpt_intr (int32 arg);
-static void	gpt_start (void);
-static uint32	gpt_counter_read (void);
-static void	gpt_scaler_set (uint32 val);
-static void	gpt_reload_set (uint32 val);
-static void	timer_ctrl (uint32 val);
-static char	*get_mem_ptr (uint32 addr, uint32 size);
-static void	store_bytes (char *mem, uint32 waddr,
-			uint32 *data, int sz, int32 *ws);
+static void decode_ersr (void);
+static void mecparerror (void);
+static void decode_memcfg (void);
+static void decode_wcr (void);
+static void decode_mcr (void);
+static void close_port (void);
+static void mec_reset (void);
+static void mec_intack (int32 level);
+static void chk_irq (void);
+static void mec_irq (int32 level);
+static void set_sfsr (uint32 fault, uint32 addr, uint32 asi, uint32 read);
+static int32 mec_read (uint32 addr, uint32 asi, uint32 * data);
+static int mec_write (uint32 addr, uint32 data);
+static void port_init (void);
+static uint32 read_uart (uint32 addr);
+static void write_uart (uint32 addr, uint32 data);
+static void flush_uart (void);
+static void uarta_tx (void);
+static void uartb_tx (void);
+static void uart_rx (int32 arg);
+static void uart_intr (int32 arg);
+static void uart_irq_start (void);
+static void wdog_intr (int32 arg);
+static void wdog_start (void);
+static void rtc_intr (int32 arg);
+static void rtc_start (void);
+static uint32 rtc_counter_read (void);
+static void rtc_scaler_set (uint32 val);
+static void rtc_reload_set (uint32 val);
+static void gpt_intr (int32 arg);
+static void gpt_start (void);
+static uint32 gpt_counter_read (void);
+static void gpt_scaler_set (uint32 val);
+static void gpt_reload_set (uint32 val);
+static void timer_ctrl (uint32 val);
+static char *get_mem_ptr (uint32 addr, uint32 size);
+static void store_bytes (char *mem, uint32 waddr,
+			 uint32 * data, int sz, int32 * ws);
 
 /* One-time init */
 
 static void
-init_sim()
+init_sim ()
 {
-    port_init();
-    ebase.ramstart = RAM_START;
+  port_init ();
+  ebase.ramstart = RAM_START;
 }
 
 /* Power-on reset init */
 
 static void
-reset()
+reset ()
 {
-    mec_reset();
-    uart_irq_start();
-    wdog_start();
-    sregs[0].intack = mec_intack;
+  mec_reset ();
+  uart_irq_start ();
+  wdog_start ();
+  sregs[0].intack = mec_intack;
 }
 
 static void
-decode_ersr()
+decode_ersr ()
 {
-    if (mec_ersr & 0x01) {
-	if (!(mec_mcr & 0x20)) {
-	    if (mec_mcr & 0x40) {
-	        sys_reset();
-	        mec_ersr = 0x8000;
-	        if (sis_verbose)
-	            printf("Error manager reset - IU in error mode\n");
-	    } else {
-	        sys_halt();
-	        mec_ersr |= 0x2000;
-	        if (sis_verbose)
-	            printf("Error manager halt - IU in error mode\n");
+  if (mec_ersr & 0x01)
+    {
+      if (!(mec_mcr & 0x20))
+	{
+	  if (mec_mcr & 0x40)
+	    {
+	      sys_reset ();
+	      mec_ersr = 0x8000;
+	      if (sis_verbose)
+		printf ("Error manager reset - IU in error mode\n");
+	    }
+	  else
+	    {
+	      sys_halt ();
+	      mec_ersr |= 0x2000;
+	      if (sis_verbose)
+		printf ("Error manager halt - IU in error mode\n");
 	    }
-	} else
-	    mec_irq(1);
+	}
+      else
+	mec_irq (1);
     }
-    if (mec_ersr & 0x04) {
-	if (!(mec_mcr & 0x200)) {
-	    if (mec_mcr & 0x400) {
-	        sys_reset();
-	        mec_ersr = 0x8000;
-	        if (sis_verbose)
-	            printf("Error manager reset - IU comparison error\n");
-	    } else {
-	        sys_halt();
-	        mec_ersr |= 0x2000;
-	        if (sis_verbose)
-	            printf("Error manager halt - IU comparison error\n");
+  if (mec_ersr & 0x04)
+    {
+      if (!(mec_mcr & 0x200))
+	{
+	  if (mec_mcr & 0x400)
+	    {
+	      sys_reset ();
+	      mec_ersr = 0x8000;
+	      if (sis_verbose)
+		printf ("Error manager reset - IU comparison error\n");
+	    }
+	  else
+	    {
+	      sys_halt ();
+	      mec_ersr |= 0x2000;
+	      if (sis_verbose)
+		printf ("Error manager halt - IU comparison error\n");
 	    }
-	} else
-	    mec_irq(1);
+	}
+      else
+	mec_irq (1);
     }
-    if (mec_ersr & 0x20) { 
-	if (!(mec_mcr & 0x2000)) {
-	    if (mec_mcr & 0x4000) {
-	        sys_reset();
-	        mec_ersr = 0x8000;
-	        if (sis_verbose)
-	            printf("Error manager reset - MEC hardware error\n");
-	    } else {
-	        sys_halt();
-	        mec_ersr |= 0x2000;
-	        if (sis_verbose)
-	            printf("Error manager halt - MEC hardware error\n");
+  if (mec_ersr & 0x20)
+    {
+      if (!(mec_mcr & 0x2000))
+	{
+	  if (mec_mcr & 0x4000)
+	    {
+	      sys_reset ();
+	      mec_ersr = 0x8000;
+	      if (sis_verbose)
+		printf ("Error manager reset - MEC hardware error\n");
+	    }
+	  else
+	    {
+	      sys_halt ();
+	      mec_ersr |= 0x2000;
+	      if (sis_verbose)
+		printf ("Error manager halt - MEC hardware error\n");
 	    }
-	} else
-	    mec_irq(1);
+	}
+      else
+	mec_irq (1);
     }
 }
 
 static void
-mecparerror()
+mecparerror ()
 {
-    mec_ersr |= 0x20;
-    decode_ersr();
+  mec_ersr |= 0x20;
+  decode_ersr ();
 }
 
 
 /* IU error mode manager */
 
 static void
-error_mode(pc)
-    uint32          pc;
+error_mode (pc)
+     uint32 pc;
 {
 
-    mec_ersr |= 0x1;
-    decode_ersr();
+  mec_ersr |= 0x1;
+  decode_ersr ();
 }
 
 
 /* Check memory settings */
 
 static void
-decode_memcfg()
+decode_memcfg ()
 {
-    if (rom8) mec_memcfg &= ~0x20000;
-    else mec_memcfg |= 0x20000;
+  if (rom8)
+    mec_memcfg &= ~0x20000;
+  else
+    mec_memcfg |= 0x20000;
 
-    mem_ramsz = (1024 * 1024) << ((mec_memcfg >> 10) & 7);
-    mem_romsz = (2 *1024 * 1024) << ((mec_memcfg >> 18) & 7);
+  mem_ramsz = (1024 * 1024) << ((mec_memcfg >> 10) & 7);
+  mem_romsz = (2 * 1024 * 1024) << ((mec_memcfg >> 18) & 7);
 
-    mem_ramstart = RAM_START;
-    mem_ramend = RAM_END;
-    mem_rammask = RAM_MASK;
+  mem_ramstart = RAM_START;
+  mem_ramend = RAM_END;
+  mem_rammask = RAM_MASK;
 
-    if (sis_verbose)
-	printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
-	       mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
+  if (sis_verbose)
+    printf ("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
+	    mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
 }
 
 static void
-decode_wcr()
+decode_wcr ()
 {
-    mem_ramr_ws = mec_wcr & 3;
-    mem_ramw_ws = (mec_wcr >> 2) & 3;
-    mem_romr_ws = (mec_wcr >> 4) & 0x0f;
-    if (rom8) {
-    	if (mem_romr_ws > 0 )  mem_romr_ws--;
-	mem_romr_ws = 5 + (4*mem_romr_ws);
+  mem_ramr_ws = mec_wcr & 3;
+  mem_ramw_ws = (mec_wcr >> 2) & 3;
+  mem_romr_ws = (mec_wcr >> 4) & 0x0f;
+  if (rom8)
+    {
+      if (mem_romr_ws > 0)
+	mem_romr_ws--;
+      mem_romr_ws = 5 + (4 * mem_romr_ws);
     }
-    mem_romw_ws = (mec_wcr >> 8) & 0x0f;
-    if (sis_verbose)
-	printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
-	       mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
+  mem_romw_ws = (mec_wcr >> 8) & 0x0f;
+  if (sis_verbose)
+    printf
+      ("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
+       mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
 }
 
 static void
-decode_mcr()
+decode_mcr ()
 {
-    mem_accprot = (mec_wpr[0] | mec_wpr[1]);
-    mem_blockprot = (mec_mcr >> 3) & 1;
-    if (sis_verbose && mem_accprot)
-	printf("Memory block write protection enabled\n");
-    if (mec_mcr & 0x08000) {
-	mec_ersr |= 0x20;
-	decode_ersr();
+  mem_accprot = (mec_wpr[0] | mec_wpr[1]);
+  mem_blockprot = (mec_mcr >> 3) & 1;
+  if (sis_verbose && mem_accprot)
+    printf ("Memory block write protection enabled\n");
+  if (mec_mcr & 0x08000)
+    {
+      mec_ersr |= 0x20;
+      decode_ersr ();
     }
-    if (sis_verbose && (mec_mcr & 2))
-	printf("Software reset enabled\n");
-    if (sis_verbose && (mec_mcr & 1))
-	printf("Power-down mode enabled\n");
+  if (sis_verbose && (mec_mcr & 2))
+    printf ("Software reset enabled\n");
+  if (sis_verbose && (mec_mcr & 1))
+    printf ("Power-down mode enabled\n");
 }
 
 /* Flush ports when simulator stops */
 
 static void
-sim_halt()
+sim_halt ()
 {
 #ifdef FAST_UART
-    flush_uart();
+  flush_uart ();
 #endif
 }
 
 static void
-close_port()
+close_port ()
 {
-    if (f1open && f1in != stdin)
-	fclose(f1in);
-    if (f2open && f2in != stdin)
-	fclose(f2in);
+  if (f1open && f1in != stdin)
+    fclose (f1in);
+  if (f2open && f2in != stdin)
+    fclose (f2in);
 }
 
 static void
-exit_sim()
+exit_sim ()
 {
-    close_port();
+  close_port ();
 }
 
 static void
-mec_reset()
+mec_reset ()
 {
-    int             i;
-
-    for (i = 0; i < 2; i++)
-	mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
-    mec_mcr = 0x01350014;
-    mec_iocr = 0;
-    mec_sfsr = 0x078;
-    mec_ffar = 0;
-    mec_ipr = 0;
-    mec_imr = 0x7ffe;
-    mec_isr = 0;
-    mec_icr = 0;
-    mec_ifr = 0;
-    mec_memcfg = 0x10000;
-    mec_wcr = -1;
-    mec_ersr = 0;		/* MEC error and status register */
-    mec_tcr = 0;		/* MEC test comtrol register */
-
-    decode_memcfg();
-    decode_wcr();
-    decode_mcr();
-
-    posted_irq = 0;
-    wnuma = wnumb = 0;
-    anum = aind = bnum = bind = 0;
-
-    uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
-    uarta_data = uartb_data = UART_THE | UART_TSE;
-
-    rtc_counter = 0xffffffff;
-    rtc_reload = 0xffffffff;
-    rtc_scaler = 0xff;
-    rtc_enabled = 0;
-    rtc_cr = 0;
-    rtc_se = 0;
-
-    gpt_counter = 0xffffffff;
-    gpt_reload = 0xffffffff;
-    gpt_scaler = 0xffff;
-    gpt_enabled = 0;
-    gpt_cr = 0;
-    gpt_se = 0;
-
-    wdog_scaler = 255;
-    wdog_rst_delay = 255;
-    wdog_counter = 0xffff;
-    wdog_rston = 0;
-    wdog_status = init;
+  int i;
+
+  for (i = 0; i < 2; i++)
+    mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
+  mec_mcr = 0x01350014;
+  mec_iocr = 0;
+  mec_sfsr = 0x078;
+  mec_ffar = 0;
+  mec_ipr = 0;
+  mec_imr = 0x7ffe;
+  mec_isr = 0;
+  mec_icr = 0;
+  mec_ifr = 0;
+  mec_memcfg = 0x10000;
+  mec_wcr = -1;
+  mec_ersr = 0;			/* MEC error and status register */
+  mec_tcr = 0;			/* MEC test comtrol register */
+
+  decode_memcfg ();
+  decode_wcr ();
+  decode_mcr ();
+
+  posted_irq = 0;
+  wnuma = wnumb = 0;
+  anum = aind = bnum = bind = 0;
+
+  uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
+  uarta_data = uartb_data = UART_THE | UART_TSE;
+
+  rtc_counter = 0xffffffff;
+  rtc_reload = 0xffffffff;
+  rtc_scaler = 0xff;
+  rtc_enabled = 0;
+  rtc_cr = 0;
+  rtc_se = 0;
+
+  gpt_counter = 0xffffffff;
+  gpt_reload = 0xffffffff;
+  gpt_scaler = 0xffff;
+  gpt_enabled = 0;
+  gpt_cr = 0;
+  gpt_se = 0;
+
+  wdog_scaler = 255;
+  wdog_rst_delay = 255;
+  wdog_counter = 0xffff;
+  wdog_rston = 0;
+  wdog_status = init;
 
 }
 
 
 
 static void
-mec_intack(level)
-    int32           level;
+mec_intack (level)
+     int32 level;
 {
-    int             irq_test;
-
-    if (sis_verbose)
-	printf("interrupt %d acknowledged\n", level);
-    irq_test = mec_tcr & 0x80000;
-    if ((irq_test) && (mec_ifr & (1 << level)))
-	mec_ifr &= ~(1 << level);
-    else
-	mec_ipr &= ~(1 << level);
-   chk_irq();
+  int irq_test;
+
+  if (sis_verbose)
+    printf ("interrupt %d acknowledged\n", level);
+  irq_test = mec_tcr & 0x80000;
+  if ((irq_test) && (mec_ifr & (1 << level)))
+    mec_ifr &= ~(1 << level);
+  else
+    mec_ipr &= ~(1 << level);
+  chk_irq ();
 }
 
 static void
-chk_irq()
+chk_irq ()
 {
-    int32           i;
-    uint32          itmp;
-    int		    old_irl;
-
-    old_irl = ext_irl[0];
-    if (mec_tcr & 0x80000) itmp = mec_ifr;
-    else itmp  = 0;
-    itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
-    ext_irl[0] = 0;
-    if (itmp != 0) {
-	for (i = 15; i > 0; i--) {
-	    if (((itmp >> i) & 1) != 0) {
-		if ((sis_verbose) && (i > old_irl)) 
-		    printf("IU irl: %d\n", i);
-		ext_irl[0] = i;
-		break;
+  int32 i;
+  uint32 itmp;
+  int old_irl;
+
+  old_irl = ext_irl[0];
+  if (mec_tcr & 0x80000)
+    itmp = mec_ifr;
+  else
+    itmp = 0;
+  itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
+  ext_irl[0] = 0;
+  if (itmp != 0)
+    {
+      for (i = 15; i > 0; i--)
+	{
+	  if (((itmp >> i) & 1) != 0)
+	    {
+	      if ((sis_verbose) && (i > old_irl))
+		printf ("IU irl: %d\n", i);
+	      ext_irl[0] = i;
+	      break;
 	    }
 	}
     }
 }
 
 static void
-mec_irq(level)
-    int32           level;
+mec_irq (level)
+     int32 level;
 {
-    mec_ipr |= (1 << level);
-    chk_irq();
+  mec_ipr |= (1 << level);
+  chk_irq ();
 }
 
 static void
-set_sfsr(fault, addr, asi, read)
-    uint32          fault;
-    uint32          addr;
-    uint32          asi;
-    uint32          read;
+set_sfsr (fault, addr, asi, read)
+     uint32 fault;
+     uint32 addr;
+     uint32 asi;
+     uint32 read;
 {
-    if ((asi == 0xa) || (asi == 0xb)) {
-	mec_ffar = addr;
-	mec_sfsr = (fault << 3) | (!read << 15);
-	mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
-	switch (asi) {
+  if ((asi == 0xa) || (asi == 0xb))
+    {
+      mec_ffar = addr;
+      mec_sfsr = (fault << 3) | (!read << 15);
+      mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
+      switch (asi)
+	{
 	case 0xa:
-	    mec_sfsr |= 0x0004;
-	    break;
+	  mec_sfsr |= 0x0004;
+	  break;
 	case 0xb:
-	    mec_sfsr |= 0x1004;
-	    break;
+	  mec_sfsr |= 0x1004;
+	  break;
 	}
     }
 }
 
 static int32
-mec_read(addr, asi, data)
-    uint32          addr;
-    uint32          asi;
-    uint32         *data;
+mec_read (addr, asi, data)
+     uint32 addr;
+     uint32 asi;
+     uint32 *data;
 {
 
-    switch (addr & 0x0ff) {
+  switch (addr & 0x0ff)
+    {
 
     case MEC_MCR:		/* 0x00 */
-	*data = mec_mcr;
-	break;
+      *data = mec_mcr;
+      break;
 
     case MEC_MEMCFG:		/* 0x10 */
-	*data = mec_memcfg;
-	break;
+      *data = mec_memcfg;
+      break;
 
     case MEC_IOCR:
-	*data = mec_iocr;	/* 0x14 */
-	break;
+      *data = mec_iocr;		/* 0x14 */
+      break;
 
     case MEC_SSA1:		/* 0x20 */
-	*data = mec_ssa[0] | (mec_wpr[0] << 23);
-	break;
+      *data = mec_ssa[0] | (mec_wpr[0] << 23);
+      break;
     case MEC_SEA1:		/* 0x24 */
-	*data = mec_sea[0];
-	break;
+      *data = mec_sea[0];
+      break;
     case MEC_SSA2:		/* 0x28 */
-	*data = mec_ssa[1] | (mec_wpr[1] << 23);
-	break;
+      *data = mec_ssa[1] | (mec_wpr[1] << 23);
+      break;
     case MEC_SEA2:		/* 0x2c */
-	*data = mec_sea[1];
-	break;
+      *data = mec_sea[1];
+      break;
 
     case MEC_ISR:		/* 0x44 */
-	*data = mec_isr;
-	break;
+      *data = mec_isr;
+      break;
 
     case MEC_IPR:		/* 0x48 */
-	*data = mec_ipr;
-	break;
+      *data = mec_ipr;
+      break;
 
     case MEC_IMR:		/* 0x4c */
-	*data = mec_imr;
-	break;
+      *data = mec_imr;
+      break;
 
     case MEC_IFR:		/* 0x54 */
-	*data = mec_ifr;
-	break;
+      *data = mec_ifr;
+      break;
 
     case MEC_RTC_COUNTER:	/* 0x80 */
-	*data = rtc_counter_read();
-	break;
+      *data = rtc_counter_read ();
+      break;
     case MEC_RTC_SCALER:	/* 0x84 */
-	if (rtc_enabled)
-	    *data = rtc_scaler - (now() - rtc_scaler_start);
-	else
-	    *data = rtc_scaler;
-	break;
+      if (rtc_enabled)
+	*data = rtc_scaler - (now () - rtc_scaler_start);
+      else
+	*data = rtc_scaler;
+      break;
 
     case MEC_GPT_COUNTER:	/* 0x88 */
-	*data = gpt_counter_read();
-	break;
+      *data = gpt_counter_read ();
+      break;
 
     case MEC_GPT_SCALER:	/* 0x8c */
-	if (rtc_enabled)
-	    *data = gpt_scaler - (now() - gpt_scaler_start);
-	else
-	    *data = gpt_scaler;
-	break;
+      if (rtc_enabled)
+	*data = gpt_scaler - (now () - gpt_scaler_start);
+      else
+	*data = gpt_scaler;
+      break;
 
 
     case MEC_SFSR:		/* 0xA0 */
-	*data = mec_sfsr;
-	break;
+      *data = mec_sfsr;
+      break;
 
     case MEC_FFAR:		/* 0xA4 */
-	*data = mec_ffar;
-	break;
+      *data = mec_ffar;
+      break;
 
     case MEC_ERSR:		/* 0xB0 */
-	*data = mec_ersr;
-	break;
+      *data = mec_ersr;
+      break;
 
     case MEC_TCR:		/* 0xD0 */
-	*data = mec_tcr;
-	break;
+      *data = mec_tcr;
+      break;
 
     case MEC_UARTA:		/* 0xE0 */
     case MEC_UARTB:		/* 0xE4 */
-	if (asi != 0xb) {
-	    set_sfsr(MEC_ACC, addr, asi, 1);
-	    return 1;
+      if (asi != 0xb)
+	{
+	  set_sfsr (MEC_ACC, addr, asi, 1);
+	  return 1;
 	}
-	*data = read_uart(addr);
-	break;
+      *data = read_uart (addr);
+      break;
 
-    case MEC_UART_CTRL:		/* 0xE8 */
+    case MEC_UART_CTRL:	/* 0xE8 */
 
-	*data = read_uart(addr);
-	break;
+      *data = read_uart (addr);
+      break;
 
     default:
-	set_sfsr(MEC_ACC, addr, asi, 1);
-	return 1;
-	break;
+      set_sfsr (MEC_ACC, addr, asi, 1);
+      return 1;
+      break;
     }
-    return MOK;
+  return MOK;
 }
 
 static int
-mec_write(addr, data)
-    uint32          addr;
-    uint32          data;
+mec_write (addr, data)
+     uint32 addr;
+     uint32 data;
 {
-    if (sis_verbose > 1)
-	printf("MEC write a: %08x, d: %08x\n",addr,data);
-    switch (addr & 0x0ff) {
+  if (sis_verbose > 1)
+    printf ("MEC write a: %08x, d: %08x\n", addr, data);
+  switch (addr & 0x0ff)
+    {
 
     case MEC_MCR:
-	mec_mcr = data;
-	decode_mcr();
-        if (mec_mcr & 0x08000) mecparerror();
-	break;
+      mec_mcr = data;
+      decode_mcr ();
+      if (mec_mcr & 0x08000)
+	mecparerror ();
+      break;
 
     case MEC_SFR:
-	if (mec_mcr & 0x2) {
-	    sys_reset();
-	    mec_ersr = 0x4000;
-    	    if (sis_verbose)
-	    	printf(" Software reset issued\n");
+      if (mec_mcr & 0x2)
+	{
+	  sys_reset ();
+	  mec_ersr = 0x4000;
+	  if (sis_verbose)
+	    printf (" Software reset issued\n");
 	}
-	break;
+      break;
 
     case MEC_IOCR:
-	mec_iocr = data;
-        if (mec_iocr & 0xC0C0C0C0) mecparerror();
-	break;
+      mec_iocr = data;
+      if (mec_iocr & 0xC0C0C0C0)
+	mecparerror ();
+      break;
 
     case MEC_SSA1:		/* 0x20 */
-        if (data & 0xFE000000) mecparerror();
-	mec_ssa[0] = data & 0x7fffff;
-	mec_wpr[0] = (data >> 23) & 0x03;
-	mem_accprot = mec_wpr[0] || mec_wpr[1];
-	if (sis_verbose && mec_wpr[0])
-	    printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
-		   mec_ssa[0] << 2, mec_sea[0] << 2);
-	break;
+      if (data & 0xFE000000)
+	mecparerror ();
+      mec_ssa[0] = data & 0x7fffff;
+      mec_wpr[0] = (data >> 23) & 0x03;
+      mem_accprot = mec_wpr[0] || mec_wpr[1];
+      if (sis_verbose && mec_wpr[0])
+	printf ("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
+		mec_ssa[0] << 2, mec_sea[0] << 2);
+      break;
     case MEC_SEA1:		/* 0x24 */
-        if (data & 0xFF800000) mecparerror();
-	mec_sea[0] = data & 0x7fffff;
-	break;
+      if (data & 0xFF800000)
+	mecparerror ();
+      mec_sea[0] = data & 0x7fffff;
+      break;
     case MEC_SSA2:		/* 0x28 */
-        if (data & 0xFE000000) mecparerror();
-	mec_ssa[1] = data & 0x7fffff;
-	mec_wpr[1] = (data >> 23) & 0x03;
-	mem_accprot = mec_wpr[0] || mec_wpr[1];
-	if (sis_verbose && mec_wpr[1])
-	    printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
-		   mec_ssa[1] << 2, mec_sea[1] << 2);
-	break;
+      if (data & 0xFE000000)
+	mecparerror ();
+      mec_ssa[1] = data & 0x7fffff;
+      mec_wpr[1] = (data >> 23) & 0x03;
+      mem_accprot = mec_wpr[0] || mec_wpr[1];
+      if (sis_verbose && mec_wpr[1])
+	printf ("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
+		mec_ssa[1] << 2, mec_sea[1] << 2);
+      break;
     case MEC_SEA2:		/* 0x2c */
-        if (data & 0xFF800000) mecparerror();
-	mec_sea[1] = data & 0x7fffff;
-	break;
+      if (data & 0xFF800000)
+	mecparerror ();
+      mec_sea[1] = data & 0x7fffff;
+      break;
 
     case MEC_UARTA:
     case MEC_UARTB:
-        if (data & 0xFFFFFF00) mecparerror();
+      if (data & 0xFFFFFF00)
+	mecparerror ();
     case MEC_UART_CTRL:
-        if (data & 0xFF00FF00) mecparerror();
-	write_uart(addr, data);
-	break;
+      if (data & 0xFF00FF00)
+	mecparerror ();
+      write_uart (addr, data);
+      break;
 
     case MEC_GPT_RELOAD:
-	gpt_reload_set(data);
-	break;
+      gpt_reload_set (data);
+      break;
 
     case MEC_GPT_SCALER:
-        if (data & 0xFFFF0000) mecparerror();
-	gpt_scaler_set(data);
-	break;
+      if (data & 0xFFFF0000)
+	mecparerror ();
+      gpt_scaler_set (data);
+      break;
 
     case MEC_TIMER_CTRL:
-        if (data & 0xFFFFF0F0) mecparerror();
-	timer_ctrl(data);
-	break;
+      if (data & 0xFFFFF0F0)
+	mecparerror ();
+      timer_ctrl (data);
+      break;
 
     case MEC_RTC_RELOAD:
-	rtc_reload_set(data);
-	break;
+      rtc_reload_set (data);
+      break;
 
     case MEC_RTC_SCALER:
-        if (data & 0xFFFFFF00) mecparerror();
-	rtc_scaler_set(data);
-	break;
+      if (data & 0xFFFFFF00)
+	mecparerror ();
+      rtc_scaler_set (data);
+      break;
 
     case MEC_SFSR:		/* 0xA0 */
-        if (data & 0xFFFF0880) mecparerror();
-	mec_sfsr = 0x78;
-	break;
+      if (data & 0xFFFF0880)
+	mecparerror ();
+      mec_sfsr = 0x78;
+      break;
 
     case MEC_ISR:
-        if (data & 0xFFFFE000) mecparerror();
-	mec_isr = data;
-	break;
+      if (data & 0xFFFFE000)
+	mecparerror ();
+      mec_isr = data;
+      break;
 
     case MEC_IMR:		/* 0x4c */
 
-        if (data & 0xFFFF8001) mecparerror();
-	mec_imr = data & 0x7ffe;
-	chk_irq();
-	break;
+      if (data & 0xFFFF8001)
+	mecparerror ();
+      mec_imr = data & 0x7ffe;
+      chk_irq ();
+      break;
 
     case MEC_ICR:		/* 0x50 */
 
-        if (data & 0xFFFF0001) mecparerror();
-	mec_ipr &= ~data & 0x0fffe;
-	chk_irq();
-	break;
+      if (data & 0xFFFF0001)
+	mecparerror ();
+      mec_ipr &= ~data & 0x0fffe;
+      chk_irq ();
+      break;
 
     case MEC_IFR:		/* 0x54 */
 
-        if (mec_tcr & 0x080000) {
-            if (data & 0xFFFF0001) mecparerror();
-	    mec_ifr = data & 0xfffe;
-	    chk_irq();
+      if (mec_tcr & 0x080000)
+	{
+	  if (data & 0xFFFF0001)
+	    mecparerror ();
+	  mec_ifr = data & 0xfffe;
+	  chk_irq ();
 	}
-	break;
+      break;
 
     case MEC_MEMCFG:		/* 0x10 */
-        if (data & 0xC0E08000) mecparerror();
-	mec_memcfg = data;
-	decode_memcfg();
-	if (mec_memcfg & 0xc0e08000)
-	    mecparerror();
-	break;
+      if (data & 0xC0E08000)
+	mecparerror ();
+      mec_memcfg = data;
+      decode_memcfg ();
+      if (mec_memcfg & 0xc0e08000)
+	mecparerror ();
+      break;
 
     case MEC_WCR:		/* 0x18 */
-	mec_wcr = data;
-	decode_wcr();
-	break;
+      mec_wcr = data;
+      decode_wcr ();
+      break;
 
     case MEC_ERSR:		/* 0xB0 */
-	if (mec_tcr & 0x100000)
-            if (data & 0xFFFFEFC0) mecparerror();
-	    mec_ersr = data & 0x103f;
-	break;
+      if (mec_tcr & 0x100000)
+	if (data & 0xFFFFEFC0)
+	  mecparerror ();
+      mec_ersr = data & 0x103f;
+      break;
 
     case MEC_TCR:		/* 0xD0 */
-        if (data & 0xFFE1FFC0) mecparerror();
-	mec_tcr = data & 0x1e003f;
-	break;
+      if (data & 0xFFE1FFC0)
+	mecparerror ();
+      mec_tcr = data & 0x1e003f;
+      break;
 
     case MEC_WDOG:		/* 0x60 */
-	wdog_scaler = (data >> 16) & 0x0ff;
-	wdog_counter = data & 0x0ffff;
-	wdog_rst_delay = data >> 24;
-	wdog_rston = 0;
-	if (wdog_status == stopped)
-	    wdog_start();
-	wdog_status = enabled;
-	break;
+      wdog_scaler = (data >> 16) & 0x0ff;
+      wdog_counter = data & 0x0ffff;
+      wdog_rst_delay = data >> 24;
+      wdog_rston = 0;
+      if (wdog_status == stopped)
+	wdog_start ();
+      wdog_status = enabled;
+      break;
 
     case MEC_TRAPD:		/* 0x64 */
-	if (wdog_status == init) {
-	    wdog_status = disabled;
-	    if (sis_verbose)
-		printf("Watchdog disabled\n");
+      if (wdog_status == init)
+	{
+	  wdog_status = disabled;
+	  if (sis_verbose)
+	    printf ("Watchdog disabled\n");
 	}
-	break;
+      break;
 
     case MEC_PWDR:
-	if (mec_mcr & 1)
-	    sregs->pwd_mode = 1;
-            sregs->pwdstart = sregs->simtime;
-	break;
+      if (mec_mcr & 1)
+	sregs->pwd_mode = 1;
+      sregs->pwdstart = sregs->simtime;
+      break;
 
     default:
-	set_sfsr(MEC_ACC, addr, 0xb, 0);
-	return 1;
-	break;
+      set_sfsr (MEC_ACC, addr, 0xb, 0);
+      return 1;
+      break;
     }
-    return MOK;
+  return MOK;
 }
 
 
 /* MEC UARTS */
 
-static int      ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
+static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
 
 static void
-init_stdio()
+init_stdio ()
 {
-    if (dumbio)
-	return; /* do nothing */
+  if (dumbio)
+    return;			/* do nothing */
 #ifdef HAVE_TERMIOS_H
-    if (ifd1 == 0 && f1open) {
-	tcsetattr(0, TCSANOW, &ioc1);
-	tcflush (ifd1, TCIFLUSH);
+  if (ifd1 == 0 && f1open)
+    {
+      tcsetattr (0, TCSANOW, &ioc1);
+      tcflush (ifd1, TCIFLUSH);
     }
-    if (ifd2 == 0 && f1open) {
-	tcsetattr(0, TCSANOW, &ioc2);
-	tcflush (ifd2, TCIFLUSH);
+  if (ifd2 == 0 && f1open)
+    {
+      tcsetattr (0, TCSANOW, &ioc2);
+      tcflush (ifd2, TCIFLUSH);
     }
 #endif
 }
 
 static void
-restore_stdio()
+restore_stdio ()
 {
-    if (dumbio)
-	return; /* do nothing */
+  if (dumbio)
+    return;			/* do nothing */
 #ifdef HAVE_TERMIOS_H
-    if (ifd1 == 0 && f1open && tty_setup)
-	tcsetattr(0, TCSANOW, &iocold1);
-    if (ifd2 == 0 && f2open && tty_setup)
-	tcsetattr(0, TCSANOW, &iocold2);
+  if (ifd1 == 0 && f1open && tty_setup)
+    tcsetattr (0, TCSANOW, &iocold1);
+  if (ifd2 == 0 && f2open && tty_setup)
+    tcsetattr (0, TCSANOW, &iocold2);
 #endif
 }
 
@@ -879,409 +937,477 @@ restore_stdio()
 	( dumbio || nouartrx ? (0) : read( _fd_, _buf_, _len_ ) )
 
 static void
-port_init()
+port_init ()
 {
 
-    if (uben) {
-	f2in = stdin;
-	f1in = NULL;
-	f2out = stdout;
-	f1out = NULL;
-    } else {
-	f1in = stdin;
-	f2in = NULL;
-	f1out = stdout;
-	f2out = NULL;
+  if (uben)
+    {
+      f2in = stdin;
+      f1in = NULL;
+      f2out = stdout;
+      f1out = NULL;
     }
-    if (uart_dev1[0] != 0)
-	if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
-	    printf("Warning, couldn't open output device %s\n", uart_dev1);
-	} else {
-	    if (sis_verbose)
-		printf("serial port A on %s\n", uart_dev1);
-	    f1in = f1out = fdopen(fd1, "r+");
-	    setbuf(f1out, NULL);
-	    f1open = 1;
-	}
-    if (f1in)
-	ifd1 = fileno(f1in);
-    if (ifd1 == 0) {
+  else
+    {
+      f1in = stdin;
+      f2in = NULL;
+      f1out = stdout;
+      f2out = NULL;
+    }
+  if (uart_dev1[0] != 0)
+    if ((fd1 = open (uart_dev1, O_RDWR | O_NONBLOCK)) < 0)
+      {
+	printf ("Warning, couldn't open output device %s\n", uart_dev1);
+      }
+    else
+      {
 	if (sis_verbose)
-	    printf("serial port A on stdin/stdout\n");
-        if (!dumbio) {
+	  printf ("serial port A on %s\n", uart_dev1);
+	f1in = f1out = fdopen (fd1, "r+");
+	setbuf (f1out, NULL);
+	f1open = 1;
+      }
+  if (f1in)
+    ifd1 = fileno (f1in);
+  if (ifd1 == 0)
+    {
+      if (sis_verbose)
+	printf ("serial port A on stdin/stdout\n");
+      if (!dumbio)
+	{
 #ifdef HAVE_TERMIOS_H
-	    tcgetattr (ifd1, &ioc1);
-	    if (tty_setup) {
-		iocold1 = ioc1;
-		ioc1.c_lflag &= ~(ICANON | ECHO);
-		ioc1.c_cc[VMIN] = 0;
-		ioc1.c_cc[VTIME] = 0;
+	  tcgetattr (ifd1, &ioc1);
+	  if (tty_setup)
+	    {
+	      iocold1 = ioc1;
+	      ioc1.c_lflag &= ~(ICANON | ECHO);
+	      ioc1.c_cc[VMIN] = 0;
+	      ioc1.c_cc[VTIME] = 0;
 	    }
 #endif
-        }
-	f1open = 1;
+	}
+      f1open = 1;
     }
 
-    if (f1out) {
-	ofd1 = fileno(f1out);
-	if (!dumbio && tty_setup && ofd1 == 1)
-	    setbuf (f1out, NULL);
+  if (f1out)
+    {
+      ofd1 = fileno (f1out);
+      if (!dumbio && tty_setup && ofd1 == 1)
+	setbuf (f1out, NULL);
     }
 
-    if (uart_dev2[0] != 0)
-	if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
-	    printf("Warning, couldn't open output device %s\n", uart_dev2);
-	} else {
-	    if (sis_verbose)
-		printf("serial port B on %s\n", uart_dev2);
-	    f2in = f2out = fdopen(fd2, "r+");
-	    setbuf(f2out, NULL);
-	    f2open = 1;
-	}
-    if (f2in)  ifd2 = fileno(f2in);
-    if (ifd2 == 0) {
+  if (uart_dev2[0] != 0)
+    if ((fd2 = open (uart_dev2, O_RDWR | O_NONBLOCK)) < 0)
+      {
+	printf ("Warning, couldn't open output device %s\n", uart_dev2);
+      }
+    else
+      {
 	if (sis_verbose)
-	    printf("serial port B on stdin/stdout\n");
-        if (!dumbio) {
+	  printf ("serial port B on %s\n", uart_dev2);
+	f2in = f2out = fdopen (fd2, "r+");
+	setbuf (f2out, NULL);
+	f2open = 1;
+      }
+  if (f2in)
+    ifd2 = fileno (f2in);
+  if (ifd2 == 0)
+    {
+      if (sis_verbose)
+	printf ("serial port B on stdin/stdout\n");
+      if (!dumbio)
+	{
 #ifdef HAVE_TERMIOS_H
-            tcgetattr(ifd2, &ioc2);
-            if (tty_setup) {
-		iocold2 = ioc2;
-		ioc2.c_lflag &= ~(ICANON | ECHO);
-		ioc2.c_cc[VMIN] = 0;
-		ioc2.c_cc[VTIME] = 0;
+	  tcgetattr (ifd2, &ioc2);
+	  if (tty_setup)
+	    {
+	      iocold2 = ioc2;
+	      ioc2.c_lflag &= ~(ICANON | ECHO);
+	      ioc2.c_cc[VMIN] = 0;
+	      ioc2.c_cc[VTIME] = 0;
 	    }
 #endif
-        }
-	f2open = 1;
+	}
+      f2open = 1;
     }
 
-    if (f2out) {
-	ofd2 = fileno(f2out);
-	if (!dumbio && tty_setup && ofd2 == 1)
-	    setbuf (f2out, NULL);
+  if (f2out)
+    {
+      ofd2 = fileno (f2out);
+      if (!dumbio && tty_setup && ofd2 == 1)
+	setbuf (f2out, NULL);
     }
 
-    wnuma = wnumb = 0;
+  wnuma = wnumb = 0;
 
 }
 
 static uint32
-read_uart(addr)
-    uint32          addr;
+read_uart (addr)
+     uint32 addr;
 {
 
-    unsigned        tmp;
+  unsigned tmp;
 
-    tmp = 0;
-    switch (addr & 0xff) {
+  tmp = 0;
+  switch (addr & 0xff)
+    {
 
     case 0xE0:			/* UART 1 */
 #ifndef _WIN32
 #ifdef FAST_UART
 
-	if (aind < anum) {
-	    if ((aind + 1) < anum)
-		mec_irq(4);
-	    return (0x700 | (uint32) aq[aind++]);
-	} else {
-	    if (f1open)
-		anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
-	    else
-		anum = 0;
-	    if (anum > 0) {
-		aind = 0;
-		if ((aind + 1) < anum)
-		    mec_irq(4);
-		return (0x700 | (uint32) aq[aind++]);
-	    } else {
-		return (0x600 | (uint32) aq[aind]);
+      if (aind < anum)
+	{
+	  if ((aind + 1) < anum)
+	    mec_irq (4);
+	  return (0x700 | (uint32) aq[aind++]);
+	}
+      else
+	{
+	  if (f1open)
+	    anum = DO_STDIO_READ (ifd1, aq, UARTBUF);
+	  else
+	    anum = 0;
+	  if (anum > 0)
+	    {
+	      aind = 0;
+	      if ((aind + 1) < anum)
+		mec_irq (4);
+	      return (0x700 | (uint32) aq[aind++]);
+	    }
+	  else
+	    {
+	      return (0x600 | (uint32) aq[aind]);
 	    }
 
 	}
 #else
-	tmp = uarta_data;
-	uarta_data &= ~UART_DR;
-	uart_stat_reg &= ~UARTA_DR;
-	return tmp;
+      tmp = uarta_data;
+      uarta_data &= ~UART_DR;
+      uart_stat_reg &= ~UARTA_DR;
+      return tmp;
 #endif
 #else
-	return 0;
+      return 0;
 #endif
-	break;
+      break;
 
     case 0xE4:			/* UART 2 */
 #ifndef _WIN32
 #ifdef FAST_UART
-	if (bind < bnum) {
-	    if ((bind + 1) < bnum)
-		mec_irq(5);
-	    return (0x700 | (uint32) bq[bind++]);
-	} else {
-	    if (f2open)
-		bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
-	    else
-		bnum = 0;
-	    if (bnum > 0) {
-		bind = 0;
-		if ((bind + 1) < bnum)
-		    mec_irq(5);
-		return (0x700 | (uint32) bq[bind++]);
-	    } else {
-		return (0x600 | (uint32) bq[bind]);
+      if (bind < bnum)
+	{
+	  if ((bind + 1) < bnum)
+	    mec_irq (5);
+	  return (0x700 | (uint32) bq[bind++]);
+	}
+      else
+	{
+	  if (f2open)
+	    bnum = DO_STDIO_READ (ifd2, bq, UARTBUF);
+	  else
+	    bnum = 0;
+	  if (bnum > 0)
+	    {
+	      bind = 0;
+	      if ((bind + 1) < bnum)
+		mec_irq (5);
+	      return (0x700 | (uint32) bq[bind++]);
+	    }
+	  else
+	    {
+	      return (0x600 | (uint32) bq[bind]);
 	    }
 
 	}
 #else
-	tmp = uartb_data;
-	uartb_data &= ~UART_DR;
-	uart_stat_reg &= ~UARTB_DR;
-	return tmp;
+      tmp = uartb_data;
+      uartb_data &= ~UART_DR;
+      uart_stat_reg &= ~UARTB_DR;
+      return tmp;
 #endif
 #else
-	return 0;
+      return 0;
 #endif
-	break;
+      break;
 
-    case 0xE8:			/* UART status register	 */
+    case 0xE8:			/* UART status register  */
 #ifndef _WIN32
 #ifdef FAST_UART
 
-	Ucontrol = 0;
-	if (aind < anum) {
-	    Ucontrol |= 0x00000001;
-	} else {
-	    if (f1open)
-		anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
-	    else
-		anum = 0;
-	    if (anum > 0) {
-		Ucontrol |= 0x00000001;
-		aind = 0;
-		mec_irq(4);
+      Ucontrol = 0;
+      if (aind < anum)
+	{
+	  Ucontrol |= 0x00000001;
+	}
+      else
+	{
+	  if (f1open)
+	    anum = DO_STDIO_READ (ifd1, aq, UARTBUF);
+	  else
+	    anum = 0;
+	  if (anum > 0)
+	    {
+	      Ucontrol |= 0x00000001;
+	      aind = 0;
+	      mec_irq (4);
 	    }
 	}
-	if (bind < bnum) {
-	    Ucontrol |= 0x00010000;
-	} else {
-	    if (f2open)
-		bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
-	    else
-		bnum = 0;
-	    if (bnum > 0) {
-		Ucontrol |= 0x00010000;
-		bind = 0;
-		mec_irq(5);
+      if (bind < bnum)
+	{
+	  Ucontrol |= 0x00010000;
+	}
+      else
+	{
+	  if (f2open)
+	    bnum = DO_STDIO_READ (ifd2, bq, UARTBUF);
+	  else
+	    bnum = 0;
+	  if (bnum > 0)
+	    {
+	      Ucontrol |= 0x00010000;
+	      bind = 0;
+	      mec_irq (5);
 	    }
 	}
 
-	Ucontrol |= 0x00060006;
-	return Ucontrol;
+      Ucontrol |= 0x00060006;
+      return Ucontrol;
 #else
-	return uart_stat_reg;
+      return uart_stat_reg;
 #endif
 #else
-	return 0x00060006;
+      return 0x00060006;
 #endif
-	break;
+      break;
     default:
-	if (sis_verbose)
-	    printf("Read from unimplemented MEC register (%x)\n", addr);
+      if (sis_verbose)
+	printf ("Read from unimplemented MEC register (%x)\n", addr);
 
     }
-    return 0;
+  return 0;
 }
 
 static void
-write_uart(addr, data)
-    uint32          addr;
-    uint32          data;
+write_uart (addr, data)
+     uint32 addr;
+     uint32 data;
 {
-    unsigned char   c;
+  unsigned char c;
 
-    c = (unsigned char) data;
-    switch (addr & 0xff) {
+  c = (unsigned char) data;
+  switch (addr & 0xff)
+    {
 
     case 0xE0:			/* UART A */
 #ifdef FAST_UART
-	if (f1open) {
-	    if (wnuma < UARTBUF)
-	        wbufa[wnuma++] = c;
-	    else {
-	        while (wnuma) {
-			wnuma -= fwrite (wbufa, 1, wnuma, f1out);
+      if (f1open)
+	{
+	  if (wnuma < UARTBUF)
+	    wbufa[wnuma++] = c;
+	  else
+	    {
+	      while (wnuma)
+		{
+		  wnuma -= fwrite (wbufa, 1, wnuma, f1out);
 		}
-		wbufa[wnuma++] = c;
+	      wbufa[wnuma++] = c;
 	    }
 	}
-	mec_irq(4);
+      mec_irq (4);
 #else
-	if (uart_stat_reg & UARTA_SRE) {
-	    uarta_sreg = c;
-	    uart_stat_reg &= ~UARTA_SRE;
-	    event(uarta_tx, 0, UART_TX_TIME);
-	} else {
-	    uarta_hreg = c;
-	    uart_stat_reg &= ~UARTA_HRE;
+      if (uart_stat_reg & UARTA_SRE)
+	{
+	  uarta_sreg = c;
+	  uart_stat_reg &= ~UARTA_SRE;
+	  event (uarta_tx, 0, UART_TX_TIME);
+	}
+      else
+	{
+	  uarta_hreg = c;
+	  uart_stat_reg &= ~UARTA_HRE;
 	}
 #endif
-	break;
+      break;
 
     case 0xE4:			/* UART B */
 #ifdef FAST_UART
-	if (f2open) {
-	    if (wnumb < UARTBUF)
-		wbufb[wnumb++] = c;
-	    else {
-		while (wnumb) {
-			wnumb -= fwrite (wbufb, 1, wnumb, f2out);
+      if (f2open)
+	{
+	  if (wnumb < UARTBUF)
+	    wbufb[wnumb++] = c;
+	  else
+	    {
+	      while (wnumb)
+		{
+		  wnumb -= fwrite (wbufb, 1, wnumb, f2out);
 		}
-		wbufb[wnumb++] = c;
+	      wbufb[wnumb++] = c;
 	    }
 	}
-	mec_irq(5);
+      mec_irq (5);
 #else
-	if (uart_stat_reg & UARTB_SRE) {
-	    uartb_sreg = c;
-	    uart_stat_reg &= ~UARTB_SRE;
-	    event(uartb_tx, 0, UART_TX_TIME);
-	} else {
-	    uartb_hreg = c;
-	    uart_stat_reg &= ~UARTB_HRE;
+      if (uart_stat_reg & UARTB_SRE)
+	{
+	  uartb_sreg = c;
+	  uart_stat_reg &= ~UARTB_SRE;
+	  event (uartb_tx, 0, UART_TX_TIME);
+	}
+      else
+	{
+	  uartb_hreg = c;
+	  uart_stat_reg &= ~UARTB_HRE;
 	}
 #endif
-	break;
+      break;
     case 0xE8:			/* UART status register */
 #ifndef FAST_UART
-	if (data & UARTA_CLR) {
-	    uart_stat_reg &= 0xFFFF0000;
-	    uart_stat_reg |= UARTA_SRE | UARTA_HRE;
+      if (data & UARTA_CLR)
+	{
+	  uart_stat_reg &= 0xFFFF0000;
+	  uart_stat_reg |= UARTA_SRE | UARTA_HRE;
 	}
-	if (data & UARTB_CLR) {
-	    uart_stat_reg &= 0x0000FFFF;
-	    uart_stat_reg |= UARTB_SRE | UARTB_HRE;
+      if (data & UARTB_CLR)
+	{
+	  uart_stat_reg &= 0x0000FFFF;
+	  uart_stat_reg |= UARTB_SRE | UARTB_HRE;
 	}
 #endif
-	break;
+      break;
     default:
-	if (sis_verbose)
-	    printf("Write to unimplemented MEC register (%x)\n", addr);
+      if (sis_verbose)
+	printf ("Write to unimplemented MEC register (%x)\n", addr);
 
     }
 }
 
 static void
-flush_uart()
+flush_uart ()
 {
-    while (wnuma && f1open) {
-	wnuma -= fwrite (wbufa, 1, wnuma, f1out);
+  while (wnuma && f1open)
+    {
+      wnuma -= fwrite (wbufa, 1, wnuma, f1out);
     }
-    while (wnumb && f2open) {
-	wnumb -= fwrite (wbufb, 1, wnumb, f2out);
+  while (wnumb && f2open)
+    {
+      wnumb -= fwrite (wbufb, 1, wnumb, f2out);
     }
 }
 
 
 
 static void
-uarta_tx()
+uarta_tx ()
 {
-    while (f1open) {
-	while (fwrite (&uarta_sreg, 1, 1, f1out) != 1)
-	    continue;
+  while (f1open)
+    {
+      while (fwrite (&uarta_sreg, 1, 1, f1out) != 1)
+	continue;
+    }
+  if (uart_stat_reg & UARTA_HRE)
+    {
+      uart_stat_reg |= UARTA_SRE;
     }
-    if (uart_stat_reg & UARTA_HRE) {
-	uart_stat_reg |= UARTA_SRE;
-    } else {
-	uarta_sreg = uarta_hreg;
-	uart_stat_reg |= UARTA_HRE;
-	event(uarta_tx, 0, UART_TX_TIME);
+  else
+    {
+      uarta_sreg = uarta_hreg;
+      uart_stat_reg |= UARTA_HRE;
+      event (uarta_tx, 0, UART_TX_TIME);
     }
-    mec_irq(4);
+  mec_irq (4);
 }
 
 static void
-uartb_tx()
+uartb_tx ()
 {
-    while (f2open) {
-	while (fwrite(&uartb_sreg, 1, 1, f2out) != 1)
-	    continue;
+  while (f2open)
+    {
+      while (fwrite (&uartb_sreg, 1, 1, f2out) != 1)
+	continue;
     }
-    if (uart_stat_reg & UARTB_HRE) {
-	uart_stat_reg |= UARTB_SRE;
-    } else {
-	uartb_sreg = uartb_hreg;
-	uart_stat_reg |= UARTB_HRE;
-	event(uartb_tx, 0, UART_TX_TIME);
+  if (uart_stat_reg & UARTB_HRE)
+    {
+      uart_stat_reg |= UARTB_SRE;
     }
-    mec_irq(5);
+  else
+    {
+      uartb_sreg = uartb_hreg;
+      uart_stat_reg |= UARTB_HRE;
+      event (uartb_tx, 0, UART_TX_TIME);
+    }
+  mec_irq (5);
 }
 
 static void
-uart_rx(arg)
-    int32         arg;
+uart_rx (arg)
+     int32 arg;
 {
-    int32           rsize;
-    char            rxd;
+  int32 rsize;
+  char rxd;
 
 
+  rsize = 0;
+  if (f1open)
+    rsize = DO_STDIO_READ (ifd1, &rxd, 1);
+  else
     rsize = 0;
-    if (f1open)
-        rsize = DO_STDIO_READ(ifd1, &rxd, 1);
-    else
-        rsize = 0;
-    if (rsize > 0) {
-	uarta_data = UART_DR | rxd;
-	if (uart_stat_reg & UARTA_HRE)
-	    uarta_data |= UART_THE;
-	if (uart_stat_reg & UARTA_SRE)
-	    uarta_data |= UART_TSE;
-	if (uart_stat_reg & UARTA_DR) {
-	    uart_stat_reg |= UARTA_OR;
-	    mec_irq(7);		/* UART error interrupt */
+  if (rsize > 0)
+    {
+      uarta_data = UART_DR | rxd;
+      if (uart_stat_reg & UARTA_HRE)
+	uarta_data |= UART_THE;
+      if (uart_stat_reg & UARTA_SRE)
+	uarta_data |= UART_TSE;
+      if (uart_stat_reg & UARTA_DR)
+	{
+	  uart_stat_reg |= UARTA_OR;
+	  mec_irq (7);		/* UART error interrupt */
 	}
-	uart_stat_reg |= UARTA_DR;
-	mec_irq(4);
+      uart_stat_reg |= UARTA_DR;
+      mec_irq (4);
     }
+  rsize = 0;
+  if (f2open)
+    rsize = DO_STDIO_READ (ifd2, &rxd, 1);
+  else
     rsize = 0;
-    if (f2open)
-        rsize = DO_STDIO_READ(ifd2, &rxd, 1);
-    else
-        rsize = 0;
-    if (rsize) {
-	uartb_data = UART_DR | rxd;
-	if (uart_stat_reg & UARTB_HRE)
-	    uartb_data |= UART_THE;
-	if (uart_stat_reg & UARTB_SRE)
-	    uartb_data |= UART_TSE;
-	if (uart_stat_reg & UARTB_DR) {
-	    uart_stat_reg |= UARTB_OR;
-	    mec_irq(7);		/* UART error interrupt */
+  if (rsize)
+    {
+      uartb_data = UART_DR | rxd;
+      if (uart_stat_reg & UARTB_HRE)
+	uartb_data |= UART_THE;
+      if (uart_stat_reg & UARTB_SRE)
+	uartb_data |= UART_TSE;
+      if (uart_stat_reg & UARTB_DR)
+	{
+	  uart_stat_reg |= UARTB_OR;
+	  mec_irq (7);		/* UART error interrupt */
 	}
-	uart_stat_reg |= UARTB_DR;
-	mec_irq(5);
+      uart_stat_reg |= UARTB_DR;
+      mec_irq (5);
     }
-    event(uart_rx, 0, UART_RX_TIME);
+  event (uart_rx, 0, UART_RX_TIME);
 }
 
 static void
-uart_intr(arg)
-    int32         arg;
+uart_intr (arg)
+     int32 arg;
 {
-    read_uart(0xE8);		/* Check for UART interrupts every 1000 clk */
-    flush_uart();		/* Flush UART ports      */
-    event(uart_intr, 0, UART_FLUSH_TIME);
+  read_uart (0xE8);		/* Check for UART interrupts every 1000 clk */
+  flush_uart ();		/* Flush UART ports      */
+  event (uart_intr, 0, UART_FLUSH_TIME);
 }
 
 
 static void
-uart_irq_start()
+uart_irq_start ()
 {
 #ifdef FAST_UART
-    event(uart_intr, 0, UART_FLUSH_TIME);
+  event (uart_intr, 0, UART_FLUSH_TIME);
 #else
 #ifndef _WIN32
-    event(uart_rx, 0, UART_RX_TIME);
+  event (uart_rx, 0, UART_RX_TIME);
 #endif
 #endif
 }
@@ -1289,173 +1415,196 @@ uart_irq_start()
 /* Watch-dog */
 
 static void
-wdog_intr(arg)
-    int32         arg;
+wdog_intr (arg)
+     int32 arg;
 {
-    if (wdog_status == disabled) {
-	wdog_status = stopped;
-    } else {
-
-	if (wdog_counter) {
-	    wdog_counter--;
-	    event(wdog_intr, 0, wdog_scaler + 1);
-	} else {
-	    if (wdog_rston) {
-		printf("Watchdog reset!\n");
-		sys_reset();
-		mec_ersr = 0xC000;
-	    } else {
-		mec_irq(15);
-		wdog_rston = 1;
-		wdog_counter = wdog_rst_delay;
-		event(wdog_intr, 0, wdog_scaler + 1);
+  if (wdog_status == disabled)
+    {
+      wdog_status = stopped;
+    }
+  else
+    {
+
+      if (wdog_counter)
+	{
+	  wdog_counter--;
+	  event (wdog_intr, 0, wdog_scaler + 1);
+	}
+      else
+	{
+	  if (wdog_rston)
+	    {
+	      printf ("Watchdog reset!\n");
+	      sys_reset ();
+	      mec_ersr = 0xC000;
+	    }
+	  else
+	    {
+	      mec_irq (15);
+	      wdog_rston = 1;
+	      wdog_counter = wdog_rst_delay;
+	      event (wdog_intr, 0, wdog_scaler + 1);
 	    }
 	}
     }
 }
 
 static void
-wdog_start()
+wdog_start ()
 {
-    event(wdog_intr, 0, wdog_scaler + 1);
-    if (sis_verbose)
-	printf("Watchdog started, scaler = %d, counter = %d\n",
-	       wdog_scaler, wdog_counter);
+  event (wdog_intr, 0, wdog_scaler + 1);
+  if (sis_verbose)
+    printf ("Watchdog started, scaler = %d, counter = %d\n",
+	    wdog_scaler, wdog_counter);
 }
 
 /* MEC timers */
 
 static void
-rtc_intr(arg)
-    int32         arg;
+rtc_intr (arg)
+     int32 arg;
 {
-    if (rtc_counter == 0) {
-
-	mec_irq(13);
-	if (rtc_cr)
-	    rtc_counter = rtc_reload;
-	else
-	    rtc_se = 0;
-    } else
-	rtc_counter -= 1;
-    if (rtc_se) {
-	event(rtc_intr, 0, rtc_scaler + 1);
-	rtc_scaler_start = now();
-	rtc_enabled = 1;
-    } else {
-	if (sis_verbose)
-	    printf("RTC stopped\n\r");
-	rtc_enabled = 0;
+  if (rtc_counter == 0)
+    {
+
+      mec_irq (13);
+      if (rtc_cr)
+	rtc_counter = rtc_reload;
+      else
+	rtc_se = 0;
+    }
+  else
+    rtc_counter -= 1;
+  if (rtc_se)
+    {
+      event (rtc_intr, 0, rtc_scaler + 1);
+      rtc_scaler_start = now ();
+      rtc_enabled = 1;
+    }
+  else
+    {
+      if (sis_verbose)
+	printf ("RTC stopped\n\r");
+      rtc_enabled = 0;
     }
 }
 
 static void
-rtc_start()
+rtc_start ()
 {
-    if (sis_verbose)
-	printf("RTC started (period %d)\n\r", rtc_scaler + 1);
-    event(rtc_intr, 0, rtc_scaler + 1);
-    rtc_scaler_start = now();
-    rtc_enabled = 1;
+  if (sis_verbose)
+    printf ("RTC started (period %d)\n\r", rtc_scaler + 1);
+  event (rtc_intr, 0, rtc_scaler + 1);
+  rtc_scaler_start = now ();
+  rtc_enabled = 1;
 }
 
 static uint32
-rtc_counter_read()
+rtc_counter_read ()
 {
-    return rtc_counter;
+  return rtc_counter;
 }
 
 static void
-rtc_scaler_set(val)
-    uint32          val;
+rtc_scaler_set (val)
+     uint32 val;
 {
-    rtc_scaler = val & 0x0ff;	/* eight-bit scaler only */
+  rtc_scaler = val & 0x0ff;	/* eight-bit scaler only */
 }
 
 static void
-rtc_reload_set(val)
-    uint32          val;
+rtc_reload_set (val)
+     uint32 val;
 {
-    rtc_reload = val;
+  rtc_reload = val;
 }
 
 static void
-gpt_intr(arg)
-    int32         arg;
+gpt_intr (arg)
+     int32 arg;
 {
-    if (gpt_counter == 0) {
-	mec_irq(12);
-	if (gpt_cr)
-	    gpt_counter = gpt_reload;
-	else
-	    gpt_se = 0;
-    } else
-	gpt_counter -= 1;
-    if (gpt_se) {
-	event(gpt_intr, 0, gpt_scaler + 1);
-	gpt_scaler_start = now();
-	gpt_enabled = 1;
-    } else {
-	if (sis_verbose)
-	    printf("GPT stopped\n\r");
-	gpt_enabled = 0;
+  if (gpt_counter == 0)
+    {
+      mec_irq (12);
+      if (gpt_cr)
+	gpt_counter = gpt_reload;
+      else
+	gpt_se = 0;
+    }
+  else
+    gpt_counter -= 1;
+  if (gpt_se)
+    {
+      event (gpt_intr, 0, gpt_scaler + 1);
+      gpt_scaler_start = now ();
+      gpt_enabled = 1;
+    }
+  else
+    {
+      if (sis_verbose)
+	printf ("GPT stopped\n\r");
+      gpt_enabled = 0;
     }
 }
 
 static void
-gpt_start()
+gpt_start ()
 {
-    if (sis_verbose)
-	printf("GPT started (period %d)\n\r", gpt_scaler + 1);
-    event(gpt_intr, 0, gpt_scaler + 1);
-    gpt_scaler_start = now();
-    gpt_enabled = 1;
+  if (sis_verbose)
+    printf ("GPT started (period %d)\n\r", gpt_scaler + 1);
+  event (gpt_intr, 0, gpt_scaler + 1);
+  gpt_scaler_start = now ();
+  gpt_enabled = 1;
 }
 
 static uint32
-gpt_counter_read()
+gpt_counter_read ()
 {
-    return gpt_counter;
+  return gpt_counter;
 }
 
 static void
-gpt_scaler_set(val)
-    uint32          val;
+gpt_scaler_set (val)
+     uint32 val;
 {
-    gpt_scaler = val & 0x0ffff;	/* 16-bit scaler */
+  gpt_scaler = val & 0x0ffff;	/* 16-bit scaler */
 }
 
 static void
-gpt_reload_set(val)
-    uint32          val;
+gpt_reload_set (val)
+     uint32 val;
 {
-    gpt_reload = val;
+  gpt_reload = val;
 }
 
 static void
-timer_ctrl(val)
-    uint32          val;
+timer_ctrl (val)
+     uint32 val;
 {
 
-    rtc_cr = ((val & TCR_TCRCR) != 0);
-    if (val & TCR_TCRCL) {
-	rtc_counter = rtc_reload;
+  rtc_cr = ((val & TCR_TCRCR) != 0);
+  if (val & TCR_TCRCL)
+    {
+      rtc_counter = rtc_reload;
     }
-    if (val & TCR_TCRSL) {
+  if (val & TCR_TCRSL)
+    {
     }
-    rtc_se = ((val & TCR_TCRSE) != 0);
-    if (rtc_se && (rtc_enabled == 0))
-	rtc_start();
-
-    gpt_cr = (val & TCR_GACR);
-    if (val & TCR_GACL) {
-	gpt_counter = gpt_reload;
+  rtc_se = ((val & TCR_TCRSE) != 0);
+  if (rtc_se && (rtc_enabled == 0))
+    rtc_start ();
+
+  gpt_cr = (val & TCR_GACR);
+  if (val & TCR_GACL)
+    {
+      gpt_counter = gpt_reload;
     }
-    if (val & TCR_GACL) {
+  if (val & TCR_GACL)
+    {
     }
-    gpt_se = (val & TCR_GASE) >> 2;
-    if (gpt_se && (gpt_enabled == 0))
-	gpt_start();
+  gpt_se = (val & TCR_GASE) >> 2;
+  if (gpt_se && (gpt_enabled == 0))
+    gpt_start ();
 }
 
 /* Store data in host byte order.  MEM points to the beginning of the
@@ -1466,241 +1615,266 @@ timer_ctrl(val)
    wait-states.  */
 
 static void
-store_bytes (char *mem, uint32 waddr, uint32 *data, int32 sz,
-	     int32 *ws)
+store_bytes (char *mem, uint32 waddr, uint32 * data, int32 sz, int32 * ws)
 {
-    switch (sz) {
-	case 0:
-	    waddr ^= EBT;
-	    mem[waddr] = *data & 0x0ff;
-	    *ws = mem_ramw_ws + 3;
-	    break;
-	case 1:
+  switch (sz)
+    {
+    case 0:
+      waddr ^= EBT;
+      mem[waddr] = *data & 0x0ff;
+      *ws = mem_ramw_ws + 3;
+      break;
+    case 1:
 #ifdef HOST_LITTLE_ENDIAN
-	    waddr ^= 2;
+      waddr ^= 2;
 #endif
-	    memcpy (&mem[waddr], data, 2);
-	    *ws = mem_ramw_ws + 3;
-	    break;
-	case 2:
-	    memcpy (&mem[waddr], data, 4);
-	    *ws = mem_ramw_ws;
-	    break;
-	case 3:
-	    memcpy (&mem[waddr], data, 8);
-	    *ws = 2 * mem_ramw_ws + STD_WS;
-	    break;
+      memcpy (&mem[waddr], data, 2);
+      *ws = mem_ramw_ws + 3;
+      break;
+    case 2:
+      memcpy (&mem[waddr], data, 4);
+      *ws = mem_ramw_ws;
+      break;
+    case 3:
+      memcpy (&mem[waddr], data, 8);
+      *ws = 2 * mem_ramw_ws + STD_WS;
+      break;
     }
 }
 
 /* Memory emulation */
 
 static int
-memory_iread (uint32 addr, uint32 *data, int32 *ws)
+memory_iread (uint32 addr, uint32 * data, int32 * ws)
 {
-    uint32          asi;
-    if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
-	memcpy (data, &ramb[addr & mem_rammask], 4);
-	*ws = mem_ramr_ws;
-	return 0;
-    } else if (addr < mem_romsz) {
-	memcpy (data, &romb[addr], 4);
-	*ws = mem_romr_ws;
-	return 0;
+  uint32 asi;
+  if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz)))
+    {
+      memcpy (data, &ramb[addr & mem_rammask], 4);
+      *ws = mem_ramr_ws;
+      return 0;
+    }
+  else if (addr < mem_romsz)
+    {
+      memcpy (data, &romb[addr], 4);
+      *ws = mem_romr_ws;
+      return 0;
     }
 
-    if (sis_verbose)
-	printf ("Memory exception at %x (illegal address)\n", addr);
-    if (sregs->psr & 0x080)
-        asi = 9;
-    else
-        asi = 8;
-    set_sfsr (UIMP_ACC, addr, asi, 1);
-    *ws = MEM_EX_WS;
-    return 1;
+  if (sis_verbose)
+    printf ("Memory exception at %x (illegal address)\n", addr);
+  if (sregs->psr & 0x080)
+    asi = 9;
+  else
+    asi = 8;
+  set_sfsr (UIMP_ACC, addr, asi, 1);
+  *ws = MEM_EX_WS;
+  return 1;
 }
 
 static int
-memory_read (uint32 addr, uint32 *data, int32 *ws)
+memory_read (uint32 addr, uint32 * data, int32 * ws)
 {
-    int32           mexc;
-    int32           asi;
-
-    if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
-	memcpy (data, &ramb[addr & mem_rammask], 4);
-	*ws = mem_ramr_ws;
-	return 0;
-    } else if ((addr >= MEC_START) && (addr < MEC_END)) {
-	asi = (sregs->psr & 0x080) ? 11 : 10;
-	mexc = mec_read(addr, asi, data);
-	if (mexc) {
-	    set_sfsr(MEC_ACC, addr, asi, 1);
-	    *ws = MEM_EX_WS;
-	} else {
-	    *ws = 0;
+  int32 mexc;
+  int32 asi;
+
+  if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz)))
+    {
+      memcpy (data, &ramb[addr & mem_rammask], 4);
+      *ws = mem_ramr_ws;
+      return 0;
+    }
+  else if ((addr >= MEC_START) && (addr < MEC_END))
+    {
+      asi = (sregs->psr & 0x080) ? 11 : 10;
+      mexc = mec_read (addr, asi, data);
+      if (mexc)
+	{
+	  set_sfsr (MEC_ACC, addr, asi, 1);
+	  *ws = MEM_EX_WS;
 	}
-	return mexc;
-    } else if (addr < mem_romsz) {
-	memcpy (data, &romb[addr], 4);
-	*ws = mem_romr_ws;
-	return 0;
+      else
+	{
+	  *ws = 0;
+	}
+      return mexc;
+    }
+  else if (addr < mem_romsz)
+    {
+      memcpy (data, &romb[addr], 4);
+      *ws = mem_romr_ws;
+      return 0;
     }
 
-    if (sis_verbose)
-	printf ("Memory exception at %x (illegal address)\n", addr);
-    asi = (sregs->psr & 0x080) ? 11 : 10;
-    set_sfsr(UIMP_ACC, addr, asi, 1);
-    *ws = MEM_EX_WS;
-    return 1;
+  if (sis_verbose)
+    printf ("Memory exception at %x (illegal address)\n", addr);
+  asi = (sregs->psr & 0x080) ? 11 : 10;
+  set_sfsr (UIMP_ACC, addr, asi, 1);
+  *ws = MEM_EX_WS;
+  return 1;
 }
 
 static int
-memory_write (uint32 addr, uint32 *data, int32 sz, int32 *ws)
+memory_write (uint32 addr, uint32 * data, int32 sz, int32 * ws)
 {
-    uint32          byte_addr;
-    uint32          byte_mask;
-    uint32          waddr;
-    uint32         *ram;
-    int32           mexc;
-    int             i;
-    int             wphit[2];
-    int             asi;
-
-    if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
-	if (mem_accprot) {
-
-	    waddr = (addr & 0x7fffff) >> 2;
-	    asi = (sregs->psr & 0x080) ? 11 : 10;
-	    for (i = 0; i < 2; i++)
-		wphit[i] =
-		    (((asi == 0xa) && (mec_wpr[i] & 1)) ||
-		     ((asi == 0xb) && (mec_wpr[i] & 2))) &&
-		    ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
-
-	    if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
-		((!mem_blockprot) &&
-		 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
-		 )) {
-		if (sis_verbose)
-		    printf("Memory access protection error at 0x%08x\n", addr);
-		set_sfsr(PROT_EXC, addr, asi, 0);
-		*ws = MEM_EX_WS;
-		return 1;
+  uint32 byte_addr;
+  uint32 byte_mask;
+  uint32 waddr;
+  uint32 *ram;
+  int32 mexc;
+  int i;
+  int wphit[2];
+  int asi;
+
+  if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz)))
+    {
+      if (mem_accprot)
+	{
+
+	  waddr = (addr & 0x7fffff) >> 2;
+	  asi = (sregs->psr & 0x080) ? 11 : 10;
+	  for (i = 0; i < 2; i++)
+	    wphit[i] =
+	      (((asi == 0xa) && (mec_wpr[i] & 1)) ||
+	       ((asi == 0xb) && (mec_wpr[i] & 2))) &&
+	      ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
+
+	  if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
+	      ((!mem_blockprot) &&
+	       !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))))
+	    {
+	      if (sis_verbose)
+		printf ("Memory access protection error at 0x%08x\n", addr);
+	      set_sfsr (PROT_EXC, addr, asi, 0);
+	      *ws = MEM_EX_WS;
+	      return 1;
 	    }
 	}
-	waddr = addr & mem_rammask;
-	store_bytes (ramb, waddr, data, sz, ws);
-	return 0;
-    } else if ((addr >= MEC_START) && (addr < MEC_END)) {
-	asi = (sregs->psr & 0x080) ? 11 : 10;
-	if ((sz != 2) || (asi != 0xb)) {
-	    set_sfsr(MEC_ACC, addr, asi, 0);
-	    *ws = MEM_EX_WS;
-	    return 1;
+      waddr = addr & mem_rammask;
+      store_bytes (ramb, waddr, data, sz, ws);
+      return 0;
+    }
+  else if ((addr >= MEC_START) && (addr < MEC_END))
+    {
+      asi = (sregs->psr & 0x080) ? 11 : 10;
+      if ((sz != 2) || (asi != 0xb))
+	{
+	  set_sfsr (MEC_ACC, addr, asi, 0);
+	  *ws = MEM_EX_WS;
+	  return 1;
+	}
+      mexc = mec_write (addr, *data);
+      if (mexc)
+	{
+	  set_sfsr (MEC_ACC, addr, asi, 0);
+	  *ws = MEM_EX_WS;
 	}
-	mexc = mec_write(addr, *data);
-	if (mexc) {
-	    set_sfsr(MEC_ACC, addr, asi, 0);
-	    *ws = MEM_EX_WS;
-	} else {
-	    *ws = 0;
+      else
+	{
+	  *ws = 0;
 	}
-	return mexc;
-    } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
-               (((mec_memcfg & 0x20000) && (sz > 1)) || 
-		(!(mec_memcfg & 0x20000) && (sz == 0)))) {
-
-	*ws = mem_romw_ws + 1;
-	if (sz == 3)
-            *ws += mem_romw_ws + STD_WS;
-	store_bytes (romb, addr, data, sz, ws);
-        return 0;
+      return mexc;
     }
-	
-    *ws = MEM_EX_WS;
-    asi = (sregs->psr & 0x080) ? 11 : 10;
-    set_sfsr(UIMP_ACC, addr, asi, 0);
-    return 1;
+  else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
+	   (((mec_memcfg & 0x20000) && (sz > 1)) ||
+	    (!(mec_memcfg & 0x20000) && (sz == 0))))
+    {
+
+      *ws = mem_romw_ws + 1;
+      if (sz == 3)
+	*ws += mem_romw_ws + STD_WS;
+      store_bytes (romb, addr, data, sz, ws);
+      return 0;
+    }
+
+  *ws = MEM_EX_WS;
+  asi = (sregs->psr & 0x080) ? 11 : 10;
+  set_sfsr (UIMP_ACC, addr, asi, 0);
+  return 1;
 }
 
-static char  *
-get_mem_ptr(addr, size)
-    uint32          addr;
-    uint32          size;
+static char *
+get_mem_ptr (addr, size)
+     uint32 addr;
+     uint32 size;
 {
-    if ((addr + size) < ROM_SIZE) {
-	return &romb[addr];
-    } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
-	return &ramb[addr & mem_rammask];
+  if ((addr + size) < ROM_SIZE)
+    {
+      return &romb[addr];
+    }
+  else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend))
+    {
+      return &ramb[addr & mem_rammask];
     }
 
-    return (char *) -1;
+  return (char *) -1;
 }
 
 static int
-sis_memory_write(addr, data, length)
-    uint32               addr;
-    const unsigned char *data;
-    uint32               length;
+sis_memory_write (addr, data, length)
+     uint32 addr;
+     const unsigned char *data;
+     uint32 length;
 {
-    char           *mem;
+  char *mem;
 
-    if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
-	return 0;
+  if ((mem = get_mem_ptr (addr, length)) == ((char *) -1))
+    return 0;
 
-    memcpy(mem, data, length);
-    return length;
+  memcpy (mem, data, length);
+  return length;
 }
 
 static int
-sis_memory_read(addr, data, length)
-    uint32          addr;
-    char           *data;
-    uint32          length;
+sis_memory_read (addr, data, length)
+     uint32 addr;
+     char *data;
+     uint32 length;
 {
-    char           *mem;
-    int            ws;
-    unsigned int   w4;
-
-    if (length == 4) {
-	memory_read (addr, &w4, &ws);
-	memcpy(data, &w4, length);
-	return 4;
+  char *mem;
+  int ws;
+  unsigned int w4;
+
+  if (length == 4)
+    {
+      memory_read (addr, &w4, &ws);
+      memcpy (data, &w4, length);
+      return 4;
     }
 
-    if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
-	return 0;
+  if ((mem = get_mem_ptr (addr, length)) == ((char *) -1))
+    return 0;
 
-    memcpy(data, mem, length);
-    return length;
+  memcpy (data, mem, length);
+  return length;
 }
 
 static void
 boot_init (void)
 {
-    mec_write(MEC_WCR, 0);	/* zero waitstates */
-    mec_write(MEC_TRAPD, 0);	/* turn off watch-dog */
-    mec_write(MEC_RTC_SCALER, ebase.freq - 1); /* generate 1 MHz RTC tick */
-    mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
-    sregs->wim = 2;
-    sregs->psr = 0x110010e0;
-    sregs->r[30] = RAM_END;
-    sregs->r[14] = sregs->r[30] - 96 * 4;
-    mec_mcr |= 1;		/* power-down enabled */
+  mec_write (MEC_WCR, 0);	/* zero waitstates */
+  mec_write (MEC_TRAPD, 0);	/* turn off watch-dog */
+  mec_write (MEC_RTC_SCALER, ebase.freq - 1);	/* generate 1 MHz RTC tick */
+  mec_write (MEC_MEMCFG, (3 << 18) | (4 << 10));	/* 1 MB ROM, 4 MB RAM */
+  sregs->wim = 2;
+  sregs->psr = 0x110010e0;
+  sregs->r[30] = RAM_END;
+  sregs->r[14] = sregs->r[30] - 96 * 4;
+  mec_mcr |= 1;			/* power-down enabled */
 }
 
 const struct memsys erc32sys = {
-    init_sim,
-    reset,
-    error_mode,
-    sim_halt,
-    exit_sim,
-    init_stdio,
-    restore_stdio,
-    memory_iread,
-    memory_read,
-    memory_write,
-    sis_memory_write,
-    sis_memory_read,
-    boot_init
+  init_sim,
+  reset,
+  error_mode,
+  sim_halt,
+  exit_sim,
+  init_stdio,
+  restore_stdio,
+  memory_iread,
+  memory_read,
+  memory_write,
+  sis_memory_write,
+  sis_memory_read,
+  boot_init
 };