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authorJiri Gaisler <jiri@gaisler.se>2019-06-11 22:30:10 +0200
committerJiri Gaisler <jiri@gaisler.se>2019-06-11 22:30:10 +0200
commit313c2c1643889a5b84dd0cff3886b22e821a5f34 (patch)
treedba621bdc66d231581eb4d34ba504c0847df3ff9
parentda44b0fa23e3a48ce1f98f7dc2b16fd91af608a9 (diff)
Fix C formatting with indent
Diffstat
-rw-r--r--erc32.c2260
-rw-r--r--exec.c171
-rw-r--r--float.c73
-rw-r--r--func.c2144
-rw-r--r--grlib.c1
-rw-r--r--grlib.h2
-rw-r--r--help.c56
-rw-r--r--interf.c340
-rw-r--r--leon2.c13
-rw-r--r--leon3.c229
-rw-r--r--remote.c9
-rw-r--r--riscv.c54
-rw-r--r--riscv.h1
-rw-r--r--sis.c477
-rw-r--r--sis.h479
-rw-r--r--sparc.c47
16 files changed, 3466 insertions, 2890 deletions
diff --git a/erc32.c b/erc32.c
index 190941e..3a7899d 100644
--- a/erc32.c
+++ b/erc32.c
@@ -131,77 +131,78 @@
/* MEC registers */
-static char fname[256];
-static uint32 mec_ssa[2]; /* Write protection start address */
-static uint32 mec_sea[2]; /* Write protection end address */
-static uint32 mec_wpr[2]; /* Write protection control fields */
-static uint32 mec_sfsr;
-static uint32 mec_ffar;
-static uint32 mec_ipr;
-static uint32 mec_imr;
-static uint32 mec_isr;
-static uint32 mec_icr;
-static uint32 mec_ifr;
-static uint32 mec_mcr; /* MEC control register */
-static uint32 mec_memcfg; /* Memory control register */
-static uint32 mec_wcr; /* MEC waitstate register */
-static uint32 mec_iocr; /* MEC IO control register */
-static uint32 posted_irq;
-static uint32 mec_ersr; /* MEC error and status register */
-static uint32 mec_tcr; /* MEC test comtrol register */
-
-static uint32 rtc_counter;
-static uint32 rtc_reload;
-static uint32 rtc_scaler;
-static uint32 rtc_scaler_start;
-static uint32 rtc_enabled;
-static uint32 rtc_cr;
-static uint32 rtc_se;
-
-static uint32 gpt_counter;
-static uint32 gpt_reload;
-static uint32 gpt_scaler;
-static uint32 gpt_scaler_start;
-static uint32 gpt_enabled;
-static uint32 gpt_cr;
-static uint32 gpt_se;
-
-static uint32 wdog_scaler;
-static uint32 wdog_counter;
-static uint32 wdog_rst_delay;
-static uint32 wdog_rston;
-
-enum wdog_type {
- init, disabled, enabled, stopped
+static char fname[256];
+static uint32 mec_ssa[2]; /* Write protection start address */
+static uint32 mec_sea[2]; /* Write protection end address */
+static uint32 mec_wpr[2]; /* Write protection control fields */
+static uint32 mec_sfsr;
+static uint32 mec_ffar;
+static uint32 mec_ipr;
+static uint32 mec_imr;
+static uint32 mec_isr;
+static uint32 mec_icr;
+static uint32 mec_ifr;
+static uint32 mec_mcr; /* MEC control register */
+static uint32 mec_memcfg; /* Memory control register */
+static uint32 mec_wcr; /* MEC waitstate register */
+static uint32 mec_iocr; /* MEC IO control register */
+static uint32 posted_irq;
+static uint32 mec_ersr; /* MEC error and status register */
+static uint32 mec_tcr; /* MEC test comtrol register */
+
+static uint32 rtc_counter;
+static uint32 rtc_reload;
+static uint32 rtc_scaler;
+static uint32 rtc_scaler_start;
+static uint32 rtc_enabled;
+static uint32 rtc_cr;
+static uint32 rtc_se;
+
+static uint32 gpt_counter;
+static uint32 gpt_reload;
+static uint32 gpt_scaler;
+static uint32 gpt_scaler_start;
+static uint32 gpt_enabled;
+static uint32 gpt_cr;
+static uint32 gpt_se;
+
+static uint32 wdog_scaler;
+static uint32 wdog_counter;
+static uint32 wdog_rst_delay;
+static uint32 wdog_rston;
+
+enum wdog_type
+{
+ init, disabled, enabled, stopped
};
static enum wdog_type wdog_status;
/* Memory support variables */
-static uint32 mem_ramr_ws; /* RAM read waitstates */
-static uint32 mem_ramw_ws; /* RAM write waitstates */
-static uint32 mem_romr_ws; /* ROM read waitstates */
-static uint32 mem_romw_ws; /* ROM write waitstates */
-static uint32 mem_ramstart; /* RAM start */
-static uint32 mem_ramend; /* RAM end */
-static uint32 mem_rammask; /* RAM address mask */
-static uint32 mem_ramsz; /* RAM size */
-static uint32 mem_romsz; /* ROM size */
-static uint32 mem_accprot; /* RAM write protection enabled */
-static uint32 mem_blockprot; /* RAM block write protection enabled */
+static uint32 mem_ramr_ws; /* RAM read waitstates */
+static uint32 mem_ramw_ws; /* RAM write waitstates */
+static uint32 mem_romr_ws; /* ROM read waitstates */
+static uint32 mem_romw_ws; /* ROM write waitstates */
+static uint32 mem_ramstart; /* RAM start */
+static uint32 mem_ramend; /* RAM end */
+static uint32 mem_rammask; /* RAM address mask */
+static uint32 mem_ramsz; /* RAM size */
+static uint32 mem_romsz; /* ROM size */
+static uint32 mem_accprot; /* RAM write protection enabled */
+static uint32 mem_blockprot; /* RAM block write protection enabled */
/* UART support variables */
-static int32 fd1, fd2; /* file descriptor for input file */
-static int32 Ucontrol; /* UART status register */
+static int32 fd1, fd2; /* file descriptor for input file */
+static int32 Ucontrol; /* UART status register */
static unsigned char aq[UARTBUF], bq[UARTBUF];
-static int32 anum, aind = 0;
-static int32 bnum, bind = 0;
-static char wbufa[UARTBUF], wbufb[UARTBUF];
+static int32 anum, aind = 0;
+static int32 bnum, bind = 0;
+static char wbufa[UARTBUF], wbufb[UARTBUF];
static unsigned wnuma;
static unsigned wnumb;
-static FILE *f1in, *f1out, *f2in, *f2out;
+static FILE *f1in, *f1out, *f2in, *f2out;
#ifdef HAVE_TERMIOS_H
static struct termios ioc1, ioc2, iocold1, iocold2;
#endif
@@ -209,669 +210,726 @@ static struct termios ioc1, ioc2, iocold1, iocold2;
#define O_NONBLOCK 0
#endif
-static int f1open = 0, f2open = 0;
+static int f1open = 0, f2open = 0;
-static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
-static uint32 uart_stat_reg;
-static uint32 uarta_data, uartb_data;
+static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
+static uint32 uart_stat_reg;
+static uint32 uarta_data, uartb_data;
/* Forward declarations */
-static void decode_ersr (void);
-static void mecparerror (void);
-static void decode_memcfg (void);
-static void decode_wcr (void);
-static void decode_mcr (void);
-static void close_port (void);
-static void mec_reset (void);
-static void mec_intack (int32 level);
-static void chk_irq (void);
-static void mec_irq (int32 level);
-static void set_sfsr (uint32 fault, uint32 addr,
- uint32 asi, uint32 read);
-static int32 mec_read (uint32 addr, uint32 asi, uint32 *data);
-static int mec_write (uint32 addr, uint32 data);
-static void port_init (void);
-static uint32 read_uart (uint32 addr);
-static void write_uart (uint32 addr, uint32 data);
-static void flush_uart (void);
-static void uarta_tx (void);
-static void uartb_tx (void);
-static void uart_rx (int32 arg);
-static void uart_intr (int32 arg);
-static void uart_irq_start (void);
-static void wdog_intr (int32 arg);
-static void wdog_start (void);
-static void rtc_intr (int32 arg);
-static void rtc_start (void);
-static uint32 rtc_counter_read (void);
-static void rtc_scaler_set (uint32 val);
-static void rtc_reload_set (uint32 val);
-static void gpt_intr (int32 arg);
-static void gpt_start (void);
-static uint32 gpt_counter_read (void);
-static void gpt_scaler_set (uint32 val);
-static void gpt_reload_set (uint32 val);
-static void timer_ctrl (uint32 val);
-static char *get_mem_ptr (uint32 addr, uint32 size);
-static void store_bytes (char *mem, uint32 waddr,
- uint32 *data, int sz, int32 *ws);
+static void decode_ersr (void);
+static void mecparerror (void);
+static void decode_memcfg (void);
+static void decode_wcr (void);
+static void decode_mcr (void);
+static void close_port (void);
+static void mec_reset (void);
+static void mec_intack (int32 level);
+static void chk_irq (void);
+static void mec_irq (int32 level);
+static void set_sfsr (uint32 fault, uint32 addr, uint32 asi, uint32 read);
+static int32 mec_read (uint32 addr, uint32 asi, uint32 * data);
+static int mec_write (uint32 addr, uint32 data);
+static void port_init (void);
+static uint32 read_uart (uint32 addr);
+static void write_uart (uint32 addr, uint32 data);
+static void flush_uart (void);
+static void uarta_tx (void);
+static void uartb_tx (void);
+static void uart_rx (int32 arg);
+static void uart_intr (int32 arg);
+static void uart_irq_start (void);
+static void wdog_intr (int32 arg);
+static void wdog_start (void);
+static void rtc_intr (int32 arg);
+static void rtc_start (void);
+static uint32 rtc_counter_read (void);
+static void rtc_scaler_set (uint32 val);
+static void rtc_reload_set (uint32 val);
+static void gpt_intr (int32 arg);
+static void gpt_start (void);
+static uint32 gpt_counter_read (void);
+static void gpt_scaler_set (uint32 val);
+static void gpt_reload_set (uint32 val);
+static void timer_ctrl (uint32 val);
+static char *get_mem_ptr (uint32 addr, uint32 size);
+static void store_bytes (char *mem, uint32 waddr,
+ uint32 * data, int sz, int32 * ws);
/* One-time init */
static void
-init_sim()
+init_sim ()
{
- port_init();
- ebase.ramstart = RAM_START;
+ port_init ();
+ ebase.ramstart = RAM_START;
}
/* Power-on reset init */
static void
-reset()
+reset ()
{
- mec_reset();
- uart_irq_start();
- wdog_start();
- sregs[0].intack = mec_intack;
+ mec_reset ();
+ uart_irq_start ();
+ wdog_start ();
+ sregs[0].intack = mec_intack;
}
static void
-decode_ersr()
+decode_ersr ()
{
- if (mec_ersr & 0x01) {
- if (!(mec_mcr & 0x20)) {
- if (mec_mcr & 0x40) {
- sys_reset();
- mec_ersr = 0x8000;
- if (sis_verbose)
- printf("Error manager reset - IU in error mode\n");
- } else {
- sys_halt();
- mec_ersr |= 0x2000;
- if (sis_verbose)
- printf("Error manager halt - IU in error mode\n");
+ if (mec_ersr & 0x01)
+ {
+ if (!(mec_mcr & 0x20))
+ {
+ if (mec_mcr & 0x40)
+ {
+ sys_reset ();
+ mec_ersr = 0x8000;
+ if (sis_verbose)
+ printf ("Error manager reset - IU in error mode\n");
+ }
+ else
+ {
+ sys_halt ();
+ mec_ersr |= 0x2000;
+ if (sis_verbose)
+ printf ("Error manager halt - IU in error mode\n");
}
- } else
- mec_irq(1);
+ }
+ else
+ mec_irq (1);
}
- if (mec_ersr & 0x04) {
- if (!(mec_mcr & 0x200)) {
- if (mec_mcr & 0x400) {
- sys_reset();
- mec_ersr = 0x8000;
- if (sis_verbose)
- printf("Error manager reset - IU comparison error\n");
- } else {
- sys_halt();
- mec_ersr |= 0x2000;
- if (sis_verbose)
- printf("Error manager halt - IU comparison error\n");
+ if (mec_ersr & 0x04)
+ {
+ if (!(mec_mcr & 0x200))
+ {
+ if (mec_mcr & 0x400)
+ {
+ sys_reset ();
+ mec_ersr = 0x8000;
+ if (sis_verbose)
+ printf ("Error manager reset - IU comparison error\n");
+ }
+ else
+ {
+ sys_halt ();
+ mec_ersr |= 0x2000;
+ if (sis_verbose)
+ printf ("Error manager halt - IU comparison error\n");
}
- } else
- mec_irq(1);
+ }
+ else
+ mec_irq (1);
}
- if (mec_ersr & 0x20) {
- if (!(mec_mcr & 0x2000)) {
- if (mec_mcr & 0x4000) {
- sys_reset();
- mec_ersr = 0x8000;
- if (sis_verbose)
- printf("Error manager reset - MEC hardware error\n");
- } else {
- sys_halt();
- mec_ersr |= 0x2000;
- if (sis_verbose)
- printf("Error manager halt - MEC hardware error\n");
+ if (mec_ersr & 0x20)
+ {
+ if (!(mec_mcr & 0x2000))
+ {
+ if (mec_mcr & 0x4000)
+ {
+ sys_reset ();
+ mec_ersr = 0x8000;
+ if (sis_verbose)
+ printf ("Error manager reset - MEC hardware error\n");
+ }
+ else
+ {
+ sys_halt ();
+ mec_ersr |= 0x2000;
+ if (sis_verbose)
+ printf ("Error manager halt - MEC hardware error\n");
}
- } else
- mec_irq(1);
+ }
+ else
+ mec_irq (1);
}
}
static void
-mecparerror()
+mecparerror ()
{
- mec_ersr |= 0x20;
- decode_ersr();
+ mec_ersr |= 0x20;
+ decode_ersr ();
}
/* IU error mode manager */
static void
-error_mode(pc)
- uint32 pc;
+error_mode (pc)
+ uint32 pc;
{
- mec_ersr |= 0x1;
- decode_ersr();
+ mec_ersr |= 0x1;
+ decode_ersr ();
}
/* Check memory settings */
static void
-decode_memcfg()
+decode_memcfg ()
{
- if (rom8) mec_memcfg &= ~0x20000;
- else mec_memcfg |= 0x20000;
+ if (rom8)
+ mec_memcfg &= ~0x20000;
+ else
+ mec_memcfg |= 0x20000;
- mem_ramsz = (1024 * 1024) << ((mec_memcfg >> 10) & 7);
- mem_romsz = (2 *1024 * 1024) << ((mec_memcfg >> 18) & 7);
+ mem_ramsz = (1024 * 1024) << ((mec_memcfg >> 10) & 7);
+ mem_romsz = (2 * 1024 * 1024) << ((mec_memcfg >> 18) & 7);
- mem_ramstart = RAM_START;
- mem_ramend = RAM_END;
- mem_rammask = RAM_MASK;
+ mem_ramstart = RAM_START;
+ mem_ramend = RAM_END;
+ mem_rammask = RAM_MASK;
- if (sis_verbose)
- printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
- mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
+ if (sis_verbose)
+ printf ("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
+ mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
}
static void
-decode_wcr()
+decode_wcr ()
{
- mem_ramr_ws = mec_wcr & 3;
- mem_ramw_ws = (mec_wcr >> 2) & 3;
- mem_romr_ws = (mec_wcr >> 4) & 0x0f;
- if (rom8) {
- if (mem_romr_ws > 0 ) mem_romr_ws--;
- mem_romr_ws = 5 + (4*mem_romr_ws);
+ mem_ramr_ws = mec_wcr & 3;
+ mem_ramw_ws = (mec_wcr >> 2) & 3;
+ mem_romr_ws = (mec_wcr >> 4) & 0x0f;
+ if (rom8)
+ {
+ if (mem_romr_ws > 0)
+ mem_romr_ws--;
+ mem_romr_ws = 5 + (4 * mem_romr_ws);
}
- mem_romw_ws = (mec_wcr >> 8) & 0x0f;
- if (sis_verbose)
- printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
- mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
+ mem_romw_ws = (mec_wcr >> 8) & 0x0f;
+ if (sis_verbose)
+ printf
+ ("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
+ mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
}
static void
-decode_mcr()
+decode_mcr ()
{
- mem_accprot = (mec_wpr[0] | mec_wpr[1]);
- mem_blockprot = (mec_mcr >> 3) & 1;
- if (sis_verbose && mem_accprot)
- printf("Memory block write protection enabled\n");
- if (mec_mcr & 0x08000) {
- mec_ersr |= 0x20;
- decode_ersr();
+ mem_accprot = (mec_wpr[0] | mec_wpr[1]);
+ mem_blockprot = (mec_mcr >> 3) & 1;
+ if (sis_verbose && mem_accprot)
+ printf ("Memory block write protection enabled\n");
+ if (mec_mcr & 0x08000)
+ {
+ mec_ersr |= 0x20;
+ decode_ersr ();
}
- if (sis_verbose && (mec_mcr & 2))
- printf("Software reset enabled\n");
- if (sis_verbose && (mec_mcr & 1))
- printf("Power-down mode enabled\n");
+ if (sis_verbose && (mec_mcr & 2))
+ printf ("Software reset enabled\n");
+ if (sis_verbose && (mec_mcr & 1))
+ printf ("Power-down mode enabled\n");
}
/* Flush ports when simulator stops */
static void
-sim_halt()
+sim_halt ()
{
#ifdef FAST_UART
- flush_uart();
+ flush_uart ();
#endif
}
static void
-close_port()
+close_port ()
{
- if (f1open && f1in != stdin)
- fclose(f1in);
- if (f2open && f2in != stdin)
- fclose(f2in);
+ if (f1open && f1in != stdin)
+ fclose (f1in);
+ if (f2open && f2in != stdin)
+ fclose (f2in);
}
static void
-exit_sim()
+exit_sim ()
{
- close_port();
+ close_port ();
}
static void
-mec_reset()
+mec_reset ()
{
- int i;
-
- for (i = 0; i < 2; i++)
- mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
- mec_mcr = 0x01350014;
- mec_iocr = 0;
- mec_sfsr = 0x078;
- mec_ffar = 0;
- mec_ipr = 0;
- mec_imr = 0x7ffe;
- mec_isr = 0;
- mec_icr = 0;
- mec_ifr = 0;
- mec_memcfg = 0x10000;
- mec_wcr = -1;
- mec_ersr = 0; /* MEC error and status register */
- mec_tcr = 0; /* MEC test comtrol register */
-
- decode_memcfg();
- decode_wcr();
- decode_mcr();
-
- posted_irq = 0;
- wnuma = wnumb = 0;
- anum = aind = bnum = bind = 0;
-
- uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
- uarta_data = uartb_data = UART_THE | UART_TSE;
-
- rtc_counter = 0xffffffff;
- rtc_reload = 0xffffffff;
- rtc_scaler = 0xff;
- rtc_enabled = 0;
- rtc_cr = 0;
- rtc_se = 0;
-
- gpt_counter = 0xffffffff;
- gpt_reload = 0xffffffff;
- gpt_scaler = 0xffff;
- gpt_enabled = 0;
- gpt_cr = 0;
- gpt_se = 0;
-
- wdog_scaler = 255;
- wdog_rst_delay = 255;
- wdog_counter = 0xffff;
- wdog_rston = 0;
- wdog_status = init;
+ int i;
+
+ for (i = 0; i < 2; i++)
+ mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
+ mec_mcr = 0x01350014;
+ mec_iocr = 0;
+ mec_sfsr = 0x078;
+ mec_ffar = 0;
+ mec_ipr = 0;
+ mec_imr = 0x7ffe;
+ mec_isr = 0;
+ mec_icr = 0;
+ mec_ifr = 0;
+ mec_memcfg = 0x10000;
+ mec_wcr = -1;
+ mec_ersr = 0; /* MEC error and status register */
+ mec_tcr = 0; /* MEC test comtrol register */
+
+ decode_memcfg ();
+ decode_wcr ();
+ decode_mcr ();
+
+ posted_irq = 0;
+ wnuma = wnumb = 0;
+ anum = aind = bnum = bind = 0;
+
+ uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
+ uarta_data = uartb_data = UART_THE | UART_TSE;
+
+ rtc_counter = 0xffffffff;
+ rtc_reload = 0xffffffff;
+ rtc_scaler = 0xff;
+ rtc_enabled = 0;
+ rtc_cr = 0;
+ rtc_se = 0;
+
+ gpt_counter = 0xffffffff;
+ gpt_reload = 0xffffffff;
+ gpt_scaler = 0xffff;
+ gpt_enabled = 0;
+ gpt_cr = 0;
+ gpt_se = 0;
+
+ wdog_scaler = 255;
+ wdog_rst_delay = 255;
+ wdog_counter = 0xffff;
+ wdog_rston = 0;
+ wdog_status = init;
}
static void
-mec_intack(level)
- int32 level;
+mec_intack (level)
+ int32 level;
{
- int irq_test;
-
- if (sis_verbose)
- printf("interrupt %d acknowledged\n", level);
- irq_test = mec_tcr & 0x80000;
- if ((irq_test) && (mec_ifr & (1 << level)))
- mec_ifr &= ~(1 << level);
- else
- mec_ipr &= ~(1 << level);
- chk_irq();
+ int irq_test;
+
+ if (sis_verbose)
+ printf ("interrupt %d acknowledged\n", level);
+ irq_test = mec_tcr & 0x80000;
+ if ((irq_test) && (mec_ifr & (1 << level)))
+ mec_ifr &= ~(1 << level);
+ else
+ mec_ipr &= ~(1 << level);
+ chk_irq ();
}
static void
-chk_irq()
+chk_irq ()
{
- int32 i;
- uint32 itmp;
- int old_irl;
-
- old_irl = ext_irl[0];
- if (mec_tcr & 0x80000) itmp = mec_ifr;
- else itmp = 0;
- itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
- ext_irl[0] = 0;
- if (itmp != 0) {
- for (i = 15; i > 0; i--) {
- if (((itmp >> i) & 1) != 0) {
- if ((sis_verbose) && (i > old_irl))
- printf("IU irl: %d\n", i);
- ext_irl[0] = i;
- break;
+ int32 i;
+ uint32 itmp;
+ int old_irl;
+
+ old_irl = ext_irl[0];
+ if (mec_tcr & 0x80000)
+ itmp = mec_ifr;
+ else
+ itmp = 0;
+ itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
+ ext_irl[0] = 0;
+ if (itmp != 0)
+ {
+ for (i = 15; i > 0; i--)
+ {
+ if (((itmp >> i) & 1) != 0)
+ {
+ if ((sis_verbose) && (i > old_irl))
+ printf ("IU irl: %d\n", i);
+ ext_irl[0] = i;
+ break;
}
}
}
}
static void
-mec_irq(level)
- int32 level;
+mec_irq (level)
+ int32 level;
{
- mec_ipr |= (1 << level);
- chk_irq();
+ mec_ipr |= (1 << level);
+ chk_irq ();
}
static void
-set_sfsr(fault, addr, asi, read)
- uint32 fault;
- uint32 addr;
- uint32 asi;
- uint32 read;
+set_sfsr (fault, addr, asi, read)
+ uint32 fault;
+ uint32 addr;
+ uint32 asi;
+ uint32 read;
{
- if ((asi == 0xa) || (asi == 0xb)) {
- mec_ffar = addr;
- mec_sfsr = (fault << 3) | (!read << 15);
- mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
- switch (asi) {
+ if ((asi == 0xa) || (asi == 0xb))
+ {
+ mec_ffar = addr;
+ mec_sfsr = (fault << 3) | (!read << 15);
+ mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
+ switch (asi)
+ {
case 0xa:
- mec_sfsr |= 0x0004;
- break;
+ mec_sfsr |= 0x0004;
+ break;
case 0xb:
- mec_sfsr |= 0x1004;
- break;
+ mec_sfsr |= 0x1004;
+ break;
}
}
}
static int32
-mec_read(addr, asi, data)
- uint32 addr;
- uint32 asi;
- uint32 *data;
+mec_read (addr, asi, data)
+ uint32 addr;
+ uint32 asi;
+ uint32 *data;
{
- switch (addr & 0x0ff) {
+ switch (addr & 0x0ff)
+ {
case MEC_MCR: /* 0x00 */
- *data = mec_mcr;
- break;
+ *data = mec_mcr;
+ break;
case MEC_MEMCFG: /* 0x10 */
- *data = mec_memcfg;
- break;
+ *data = mec_memcfg;
+ break;
case MEC_IOCR:
- *data = mec_iocr; /* 0x14 */
- break;
+ *data = mec_iocr; /* 0x14 */
+ break;
case MEC_SSA1: /* 0x20 */
- *data = mec_ssa[0] | (mec_wpr[0] << 23);
- break;
+ *data = mec_ssa[0] | (mec_wpr[0] << 23);
+ break;
case MEC_SEA1: /* 0x24 */
- *data = mec_sea[0];
- break;
+ *data = mec_sea[0];
+ break;
case MEC_SSA2: /* 0x28 */
- *data = mec_ssa[1] | (mec_wpr[1] << 23);
- break;
+ *data = mec_ssa[1] | (mec_wpr[1] << 23);
+ break;
case MEC_SEA2: /* 0x2c */
- *data = mec_sea[1];
- break;
+ *data = mec_sea[1];
+ break;
case MEC_ISR: /* 0x44 */
- *data = mec_isr;
- break;
+ *data = mec_isr;
+ break;
case MEC_IPR: /* 0x48 */
- *data = mec_ipr;
- break;
+ *data = mec_ipr;
+ break;
case MEC_IMR: /* 0x4c */
- *data = mec_imr;
- break;
+ *data = mec_imr;
+ break;
case MEC_IFR: /* 0x54 */
- *data = mec_ifr;
- break;
+ *data = mec_ifr;
+ break;
case MEC_RTC_COUNTER: /* 0x80 */
- *data = rtc_counter_read();
- break;
+ *data = rtc_counter_read ();
+ break;
case MEC_RTC_SCALER: /* 0x84 */
- if (rtc_enabled)
- *data = rtc_scaler - (now() - rtc_scaler_start);
- else
- *data = rtc_scaler;
- break;
+ if (rtc_enabled)
+ *data = rtc_scaler - (now () - rtc_scaler_start);
+ else
+ *data = rtc_scaler;
+ break;
case MEC_GPT_COUNTER: /* 0x88 */
- *data = gpt_counter_read();
- break;
+ *data = gpt_counter_read ();
+ break;
case MEC_GPT_SCALER: /* 0x8c */
- if (rtc_enabled)
- *data = gpt_scaler - (now() - gpt_scaler_start);
- else
- *data = gpt_scaler;
- break;
+ if (rtc_enabled)
+ *data = gpt_scaler - (now () - gpt_scaler_start);
+ else
+ *data = gpt_scaler;
+ break;
case MEC_SFSR: /* 0xA0 */
- *data = mec_sfsr;
- break;
+ *data = mec_sfsr;
+ break;
case MEC_FFAR: /* 0xA4 */
- *data = mec_ffar;
- break;
+ *data = mec_ffar;
+ break;
case MEC_ERSR: /* 0xB0 */
- *data = mec_ersr;
- break;
+ *data = mec_ersr;
+ break;
case MEC_TCR: /* 0xD0 */
- *data = mec_tcr;
- break;
+ *data = mec_tcr;
+ break;
case MEC_UARTA: /* 0xE0 */
case MEC_UARTB: /* 0xE4 */
- if (asi != 0xb) {
- set_sfsr(MEC_ACC, addr, asi, 1);
- return 1;
+ if (asi != 0xb)
+ {
+ set_sfsr (MEC_ACC, addr, asi, 1);
+ return 1;
}
- *data = read_uart(addr);
- break;
+ *data = read_uart (addr);
+ break;
- case MEC_UART_CTRL: /* 0xE8 */
+ case MEC_UART_CTRL: /* 0xE8 */
- *data = read_uart(addr);
- break;
+ *data = read_uart (addr);
+ break;
default:
- set_sfsr(MEC_ACC, addr, asi, 1);
- return 1;
- break;
+ set_sfsr (MEC_ACC, addr, asi, 1);
+ return 1;
+ break;
}
- return MOK;
+ return MOK;
}
static int
-mec_write(addr, data)
- uint32 addr;
- uint32 data;
+mec_write (addr, data)
+ uint32 addr;
+ uint32 data;
{
- if (sis_verbose > 1)
- printf("MEC write a: %08x, d: %08x\n",addr,data);
- switch (addr & 0x0ff) {
+ if (sis_verbose > 1)
+ printf ("MEC write a: %08x, d: %08x\n", addr, data);
+ switch (addr & 0x0ff)
+ {
case MEC_MCR:
- mec_mcr = data;
- decode_mcr();
- if (mec_mcr & 0x08000) mecparerror();
- break;
+ mec_mcr = data;
+ decode_mcr ();
+ if (mec_mcr & 0x08000)
+ mecparerror ();
+ break;
case MEC_SFR:
- if (mec_mcr & 0x2) {
- sys_reset();
- mec_ersr = 0x4000;
- if (sis_verbose)
- printf(" Software reset issued\n");
+ if (mec_mcr & 0x2)
+ {
+ sys_reset ();
+ mec_ersr = 0x4000;
+ if (sis_verbose)
+ printf (" Software reset issued\n");
}
- break;
+ break;
case MEC_IOCR:
- mec_iocr = data;
- if (mec_iocr & 0xC0C0C0C0) mecparerror();
- break;
+ mec_iocr = data;
+ if (mec_iocr & 0xC0C0C0C0)
+ mecparerror ();
+ break;
case MEC_SSA1: /* 0x20 */
- if (data & 0xFE000000) mecparerror();
- mec_ssa[0] = data & 0x7fffff;
- mec_wpr[0] = (data >> 23) & 0x03;
- mem_accprot = mec_wpr[0] || mec_wpr[1];
- if (sis_verbose && mec_wpr[0])
- printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
- mec_ssa[0] << 2, mec_sea[0] << 2);
- break;
+ if (data & 0xFE000000)
+ mecparerror ();
+ mec_ssa[0] = data & 0x7fffff;
+ mec_wpr[0] = (data >> 23) & 0x03;
+ mem_accprot = mec_wpr[0] || mec_wpr[1];
+ if (sis_verbose && mec_wpr[0])
+ printf ("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
+ mec_ssa[0] << 2, mec_sea[0] << 2);
+ break;
case MEC_SEA1: /* 0x24 */
- if (data & 0xFF800000) mecparerror();
- mec_sea[0] = data & 0x7fffff;
- break;
+ if (data & 0xFF800000)
+ mecparerror ();
+ mec_sea[0] = data & 0x7fffff;
+ break;
case MEC_SSA2: /* 0x28 */
- if (data & 0xFE000000) mecparerror();
- mec_ssa[1] = data & 0x7fffff;
- mec_wpr[1] = (data >> 23) & 0x03;
- mem_accprot = mec_wpr[0] || mec_wpr[1];
- if (sis_verbose && mec_wpr[1])
- printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
- mec_ssa[1] << 2, mec_sea[1] << 2);
- break;
+ if (data & 0xFE000000)
+ mecparerror ();
+ mec_ssa[1] = data & 0x7fffff;
+ mec_wpr[1] = (data >> 23) & 0x03;
+ mem_accprot = mec_wpr[0] || mec_wpr[1];
+ if (sis_verbose && mec_wpr[1])
+ printf ("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
+ mec_ssa[1] << 2, mec_sea[1] << 2);
+ break;
case MEC_SEA2: /* 0x2c */
- if (data & 0xFF800000) mecparerror();
- mec_sea[1] = data & 0x7fffff;
- break;
+ if (data & 0xFF800000)
+ mecparerror ();
+ mec_sea[1] = data & 0x7fffff;
+ break;
case MEC_UARTA:
case MEC_UARTB:
- if (data & 0xFFFFFF00) mecparerror();
+ if (data & 0xFFFFFF00)
+ mecparerror ();
case MEC_UART_CTRL:
- if (data & 0xFF00FF00) mecparerror();
- write_uart(addr, data);
- break;
+ if (data & 0xFF00FF00)
+ mecparerror ();
+ write_uart (addr, data);
+ break;
case MEC_GPT_RELOAD:
- gpt_reload_set(data);
- break;
+ gpt_reload_set (data);
+ break;
case MEC_GPT_SCALER:
- if (data & 0xFFFF0000) mecparerror();
- gpt_scaler_set(data);
- break;
+ if (data & 0xFFFF0000)
+ mecparerror ();
+ gpt_scaler_set (data);
+ break;
case MEC_TIMER_CTRL:
- if (data & 0xFFFFF0F0) mecparerror();
- timer_ctrl(data);
- break;
+ if (data & 0xFFFFF0F0)
+ mecparerror ();
+ timer_ctrl (data);
+ break;
case MEC_RTC_RELOAD:
- rtc_reload_set(data);
- break;
+ rtc_reload_set (data);
+ break;
case MEC_RTC_SCALER:
- if (data & 0xFFFFFF00) mecparerror();
- rtc_scaler_set(data);
- break;
+ if (data & 0xFFFFFF00)
+ mecparerror ();
+ rtc_scaler_set (data);
+ break;
case MEC_SFSR: /* 0xA0 */
- if (data & 0xFFFF0880) mecparerror();
- mec_sfsr = 0x78;
- break;
+ if (data & 0xFFFF0880)
+ mecparerror ();
+ mec_sfsr = 0x78;
+ break;
case MEC_ISR:
- if (data & 0xFFFFE000) mecparerror();
- mec_isr = data;
- break;
+ if (data & 0xFFFFE000)
+ mecparerror ();
+ mec_isr = data;
+ break;
case MEC_IMR: /* 0x4c */
- if (data & 0xFFFF8001) mecparerror();
- mec_imr = data & 0x7ffe;
- chk_irq();
- break;
+ if (data & 0xFFFF8001)
+ mecparerror ();
+ mec_imr = data & 0x7ffe;
+ chk_irq ();
+ break;
case MEC_ICR: /* 0x50 */
- if (data & 0xFFFF0001) mecparerror();
- mec_ipr &= ~data & 0x0fffe;
- chk_irq();
- break;
+ if (data & 0xFFFF0001)
+ mecparerror ();
+ mec_ipr &= ~data & 0x0fffe;
+ chk_irq ();
+ break;
case MEC_IFR: /* 0x54 */
- if (mec_tcr & 0x080000) {
- if (data & 0xFFFF0001) mecparerror();
- mec_ifr = data & 0xfffe;
- chk_irq();
+ if (mec_tcr & 0x080000)
+ {
+ if (data & 0xFFFF0001)
+ mecparerror ();
+ mec_ifr = data & 0xfffe;
+ chk_irq ();
}
- break;
+ break;
case MEC_MEMCFG: /* 0x10 */
- if (data & 0xC0E08000) mecparerror();
- mec_memcfg = data;
- decode_memcfg();
- if (mec_memcfg & 0xc0e08000)
- mecparerror();
- break;
+ if (data & 0xC0E08000)
+ mecparerror ();
+ mec_memcfg = data;
+ decode_memcfg ();
+ if (mec_memcfg & 0xc0e08000)
+ mecparerror ();
+ break;
case MEC_WCR: /* 0x18 */
- mec_wcr = data;
- decode_wcr();
- break;
+ mec_wcr = data;
+ decode_wcr ();
+ break;
case MEC_ERSR: /* 0xB0 */
- if (mec_tcr & 0x100000)
- if (data & 0xFFFFEFC0) mecparerror();
- mec_ersr = data & 0x103f;
- break;
+ if (mec_tcr & 0x100000)
+ if (data & 0xFFFFEFC0)
+ mecparerror ();
+ mec_ersr = data & 0x103f;
+ break;
case MEC_TCR: /* 0xD0 */
- if (data & 0xFFE1FFC0) mecparerror();
- mec_tcr = data & 0x1e003f;
- break;
+ if (data & 0xFFE1FFC0)
+ mecparerror ();
+ mec_tcr = data & 0x1e003f;
+ break;
case MEC_WDOG: /* 0x60 */
- wdog_scaler = (data >> 16) & 0x0ff;
- wdog_counter = data & 0x0ffff;
- wdog_rst_delay = data >> 24;
- wdog_rston = 0;
- if (wdog_status == stopped)
- wdog_start();
- wdog_status = enabled;
- break;
+ wdog_scaler = (data >> 16) & 0x0ff;
+ wdog_counter = data & 0x0ffff;
+ wdog_rst_delay = data >> 24;
+ wdog_rston = 0;
+ if (wdog_status == stopped)
+ wdog_start ();
+ wdog_status = enabled;
+ break;
case MEC_TRAPD: /* 0x64 */
- if (wdog_status == init) {
- wdog_status = disabled;
- if (sis_verbose)
- printf("Watchdog disabled\n");
+ if (wdog_status == init)
+ {
+ wdog_status = disabled;
+ if (sis_verbose)
+ printf ("Watchdog disabled\n");
}
- break;
+ break;
case MEC_PWDR:
- if (mec_mcr & 1)
- sregs->pwd_mode = 1;
- sregs->pwdstart = sregs->simtime;
- break;
+ if (mec_mcr & 1)
+ sregs->pwd_mode = 1;
+ sregs->pwdstart = sregs->simtime;
+ break;
default:
- set_sfsr(MEC_ACC, addr, 0xb, 0);
- return 1;
- break;
+ set_sfsr (MEC_ACC, addr, 0xb, 0);
+ return 1;
+ break;
}
- return MOK;
+ return MOK;
}
/* MEC UARTS */
-static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
+static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
static void
-init_stdio()
+init_stdio ()
{
- if (dumbio)
- return; /* do nothing */
+ if (dumbio)
+ return; /* do nothing */
#ifdef HAVE_TERMIOS_H
- if (ifd1 == 0 && f1open) {
- tcsetattr(0, TCSANOW, &ioc1);
- tcflush (ifd1, TCIFLUSH);
+ if (ifd1 == 0 && f1open)
+ {
+ tcsetattr (0, TCSANOW, &ioc1);
+ tcflush (ifd1, TCIFLUSH);
}
- if (ifd2 == 0 && f1open) {
- tcsetattr(0, TCSANOW, &ioc2);
- tcflush (ifd2, TCIFLUSH);
+ if (ifd2 == 0 && f1open)
+ {
+ tcsetattr (0, TCSANOW, &ioc2);
+ tcflush (ifd2, TCIFLUSH);
}
#endif
}
static void
-restore_stdio()
+restore_stdio ()
{
- if (dumbio)
- return; /* do nothing */
+ if (dumbio)
+ return; /* do nothing */
#ifdef HAVE_TERMIOS_H
- if (ifd1 == 0 && f1open && tty_setup)
- tcsetattr(0, TCSANOW, &iocold1);
- if (ifd2 == 0 && f2open && tty_setup)
- tcsetattr(0, TCSANOW, &iocold2);
+ if (ifd1 == 0 && f1open && tty_setup)
+ tcsetattr (0, TCSANOW, &iocold1);
+ if (ifd2 == 0 && f2open && tty_setup)
+ tcsetattr (0, TCSANOW, &iocold2);
#endif
}
@@ -879,409 +937,477 @@ restore_stdio()
( dumbio || nouartrx ? (0) : read( _fd_, _buf_, _len_ ) )
static void
-port_init()
+port_init ()
{
- if (uben) {
- f2in = stdin;
- f1in = NULL;
- f2out = stdout;
- f1out = NULL;
- } else {
- f1in = stdin;
- f2in = NULL;
- f1out = stdout;
- f2out = NULL;
+ if (uben)
+ {
+ f2in = stdin;
+ f1in = NULL;
+ f2out = stdout;
+ f1out = NULL;
}
- if (uart_dev1[0] != 0)
- if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
- printf("Warning, couldn't open output device %s\n", uart_dev1);
- } else {
- if (sis_verbose)
- printf("serial port A on %s\n", uart_dev1);
- f1in = f1out = fdopen(fd1, "r+");
- setbuf(f1out, NULL);
- f1open = 1;
- }
- if (f1in)
- ifd1 = fileno(f1in);
- if (ifd1 == 0) {
+ else
+ {
+ f1in = stdin;
+ f2in = NULL;
+ f1out = stdout;
+ f2out = NULL;
+ }
+ if (uart_dev1[0] != 0)
+ if ((fd1 = open (uart_dev1, O_RDWR | O_NONBLOCK)) < 0)
+ {
+ printf ("Warning, couldn't open output device %s\n", uart_dev1);
+ }
+ else
+ {
if (sis_verbose)
- printf("serial port A on stdin/stdout\n");
- if (!dumbio) {
+ printf ("serial port A on %s\n", uart_dev1);
+ f1in = f1out = fdopen (fd1, "r+");
+ setbuf (f1out, NULL);
+ f1open = 1;
+ }
+ if (f1in)
+ ifd1 = fileno (f1in);
+ if (ifd1 == 0)
+ {
+ if (sis_verbose)
+ printf ("serial port A on stdin/stdout\n");
+ if (!dumbio)
+ {
#ifdef HAVE_TERMIOS_H
- tcgetattr (ifd1, &ioc1);
- if (tty_setup) {
- iocold1 = ioc1;
- ioc1.c_lflag &= ~(ICANON | ECHO);
- ioc1.c_cc[VMIN] = 0;
- ioc1.c_cc[VTIME] = 0;
+ tcgetattr (ifd1, &ioc1);
+ if (tty_setup)
+ {
+ iocold1 = ioc1;
+ ioc1.c_lflag &= ~(ICANON | ECHO);
+ ioc1.c_cc[VMIN] = 0;
+ ioc1.c_cc[VTIME] = 0;
}
#endif
- }
- f1open = 1;
+ }
+ f1open = 1;
}
- if (f1out) {
- ofd1 = fileno(f1out);
- if (!dumbio && tty_setup && ofd1 == 1)
- setbuf (f1out, NULL);
+ if (f1out)
+ {
+ ofd1 = fileno (f1out);
+ if (!dumbio && tty_setup && ofd1 == 1)
+ setbuf (f1out, NULL);
}
- if (uart_dev2[0] != 0)
- if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
- printf("Warning, couldn't open output device %s\n", uart_dev2);
- } else {
- if (sis_verbose)
- printf("serial port B on %s\n", uart_dev2);
- f2in = f2out = fdopen(fd2, "r+");
- setbuf(f2out, NULL);
- f2open = 1;
- }
- if (f2in) ifd2 = fileno(f2in);
- if (ifd2 == 0) {
+ if (uart_dev2[0] != 0)
+ if ((fd2 = open (uart_dev2, O_RDWR | O_NONBLOCK)) < 0)
+ {
+ printf ("Warning, couldn't open output device %s\n", uart_dev2);
+ }
+ else
+ {
if (sis_verbose)
- printf("serial port B on stdin/stdout\n");
- if (!dumbio) {
+ printf ("serial port B on %s\n", uart_dev2);
+ f2in = f2out = fdopen (fd2, "r+");
+ setbuf (f2out, NULL);
+ f2open = 1;
+ }
+ if (f2in)
+ ifd2 = fileno (f2in);
+ if (ifd2 == 0)
+ {
+ if (sis_verbose)
+ printf ("serial port B on stdin/stdout\n");
+ if (!dumbio)
+ {
#ifdef HAVE_TERMIOS_H
- tcgetattr(ifd2, &ioc2);
- if (tty_setup) {
- iocold2 = ioc2;
- ioc2.c_lflag &= ~(ICANON | ECHO);
- ioc2.c_cc[VMIN] = 0;
- ioc2.c_cc[VTIME] = 0;
+ tcgetattr (ifd2, &ioc2);
+ if (tty_setup)
+ {
+ iocold2 = ioc2;
+ ioc2.c_lflag &= ~(ICANON | ECHO);
+ ioc2.c_cc[VMIN] = 0;
+ ioc2.c_cc[VTIME] = 0;
}
#endif
- }
- f2open = 1;
+ }
+ f2open = 1;
}
- if (f2out) {
- ofd2 = fileno(f2out);
- if (!dumbio && tty_setup && ofd2 == 1)
- setbuf (f2out, NULL);
+ if (f2out)
+ {
+ ofd2 = fileno (f2out);
+ if (!dumbio && tty_setup && ofd2 == 1)
+ setbuf (f2out, NULL);
}
- wnuma = wnumb = 0;
+ wnuma = wnumb = 0;
}
static uint32
-read_uart(addr)
- uint32 addr;
+read_uart (addr)
+ uint32 addr;
{
- unsigned tmp;
+ unsigned tmp;
- tmp = 0;
- switch (addr & 0xff) {
+ tmp = 0;
+ switch (addr & 0xff)
+ {
case 0xE0: /* UART 1 */
#ifndef _WIN32
#ifdef FAST_UART
- if (aind < anum) {
- if ((aind + 1) < anum)
- mec_irq(4);
- return (0x700 | (uint32) aq[aind++]);
- } else {
- if (f1open)
- anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
- else
- anum = 0;
- if (anum > 0) {
- aind = 0;
- if ((aind + 1) < anum)
- mec_irq(4);
- return (0x700 | (uint32) aq[aind++]);
- } else {
- return (0x600 | (uint32) aq[aind]);
+ if (aind < anum)
+ {
+ if ((aind + 1) < anum)
+ mec_irq (4);
+ return (0x700 | (uint32) aq[aind++]);
+ }
+ else
+ {
+ if (f1open)
+ anum = DO_STDIO_READ (ifd1, aq, UARTBUF);
+ else
+ anum = 0;
+ if (anum > 0)
+ {
+ aind = 0;
+ if ((aind + 1) < anum)
+ mec_irq (4);
+ return (0x700 | (uint32) aq[aind++]);
+ }
+ else
+ {
+ return (0x600 | (uint32) aq[aind]);
}
}
#else
- tmp = uarta_data;
- uarta_data &= ~UART_DR;
- uart_stat_reg &= ~UARTA_DR;
- return tmp;
+ tmp = uarta_data;
+ uarta_data &= ~UART_DR;
+ uart_stat_reg &= ~UARTA_DR;
+ return tmp;
#endif
#else
- return 0;
+ return 0;
#endif
- break;
+ break;
case 0xE4: /* UART 2 */
#ifndef _WIN32
#ifdef FAST_UART
- if (bind < bnum) {
- if ((bind + 1) < bnum)
- mec_irq(5);
- return (0x700 | (uint32) bq[bind++]);
- } else {
- if (f2open)
- bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
- else
- bnum = 0;
- if (bnum > 0) {
- bind = 0;
- if ((bind + 1) < bnum)
- mec_irq(5);
- return (0x700 | (uint32) bq[bind++]);
- } else {
- return (0x600 | (uint32) bq[bind]);
+ if (bind < bnum)
+ {
+ if ((bind + 1) < bnum)
+ mec_irq (5);
+ return (0x700 | (uint32) bq[bind++]);
+ }
+ else
+ {
+ if (f2open)
+ bnum = DO_STDIO_READ (ifd2, bq, UARTBUF);
+ else
+ bnum = 0;
+ if (bnum > 0)
+ {
+ bind = 0;
+ if ((bind + 1) < bnum)
+ mec_irq (5);
+ return (0x700 | (uint32) bq[bind++]);
+ }
+ else
+ {
+ return (0x600 | (uint32) bq[bind]);
}
}
#else
- tmp = uartb_data;
- uartb_data &= ~UART_DR;
- uart_stat_reg &= ~UARTB_DR;
- return tmp;
+ tmp = uartb_data;
+ uartb_data &= ~UART_DR;
+ uart_stat_reg &= ~UARTB_DR;
+ return tmp;
#endif
#else
- return 0;
+ return 0;
#endif
- break;
+ break;
- case 0xE8: /* UART status register */
+ case 0xE8: /* UART status register */
#ifndef _WIN32
#ifdef FAST_UART
- Ucontrol = 0;
- if (aind < anum) {
- Ucontrol |= 0x00000001;
- } else {
- if (f1open)
- anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
- else
- anum = 0;
- if (anum > 0) {
- Ucontrol |= 0x00000001;
- aind = 0;
- mec_irq(4);
+ Ucontrol = 0;
+ if (aind < anum)
+ {
+ Ucontrol |= 0x00000001;
+ }
+ else
+ {
+ if (f1open)
+ anum = DO_STDIO_READ (ifd1, aq, UARTBUF);
+ else
+ anum = 0;
+ if (anum > 0)
+ {
+ Ucontrol |= 0x00000001;
+ aind = 0;
+ mec_irq (4);
}
}
- if (bind < bnum) {
- Ucontrol |= 0x00010000;
- } else {
- if (f2open)
- bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
- else
- bnum = 0;
- if (bnum > 0) {
- Ucontrol |= 0x00010000;
- bind = 0;
- mec_irq(5);
+ if (bind < bnum)
+ {
+ Ucontrol |= 0x00010000;
+ }
+ else
+ {
+ if (f2open)
+ bnum = DO_STDIO_READ (ifd2, bq, UARTBUF);
+ else
+ bnum = 0;
+ if (bnum > 0)
+ {
+ Ucontrol |= 0x00010000;
+ bind = 0;
+ mec_irq (5);
}
}
- Ucontrol |= 0x00060006;
- return Ucontrol;
+ Ucontrol |= 0x00060006;
+ return Ucontrol;
#else
- return uart_stat_reg;
+ return uart_stat_reg;
#endif
#else
- return 0x00060006;
+ return 0x00060006;
#endif
- break;
+ break;
default:
- if (sis_verbose)
- printf("Read from unimplemented MEC register (%x)\n", addr);
+ if (sis_verbose)
+ printf ("Read from unimplemented MEC register (%x)\n", addr);
}
- return 0;
+ return 0;
}
static void
-write_uart(addr, data)
- uint32 addr;
- uint32 data;
+write_uart (addr, data)
+ uint32 addr;
+ uint32 data;
{
- unsigned char c;
+ unsigned char c;
- c = (unsigned char) data;
- switch (addr & 0xff) {
+ c = (unsigned char) data;
+ switch (addr & 0xff)
+ {
case 0xE0: /* UART A */
#ifdef FAST_UART
- if (f1open) {
- if (wnuma < UARTBUF)
- wbufa[wnuma++] = c;
- else {
- while (wnuma) {
- wnuma -= fwrite (wbufa, 1, wnuma, f1out);
+ if (f1open)
+ {
+ if (wnuma < UARTBUF)
+ wbufa[wnuma++] = c;
+ else
+ {
+ while (wnuma)
+ {
+ wnuma -= fwrite (wbufa, 1, wnuma, f1out);
}
- wbufa[wnuma++] = c;
+ wbufa[wnuma++] = c;
}
}
- mec_irq(4);
+ mec_irq (4);
#else
- if (uart_stat_reg & UARTA_SRE) {
- uarta_sreg = c;
- uart_stat_reg &= ~UARTA_SRE;
- event(uarta_tx, 0, UART_TX_TIME);
- } else {
- uarta_hreg = c;
- uart_stat_reg &= ~UARTA_HRE;
+ if (uart_stat_reg & UARTA_SRE)
+ {
+ uarta_sreg = c;
+ uart_stat_reg &= ~UARTA_SRE;
+ event (uarta_tx, 0, UART_TX_TIME);
+ }
+ else
+ {
+ uarta_hreg = c;
+ uart_stat_reg &= ~UARTA_HRE;
}
#endif
- break;
+ break;
case 0xE4: /* UART B */
#ifdef FAST_UART
- if (f2open) {
- if (wnumb < UARTBUF)
- wbufb[wnumb++] = c;
- else {
- while (wnumb) {
- wnumb -= fwrite (wbufb, 1, wnumb, f2out);
+ if (f2open)
+ {
+ if (wnumb < UARTBUF)
+ wbufb[wnumb++] = c;
+ else
+ {
+ while (wnumb)
+ {
+ wnumb -= fwrite (wbufb, 1, wnumb, f2out);
}
- wbufb[wnumb++] = c;
+ wbufb[wnumb++] = c;
}
}
- mec_irq(5);
+ mec_irq (5);
#else
- if (uart_stat_reg & UARTB_SRE) {
- uartb_sreg = c;
- uart_stat_reg &= ~UARTB_SRE;
- event(uartb_tx, 0, UART_TX_TIME);
- } else {
- uartb_hreg = c;
- uart_stat_reg &= ~UARTB_HRE;
+ if (uart_stat_reg & UARTB_SRE)
+ {
+ uartb_sreg = c;
+ uart_stat_reg &= ~UARTB_SRE;
+ event (uartb_tx, 0, UART_TX_TIME);
+ }
+ else
+ {
+ uartb_hreg = c;
+ uart_stat_reg &= ~UARTB_HRE;
}
#endif
- break;
+ break;
case 0xE8: /* UART status register */
#ifndef FAST_UART
- if (data & UARTA_CLR) {
- uart_stat_reg &= 0xFFFF0000;
- uart_stat_reg |= UARTA_SRE | UARTA_HRE;
+ if (data & UARTA_CLR)
+ {
+ uart_stat_reg &= 0xFFFF0000;
+ uart_stat_reg |= UARTA_SRE | UARTA_HRE;
}
- if (data & UARTB_CLR) {
- uart_stat_reg &= 0x0000FFFF;
- uart_stat_reg |= UARTB_SRE | UARTB_HRE;
+ if (data & UARTB_CLR)
+ {
+ uart_stat_reg &= 0x0000FFFF;
+ uart_stat_reg |= UARTB_SRE | UARTB_HRE;
}
#endif
- break;
+ break;
default:
- if (sis_verbose)
- printf("Write to unimplemented MEC register (%x)\n", addr);
+ if (sis_verbose)
+ printf ("Write to unimplemented MEC register (%x)\n", addr);
}
}
static void
-flush_uart()
+flush_uart ()
{
- while (wnuma && f1open) {
- wnuma -= fwrite (wbufa, 1, wnuma, f1out);
+ while (wnuma && f1open)
+ {
+ wnuma -= fwrite (wbufa, 1, wnuma, f1out);
}
- while (wnumb && f2open) {
- wnumb -= fwrite (wbufb, 1, wnumb, f2out);
+ while (wnumb && f2open)
+ {
+ wnumb -= fwrite (wbufb, 1, wnumb, f2out);
}
}
static void
-uarta_tx()
+uarta_tx ()
{
- while (f1open) {
- while (fwrite (&uarta_sreg, 1, 1, f1out) != 1)
- continue;
+ while (f1open)
+ {
+ while (fwrite (&uarta_sreg, 1, 1, f1out) != 1)
+ continue;
+ }
+ if (uart_stat_reg & UARTA_HRE)
+ {
+ uart_stat_reg |= UARTA_SRE;
}
- if (uart_stat_reg & UARTA_HRE) {
- uart_stat_reg |= UARTA_SRE;
- } else {
- uarta_sreg = uarta_hreg;
- uart_stat_reg |= UARTA_HRE;
- event(uarta_tx, 0, UART_TX_TIME);
+ else
+ {
+ uarta_sreg = uarta_hreg;
+ uart_stat_reg |= UARTA_HRE;
+ event (uarta_tx, 0, UART_TX_TIME);
}
- mec_irq(4);
+ mec_irq (4);
}
static void
-uartb_tx()
+uartb_tx ()
{
- while (f2open) {
- while (fwrite(&uartb_sreg, 1, 1, f2out) != 1)
- continue;
+ while (f2open)
+ {
+ while (fwrite (&uartb_sreg, 1, 1, f2out) != 1)
+ continue;
}
- if (uart_stat_reg & UARTB_HRE) {
- uart_stat_reg |= UARTB_SRE;
- } else {
- uartb_sreg = uartb_hreg;
- uart_stat_reg |= UARTB_HRE;
- event(uartb_tx, 0, UART_TX_TIME);
+ if (uart_stat_reg & UARTB_HRE)
+ {
+ uart_stat_reg |= UARTB_SRE;
}
- mec_irq(5);
+ else
+ {
+ uartb_sreg = uartb_hreg;
+ uart_stat_reg |= UARTB_HRE;
+ event (uartb_tx, 0, UART_TX_TIME);
+ }
+ mec_irq (5);
}
static void
-uart_rx(arg)
- int32 arg;
+uart_rx (arg)
+ int32 arg;
{
- int32 rsize;
- char rxd;
+ int32 rsize;
+ char rxd;
+ rsize = 0;
+ if (f1open)
+ rsize = DO_STDIO_READ (ifd1, &rxd, 1);
+ else
rsize = 0;
- if (f1open)
- rsize = DO_STDIO_READ(ifd1, &rxd, 1);
- else
- rsize = 0;
- if (rsize > 0) {
- uarta_data = UART_DR | rxd;
- if (uart_stat_reg & UARTA_HRE)
- uarta_data |= UART_THE;
- if (uart_stat_reg & UARTA_SRE)
- uarta_data |= UART_TSE;
- if (uart_stat_reg & UARTA_DR) {
- uart_stat_reg |= UARTA_OR;
- mec_irq(7); /* UART error interrupt */
+ if (rsize > 0)
+ {
+ uarta_data = UART_DR | rxd;
+ if (uart_stat_reg & UARTA_HRE)
+ uarta_data |= UART_THE;
+ if (uart_stat_reg & UARTA_SRE)
+ uarta_data |= UART_TSE;
+ if (uart_stat_reg & UARTA_DR)
+ {
+ uart_stat_reg |= UARTA_OR;
+ mec_irq (7); /* UART error interrupt */
}
- uart_stat_reg |= UARTA_DR;
- mec_irq(4);
+ uart_stat_reg |= UARTA_DR;
+ mec_irq (4);
}
+ rsize = 0;
+ if (f2open)
+ rsize = DO_STDIO_READ (ifd2, &rxd, 1);
+ else
rsize = 0;
- if (f2open)
- rsize = DO_STDIO_READ(ifd2, &rxd, 1);
- else
- rsize = 0;
- if (rsize) {
- uartb_data = UART_DR | rxd;
- if (uart_stat_reg & UARTB_HRE)
- uartb_data |= UART_THE;
- if (uart_stat_reg & UARTB_SRE)
- uartb_data |= UART_TSE;
- if (uart_stat_reg & UARTB_DR) {
- uart_stat_reg |= UARTB_OR;
- mec_irq(7); /* UART error interrupt */
+ if (rsize)
+ {
+ uartb_data = UART_DR | rxd;
+ if (uart_stat_reg & UARTB_HRE)
+ uartb_data |= UART_THE;
+ if (uart_stat_reg & UARTB_SRE)
+ uartb_data |= UART_TSE;
+ if (uart_stat_reg & UARTB_DR)
+ {
+ uart_stat_reg |= UARTB_OR;
+ mec_irq (7); /* UART error interrupt */
}
- uart_stat_reg |= UARTB_DR;
- mec_irq(5);
+ uart_stat_reg |= UARTB_DR;
+ mec_irq (5);
}
- event(uart_rx, 0, UART_RX_TIME);
+ event (uart_rx, 0, UART_RX_TIME);
}
static void
-uart_intr(arg)
- int32 arg;
+uart_intr (arg)
+ int32 arg;
{
- read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
- flush_uart(); /* Flush UART ports */
- event(uart_intr, 0, UART_FLUSH_TIME);
+ read_uart (0xE8); /* Check for UART interrupts every 1000 clk */
+ flush_uart (); /* Flush UART ports */
+ event (uart_intr, 0, UART_FLUSH_TIME);
}
static void
-uart_irq_start()
+uart_irq_start ()
{
#ifdef FAST_UART
- event(uart_intr, 0, UART_FLUSH_TIME);
+ event (uart_intr, 0, UART_FLUSH_TIME);
#else
#ifndef _WIN32
- event(uart_rx, 0, UART_RX_TIME);
+ event (uart_rx, 0, UART_RX_TIME);
#endif
#endif
}
@@ -1289,173 +1415,196 @@ uart_irq_start()
/* Watch-dog */
static void
-wdog_intr(arg)
- int32 arg;
+wdog_intr (arg)
+ int32 arg;
{
- if (wdog_status == disabled) {
- wdog_status = stopped;
- } else {
-
- if (wdog_counter) {
- wdog_counter--;
- event(wdog_intr, 0, wdog_scaler + 1);
- } else {
- if (wdog_rston) {
- printf("Watchdog reset!\n");
- sys_reset();
- mec_ersr = 0xC000;
- } else {
- mec_irq(15);
- wdog_rston = 1;
- wdog_counter = wdog_rst_delay;
- event(wdog_intr, 0, wdog_scaler + 1);
+ if (wdog_status == disabled)
+ {
+ wdog_status = stopped;
+ }
+ else
+ {
+
+ if (wdog_counter)
+ {
+ wdog_counter--;
+ event (wdog_intr, 0, wdog_scaler + 1);
+ }
+ else
+ {
+ if (wdog_rston)
+ {
+ printf ("Watchdog reset!\n");
+ sys_reset ();
+ mec_ersr = 0xC000;
+ }
+ else
+ {
+ mec_irq (15);
+ wdog_rston = 1;
+ wdog_counter = wdog_rst_delay;
+ event (wdog_intr, 0, wdog_scaler + 1);
}
}
}
}
static void
-wdog_start()
+wdog_start ()
{
- event(wdog_intr, 0, wdog_scaler + 1);
- if (sis_verbose)
- printf("Watchdog started, scaler = %d, counter = %d\n",
- wdog_scaler, wdog_counter);
+ event (wdog_intr, 0, wdog_scaler + 1);
+ if (sis_verbose)
+ printf ("Watchdog started, scaler = %d, counter = %d\n",
+ wdog_scaler, wdog_counter);
}
/* MEC timers */
static void
-rtc_intr(arg)
- int32 arg;
+rtc_intr (arg)
+ int32 arg;
{
- if (rtc_counter == 0) {
-
- mec_irq(13);
- if (rtc_cr)
- rtc_counter = rtc_reload;
- else
- rtc_se = 0;
- } else
- rtc_counter -= 1;
- if (rtc_se) {
- event(rtc_intr, 0, rtc_scaler + 1);
- rtc_scaler_start = now();
- rtc_enabled = 1;
- } else {
- if (sis_verbose)
- printf("RTC stopped\n\r");
- rtc_enabled = 0;
+ if (rtc_counter == 0)
+ {
+
+ mec_irq (13);
+ if (rtc_cr)
+ rtc_counter = rtc_reload;
+ else
+ rtc_se = 0;
+ }
+ else
+ rtc_counter -= 1;
+ if (rtc_se)
+ {
+ event (rtc_intr, 0, rtc_scaler + 1);
+ rtc_scaler_start = now ();
+ rtc_enabled = 1;
+ }
+ else
+ {
+ if (sis_verbose)
+ printf ("RTC stopped\n\r");
+ rtc_enabled = 0;
}
}
static void
-rtc_start()
+rtc_start ()
{
- if (sis_verbose)
- printf("RTC started (period %d)\n\r", rtc_scaler + 1);
- event(rtc_intr, 0, rtc_scaler + 1);
- rtc_scaler_start = now();
- rtc_enabled = 1;
+ if (sis_verbose)
+ printf ("RTC started (period %d)\n\r", rtc_scaler + 1);
+ event (rtc_intr, 0, rtc_scaler + 1);
+ rtc_scaler_start = now ();
+ rtc_enabled = 1;
}
static uint32
-rtc_counter_read()
+rtc_counter_read ()
{
- return rtc_counter;
+ return rtc_counter;
}
static void
-rtc_scaler_set(val)
- uint32 val;
+rtc_scaler_set (val)
+ uint32 val;
{
- rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
+ rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
}
static void
-rtc_reload_set(val)
- uint32 val;
+rtc_reload_set (val)
+ uint32 val;
{
- rtc_reload = val;
+ rtc_reload = val;
}
static void
-gpt_intr(arg)
- int32 arg;
+gpt_intr (arg)
+ int32 arg;
{
- if (gpt_counter == 0) {
- mec_irq(12);
- if (gpt_cr)
- gpt_counter = gpt_reload;
- else
- gpt_se = 0;
- } else
- gpt_counter -= 1;
- if (gpt_se) {
- event(gpt_intr, 0, gpt_scaler + 1);
- gpt_scaler_start = now();
- gpt_enabled = 1;
- } else {
- if (sis_verbose)
- printf("GPT stopped\n\r");
- gpt_enabled = 0;
+ if (gpt_counter == 0)
+ {
+ mec_irq (12);
+ if (gpt_cr)
+ gpt_counter = gpt_reload;
+ else
+ gpt_se = 0;
+ }
+ else
+ gpt_counter -= 1;
+ if (gpt_se)
+ {
+ event (gpt_intr, 0, gpt_scaler + 1);
+ gpt_scaler_start = now ();
+ gpt_enabled = 1;
+ }
+ else
+ {
+ if (sis_verbose)
+ printf ("GPT stopped\n\r");
+ gpt_enabled = 0;
}
}
static void
-gpt_start()
+gpt_start ()
{
- if (sis_verbose)
- printf("GPT started (period %d)\n\r", gpt_scaler + 1);
- event(gpt_intr, 0, gpt_scaler + 1);
- gpt_scaler_start = now();
- gpt_enabled = 1;
+ if (sis_verbose)
+ printf ("GPT started (period %d)\n\r", gpt_scaler + 1);
+ event (gpt_intr, 0, gpt_scaler + 1);
+ gpt_scaler_start = now ();
+ gpt_enabled = 1;
}
static uint32
-gpt_counter_read()
+gpt_counter_read ()
{
- return gpt_counter;
+ return gpt_counter;
}
static void
-gpt_scaler_set(val)
- uint32 val;
+gpt_scaler_set (val)
+ uint32 val;
{
- gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
+ gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
}
static void
-gpt_reload_set(val)
- uint32 val;
+gpt_reload_set (val)
+ uint32 val;
{
- gpt_reload = val;
+ gpt_reload = val;
}
static void
-timer_ctrl(val)
- uint32 val;
+timer_ctrl (val)
+ uint32 val;
{
- rtc_cr = ((val & TCR_TCRCR) != 0);
- if (val & TCR_TCRCL) {
- rtc_counter = rtc_reload;
+ rtc_cr = ((val & TCR_TCRCR) != 0);
+ if (val & TCR_TCRCL)
+ {
+ rtc_counter = rtc_reload;
}
- if (val & TCR_TCRSL) {
+ if (val & TCR_TCRSL)
+ {
}
- rtc_se = ((val & TCR_TCRSE) != 0);
- if (rtc_se && (rtc_enabled == 0))
- rtc_start();
-
- gpt_cr = (val & TCR_GACR);
- if (val & TCR_GACL) {
- gpt_counter = gpt_reload;
+ rtc_se = ((val & TCR_TCRSE) != 0);
+ if (rtc_se && (rtc_enabled == 0))
+ rtc_start ();
+
+ gpt_cr = (val & TCR_GACR);
+ if (val & TCR_GACL)
+ {
+ gpt_counter = gpt_reload;
}
- if (val & TCR_GACL) {
+ if (val & TCR_GACL)
+ {
}
- gpt_se = (val & TCR_GASE) >> 2;
- if (gpt_se && (gpt_enabled == 0))
- gpt_start();
+ gpt_se = (val & TCR_GASE) >> 2;
+ if (gpt_se && (gpt_enabled == 0))
+ gpt_start ();
}
/* Store data in host byte order. MEM points to the beginning of the
@@ -1466,241 +1615,266 @@ timer_ctrl(val)
wait-states. */
static void
-store_bytes (char *mem, uint32 waddr, uint32 *data, int32 sz,
- int32 *ws)
+store_bytes (char *mem, uint32 waddr, uint32 * data, int32 sz, int32 * ws)
{
- switch (sz) {
- case 0:
- waddr ^= EBT;
- mem[waddr] = *data & 0x0ff;
- *ws = mem_ramw_ws + 3;
- break;
- case 1:
+ switch (sz)
+ {
+ case 0:
+ waddr ^= EBT;
+ mem[waddr] = *data & 0x0ff;
+ *ws = mem_ramw_ws + 3;
+ break;
+ case 1:
#ifdef HOST_LITTLE_ENDIAN
- waddr ^= 2;
+ waddr ^= 2;
#endif
- memcpy (&mem[waddr], data, 2);
- *ws = mem_ramw_ws + 3;
- break;
- case 2:
- memcpy (&mem[waddr], data, 4);
- *ws = mem_ramw_ws;
- break;
- case 3:
- memcpy (&mem[waddr], data, 8);
- *ws = 2 * mem_ramw_ws + STD_WS;
- break;
+ memcpy (&mem[waddr], data, 2);
+ *ws = mem_ramw_ws + 3;
+ break;
+ case 2:
+ memcpy (&mem[waddr], data, 4);
+ *ws = mem_ramw_ws;
+ break;
+ case 3:
+ memcpy (&mem[waddr], data, 8);
+ *ws = 2 * mem_ramw_ws + STD_WS;
+ break;
}
}
/* Memory emulation */
static int
-memory_iread (uint32 addr, uint32 *data, int32 *ws)
+memory_iread (uint32 addr, uint32 * data, int32 * ws)
{
- uint32 asi;
- if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
- memcpy (data, &ramb[addr & mem_rammask], 4);
- *ws = mem_ramr_ws;
- return 0;
- } else if (addr < mem_romsz) {
- memcpy (data, &romb[addr], 4);
- *ws = mem_romr_ws;
- return 0;
+ uint32 asi;
+ if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz)))
+ {
+ memcpy (data, &ramb[addr & mem_rammask], 4);
+ *ws = mem_ramr_ws;
+ return 0;
+ }
+ else if (addr < mem_romsz)
+ {
+ memcpy (data, &romb[addr], 4);
+ *ws = mem_romr_ws;
+ return 0;
}
- if (sis_verbose)
- printf ("Memory exception at %x (illegal address)\n", addr);
- if (sregs->psr & 0x080)
- asi = 9;
- else
- asi = 8;
- set_sfsr (UIMP_ACC, addr, asi, 1);
- *ws = MEM_EX_WS;
- return 1;
+ if (sis_verbose)
+ printf ("Memory exception at %x (illegal address)\n", addr);
+ if (sregs->psr & 0x080)
+ asi = 9;
+ else
+ asi = 8;
+ set_sfsr (UIMP_ACC, addr, asi, 1);
+ *ws = MEM_EX_WS;
+ return 1;
}
static int
-memory_read (uint32 addr, uint32 *data, int32 *ws)
+memory_read (uint32 addr, uint32 * data, int32 * ws)
{
- int32 mexc;
- int32 asi;
-
- if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
- memcpy (data, &ramb[addr & mem_rammask], 4);
- *ws = mem_ramr_ws;
- return 0;
- } else if ((addr >= MEC_START) && (addr < MEC_END)) {
- asi = (sregs->psr & 0x080) ? 11 : 10;
- mexc = mec_read(addr, asi, data);
- if (mexc) {
- set_sfsr(MEC_ACC, addr, asi, 1);
- *ws = MEM_EX_WS;
- } else {
- *ws = 0;
+ int32 mexc;
+ int32 asi;
+
+ if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz)))
+ {
+ memcpy (data, &ramb[addr & mem_rammask], 4);
+ *ws = mem_ramr_ws;
+ return 0;
+ }
+ else if ((addr >= MEC_START) && (addr < MEC_END))
+ {
+ asi = (sregs->psr & 0x080) ? 11 : 10;
+ mexc = mec_read (addr, asi, data);
+ if (mexc)
+ {
+ set_sfsr (MEC_ACC, addr, asi, 1);
+ *ws = MEM_EX_WS;
}
- return mexc;
- } else if (addr < mem_romsz) {
- memcpy (data, &romb[addr], 4);
- *ws = mem_romr_ws;
- return 0;
+ else
+ {
+ *ws = 0;
+ }
+ return mexc;
+ }
+ else if (addr < mem_romsz)
+ {
+ memcpy (data, &romb[addr], 4);
+ *ws = mem_romr_ws;
+ return 0;
}
- if (sis_verbose)
- printf ("Memory exception at %x (illegal address)\n", addr);
- asi = (sregs->psr & 0x080) ? 11 : 10;
- set_sfsr(UIMP_ACC, addr, asi, 1);
- *ws = MEM_EX_WS;
- return 1;
+ if (sis_verbose)
+ printf ("Memory exception at %x (illegal address)\n", addr);
+ asi = (sregs->psr & 0x080) ? 11 : 10;
+ set_sfsr (UIMP_ACC, addr, asi, 1);
+ *ws = MEM_EX_WS;
+ return 1;
}
static int
-memory_write (uint32 addr, uint32 *data, int32 sz, int32 *ws)
+memory_write (uint32 addr, uint32 * data, int32 sz, int32 * ws)
{
- uint32 byte_addr;
- uint32 byte_mask;
- uint32 waddr;
- uint32 *ram;
- int32 mexc;
- int i;
- int wphit[2];
- int asi;
-
- if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
- if (mem_accprot) {
-
- waddr = (addr & 0x7fffff) >> 2;
- asi = (sregs->psr & 0x080) ? 11 : 10;
- for (i = 0; i < 2; i++)
- wphit[i] =
- (((asi == 0xa) && (mec_wpr[i] & 1)) ||
- ((asi == 0xb) && (mec_wpr[i] & 2))) &&
- ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
-
- if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
- ((!mem_blockprot) &&
- !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
- )) {
- if (sis_verbose)
- printf("Memory access protection error at 0x%08x\n", addr);
- set_sfsr(PROT_EXC, addr, asi, 0);
- *ws = MEM_EX_WS;
- return 1;
+ uint32 byte_addr;
+ uint32 byte_mask;
+ uint32 waddr;
+ uint32 *ram;
+ int32 mexc;
+ int i;
+ int wphit[2];
+ int asi;
+
+ if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz)))
+ {
+ if (mem_accprot)
+ {
+
+ waddr = (addr & 0x7fffff) >> 2;
+ asi = (sregs->psr & 0x080) ? 11 : 10;
+ for (i = 0; i < 2; i++)
+ wphit[i] =
+ (((asi == 0xa) && (mec_wpr[i] & 1)) ||
+ ((asi == 0xb) && (mec_wpr[i] & 2))) &&
+ ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
+
+ if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
+ ((!mem_blockprot) &&
+ !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))))
+ {
+ if (sis_verbose)
+ printf ("Memory access protection error at 0x%08x\n", addr);
+ set_sfsr (PROT_EXC, addr, asi, 0);
+ *ws = MEM_EX_WS;
+ return 1;
}
}
- waddr = addr & mem_rammask;
- store_bytes (ramb, waddr, data, sz, ws);
- return 0;
- } else if ((addr >= MEC_START) && (addr < MEC_END)) {
- asi = (sregs->psr & 0x080) ? 11 : 10;
- if ((sz != 2) || (asi != 0xb)) {
- set_sfsr(MEC_ACC, addr, asi, 0);
- *ws = MEM_EX_WS;
- return 1;
+ waddr = addr & mem_rammask;
+ store_bytes (ramb, waddr, data, sz, ws);
+ return 0;
+ }
+ else if ((addr >= MEC_START) && (addr < MEC_END))
+ {
+ asi = (sregs->psr & 0x080) ? 11 : 10;
+ if ((sz != 2) || (asi != 0xb))
+ {
+ set_sfsr (MEC_ACC, addr, asi, 0);
+ *ws = MEM_EX_WS;
+ return 1;
+ }
+ mexc = mec_write (addr, *data);
+ if (mexc)
+ {
+ set_sfsr (MEC_ACC, addr, asi, 0);
+ *ws = MEM_EX_WS;
}
- mexc = mec_write(addr, *data);
- if (mexc) {
- set_sfsr(MEC_ACC, addr, asi, 0);
- *ws = MEM_EX_WS;
- } else {
- *ws = 0;
+ else
+ {
+ *ws = 0;
}
- return mexc;
- } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
- (((mec_memcfg & 0x20000) && (sz > 1)) ||
- (!(mec_memcfg & 0x20000) && (sz == 0)))) {
-
- *ws = mem_romw_ws + 1;
- if (sz == 3)
- *ws += mem_romw_ws + STD_WS;
- store_bytes (romb, addr, data, sz, ws);
- return 0;
+ return mexc;
}
-
- *ws = MEM_EX_WS;
- asi = (sregs->psr & 0x080) ? 11 : 10;
- set_sfsr(UIMP_ACC, addr, asi, 0);
- return 1;
+ else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
+ (((mec_memcfg & 0x20000) && (sz > 1)) ||
+ (!(mec_memcfg & 0x20000) && (sz == 0))))
+ {
+
+ *ws = mem_romw_ws + 1;
+ if (sz == 3)
+ *ws += mem_romw_ws + STD_WS;
+ store_bytes (romb, addr, data, sz, ws);
+ return 0;
+ }
+
+ *ws = MEM_EX_WS;
+ asi = (sregs->psr & 0x080) ? 11 : 10;
+ set_sfsr (UIMP_ACC, addr, asi, 0);
+ return 1;
}
-static char *
-get_mem_ptr(addr, size)
- uint32 addr;
- uint32 size;
+static char *
+get_mem_ptr (addr, size)
+ uint32 addr;
+ uint32 size;
{
- if ((addr + size) < ROM_SIZE) {
- return &romb[addr];
- } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
- return &ramb[addr & mem_rammask];
+ if ((addr + size) < ROM_SIZE)
+ {
+ return &romb[addr];
+ }
+ else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend))
+ {
+ return &ramb[addr & mem_rammask];
}
- return (char *) -1;
+ return (char *) -1;
}
static int
-sis_memory_write(addr, data, length)
- uint32 addr;
- const unsigned char *data;
- uint32 length;
+sis_memory_write (addr, data, length)
+ uint32 addr;
+ const unsigned char *data;
+ uint32 length;
{
- char *mem;
+ char *mem;
- if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
- return 0;
+ if ((mem = get_mem_ptr (addr, length)) == ((char *) -1))
+ return 0;
- memcpy(mem, data, length);
- return length;
+ memcpy (mem, data, length);
+ return length;
}
static int
-sis_memory_read(addr, data, length)
- uint32 addr;
- char *data;
- uint32 length;
+sis_memory_read (addr, data, length)
+ uint32 addr;
+ char *data;
+ uint32 length;
{
- char *mem;
- int ws;
- unsigned int w4;
-
- if (length == 4) {
- memory_read (addr, &w4, &ws);
- memcpy(data, &w4, length);
- return 4;
+ char *mem;
+ int ws;
+ unsigned int w4;
+
+ if (length == 4)
+ {
+ memory_read (addr, &w4, &ws);
+ memcpy (data, &w4, length);
+ return 4;
}
- if ((mem = get_mem_ptr(addr, length)) == ((char *) -1))
- return 0;
+ if ((mem = get_mem_ptr (addr, length)) == ((char *) -1))
+ return 0;
- memcpy(data, mem, length);
- return length;
+ memcpy (data, mem, length);
+ return length;
}
static void
boot_init (void)
{
- mec_write(MEC_WCR, 0); /* zero waitstates */
- mec_write(MEC_TRAPD, 0); /* turn off watch-dog */
- mec_write(MEC_RTC_SCALER, ebase.freq - 1); /* generate 1 MHz RTC tick */
- mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
- sregs->wim = 2;
- sregs->psr = 0x110010e0;
- sregs->r[30] = RAM_END;
- sregs->r[14] = sregs->r[30] - 96 * 4;
- mec_mcr |= 1; /* power-down enabled */
+ mec_write (MEC_WCR, 0); /* zero waitstates */
+ mec_write (MEC_TRAPD, 0); /* turn off watch-dog */
+ mec_write (MEC_RTC_SCALER, ebase.freq - 1); /* generate 1 MHz RTC tick */
+ mec_write (MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
+ sregs->wim = 2;
+ sregs->psr = 0x110010e0;
+ sregs->r[30] = RAM_END;
+ sregs->r[14] = sregs->r[30] - 96 * 4;
+ mec_mcr |= 1; /* power-down enabled */
}
const struct memsys erc32sys = {
- init_sim,
- reset,
- error_mode,
- sim_halt,
- exit_sim,
- init_stdio,
- restore_stdio,
- memory_iread,
- memory_read,
- memory_write,
- sis_memory_write,
- sis_memory_read,
- boot_init
+ init_sim,
+ reset,
+ error_mode,
+ sim_halt,
+ exit_sim,
+ init_stdio,
+ restore_stdio,
+ memory_iread,
+ memory_read,
+ memory_write,
+ sis_memory_write,
+ sis_memory_read,
+ boot_init
};
diff --git a/exec.c b/exec.c
index d0b31f9..3c9548d 100644
--- a/exec.c
+++ b/exec.c
@@ -43,7 +43,8 @@ add32 (uint32 n1, uint32 n2, int *carry)
/* Multiply two 32-bit integers. */
void
-mul64 (uint32 n1, uint32 n2, uint32 *result_hi, uint32 *result_lo, int msigned)
+mul64 (uint32 n1, uint32 n2, uint32 * result_hi, uint32 * result_lo,
+ int msigned)
{
uint32 lo, mid1, mid2, hi, reg_lo, reg_hi;
int carry;
@@ -58,16 +59,16 @@ mul64 (uint32 n1, uint32 n2, uint32 *result_hi, uint32 *result_lo, int msigned)
n1 = -n1;
if (n2 & SIGN_BIT)
n2 = -n2;
-
+
}
-
+
/* We can split the 32x32 into four 16x16 operations. This ensures
that we do not lose precision on 32bit only hosts: */
- lo = ((n1 & 0xFFFF) * (n2 & 0xFFFF));
+ lo = ((n1 & 0xFFFF) * (n2 & 0xFFFF));
mid1 = ((n1 & 0xFFFF) * ((n2 >> 16) & 0xFFFF));
mid2 = (((n1 >> 16) & 0xFFFF) * (n2 & 0xFFFF));
- hi = (((n1 >> 16) & 0xFFFF) * ((n2 >> 16) & 0xFFFF));
-
+ hi = (((n1 >> 16) & 0xFFFF) * ((n2 >> 16) & 0xFFFF));
+
/* We now need to add all of these results together, taking care
to propogate the carries from the additions: */
reg_lo = add32 (lo, (mid1 << 16), &carry);
@@ -78,12 +79,12 @@ mul64 (uint32 n1, uint32 n2, uint32 *result_hi, uint32 *result_lo, int msigned)
/* Negate result if necessary. */
if (sign)
{
- reg_hi = ~ reg_hi;
- reg_lo = - reg_lo;
+ reg_hi = ~reg_hi;
+ reg_lo = -reg_lo;
if (reg_lo == 0)
reg_hi++;
}
-
+
*result_lo = reg_lo;
*result_hi = reg_hi;
}
@@ -93,7 +94,7 @@ mul64 (uint32 n1, uint32 n2, uint32 *result_hi, uint32 *result_lo, int msigned)
that the host compiler supports long long operations. */
void
-div64 (uint32 n1_hi, uint32 n1_low, uint32 n2, uint32 *result, int msigned)
+div64 (uint32 n1_hi, uint32 n1_low, uint32 n2, uint32 * result, int msigned)
{
uint64 n1;
@@ -114,92 +115,100 @@ div64 (uint32 n1_hi, uint32 n1_low, uint32 n2, uint32 *result, int msigned)
}
void
-init_regs(sregs)
- struct pstate *sregs;
+init_regs (sregs)
+ struct pstate *sregs;
{
int i;
ebase.wphit = 0;
- for (i=0; i<NCPU; i++) {
- sregs[i].pc = 0;
- sregs[i].npc = 4;
- sregs[i].trap = 0;
- sregs[i].psr &= 0x00f03fdf;
- if (cputype == CPU_LEON3)
- sregs[i].psr |= 0xF3000080; /* Set supervisor bit */
- else
- if (cputype == CPU_LEON2)
- sregs[i].psr |= 0x00000080; /* Set supervisor bit */
- else
- sregs[i].psr |= 0x11000080; /* Set supervisor bit */
- sregs[i].breakpoint = 0;
- sregs[i].fpstate = 0;
- sregs[i].fpqn = 0;
- sregs[i].ftime = 0;
- sregs[i].ltime = 0;
- sregs[i].err_mode = 0;
- ext_irl[i] = 0;
- sregs[i].g[0] = 0;
- sregs[i].r[0] = 0;
- sregs[i].fs = (float32 *) sregs[i].fd;
- sregs[i].fsi = (int32 *) sregs[i].fd;
- sregs[i].fsr = 0;
- sregs[i].fpu_pres = !nfp;
- set_fsr(sregs[i].fsr);
- sregs[i].ildreg = 0;
- sregs[i].ildtime = 0;
-
- sregs[i].y = 0;
- sregs[i].asr17 = 0;
-
- sregs[i].rett_err = 0;
- sregs[i].jmpltime = 0;
- if (cputype == CPU_LEON3) {
- sregs[i].asr17 = 0x04000107 | (i << 28);
- if (!nfp) sregs[i].asr17 |= (3 << 10); /* Meiko FPU */
+ for (i = 0; i < NCPU; i++)
+ {
+ sregs[i].pc = 0;
+ sregs[i].npc = 4;
+ sregs[i].trap = 0;
+ sregs[i].psr &= 0x00f03fdf;
+ if (cputype == CPU_LEON3)
+ sregs[i].psr |= 0xF3000080; /* Set supervisor bit */
+ else if (cputype == CPU_LEON2)
+ sregs[i].psr |= 0x00000080; /* Set supervisor bit */
+ else
+ sregs[i].psr |= 0x11000080; /* Set supervisor bit */
+ sregs[i].breakpoint = 0;
+ sregs[i].fpstate = 0;
+ sregs[i].fpqn = 0;
+ sregs[i].ftime = 0;
+ sregs[i].ltime = 0;
+ sregs[i].err_mode = 0;
+ ext_irl[i] = 0;
+ sregs[i].g[0] = 0;
+ sregs[i].r[0] = 0;
+ sregs[i].fs = (float32 *) sregs[i].fd;
+ sregs[i].fsi = (int32 *) sregs[i].fd;
+ sregs[i].fsr = 0;
+ sregs[i].fpu_pres = !nfp;
+ set_fsr (sregs[i].fsr);
+ sregs[i].ildreg = 0;
+ sregs[i].ildtime = 0;
+
+ sregs[i].y = 0;
+ sregs[i].asr17 = 0;
+
+ sregs[i].rett_err = 0;
+ sregs[i].jmpltime = 0;
+ if (cputype == CPU_LEON3)
+ {
+ sregs[i].asr17 = 0x04000107 | (i << 28);
+ if (!nfp)
+ sregs[i].asr17 |= (3 << 10); /* Meiko FPU */
+ }
+ sregs[i].cpu = i;
+ sregs[i].simtime = 0;
+ sregs[i].pwdtime = 0;
+ sregs[i].pwdstart = 0;
+ if (i == 0)
+ sregs[i].pwd_mode = 0;
+ else
+ sregs[i].pwd_mode = 1;
+ sregs[i].mip = 0;
+ sregs[i].mstatus = 0;
+ sregs[i].mie = 0;
+ sregs[i].mpp = 0;
+ sregs[i].mode = 1;
+ sregs[i].lrq = 0;
+ sregs[i].bphit = 0;
}
- sregs[i].cpu = i;
- sregs[i].simtime = 0;
- sregs[i].pwdtime = 0;
- sregs[i].pwdstart = 0;
- if (i == 0)
- sregs[i].pwd_mode = 0;
- else
- sregs[i].pwd_mode = 1;
- sregs[i].mip = 0;
- sregs[i].mstatus = 0;
- sregs[i].mie = 0;
- sregs[i].mpp = 0;
- sregs[i].mode = 1;
- sregs[i].lrq = 0;
- sregs[i].bphit = 0;
- }
}
#ifdef ENABLE_L1CACHE
void
-l1data_snoop(uint32 address, uint32 cpu)
+l1data_snoop (uint32 address, uint32 cpu)
{
- int i;
- for (i=0; i<ncpu; i++) {
- if (sregs[i].l1dtags[(address >> L1DLINEBITS) & L1DMASK] == (address >> L1DLINEBITS)) {
- if (cpu != i) {
- sregs[i].l1dtags[(address >> L1DLINEBITS) & L1DMASK] = 0;
-// printf("l1 snoop hit : 0x%08X, %d %d\n", address, cpu, i);
- }
- }
+ int i;
+ for (i = 0; i < ncpu; i++)
+ {
+ if (sregs[i].l1dtags[(address >> L1DLINEBITS) & L1DMASK] ==
+ (address >> L1DLINEBITS))
+ {
+ if (cpu != i)
+ {
+ sregs[i].l1dtags[(address >> L1DLINEBITS) & L1DMASK] = 0;
+// printf("l1 snoop hit : 0x%08X, %d %d\n", address, cpu, i);
+ }
}
+ }
}
void
-l1data_update(uint32 address, uint32 cpu)
+l1data_update (uint32 address, uint32 cpu)
{
- if (sregs[cpu].l1dtags[address >> L1DLINEBITS & L1DMASK] != (address >> L1DLINEBITS))
- {
- sregs[cpu].l1dtags[(address >> L1DLINEBITS) & L1DMASK] = (address >> L1DLINEBITS);
- sregs[cpu].hold += T_L1DMISS;
- sregs[cpu].l1dmiss++;
- }
+ if (sregs[cpu].l1dtags[address >> L1DLINEBITS & L1DMASK] !=
+ (address >> L1DLINEBITS))
+ {
+ sregs[cpu].l1dtags[(address >> L1DLINEBITS) & L1DMASK] =
+ (address >> L1DLINEBITS);
+ sregs[cpu].hold += T_L1DMISS;
+ sregs[cpu].l1dmiss++;
+ }
}
#endif
diff --git a/float.c b/float.c
index f0a912c..58c307e 100644
--- a/float.c
+++ b/float.c
@@ -32,53 +32,54 @@
/* This routine should return the accrued exceptions */
int
-get_accex()
+get_accex ()
{
- int fexc, accx;
+ int fexc, accx;
- fexc = fetestexcept (FE_ALL_EXCEPT);
- accx = 0;
- if (fexc & FE_INEXACT)
- accx |= 1;
- if (fexc & FE_DIVBYZERO)
- accx |= 2;
- if (fexc & FE_UNDERFLOW)
- accx |= 4;
- if (fexc & FE_OVERFLOW)
- accx |= 8;
- if (fexc & FE_INVALID)
- accx |= 0x10;
- return accx;
+ fexc = fetestexcept (FE_ALL_EXCEPT);
+ accx = 0;
+ if (fexc & FE_INEXACT)
+ accx |= 1;
+ if (fexc & FE_DIVBYZERO)
+ accx |= 2;
+ if (fexc & FE_UNDERFLOW)
+ accx |= 4;
+ if (fexc & FE_OVERFLOW)
+ accx |= 8;
+ if (fexc & FE_INVALID)
+ accx |= 0x10;
+ return accx;
}
/* How to clear the accrued exceptions */
void
-clear_accex()
+clear_accex ()
{
- feclearexcept (FE_ALL_EXCEPT);
+ feclearexcept (FE_ALL_EXCEPT);
}
/* How to map SPARC FSR onto the host */
void
-set_fsr(fsr)
-uint32 fsr;
+set_fsr (fsr)
+ uint32 fsr;
{
- int fround;
+ int fround;
- fsr >>= 30;
- switch (fsr) {
- case 0:
- fround = FE_TONEAREST;
- break;
- case 1:
- fround = FE_TOWARDZERO;
- break;
- case 2:
- fround = FE_UPWARD;
- break;
- case 3:
- fround = FE_DOWNWARD;
- break;
- }
- fesetround (fround);
+ fsr >>= 30;
+ switch (fsr)
+ {
+ case 0:
+ fround = FE_TONEAREST;
+ break;
+ case 1:
+ fround = FE_TOWARDZERO;
+ break;
+ case 2:
+ fround = FE_UPWARD;
+ break;
+ case 3:
+ fround = FE_DOWNWARD;
+ break;
+ }
+ fesetround (fround);
}
diff --git a/func.c b/func.c
index 437837c..7dc0e67 100644
--- a/func.c
+++ b/func.c
@@ -40,37 +40,37 @@ int dumbio = 0;
/* set if UARTs are connected to a tty, enable by default */
int tty_setup = 1;
-struct pstate sregs[NCPU];
-struct estate ebase;
-struct evcell evbuf[EVENT_MAX];
-
-int ctrl_c = 0;
-int sis_verbose = 0;
-char *sis_version = PACKAGE_VERSION;
-int nfp = 0;
-int ift = 0;
-int wrp = 0;
-int rom8 = 0;
-int uben = 0;
-int termsave;
-char uart_dev1[128] = "";
-char uart_dev2[128] = "";
-uint32 last_load_addr = 0;
-int nouartrx = 0;
-int port = 1234;
-int sim_run = 0;
+struct pstate sregs[NCPU];
+struct estate ebase;
+struct evcell evbuf[EVENT_MAX];
+
+int ctrl_c = 0;
+int sis_verbose = 0;
+char *sis_version = PACKAGE_VERSION;
+int nfp = 0;
+int ift = 0;
+int wrp = 0;
+int rom8 = 0;
+int uben = 0;
+int termsave;
+char uart_dev1[128] = "";
+char uart_dev2[128] = "";
+uint32 last_load_addr = 0;
+int nouartrx = 0;
+int port = 1234;
+int sim_run = 0;
/* RAM and ROM for all systems */
char romb[ROM_SIZE];
char ramb[RAM_SIZE];
const struct memsys *ms = &erc32sys;
-int cputype = 0; /* 0 = erc32, 2 = leon2,3 = leon3, 5 = riscv */
-int sis_gdb_break;
-int cpu = 0; /* active cpu */
-int ncpu = 1; /* number of cpus to emulate */
-int delta = 50; /* time slice for MP simulation */
+int cputype = 0; /* 0 = erc32, 2 = leon2,3 = leon3, 5 = riscv */
+int sis_gdb_break;
+int cpu = 0; /* active cpu */
+int ncpu = 1; /* number of cpus to emulate */
+int delta = 50; /* time slice for MP simulation */
const struct cpu_arch *arch = &sparc;
-uint32 daddr = 0;
+uint32 daddr = 0;
/*
static bfd *abfd;
static asymbol **asymbols;
@@ -80,539 +80,710 @@ static int symcount = 0;
/* Forward declarations */
-static int batch (struct pstate *sregs, char *fname);
-static void init_event (void);
-static void disp_mem (uint32 addr, uint32 len);
-static ssize_t mygetline (char **lineptr, size_t *n, FILE *stream);
-static void symprint();
-static uint32 symtoaddr(char *s);
+static int batch (struct pstate *sregs, char *fname);
+static void init_event (void);
+static void disp_mem (uint32 addr, uint32 len);
+static ssize_t mygetline (char **lineptr, size_t * n, FILE * stream);
+static void symprint ();
+static uint32 symtoaddr (char *s);
static int
-batch(sregs, fname)
- struct pstate *sregs;
- char *fname;
+batch (sregs, fname)
+ struct pstate *sregs;
+ char *fname;
{
- FILE *fp;
- char *lbuf = NULL;
- size_t len = 0;
- size_t slen;
-
- if ((fp = fopen(fname, "r")) == NULL) {
- fprintf(stderr, "couldn't open batch file %s\n", fname);
- return 0;
+ FILE *fp;
+ char *lbuf = NULL;
+ size_t len = 0;
+ size_t slen;
+
+ if ((fp = fopen (fname, "r")) == NULL)
+ {
+ fprintf (stderr, "couldn't open batch file %s\n", fname);
+ return 0;
}
- while (mygetline(&lbuf, &len, fp) > -1) {
- slen = strlen(lbuf);
- if (slen && (lbuf[slen - 1] == '\n')) {
- lbuf[slen - 1] = 0;
- printf("sis> %s\n", lbuf);
- exec_cmd(lbuf);
+ while (mygetline (&lbuf, &len, fp) > -1)
+ {
+ slen = strlen (lbuf);
+ if (slen && (lbuf[slen - 1] == '\n'))
+ {
+ lbuf[slen - 1] = 0;
+ printf ("sis> %s\n", lbuf);
+ exec_cmd (lbuf);
}
}
- free(lbuf);
- fclose(fp);
- return 1;
+ free (lbuf);
+ fclose (fp);
+ return 1;
}
+
static uint64
limcalc (freq)
- float32 freq;
+ float32 freq;
{
- uint64 unit, lim;
- double flim;
- char *cmd1, *cmd2;
-
- unit = 1;
- lim = -1;
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- lim = VAL(cmd1);
- if ((cmd2 = strtok(NULL, " \t\n\r")) != NULL) {
- if (strcmp(cmd2,"us")==0) unit = 1;
- if (strcmp(cmd2,"ms")==0) unit = 1000;
- if (strcmp(cmd2,"s")==0) unit = 1000000;
- }
- flim = (double) lim * (double) unit * (double) freq +
- (double) ebase.simtime;
- if (flim > ebase.simtime) {
- lim = (uint64) flim;
- } else {
- printf("error in expression\n");
- lim = 0;
- }
+ uint64 unit, lim;
+ double flim;
+ char *cmd1, *cmd2;
+
+ unit = 1;
+ lim = -1;
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ lim = VAL (cmd1);
+ if ((cmd2 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ if (strcmp (cmd2, "us") == 0)
+ unit = 1;
+ if (strcmp (cmd2, "ms") == 0)
+ unit = 1000;
+ if (strcmp (cmd2, "s") == 0)
+ unit = 1000000;
+ }
+ flim = (double) lim *(double) unit *(double) freq +
+ (double) ebase.simtime;
+ if (flim > ebase.simtime)
+ {
+ lim = (uint64) flim;
+ }
+ else
+ {
+ printf ("error in expression\n");
+ lim = 0;
+ }
}
- return lim;
+ return lim;
}
int
-exec_cmd(const char *cmd)
+exec_cmd (const char *cmd)
{
- char *cmd1, *cmd2;
- int32 stat, i;
- uint32 len, clen, j;
- char *cmdsave, *cmdsave2 = NULL;
-
- stat = OK;
- if (!cmd)
- return stat;
- cmdsave = strdup(cmd);
- cmdsave2 = strdup (cmd);
- if ((cmd1 = strtok (cmdsave2, " \t")) != NULL) {
- clen = strlen(cmd1);
- if (strncmp(cmd1, "bp", clen) == 0) {
- for (i = 0; i < ebase.bptnum; i++) {
- printf(" %d : 0x%08x\n", i + 1, ebase.bpts[i]);
+ char *cmd1, *cmd2;
+ int32 stat, i;
+ uint32 len, clen, j;
+ char *cmdsave, *cmdsave2 = NULL;
+
+ stat = OK;
+ if (!cmd)
+ return stat;
+ cmdsave = strdup (cmd);
+ cmdsave2 = strdup (cmd);
+ if ((cmd1 = strtok (cmdsave2, " \t")) != NULL)
+ {
+ clen = strlen (cmd1);
+ if (strncmp (cmd1, "bp", clen) == 0)
+ {
+ for (i = 0; i < ebase.bptnum; i++)
+ {
+ printf (" %d : 0x%08x\n", i + 1, ebase.bpts[i]);
}
- } else if ((strncmp(cmd1, "+bp", clen) == 0) ||
- (strncmp(cmd1, "break", clen) == 0)) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- if (isdigit(cmd1[0]))
- len = VAL(cmd1);
- /*
- else
- len = symtoaddr(cmd1);
- */
- if (len) {
- ebase.bpts[ebase.bptnum] = len & ~0x1;
- printf("added breakpoint %d at 0x%08x\n",
- ebase.bptnum + 1, ebase.bpts[ebase.bptnum]);
- ebase.bptnum += 1;
+ }
+ else if ((strncmp (cmd1, "+bp", clen) == 0) ||
+ (strncmp (cmd1, "break", clen) == 0))
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ if (isdigit (cmd1[0]))
+ len = VAL (cmd1);
+ /*
+ else
+ len = symtoaddr(cmd1);
+ */
+ if (len)
+ {
+ ebase.bpts[ebase.bptnum] = len & ~0x1;
+ printf ("added breakpoint %d at 0x%08x\n",
+ ebase.bptnum + 1, ebase.bpts[ebase.bptnum]);
+ ebase.bptnum += 1;
}
- } else {
- for (i = 0; i < ebase.bptnum; i++) {
- printf(" %d : 0x%08x\n", i + 1, ebase.bpts[i]);
- }
}
- } else if ((strncmp(cmd1, "-bp", clen) == 0) ||
- (strncmp(cmd1, "delete", clen) == 0)) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- i = VAL(cmd1) - 1;
- if ((i >= 0) && (i < ebase.bptnum)) {
- printf("deleted breakpoint %d at 0x%08x\n", i + 1,
- ebase.bpts[i]);
- for (; i < ebase.bptnum - 1; i++) {
- ebase.bpts[i] = ebase.bpts[i + 1];
+ else
+ {
+ for (i = 0; i < ebase.bptnum; i++)
+ {
+ printf (" %d : 0x%08x\n", i + 1, ebase.bpts[i]);
+ }
+ }
+ }
+ else if ((strncmp (cmd1, "-bp", clen) == 0) ||
+ (strncmp (cmd1, "delete", clen) == 0))
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ i = VAL (cmd1) - 1;
+ if ((i >= 0) && (i < ebase.bptnum))
+ {
+ printf ("deleted breakpoint %d at 0x%08x\n", i + 1,
+ ebase.bpts[i]);
+ for (; i < ebase.bptnum - 1; i++)
+ {
+ ebase.bpts[i] = ebase.bpts[i + 1];
}
- ebase.bptnum -= 1;
+ ebase.bptnum -= 1;
}
}
- } else if (strncmp(cmd1, "batch", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- printf("no file specified\n");
- } else {
- batch(sregs, cmd1);
+ }
+ else if (strncmp (cmd1, "batch", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) == NULL)
+ {
+ printf ("no file specified\n");
+ }
+ else
+ {
+ batch (sregs, cmd1);
+ }
+ }
+ else if (strncmp (cmd1, "cont", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) == NULL)
+ {
+ stat = run_sim (UINT64_MAX / 2, 0);
}
- } else if (strncmp(cmd1, "cont", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- stat = run_sim(UINT64_MAX/2, 0);
- } else {
- stat = run_sim(VAL(cmd1), 0);
+ else
+ {
+ stat = run_sim (VAL (cmd1), 0);
}
- daddr = sregs->pc;
- ms->sim_halt ();
- } else if (strncmp(cmd1, "debug", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- sis_verbose = VAL(cmd1);
+ daddr = sregs->pc;
+ ms->sim_halt ();
+ }
+ else if (strncmp (cmd1, "debug", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ sis_verbose = VAL (cmd1);
}
- printf("Debug level = %d\n",sis_verbose);
- } else if (strncmp(cmd1, "disas", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- daddr = VAL(cmd1);
+ printf ("Debug level = %d\n", sis_verbose);
+ }
+ else if (strncmp (cmd1, "disas", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ daddr = VAL (cmd1);
+ }
+ if ((cmd2 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ len = VAL (cmd2);
+ }
+ else
+ len = 16;
+ printf ("\n");
+ daddr = dis_mem (daddr, len);
+ printf ("\n");
+ }
+ else if (strncmp (cmd1, "echo", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ printf ("%s\n", (&cmdsave[clen + 1]));
+ }
+ }
+ else if (strncmp (cmd1, "float", clen) == 0)
+ {
+ arch->display_fpu (sregs);
+ }
+ else if (strncmp (cmd1, "go", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) == NULL)
+ {
+ len = last_load_addr;
}
- if ((cmd2 = strtok(NULL, " \t\n\r")) != NULL) {
- len = VAL(cmd2);
- } else
- len = 16;
- printf("\n");
- daddr = dis_mem(daddr, len);
- printf("\n");
- } else if (strncmp(cmd1, "echo", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- printf("%s\n", (&cmdsave[clen+1]));
+ else
+ {
+ len = VAL (cmd1);
}
- } else if (strncmp(cmd1, "float", clen) == 0) {
- arch->display_fpu(sregs);
- } else if (strncmp(cmd1, "go", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- len = last_load_addr;
- } else {
- len = VAL(cmd1);
+ for (i = 0; i < ncpu; i++)
+ {
+ sregs[i].pc = len & ~1;
+ sregs[i].npc = sregs->pc + 4;
}
- for (i=0; i<ncpu; i++) {
- sregs[i].pc = len & ~1;
- sregs[i].npc = sregs->pc + 4;
+ if ((sregs->pc != 0) && (ebase.simtime == 0))
+ ms->boot_init ();
+ printf ("resuming at 0x%08x\n", sregs->pc);
+ if ((cmd2 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ stat = run_sim (VAL (cmd2), 0);
}
- if ((sregs->pc != 0) && (ebase.simtime == 0))
- ms->boot_init ();
- printf("resuming at 0x%08x\n",sregs->pc);
- if ((cmd2 = strtok(NULL, " \t\n\r")) != NULL) {
- stat = run_sim(VAL(cmd2), 0);
- } else {
- stat = run_sim(UINT64_MAX/2, 0);
+ else
+ {
+ stat = run_sim (UINT64_MAX / 2, 0);
}
- daddr = sregs->pc;
- ms->sim_halt ();
- } else if (strncmp(cmd1, "gdb", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- port = VAL(cmd1);
- if (port < 1024) port = 1024;
+ daddr = sregs->pc;
+ ms->sim_halt ();
+ }
+ else if (strncmp (cmd1, "gdb", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ port = VAL (cmd1);
+ if (port < 1024)
+ port = 1024;
}
- gdb_remote(port);
- } else if (strncmp(cmd1, "help", clen) == 0) {
- gen_help();
- } else if (strncmp(cmd1, "history", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- ebase.histlen = VAL(cmd1);
- for (i=0; i<ncpu; i++) {
- if (sregs[i].histbuf != NULL)
- free(sregs[i].histbuf);
- sregs[i].histbuf = (struct histype *) calloc(ebase.histlen, sizeof(struct histype));
- sregs[i].histind = 0;
+ gdb_remote (port);
+ }
+ else if (strncmp (cmd1, "help", clen) == 0)
+ {
+ gen_help ();
+ }
+ else if (strncmp (cmd1, "history", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ ebase.histlen = VAL (cmd1);
+ for (i = 0; i < ncpu; i++)
+ {
+ if (sregs[i].histbuf != NULL)
+ free (sregs[i].histbuf);
+ sregs[i].histbuf =
+ (struct histype *) calloc (ebase.histlen,
+ sizeof (struct histype));
+ sregs[i].histind = 0;
}
- printf("trace history length = %d\n\r", ebase.histlen);
-
- } else {
- j = sregs[cpu].histind;
- for (i = 0; i < ebase.histlen; i++) {
- if (j >= ebase.histlen)
- j = 0;
- printf(" %8" PRIu64 " ", sregs[cpu].histbuf[j].time);
- dis_mem(sregs[cpu].histbuf[j].addr, 1);
- j++;
+ printf ("trace history length = %d\n\r", ebase.histlen);
+
+ }
+ else
+ {
+ j = sregs[cpu].histind;
+ for (i = 0; i < ebase.histlen; i++)
+ {
+ if (j >= ebase.histlen)
+ j = 0;
+ printf (" %8" PRIu64 " ", sregs[cpu].histbuf[j].time);
+ dis_mem (sregs[cpu].histbuf[j].addr, 1);
+ j++;
}
}
- } else if (strncmp(cmd1, "load", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- last_load_addr = elf_load(cmd1, 1);
- daddr = last_load_addr;
- while ((cmd1 = strtok(NULL, " \t\n\r")) != NULL)
- last_load_addr = elf_load(cmd1, 1);
- } else {
- printf("load: no file specified\n");
+ }
+ else if (strncmp (cmd1, "load", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ last_load_addr = elf_load (cmd1, 1);
+ daddr = last_load_addr;
+ while ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ last_load_addr = elf_load (cmd1, 1);
}
- } else if (strncmp(cmd1, "mem", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL)
- daddr = VAL(cmd1);
- if ((cmd2 = strtok(NULL, " \t\n\r")) != NULL)
- len = VAL(cmd2);
- else
- len = 64;
- disp_mem(daddr, len);
- daddr += len;
- } else if (strncmp(cmd1, "cpu", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- cpu = VAL(cmd1);
- if (cpu > NCPU) cpu = NCPU;
+ else
+ {
+ printf ("load: no file specified\n");
}
- printf("active cpu: %d\n", cpu);
- } else if (strncmp(cmd1, "ncpu", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- ncpu = VAL(cmd1);
- if (ncpu > NCPU) ncpu = NCPU;
+ }
+ else if (strncmp (cmd1, "mem", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ daddr = VAL (cmd1);
+ if ((cmd2 = strtok (NULL, " \t\n\r")) != NULL)
+ len = VAL (cmd2);
+ else
+ len = 64;
+ disp_mem (daddr, len);
+ daddr += len;
+ }
+ else if (strncmp (cmd1, "cpu", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ cpu = VAL (cmd1);
+ if (cpu > NCPU)
+ cpu = NCPU;
+ }
+ printf ("active cpu: %d\n", cpu);
+ }
+ else if (strncmp (cmd1, "ncpu", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ ncpu = VAL (cmd1);
+ if (ncpu > NCPU)
+ ncpu = NCPU;
+ }
+ printf ("number of online cpus: %d\n", ncpu);
+ }
+ else if (strncmp (cmd1, "wmem", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ daddr = VAL (cmd1);
+ if ((cmd2 = strtok (NULL, " \t\n\r")) != NULL)
+ len = VAL (cmd2);
+ ms->sis_memory_write (daddr, (char *) &len, 4);
+ }
+ else if (strncmp (cmd1, "perf", clen) == 0)
+ {
+ cmd1 = strtok (NULL, " \t\n\r");
+ if ((cmd1 != NULL) && (strncmp (cmd1, "reset", strlen (cmd1)) == 0))
+ {
+ reset_stat (sregs);
}
- printf("number of online cpus: %d\n", ncpu);
- } else if (strncmp(cmd1, "wmem", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL)
- daddr = VAL(cmd1);
- if ((cmd2 = strtok(NULL, " \t\n\r")) != NULL)
- len = VAL(cmd2);
- ms->sis_memory_write (daddr, (char *) &len, 4);
- } else if (strncmp(cmd1, "perf", clen) == 0) {
- cmd1 = strtok(NULL, " \t\n\r");
- if ((cmd1 != NULL) &&
- (strncmp(cmd1, "reset", strlen(cmd1)) == 0)) {
- reset_stat(sregs);
- } else
- show_stat(sregs);
- } else if (strncmp(cmd1, "quit", clen) == 0) {
- stat = QUIT;
- } else if (strncmp(cmd1, "csr", clen) == 0) {
- arch->display_special(&sregs[cpu]);
- } else if (strncmp(cmd1, "reg", clen) == 0) {
- cmd1 = strtok(NULL, " \t\n\r");
- cmd2 = strtok(NULL, " \t\n\r");
- if (cmd2 != NULL)
- arch->set_register(&sregs[cpu], cmd1, VAL(cmd2), 0);
- /*
- else if (cmd1 != NULL)
- disp_reg(&sregs[cpu], cmd1);
- */
- else {
- arch->display_registers(&sregs[cpu]);
- arch->display_ctrl(&sregs[cpu]);
+ else
+ show_stat (sregs);
+ }
+ else if (strncmp (cmd1, "quit", clen) == 0)
+ {
+ stat = QUIT;
+ }
+ else if (strncmp (cmd1, "csr", clen) == 0)
+ {
+ arch->display_special (&sregs[cpu]);
+ }
+ else if (strncmp (cmd1, "reg", clen) == 0)
+ {
+ cmd1 = strtok (NULL, " \t\n\r");
+ cmd2 = strtok (NULL, " \t\n\r");
+ if (cmd2 != NULL)
+ arch->set_register (&sregs[cpu], cmd1, VAL (cmd2), 0);
+ /*
+ else if (cmd1 != NULL)
+ disp_reg(&sregs[cpu], cmd1);
+ */
+ else
+ {
+ arch->display_registers (&sregs[cpu]);
+ arch->display_ctrl (&sregs[cpu]);
}
- } else if (strncmp(cmd1, "reset", clen) == 0) {
- ebase.simtime = 0;
- ebase.simstart = 0;
- reset_all();
- reset_stat(sregs);
- } else if (strncmp(cmd1, "run", clen) == 0) {
- ebase.simtime = 0;
- ebase.simstart = 0;
- reset_all();
- reset_stat(sregs);
- if (last_load_addr != 0) {
- for (i=0; i<ncpu; i++) {
- sregs[i].pc = last_load_addr & ~3;
- sregs[i].npc = sregs[i].pc + 4;
+ }
+ else if (strncmp (cmd1, "reset", clen) == 0)
+ {
+ ebase.simtime = 0;
+ ebase.simstart = 0;
+ reset_all ();
+ reset_stat (sregs);
+ }
+ else if (strncmp (cmd1, "run", clen) == 0)
+ {
+ ebase.simtime = 0;
+ ebase.simstart = 0;
+ reset_all ();
+ reset_stat (sregs);
+ if (last_load_addr != 0)
+ {
+ for (i = 0; i < ncpu; i++)
+ {
+ sregs[i].pc = last_load_addr & ~3;
+ sregs[i].npc = sregs[i].pc + 4;
}
- }
- if ((sregs->pc != 0) && (ebase.simtime == 0)) ms->boot_init ();
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- stat = run_sim(UINT64_MAX/2, 0);
- } else {
- stat = run_sim(VAL(cmd1), 0);
}
- daddr = sregs->pc;
- ms->sim_halt ();
- } else if (strncmp(cmd1, "shell", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- if (system(&cmdsave[clen])) {
- /* Silence unused return value warning. */
+ if ((sregs->pc != 0) && (ebase.simtime == 0))
+ ms->boot_init ();
+ if ((cmd1 = strtok (NULL, " \t\n\r")) == NULL)
+ {
+ stat = run_sim (UINT64_MAX / 2, 0);
+ }
+ else
+ {
+ stat = run_sim (VAL (cmd1), 0);
+ }
+ daddr = sregs->pc;
+ ms->sim_halt ();
+ }
+ else if (strncmp (cmd1, "shell", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ if (system (&cmdsave[clen]))
+ {
+ /* Silence unused return value warning. */
}
}
- /*
- } else if (strncmp(cmd1, "sym", clen) == 0) {
- symprint ();
- */
- } else if (strncmp(cmd1, "step", clen) == 0) {
- stat = run_sim(1, 1);
- daddr = sregs->pc;
- ms->sim_halt ();
- } else if (strncmp(cmd1, "tcont", clen) == 0) {
- ebase.tlimit = limcalc(ebase.freq);
- stat = run_sim(UINT64_MAX/2, 0);
- daddr = sregs->pc;
- ms->sim_halt ();
- } else if (strncmp(cmd1, "tgo", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- len = last_load_addr;
- } else {
- len = VAL(cmd1);
- ebase.tlimit = limcalc(ebase.freq);
+ /*
+ } else if (strncmp(cmd1, "sym", clen) == 0) {
+ symprint ();
+ */
+ }
+ else if (strncmp (cmd1, "step", clen) == 0)
+ {
+ stat = run_sim (1, 1);
+ daddr = sregs->pc;
+ ms->sim_halt ();
+ }
+ else if (strncmp (cmd1, "tcont", clen) == 0)
+ {
+ ebase.tlimit = limcalc (ebase.freq);
+ stat = run_sim (UINT64_MAX / 2, 0);
+ daddr = sregs->pc;
+ ms->sim_halt ();
+ }
+ else if (strncmp (cmd1, "tgo", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) == NULL)
+ {
+ len = last_load_addr;
+ }
+ else
+ {
+ len = VAL (cmd1);
+ ebase.tlimit = limcalc (ebase.freq);
+ }
+ sregs->pc = len & ~1;
+ sregs->npc = sregs->pc + 4;
+ printf ("resuming at 0x%08x\n", sregs->pc);
+ stat = run_sim (UINT64_MAX / 2, 0);
+ daddr = sregs->pc;
+ ms->sim_halt ();
+ }
+ else if (strncmp (cmd1, "tlimit", clen) == 0)
+ {
+ ebase.tlimit = limcalc (ebase.freq);
+ if (ebase.tlimit != (uint32) - 1)
+ if (sis_verbose)
+ printf ("simulation limit = %u (%.3f ms)\n",
+ (uint32) ebase.tlimit,
+ ebase.tlimit / ebase.freq / 1000);
+ }
+ else if (strncmp (cmd1, "tra", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) == NULL)
+ {
+ stat = run_sim (UINT64_MAX / 2, 1);
}
- sregs->pc = len & ~1;
- sregs->npc = sregs->pc + 4;
- printf("resuming at 0x%08x\n",sregs->pc);
- stat = run_sim(UINT64_MAX/2, 0);
- daddr = sregs->pc;
- ms->sim_halt ();
- } else if (strncmp(cmd1, "tlimit", clen) == 0) {
- ebase.tlimit = limcalc(ebase.freq);
- if (ebase.tlimit != (uint32) -1)
- if (sis_verbose)
- printf("simulation limit = %u (%.3f ms)\n",
- (uint32) ebase.tlimit, ebase.tlimit / ebase.freq / 1000);
- } else if (strncmp(cmd1, "tra", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) == NULL) {
- stat = run_sim(UINT64_MAX/2, 1);
- } else {
- stat = run_sim(VAL(cmd1), 1);
+ else
+ {
+ stat = run_sim (VAL (cmd1), 1);
}
- printf("\n");
- daddr = sregs->pc;
- ms->sim_halt ();
- } else if (strncmp(cmd1, "trun", clen) == 0) {
- ebase.simtime = 0;
- ebase.simstart = 0;
- reset_all();
- reset_stat(sregs);
- if (last_load_addr != 0) {
- for (i=0; i<ncpu; i++) {
- sregs[i].pc = last_load_addr & ~3;
- sregs[i].npc = sregs[i].pc + 4;
+ printf ("\n");
+ daddr = sregs->pc;
+ ms->sim_halt ();
+ }
+ else if (strncmp (cmd1, "trun", clen) == 0)
+ {
+ ebase.simtime = 0;
+ ebase.simstart = 0;
+ reset_all ();
+ reset_stat (sregs);
+ if (last_load_addr != 0)
+ {
+ for (i = 0; i < ncpu; i++)
+ {
+ sregs[i].pc = last_load_addr & ~3;
+ sregs[i].npc = sregs[i].pc + 4;
}
- }
- if ((sregs->pc != 0) && (ebase.simtime == 0)) ms->boot_init ();
- ebase.tlimit = limcalc(ebase.freq);
- stat = run_sim(UINT64_MAX/2, 0);
- daddr = sregs->pc;
- ms->sim_halt ();
- } else if (strncmp(cmd1, "wp", clen) == 0) {
- for (i = 0; i < ebase.wprnum; i++) {
- printf(" %d : 0x%08x (read)\n", i + 1, ebase.wprs[i]);
}
- for (i = 0; i < ebase.wpwnum; i++) {
- printf(" %d : 0x%08x (write)\n", i + 1, ebase.wpws[i]);
+ if ((sregs->pc != 0) && (ebase.simtime == 0))
+ ms->boot_init ();
+ ebase.tlimit = limcalc (ebase.freq);
+ stat = run_sim (UINT64_MAX / 2, 0);
+ daddr = sregs->pc;
+ ms->sim_halt ();
+ }
+ else if (strncmp (cmd1, "wp", clen) == 0)
+ {
+ for (i = 0; i < ebase.wprnum; i++)
+ {
+ printf (" %d : 0x%08x (read)\n", i + 1, ebase.wprs[i]);
}
- } else if (strncmp(cmd1, "+wpr", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- ebase.wprs[ebase.wprnum] = VAL(cmd1) & ~0x3;
- ebase.wprm[ebase.wprnum] = 3;
- printf("added read watchpoint %d at 0x%08x\n",
- ebase.wprnum + 1, ebase.wprs[ebase.wprnum]);
- ebase.wprnum += 1;
+ for (i = 0; i < ebase.wpwnum; i++)
+ {
+ printf (" %d : 0x%08x (write)\n", i + 1, ebase.wpws[i]);
}
- } else if (strncmp(cmd1, "-wpr", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- i = VAL(cmd1) - 1;
- if ((i >= 0) && (i < ebase.wprnum)) {
- printf("deleted read watchpoint %d at 0x%08x\n", i + 1,
- ebase.wprs[i]);
- for (; i < ebase.wprnum - 1; i++) {
- ebase.wprs[i] = ebase.wprs[i + 1];
+ }
+ else if (strncmp (cmd1, "+wpr", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ ebase.wprs[ebase.wprnum] = VAL (cmd1) & ~0x3;
+ ebase.wprm[ebase.wprnum] = 3;
+ printf ("added read watchpoint %d at 0x%08x\n",
+ ebase.wprnum + 1, ebase.wprs[ebase.wprnum]);
+ ebase.wprnum += 1;
+ }
+ }
+ else if (strncmp (cmd1, "-wpr", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ i = VAL (cmd1) - 1;
+ if ((i >= 0) && (i < ebase.wprnum))
+ {
+ printf ("deleted read watchpoint %d at 0x%08x\n", i + 1,
+ ebase.wprs[i]);
+ for (; i < ebase.wprnum - 1; i++)
+ {
+ ebase.wprs[i] = ebase.wprs[i + 1];
}
- ebase.wprnum -= 1;
+ ebase.wprnum -= 1;
}
}
- } else if ((strncmp(cmd1, "+wpw", clen) == 0) ||
- (strncmp(cmd1, "watch", clen) == 0)) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- ebase.wpws[ebase.wpwnum] = VAL(cmd1) & ~0x3;
- ebase.wpwm[ebase.wpwnum] = 3;
- printf("added write watchpoint %d at 0x%08x\n",
- ebase.wpwnum + 1, ebase.wpws[ebase.wpwnum]);
- ebase.wpwnum += 1;
- } else {
- for (i = 0; i < ebase.wpwnum; i++) {
- printf(" %d : 0x%08x (write)\n", i + 1, ebase.wpws[i]);
- }
+ }
+ else if ((strncmp (cmd1, "+wpw", clen) == 0) ||
+ (strncmp (cmd1, "watch", clen) == 0))
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ ebase.wpws[ebase.wpwnum] = VAL (cmd1) & ~0x3;
+ ebase.wpwm[ebase.wpwnum] = 3;
+ printf ("added write watchpoint %d at 0x%08x\n",
+ ebase.wpwnum + 1, ebase.wpws[ebase.wpwnum]);
+ ebase.wpwnum += 1;
+ }
+ else
+ {
+ for (i = 0; i < ebase.wpwnum; i++)
+ {
+ printf (" %d : 0x%08x (write)\n", i + 1, ebase.wpws[i]);
+ }
}
- } else if (strncmp(cmd1, "-wpw", clen) == 0) {
- if ((cmd1 = strtok(NULL, " \t\n\r")) != NULL) {
- i = VAL(cmd1) - 1;
- if ((i >= 0) && (i < ebase.wpwnum)) {
- printf("deleted write watchpoint %d at 0x%08x\n", i + 1,
- ebase.wpws[i]);
- for (; i < ebase.wpwnum - 1; i++) {
- ebase.wpws[i] = ebase.wpws[i + 1];
+ }
+ else if (strncmp (cmd1, "-wpw", clen) == 0)
+ {
+ if ((cmd1 = strtok (NULL, " \t\n\r")) != NULL)
+ {
+ i = VAL (cmd1) - 1;
+ if ((i >= 0) && (i < ebase.wpwnum))
+ {
+ printf ("deleted write watchpoint %d at 0x%08x\n", i + 1,
+ ebase.wpws[i]);
+ for (; i < ebase.wpwnum - 1; i++)
+ {
+ ebase.wpws[i] = ebase.wpws[i + 1];
}
- ebase.wpwnum -= 1;
+ ebase.wpwnum -= 1;
}
}
- } else
- printf("syntax error\n");
+ }
+ else
+ printf ("syntax error\n");
}
- if (cmdsave2 != NULL)
- free(cmdsave2);
- if (cmdsave != NULL)
- free(cmdsave);
- return stat;
+ if (cmdsave2 != NULL)
+ free (cmdsave2);
+ if (cmdsave != NULL)
+ free (cmdsave);
+ return stat;
}
void
-reset_stat(sregs)
- struct pstate *sregs;
+reset_stat (sregs)
+ struct pstate *sregs;
{
- ebase.tottime = 0.0;
- sregs->pwdtime = 0;
- sregs->ninst = 0;
- sregs->fholdt = 0;
- sregs->holdt = 0;
- sregs->icntt = 0;
- sregs->finst = 0;
- sregs->nstore = 0;
- sregs->nload = 0;
- sregs->nbranch = 0;
- ebase.simstart = ebase.simtime;
- sregs->l1imiss = 0;
- sregs->l1dmiss = 0;
+ ebase.tottime = 0.0;
+ sregs->pwdtime = 0;
+ sregs->ninst = 0;
+ sregs->fholdt = 0;
+ sregs->holdt = 0;
+ sregs->icntt = 0;
+ sregs->finst = 0;
+ sregs->nstore = 0;
+ sregs->nload = 0;
+ sregs->nbranch = 0;
+ ebase.simstart = ebase.simtime;
+ sregs->l1imiss = 0;
+ sregs->l1dmiss = 0;
}
void
-show_stat(sregs)
- struct pstate *sregs;
+show_stat (sregs)
+ struct pstate *sregs;
{
- uint64 iinst, ninst, pwdtime;
- uint64 stime, atime;
- int i;
-
- ninst = 0;
- pwdtime = 0;
- atime = 0;
- if (ebase.tottime == 0.0)
- ebase.tottime += 1E-6;
- for (i=0; i<ncpu; i++) {
- if (sregs[i].pwd_mode) {
- sregs[i].pwdtime += sregs[i].simtime - sregs[i].pwdstart;
- sregs[i].pwdstart = sregs[i].simtime;
+ uint64 iinst, ninst, pwdtime;
+ uint64 stime, atime;
+ int i;
+
+ ninst = 0;
+ pwdtime = 0;
+ atime = 0;
+ if (ebase.tottime == 0.0)
+ ebase.tottime += 1E-6;
+ for (i = 0; i < ncpu; i++)
+ {
+ if (sregs[i].pwd_mode)
+ {
+ sregs[i].pwdtime += sregs[i].simtime - sregs[i].pwdstart;
+ sregs[i].pwdstart = sregs[i].simtime;
}
- ninst += sregs[i].ninst;
- pwdtime += sregs[i].pwdtime;
+ ninst += sregs[i].ninst;
+ pwdtime += sregs[i].pwdtime;
}
- stime = ebase.simtime - ebase.simstart; /* Total simulated time */
- printf ("\n Frequency : %4.1f MHz\n", ebase.freq);
- printf(" Cycles : %" PRIu64 "\n", stime);
- printf(" Instructions : %" PRIu64 "\n", ninst);
- printf(" Simulated time : %.2f s\n",
- (double) (stime) / 1000000.0 / ebase.freq);
- printf(" System perf. : %.2f MOPS\n",
- (double) ninst / ((double) (stime) / ebase.freq));
- printf(" Real-time perf. : %.2f %%\n",
- 100.0 / (ebase.tottime / ((double) (stime) / (ebase.freq * 1.0E6))));
- printf(" Simulator perf. : %.2f MIPS\n",
- (double)(ninst / ebase.tottime / 1E6));
- printf(" Wall time : %.2f s\n\n", ebase.tottime);
- printf (" Core MIPS MFLOPS CPI Util"
+ stime = ebase.simtime - ebase.simstart; /* Total simulated time */
+ printf ("\n Frequency : %4.1f MHz\n", ebase.freq);
+ printf (" Cycles : %" PRIu64 "\n", stime);
+ printf (" Instructions : %" PRIu64 "\n", ninst);
+ printf (" Simulated time : %.2f s\n",
+ (double) (stime) / 1000000.0 / ebase.freq);
+ printf (" System perf. : %.2f MOPS\n",
+ (double) ninst / ((double) (stime) / ebase.freq));
+ printf (" Real-time perf. : %.2f %%\n",
+ 100.0 / (ebase.tottime /
+ ((double) (stime) / (ebase.freq * 1.0E6))));
+ printf (" Simulator perf. : %.2f MIPS\n",
+ (double) (ninst / ebase.tottime / 1E6));
+ printf (" Wall time : %.2f s\n\n", ebase.tottime);
+ printf (" Core MIPS MFLOPS CPI Util"
#ifdef ENABLE_L1CACHE
- " IHit DHit"
+ " IHit DHit"
#endif
- "\n"
- );
- for (i=0; i<ncpu; i++) {
+ "\n");
+ for (i = 0; i < ncpu; i++)
+ {
#ifdef STAT
- iinst = sregs[i].ninst - sregs[i].finst - sregs[i].nload - sregs[i].nstore -
- sregs[i].nbranch;
+ iinst =
+ sregs[i].ninst - sregs[i].finst - sregs[i].nload - sregs[i].nstore -
+ sregs[i].nbranch;
#endif
- stime = sregs[i].simtime - ebase.simstart + 1; /* Core simulated time */
- printf (" %d %5.2f %5.2f %5.2f %5.2f%%"
+ stime = sregs[i].simtime - ebase.simstart + 1; /* Core simulated time */
+ printf (" %d %5.2f %5.2f %5.2f %5.2f%%"
#ifdef ENABLE_L1CACHE
- " %5.2f%% %5.2f%%"
+ " %5.2f%% %5.2f%%"
#endif
- "\n", i,
- ebase.freq * (double) (sregs[i].ninst - sregs[i].finst) /
- (double) (stime - sregs[i].pwdtime),
- ebase.freq * (double) sregs[i].finst / (double) (stime - sregs[i].pwdtime),
- (double) (stime - sregs[i].pwdtime) / (double) (sregs[i].ninst + 1),
- 100.0 * (1.0 - ((double) sregs[i].pwdtime / (double) stime))
+ "\n", i,
+ ebase.freq * (double) (sregs[i].ninst - sregs[i].finst) /
+ (double) (stime - sregs[i].pwdtime),
+ ebase.freq * (double) sregs[i].finst / (double) (stime -
+ sregs[i].
+ pwdtime),
+ (double) (stime - sregs[i].pwdtime) / (double) (sregs[i].ninst +
+ 1),
+ 100.0 * (1.0 - ((double) sregs[i].pwdtime / (double) stime))
#ifdef ENABLE_L1CACHE
- ,(double) (sregs[i].ninst - sregs[i].l1imiss + 1) /
- (double) (sregs[i].ninst + 1) * 100.0,
- (double) (sregs[i].nload + sregs[i].nstore - sregs[i].l1dmiss + 1) /
- (double) (sregs[i].nload + sregs[i].nstore + 1) * 100.0
+ , (double) (sregs[i].ninst - sregs[i].l1imiss + 1) /
+ (double) (sregs[i].ninst + 1) * 100.0,
+ (double) (sregs[i].nload + sregs[i].nstore - sregs[i].l1dmiss +
+ 1) / (double) (sregs[i].nload + sregs[i].nstore +
+ 1) * 100.0
#endif
- ) ;
+ );
}
#ifdef STAT
- printf (" integer : %9.2f %%\n", 100.0 * (double) iinst / (double) sregs[i].ninst);
- printf(" load : %9.2f %%\n",
- 100.0 * (double) sregs->nload / (double) sregs[i].ninst);
- printf(" store : %9.2f %%\n",
- 100.0 * (double) sregs->nstore / (double) sregs[i].ninst);
- printf(" branch : %9.2f %%\n",
- 100.0 * (double) sregs->nbranch / (double) sregs[i].ninst);
- printf(" float : %9.2f %%\n",
- 100.0 * (double) sregs->finst / (double) sregs[i].ninst);
- printf(" Integer CPI : %9.2f\n",
- ((double) (stime - sregs[i].pwdtime - sregs[i].fholdt - sregs[i].finst))
- /
- (double) (sregs[i].ninst - sregs[i].finst));
- printf(" Float CPI : %9.2f\n",
- ((double) sregs[i].fholdt / (double) sregs[i].finst) + 1.0);
+ printf (" integer : %9.2f %%\n",
+ 100.0 * (double) iinst / (double) sregs[i].ninst);
+ printf (" load : %9.2f %%\n",
+ 100.0 * (double) sregs->nload / (double) sregs[i].ninst);
+ printf (" store : %9.2f %%\n",
+ 100.0 * (double) sregs->nstore / (double) sregs[i].ninst);
+ printf (" branch : %9.2f %%\n",
+ 100.0 * (double) sregs->nbranch / (double) sregs[i].ninst);
+ printf (" float : %9.2f %%\n",
+ 100.0 * (double) sregs->finst / (double) sregs[i].ninst);
+ printf (" Integer CPI : %9.2f\n",
+ ((double)
+ (stime - sregs[i].pwdtime - sregs[i].fholdt -
+ sregs[i].finst)) / (double) (sregs[i].ninst - sregs[i].finst));
+ printf (" Float CPI : %9.2f\n",
+ ((double) sregs[i].fholdt / (double) sregs[i].finst) + 1.0);
#endif
- printf("\n");
+ printf ("\n");
}
void
-init_bpt(sregs)
- struct pstate *sregs;
+init_bpt (sregs)
+ struct pstate *sregs;
{
- int i;
-
- ebase.bptnum = 0;
- ebase.wprnum = 0;
- ebase.wpwnum = 0;
- ebase.histlen = 0;
- for (i=0; i<ncpu; i++) {
- sregs[i].histind = 0;
- sregs[i].histbuf = NULL;
+ int i;
+
+ ebase.bptnum = 0;
+ ebase.wprnum = 0;
+ ebase.wpwnum = 0;
+ ebase.histlen = 0;
+ for (i = 0; i < ncpu; i++)
+ {
+ sregs[i].histind = 0;
+ sregs[i].histbuf = NULL;
}
- ebase.tlimit = 0;
+ ebase.tlimit = 0;
}
/* taken from gdbserver */
@@ -654,600 +825,686 @@ check_interrup ()
}
void
-int_handler(int sig)
+int_handler (int sig)
{
- int count;
+ int count;
- switch(sig) {
- case SIGIO :
- if (sim_run) {
- check_interrup();
- }
+ switch (sig)
+ {
+ case SIGIO:
+ if (sim_run)
+ {
+ check_interrup ();
+ }
break;
- case SIGINT :
- ctrl_c = 1;
- if (!sim_run) {
- if (new_socket > 0)
- close(new_socket);
- else
- exit(0);
+ case SIGINT:
+ ctrl_c = 1;
+ if (!sim_run)
+ {
+ if (new_socket > 0)
+ close (new_socket);
+ else
+ exit (0);
}
- break;
+ break;
default:
- printf("\n\n Signal handler error (%d)\n\n", sig);
+ printf ("\n\n Signal handler error (%d)\n\n", sig);
}
}
void
-init_signals()
+init_signals ()
{
- typedef void (*PFI) ();
- static PFI int_tab[2];
+ typedef void (*PFI) ();
+ static PFI int_tab[2];
- int_tab[0] = signal(SIGTERM, int_handler);
- int_tab[1] = signal(SIGINT, int_handler);
+ int_tab[0] = signal (SIGTERM, int_handler);
+ int_tab[1] = signal (SIGINT, int_handler);
}
-void print_insn_sis(uint32 addr)
+void
+print_insn_sis (uint32 addr)
{
- char i[4];
+ char i[4];
- ms->sis_memory_read (addr, i, 4);
- arch->disas(addr );
+ ms->sis_memory_read (addr, i, 4);
+ arch->disas (addr);
}
static void
-disp_mem(addr, len)
- uint32 addr;
- uint32 len;
+disp_mem (addr, len)
+ uint32 addr;
+ uint32 len;
{
- uint32 i;
- union {
- char u8[4];
- uint32 u32;
- } data;
- uint32 mem[4], j;
- char *p;
-
- for (i = addr & ~3; i < ((addr + len) & ~3); i += 16) {
- printf("\n %8X ", i);
- for (j = 0; j < 4; j++) {
- ms->sis_memory_read ((i + (j * 4)), data.u8, 4);
- printf ("%08x ", data.u32);
- mem[j] = data.u32;
+ uint32 i;
+ union
+ {
+ char u8[4];
+ uint32 u32;
+ } data;
+ uint32 mem[4], j;
+ char *p;
+
+ for (i = addr & ~3; i < ((addr + len) & ~3); i += 16)
+ {
+ printf ("\n %8X ", i);
+ for (j = 0; j < 4; j++)
+ {
+ ms->sis_memory_read ((i + (j * 4)), data.u8, 4);
+ printf ("%08x ", data.u32);
+ mem[j] = data.u32;
}
- printf(" ");
- p = (char *) mem;
- for (j = 0; j < 16; j++) {
- if (isprint (p[j ^ arch->endian]))
- putchar (p[j ^ arch->endian]);
- else
- putchar('.');
+ printf (" ");
+ p = (char *) mem;
+ for (j = 0; j < 16; j++)
+ {
+ if (isprint (p[j ^ arch->endian]))
+ putchar (p[j ^ arch->endian]);
+ else
+ putchar ('.');
}
}
- printf("\n\n");
+ printf ("\n\n");
}
uint32
-dis_mem(addr, len)
- uint32 addr;
- uint32 len;
+dis_mem (addr, len)
+ uint32 addr;
+ uint32 len;
{
- uint32 i, data;
-
- for (i = 0; i < len; i ++) {
- ms->sis_memory_read (addr,(char *) &data, 4);
- if ((cputype == CPU_RISCV) && ((data & 3) != 3)) {
- data &= 0x0ffff;
- printf (" %08x: %04x ", addr, data);
- } else
- printf (" %08x: %08x ", addr, data);
- print_insn_sis(addr);
- if (i >= 0xfffffffc) break;
- printf("\n");
- if ((cputype == CPU_RISCV) &&((data & 3) != 3))
- addr += 2;
- else
- addr += 4;
+ uint32 i, data;
+
+ for (i = 0; i < len; i++)
+ {
+ ms->sis_memory_read (addr, (char *) &data, 4);
+ if ((cputype == CPU_RISCV) && ((data & 3) != 3))
+ {
+ data &= 0x0ffff;
+ printf (" %08x: %04x ", addr, data);
+ }
+ else
+ printf (" %08x: %08x ", addr, data);
+ print_insn_sis (addr);
+ if (i >= 0xfffffffc)
+ break;
+ printf ("\n");
+ if ((cputype == CPU_RISCV) && ((data & 3) != 3))
+ addr += 2;
+ else
+ addr += 4;
}
- return addr;
+ return addr;
}
/* Add event to event queue */
void
-event(cfunc, arg, delta)
- void (*cfunc) ();
- int32 arg;
- uint64 delta;
+event (cfunc, arg, delta)
+ void (*cfunc) ();
+ int32 arg;
+ uint64 delta;
{
- struct evcell *ev1, *evins;
+ struct evcell *ev1, *evins;
- if (ebase.freeq == NULL) {
- printf("Error, too many events in event queue\n");
- return;
+ if (ebase.freeq == NULL)
+ {
+ printf ("Error, too many events in event queue\n");
+ return;
}
- ev1 = &ebase.eq;
- delta += ebase.simtime;
- while ((ev1->nxt != NULL) && (ev1->nxt->time <= delta)) {
- ev1 = ev1->nxt;
+ ev1 = &ebase.eq;
+ delta += ebase.simtime;
+ while ((ev1->nxt != NULL) && (ev1->nxt->time <= delta))
+ {
+ ev1 = ev1->nxt;
+ }
+ if (ev1->nxt == NULL)
+ {
+ ev1->nxt = ebase.freeq;
+ ebase.freeq = ebase.freeq->nxt;
+ ev1->nxt->nxt = NULL;
}
- if (ev1->nxt == NULL) {
- ev1->nxt = ebase.freeq;
- ebase.freeq = ebase.freeq->nxt;
- ev1->nxt->nxt = NULL;
- } else {
- evins = ebase.freeq;
- ebase.freeq = ebase.freeq->nxt;
- evins->nxt = ev1->nxt;
- ev1->nxt = evins;
+ else
+ {
+ evins = ebase.freeq;
+ ebase.freeq = ebase.freeq->nxt;
+ evins->nxt = ev1->nxt;
+ ev1->nxt = evins;
}
- ev1->nxt->time = delta;
- ev1->nxt->cfunc = cfunc;
- ev1->nxt->arg = arg;
- ebase.evtime = ebase.eq.nxt->time;
+ ev1->nxt->time = delta;
+ ev1->nxt->cfunc = cfunc;
+ ev1->nxt->arg = arg;
+ ebase.evtime = ebase.eq.nxt->time;
}
/* remove event from event queue */
void
-remove_event(cfunc, arg)
- void (*cfunc) ();
- int32 arg;
+remove_event (cfunc, arg)
+ void (*cfunc) ();
+ int32 arg;
{
- struct evcell *ev1, *evdel;
-
- ev1 = &ebase.eq;
- while (ev1->nxt != NULL) {
- if ((ev1->nxt->cfunc == cfunc) && ((arg == ev1->nxt->arg) || (arg < 0))){
- evdel = ev1->nxt;
- ev1->nxt = ev1->nxt->nxt;
- evdel->nxt = ebase.freeq;
- ebase.freeq = evdel;
+ struct evcell *ev1, *evdel;
+
+ ev1 = &ebase.eq;
+ while (ev1->nxt != NULL)
+ {
+ if ((ev1->nxt->cfunc == cfunc) && ((arg == ev1->nxt->arg) || (arg < 0)))
+ {
+ evdel = ev1->nxt;
+ ev1->nxt = ev1->nxt->nxt;
+ evdel->nxt = ebase.freeq;
+ ebase.freeq = evdel;
}
- ev1 = ev1->nxt;
+ ev1 = ev1->nxt;
}
- ebase.evtime = ebase.eq.nxt->time;
+ ebase.evtime = ebase.eq.nxt->time;
}
static void
last_event (int32 arg)
{
- printf("Warning: end of time ... exiting!\n");
- exit(0);
+ printf ("Warning: end of time ... exiting!\n");
+ exit (0);
}
void
-init_event()
+init_event ()
{
- int32 i;
+ int32 i;
- ebase.eq.nxt = NULL;
- ebase.freeq = evbuf;
- for (i = 0; i < EVENT_MAX; i++) {
- evbuf[i].nxt = &evbuf[i + 1];
+ ebase.eq.nxt = NULL;
+ ebase.freeq = evbuf;
+ for (i = 0; i < EVENT_MAX; i++)
+ {
+ evbuf[i].nxt = &evbuf[i + 1];
}
- evbuf[EVENT_MAX - 1].nxt = NULL;
- event(last_event, 0, UINT64_MAX);
+ evbuf[EVENT_MAX - 1].nxt = NULL;
+ event (last_event, 0, UINT64_MAX);
}
/* Advance simulator time */
void
-advance_time(endtime)
- uint64 endtime;
+advance_time (endtime)
+ uint64 endtime;
{
- struct evcell *evrem;
- void (*cfunc) ();
- uint32 arg;
-
- while (ebase.evtime <= endtime) {
- ebase.simtime = ebase.eq.nxt->time;
- cfunc = ebase.eq.nxt->cfunc;
- arg = ebase.eq.nxt->arg;
- evrem = ebase.eq.nxt;
- ebase.eq.nxt = ebase.eq.nxt->nxt;
- ebase.evtime = ebase.eq.nxt->time;
- evrem->nxt = ebase.freeq;
- ebase.freeq = evrem;
- cfunc(arg);
+ struct evcell *evrem;
+ void (*cfunc) ();
+ uint32 arg;
+
+ while (ebase.evtime <= endtime)
+ {
+ ebase.simtime = ebase.eq.nxt->time;
+ cfunc = ebase.eq.nxt->cfunc;
+ arg = ebase.eq.nxt->arg;
+ evrem = ebase.eq.nxt;
+ ebase.eq.nxt = ebase.eq.nxt->nxt;
+ ebase.evtime = ebase.eq.nxt->time;
+ evrem->nxt = ebase.freeq;
+ ebase.freeq = evrem;
+ cfunc (arg);
}
- ebase.simtime = endtime;
+ ebase.simtime = endtime;
}
uint32
-now()
+now ()
{
- return (uint32) ebase.simtime;
+ return (uint32) ebase.simtime;
}
void
-pwd_enter(struct pstate *sregs)
+pwd_enter (struct pstate *sregs)
{
- sregs->pwd_mode = 1;
- sregs->pwdstart = sregs->simtime;
- sregs->hold += delta;
+ sregs->pwd_mode = 1;
+ sregs->pwdstart = sregs->simtime;
+ sregs->hold += delta;
}
int
-check_bpt(sregs)
- struct pstate *sregs;
+check_bpt (sregs)
+ struct pstate *sregs;
{
- int32 i;
+ int32 i;
- if (sregs->bphit) {
- sregs->bphit = 0;
- return 0;
+ if (sregs->bphit)
+ {
+ sregs->bphit = 0;
+ return 0;
}
- for (i = 0; i < (int32) ebase.bptnum; i++) {
- if (sregs->pc == ebase.bpts[i])
- return BPT_HIT;
+ for (i = 0; i < (int32) ebase.bptnum; i++)
+ {
+ if (sregs->pc == ebase.bpts[i])
+ return BPT_HIT;
}
- return 0;
+ return 0;
}
int
-check_wpr( struct pstate *sregs, int32 address, unsigned char mask)
+check_wpr (struct pstate *sregs, int32 address, unsigned char mask)
{
- int32 i, msk;
-
- for (i = 0; i < ebase.wprnum; i++) {
- msk = ~(mask | ebase.wprm[i]);
- if (((address ^ ebase.wprs[i]) & msk) == 0) {
- ebase.wpaddress = address;
- if (ebase.wphit) return (0);
- return (WPT_HIT);
+ int32 i, msk;
+
+ for (i = 0; i < ebase.wprnum; i++)
+ {
+ msk = ~(mask | ebase.wprm[i]);
+ if (((address ^ ebase.wprs[i]) & msk) == 0)
+ {
+ ebase.wpaddress = address;
+ if (ebase.wphit)
+ return (0);
+ return (WPT_HIT);
}
}
- return (0);
+ return (0);
}
int
-check_wpw( struct pstate *sregs, int32 address, unsigned char mask)
+check_wpw (struct pstate *sregs, int32 address, unsigned char mask)
{
- int32 i, msk;
-
- for (i = 0; i < ebase.wpwnum; i++) {
- msk = ~(mask | ebase.wpwm[i]);
- if (((address ^ ebase.wpws[i]) & msk) == 0) {
- ebase.wpaddress = ebase.wpws[i];
- if (ebase.wphit) return (0);
- return (WPT_HIT);
+ int32 i, msk;
+
+ for (i = 0; i < ebase.wpwnum; i++)
+ {
+ msk = ~(mask | ebase.wpwm[i]);
+ if (((address ^ ebase.wpws[i]) & msk) == 0)
+ {
+ ebase.wpaddress = ebase.wpws[i];
+ if (ebase.wphit)
+ return (0);
+ return (WPT_HIT);
}
}
- return (0);
+ return (0);
}
void
-reset_all()
+reset_all ()
{
- init_event(); /* Clear event queue */
- init_regs(sregs);
- ms->reset ();
+ init_event (); /* Clear event queue */
+ init_regs (sregs);
+ ms->reset ();
}
void
-sys_reset()
+sys_reset ()
{
- reset_all();
- sregs[0].trap = 256; /* Force fake reset trap */
+ reset_all ();
+ sregs[0].trap = 256; /* Force fake reset trap */
}
void
-sys_halt()
+sys_halt ()
{
- sregs[0].trap = 257; /* Force fake halt trap */
+ sregs[0].trap = 257; /* Force fake halt trap */
}
/* simulate one core instruction-wise */
static int
-run_sim_un(sregs, icount, dis)
- struct pstate *sregs;
- uint64 icount;
- int dis;
+run_sim_un (sregs, icount, dis)
+ struct pstate *sregs;
+ uint64 icount;
+ int dis;
{
- int irq, mexc, deb;
- uint32 *inst;
-
- if (sregs->err_mode) icount = 0;
- deb = dis || ebase.histlen || ebase.bptnum;
- mexc = irq = 0;
- while (icount > 0) {
- if (sregs->pwd_mode) {
- sregs->simtime = ebase.evtime; /* skip forward to next event */
- if (ext_irl[sregs->cpu]) irq = arch->check_interrupts(sregs);
- } else {
- sregs->icnt = 1;
- sregs->fhold = 0;
- if (ext_irl[sregs->cpu]) irq = arch->check_interrupts(sregs);
- if (!irq) {
+ int irq, mexc, deb;
+ uint32 *inst;
+
+ if (sregs->err_mode)
+ icount = 0;
+ deb = dis || ebase.histlen || ebase.bptnum;
+ mexc = irq = 0;
+ while (icount > 0)
+ {
+ if (sregs->pwd_mode)
+ {
+ sregs->simtime = ebase.evtime; /* skip forward to next event */
+ if (ext_irl[sregs->cpu])
+ irq = arch->check_interrupts (sregs);
+ }
+ else
+ {
+ sregs->icnt = 1;
+ sregs->fhold = 0;
+ if (ext_irl[sregs->cpu])
+ irq = arch->check_interrupts (sregs);
+ if (!irq)
+ {
#ifdef ROM_ENABLED
- mexc = ms->memory_iread (sregs->pc, &sregs->inst, &sregs->hold);
+ mexc = ms->memory_iread (sregs->pc, &sregs->inst, &sregs->hold);
#else
- inst = (uint32 *) &ramb[sregs->pc & RAM_MASK];
- sregs->inst = *inst;
- sregs->hold = 0;
+ inst = (uint32 *) & ramb[sregs->pc & RAM_MASK];
+ sregs->inst = *inst;
+ sregs->hold = 0;
#endif
- if (mexc) {
- sregs->trap = I_ACC_EXC;
- } else {
- if (deb) {
- if ((ebase.bptnum) && (sregs->bphit = check_bpt(sregs)))
- icount = 0;
- else {
- if (ebase.histlen) {
- sregs->histbuf[sregs->histind].addr = sregs->pc;
- sregs->histbuf[sregs->histind].time = ebase.simtime;
- sregs->histind++;
- if (sregs->histind >= ebase.histlen)
+ if (mexc)
+ {
+ sregs->trap = I_ACC_EXC;
+ }
+ else
+ {
+ if (deb)
+ {
+ if ((ebase.bptnum)
+ && (sregs->bphit = check_bpt (sregs)))
+ icount = 0;
+ else
+ {
+ if (ebase.histlen)
+ {
+ sregs->histbuf[sregs->histind].addr = sregs->pc;
+ sregs->histbuf[sregs->histind].time =
+ ebase.simtime;
+ sregs->histind++;
+ if (sregs->histind >= ebase.histlen)
sregs->histind = 0;
- }
- if (dis) {
- printf(" %8" PRIu64 " ", ebase.simtime);
- dis_mem(sregs->pc, 1);
- }
- arch->dispatch_instruction(sregs);
+ }
+ if (dis)
+ {
+ printf (" %8" PRIu64 " ", ebase.simtime);
+ dis_mem (sregs->pc, 1);
+ }
+ arch->dispatch_instruction (sregs);
icount--;
- advance_time(sregs->simtime);
+ advance_time (sregs->simtime);
}
- } else {
- arch->dispatch_instruction(sregs);
- icount--;
+ }
+ else
+ {
+ arch->dispatch_instruction (sregs);
+ icount--;
}
}
- } else
- sregs->trap = irq + 16;
- if (sregs->trap) {
- irq = 0;
- if ((sregs->err_mode = arch->execute_trap(sregs)) == WPT_HIT) {
- sregs->err_mode = 0;
- sregs->trap = 0;
- icount = 0;
- ebase.bpcpu = sregs->cpu;
- if (ebase.histlen) {
- sregs->histind--;
- if (sregs->histind >= ebase.histlen)
- sregs->histind = ebase.histlen - 1;
+ }
+ else
+ sregs->trap = irq + 16;
+ if (sregs->trap)
+ {
+ irq = 0;
+ if ((sregs->err_mode = arch->execute_trap (sregs)) == WPT_HIT)
+ {
+ sregs->err_mode = 0;
+ sregs->trap = 0;
+ icount = 0;
+ ebase.bpcpu = sregs->cpu;
+ if (ebase.histlen)
+ {
+ sregs->histind--;
+ if (sregs->histind >= ebase.histlen)
+ sregs->histind = ebase.histlen - 1;
}
}
- if (sregs->err_mode) {
- ms->error_mode (sregs->pc);
- icount = 0;
- ebase.bpcpu = sregs->cpu;
+ if (sregs->err_mode)
+ {
+ ms->error_mode (sregs->pc);
+ icount = 0;
+ ebase.bpcpu = sregs->cpu;
}
}
#ifdef STAT
- sregs->fholdt += sregs->fhold;
- sregs->holdt += sregs->hold;
- sregs->icntt += sregs->icnt;
+ sregs->fholdt += sregs->fhold;
+ sregs->holdt += sregs->hold;
+ sregs->icntt += sregs->icnt;
#endif
- sregs->simtime += sregs->icnt + sregs->hold + sregs->fhold;
+ sregs->simtime += sregs->icnt + sregs->hold + sregs->fhold;
}
- if (sregs->simtime >= ebase.evtime)
- advance_time(sregs->simtime);
- if (ctrl_c) {
- icount = 0;
+ if (sregs->simtime >= ebase.evtime)
+ advance_time (sregs->simtime);
+ if (ctrl_c)
+ {
+ icount = 0;
}
}
- advance_time(sregs->simtime);
- if (sregs->err_mode)
- return ERROR;
- if (sregs->bphit)
- return (BPT_HIT);
- if (ebase.wphit)
- return (WPT_HIT);
- if (ctrl_c) {
- return CTRL_C;
+ advance_time (sregs->simtime);
+ if (sregs->err_mode)
+ return ERROR;
+ if (sregs->bphit)
+ return (BPT_HIT);
+ if (ebase.wphit)
+ return (WPT_HIT);
+ if (ctrl_c)
+ {
+ return CTRL_C;
}
- return TIME_OUT;
+ return TIME_OUT;
}
/* stop simulation after specified time */
static void
-sim_timeout(int32 arg)
+sim_timeout (int32 arg)
{
- ctrl_c = arg;
+ ctrl_c = arg;
}
/* simulate one core time-wise */
static void
-run_sim_core(sregs, ntime, deb, dis)
- struct pstate *sregs;
- uint64 ntime;
- int deb;
- int dis;
+run_sim_core (sregs, ntime, deb, dis)
+ struct pstate *sregs;
+ uint64 ntime;
+ int deb;
+ int dis;
{
- int mexc, irq;
- mexc = irq = 0;
- if (sregs->pwd_mode == 0)
- while (ntime > sregs->simtime) {
- if (ext_irl[sregs->cpu])
- irq = arch->check_interrupts(sregs);
- else
- irq = 0;
- sregs->icnt = 1;
+ int mexc, irq;
+ mexc = irq = 0;
+ if (sregs->pwd_mode == 0)
+ while (ntime > sregs->simtime)
+ {
+ if (ext_irl[sregs->cpu])
+ irq = arch->check_interrupts (sregs);
+ else
+ irq = 0;
+ sregs->icnt = 1;
#ifdef ROM_ENABLED
- mexc = ms->memory_iread (sregs->pc, &sregs->inst, &sregs->hold);
+ mexc = ms->memory_iread (sregs->pc, &sregs->inst, &sregs->hold);
#else
- sregs->inst = *((uint32 *) &ramb[sregs->pc & RAM_MASK]);
- sregs->hold = 0;
+ sregs->inst = *((uint32 *) & ramb[sregs->pc & RAM_MASK]);
+ sregs->hold = 0;
#endif
#ifdef ENABLE_L1CACHE
- if (sregs->l1itags[(sregs->pc >> L1ILINEBITS) & L1IMASK] != (sregs->pc >> L1ILINEBITS)) {
- sregs->hold = T_L1IMISS;
- sregs->l1itags[(sregs->pc >> L1ILINEBITS) & L1IMASK] = (sregs->pc >> L1ILINEBITS);
- sregs->l1imiss++;
- }
+ if (sregs->l1itags[(sregs->pc >> L1ILINEBITS) & L1IMASK] !=
+ (sregs->pc >> L1ILINEBITS))
+ {
+ sregs->hold = T_L1IMISS;
+ sregs->l1itags[(sregs->pc >> L1ILINEBITS) & L1IMASK] =
+ (sregs->pc >> L1ILINEBITS);
+ sregs->l1imiss++;
+ }
#endif
- sregs->fhold = 0;
- if (!irq) {
- if (mexc) {
- sregs->trap = I_ACC_EXC;
- } else {
- if (deb) {
- if ((ebase.bptnum) && (sregs->bphit = check_bpt(sregs))) {
- ntime = sregs->simtime;
- ctrl_c = 1;
- ebase.bpcpu = sregs->cpu;
- break;
- }
- if (ebase.histlen) {
- sregs->histbuf[sregs->histind].addr = sregs->pc;
- sregs->histbuf[sregs->histind].time = sregs->simtime;
- sregs->histind++;
- if (sregs->histind >= ebase.histlen)
- sregs->histind = 0;
- }
- if (dis) {
- printf("cpu %d %8" PRIu64 " ", sregs->cpu, sregs->simtime);
- dis_mem(sregs->pc, 1);
- }
- arch->dispatch_instruction(sregs);
- } else {
- arch->dispatch_instruction(sregs);
- }
- }
- } else
- sregs->trap = irq + 16;
- if (sregs->trap) {
- irq = 0;
- if ((sregs->err_mode = arch->execute_trap(sregs)) == WPT_HIT) {
- sregs->err_mode = 0;
- sregs->trap = 0;
- ntime = sregs->simtime;
- ctrl_c = 1;
- ebase.bpcpu = sregs->cpu;
- if (ebase.histlen) {
- sregs->histind--;
+ sregs->fhold = 0;
+ if (!irq)
+ {
+ if (mexc)
+ {
+ sregs->trap = I_ACC_EXC;
+ }
+ else
+ {
+ if (deb)
+ {
+ if ((ebase.bptnum) && (sregs->bphit = check_bpt (sregs)))
+ {
+ ntime = sregs->simtime;
+ ctrl_c = 1;
+ ebase.bpcpu = sregs->cpu;
+ break;
+ }
+ if (ebase.histlen)
+ {
+ sregs->histbuf[sregs->histind].addr = sregs->pc;
+ sregs->histbuf[sregs->histind].time = sregs->simtime;
+ sregs->histind++;
if (sregs->histind >= ebase.histlen)
- sregs->histind = ebase.histlen - 1;
- }
- break;
- }
- if (sregs->err_mode) {
- ms->error_mode (sregs->pc);
- sregs->pwd_mode = 1;
- sregs->pwdstart = sregs->simtime;
- sregs->simtime = ntime;
- ctrl_c = 1;
- ebase.bpcpu = sregs->cpu;
- break;
- }
- }
+ sregs->histind = 0;
+ }
+ if (dis)
+ {
+ printf ("cpu %d %8" PRIu64 " ", sregs->cpu,
+ sregs->simtime);
+ dis_mem (sregs->pc, 1);
+ }
+ arch->dispatch_instruction (sregs);
+ }
+ else
+ {
+ arch->dispatch_instruction (sregs);
+ }
+ }
+ }
+ else
+ sregs->trap = irq + 16;
+ if (sregs->trap)
+ {
+ irq = 0;
+ if ((sregs->err_mode = arch->execute_trap (sregs)) == WPT_HIT)
+ {
+ sregs->err_mode = 0;
+ sregs->trap = 0;
+ ntime = sregs->simtime;
+ ctrl_c = 1;
+ ebase.bpcpu = sregs->cpu;
+ if (ebase.histlen)
+ {
+ sregs->histind--;
+ if (sregs->histind >= ebase.histlen)
+ sregs->histind = ebase.histlen - 1;
+ }
+ break;
+ }
+ if (sregs->err_mode)
+ {
+ ms->error_mode (sregs->pc);
+ sregs->pwd_mode = 1;
+ sregs->pwdstart = sregs->simtime;
+ sregs->simtime = ntime;
+ ctrl_c = 1;
+ ebase.bpcpu = sregs->cpu;
+ break;
+ }
+ }
#ifdef STAT
- sregs->fholdt += sregs->fhold;
- sregs->holdt += sregs->hold;
- sregs->icntt += sregs->icnt;
+ sregs->fholdt += sregs->fhold;
+ sregs->holdt += sregs->hold;
+ sregs->icntt += sregs->icnt;
#endif
- sregs->simtime += sregs->icnt + sregs->hold + sregs->fhold;
- }
- else {
- sregs->simtime = ntime;
- if (ext_irl[sregs->cpu]) irq = arch->check_interrupts(sregs);
- }
- sregs->lrq = 0;
+ sregs->simtime += sregs->icnt + sregs->hold + sregs->fhold;
+ }
+ else
+ {
+ sregs->simtime = ntime;
+ if (ext_irl[sregs->cpu])
+ irq = arch->check_interrupts (sregs);
+ }
+ sregs->lrq = 0;
}
/* time slice simulation of cpu cores in MP system */
static int
-run_sim_mp(icount, dis)
- uint64 icount;
- int dis;
+run_sim_mp (icount, dis)
+ uint64 icount;
+ int dis;
{
- uint64 ntime, etime;
- int deb, i, j;
- int err_mode, bphit, wphit, oldcpu;
-
- err_mode = bphit = wphit = 0;
- icount += ebase.simtime;
- for(i=0; i<ncpu; i++) {
- if (sregs[i].err_mode) {
+ uint64 ntime, etime;
+ int deb, i, j;
+ int err_mode, bphit, wphit, oldcpu;
+
+ err_mode = bphit = wphit = 0;
+ icount += ebase.simtime;
+ for (i = 0; i < ncpu; i++)
+ {
+ if (sregs[i].err_mode)
+ {
icount = 0;
err_mode = 1;
- }
+ }
}
- while (icount > ebase.simtime) {
+ while (icount > ebase.simtime)
+ {
ntime = ebase.simtime + delta;
- if (ntime > icount) ntime = icount;
- if (ntime > ebase.evtime) ntime = ebase.evtime;
- for(i=0; i<ncpu; i++) {
- deb = dis || ebase.histlen || ebase.bptnum;
- etime = ntime;
- run_sim_core(&sregs[i], ntime, deb, dis);
- err_mode |= sregs[i].err_mode;
- bphit |= sregs[i].bphit;
- wphit |= ebase.wphit;
- if (sregs[i].simtime < etime)
+ if (ntime > icount)
+ ntime = icount;
+ if (ntime > ebase.evtime)
+ ntime = ebase.evtime;
+ for (i = 0; i < ncpu; i++)
+ {
+ deb = dis || ebase.histlen || ebase.bptnum;
+ etime = ntime;
+ run_sim_core (&sregs[i], ntime, deb, dis);
+ err_mode |= sregs[i].err_mode;
+ bphit |= sregs[i].bphit;
+ wphit |= ebase.wphit;
+ if (sregs[i].simtime < etime)
etime = sregs[i].simtime;
- }
- advance_time(etime);
- if (ctrl_c) {
+ }
+ advance_time (etime);
+ if (ctrl_c)
+ {
icount = 0;
- }
+ }
}
- oldcpu = cpu;
- cpu = ebase.bpcpu;
- if (err_mode == NULL_HIT)
- return NULL_HIT;
- if (err_mode)
- return ERROR;
- if (bphit)
- return (BPT_HIT);
- if (wphit)
- return (WPT_HIT);
- if (ctrl_c) {
- return CTRL_C;
+ oldcpu = cpu;
+ cpu = ebase.bpcpu;
+ if (err_mode == NULL_HIT)
+ return NULL_HIT;
+ if (err_mode)
+ return ERROR;
+ if (bphit)
+ return (BPT_HIT);
+ if (wphit)
+ return (WPT_HIT);
+ if (ctrl_c)
+ {
+ return CTRL_C;
}
- cpu = oldcpu;
- return TIME_OUT;
+ cpu = oldcpu;
+ return TIME_OUT;
}
int
-run_sim(icount, dis)
- uint64 icount;
- int dis;
+run_sim (icount, dis)
+ uint64 icount;
+ int dis;
{
- int res;
-
- ctrl_c = 0;
- sim_run = 1;
- ebase.starttime = get_time();
- ms->init_stdio ();
- if (ebase.tlimit > ebase.simtime)
- event(sim_timeout, 2, ebase.tlimit - ebase.simtime);
- if (ebase.coven)
- cov_start(sregs[0].pc);
- if ((ncpu == 1) || (icount == 1))
- res = run_sim_un(&sregs[cpu], icount, dis);
- else
- res = run_sim_mp(icount, dis);
- remove_event(sim_timeout, -1);
- ebase.tottime += get_time() - ebase.starttime;
- ms->restore_stdio ();
- if ((res == CTRL_C) && (ctrl_c == 2))
- printf("\nTime-out limit reached\n");
- sim_run = 0;
- return res;
+ int res;
+
+ ctrl_c = 0;
+ sim_run = 1;
+ ebase.starttime = get_time ();
+ ms->init_stdio ();
+ if (ebase.tlimit > ebase.simtime)
+ event (sim_timeout, 2, ebase.tlimit - ebase.simtime);
+ if (ebase.coven)
+ cov_start (sregs[0].pc);
+ if ((ncpu == 1) || (icount == 1))
+ res = run_sim_un (&sregs[cpu], icount, dis);
+ else
+ res = run_sim_mp (icount, dis);
+ remove_event (sim_timeout, -1);
+ ebase.tottime += get_time () - ebase.starttime;
+ ms->restore_stdio ();
+ if ((res == CTRL_C) && (ctrl_c == 2))
+ printf ("\nTime-out limit reached\n");
+ sim_run = 0;
+ return res;
}
-double get_time (void)
+double
+get_time (void)
{
- double usec;
+ double usec;
- struct timeval tm;
+ struct timeval tm;
- gettimeofday (&tm, NULL);
- usec = ((double) tm.tv_sec) * 1E6 + ((double) tm.tv_usec);
- return usec / 1E6;
+ gettimeofday (&tm, NULL);
+ usec = ((double) tm.tv_sec) * 1E6 + ((double) tm.tv_usec);
+ return usec / 1E6;
}
/* Local version of getline() since not all systems supports it */
@@ -1255,7 +1512,7 @@ double get_time (void)
static const int line_size = 128;
static ssize_t
-mygetdelim (char **lineptr, size_t *n, int delim, FILE *stream)
+mygetdelim (char **lineptr, size_t * n, int delim, FILE * stream)
{
int indx = 0;
int c;
@@ -1269,7 +1526,7 @@ mygetdelim (char **lineptr, size_t *n, int delim, FILE *stream)
{
*lineptr = malloc (line_size);
if (*lineptr == NULL)
- return -1;
+ return -1;
*n = line_size;
}
@@ -1280,31 +1537,31 @@ mygetdelim (char **lineptr, size_t *n, int delim, FILE *stream)
{
/* Check if more memory is needed. */
if (indx >= *n)
- {
- *lineptr = realloc (*lineptr, *n + line_size);
- if (*lineptr == NULL)
- {
- return -1;
- }
- /* Clear the rest of the line. */
- memset(*lineptr + *n, '\0', line_size);
- *n += line_size;
- }
+ {
+ *lineptr = realloc (*lineptr, *n + line_size);
+ if (*lineptr == NULL)
+ {
+ return -1;
+ }
+ /* Clear the rest of the line. */
+ memset (*lineptr + *n, '\0', line_size);
+ *n += line_size;
+ }
/* Push the result in the line. */
(*lineptr)[indx++] = c;
/* Bail out. */
if (c == delim)
- {
- break;
- }
+ {
+ break;
+ }
}
return (c == EOF) ? -1 : indx;
}
static ssize_t
-mygetline (char **lineptr, size_t *n, FILE *stream)
+mygetline (char **lineptr, size_t * n, FILE * stream)
{
return mygetdelim (lineptr, n, '\n', stream);
}
@@ -1317,67 +1574,78 @@ mygetline (char **lineptr, size_t *n, FILE *stream)
#define COV_BT 8
#define COV_BNT 16
-unsigned char covram[0x01000000/4];
+unsigned char covram[0x01000000 / 4];
-void cov_start(int address)
+void
+cov_start (int address)
{
covram[(address >> 2) & RAM_MASK] |= (COV_START | COV_EXEC);
}
-void cov_exec(int address)
+
+void
+cov_exec (int address)
{
covram[(address >> 2) & RAM_MASK] |= COV_EXEC;
}
-void cov_bt(int address1, int address2)
+void
+cov_bt (int address1, int address2)
{
covram[(address1 >> 2) & RAM_MASK] |= (COV_BT | COV_EXEC);
covram[(address2 >> 2) & RAM_MASK] |= (COV_START | COV_EXEC);
}
-void cov_bnt(int address)
+void
+cov_bnt (int address)
{
covram[(address >> 2) & RAM_MASK] |= (COV_BNT | COV_EXEC);
}
-void cov_jmp(int address1, int address2)
+void
+cov_jmp (int address1, int address2)
{
covram[(address1 >> 2) & RAM_MASK] |= (COV_JMP | COV_EXEC);
covram[(address2 >> 2) & RAM_MASK] |= (COV_START | COV_EXEC);
}
-void cov_save(char *name)
+void
+cov_save (char *name)
{
FILE *fp;
char filename[1024];
int i, j, k, state;
- strcpy(filename, name);
- strcat(filename, ".cov");
+ strcpy (filename, name);
+ strcat (filename, ".cov");
fp = fopen (filename, "w");
state = 0;
- for (i=0; i<RAM_SIZE/4; i+=32) {
- k =0;
- for (j=0; j<32; j++) {
- k |= covram[i+j];
- }
- if (k || state) {
- fprintf(fp, "%08x : ", ebase.ramstart + i*4);
- for (j=0; j<32; j++) {
- if (state)
- covram[i+j] |= COV_EXEC;
- if (covram[i+j] & COV_START)
- state = 1;
- if (covram[i+j] & (COV_JMP | COV_BT | COV_BNT))
- state = 0;
- if ((ebase.ramstart + (i+j)*4) == sregs[0].pc)
- state = 0;
- covram[i+j] &= ~0x6;
- fprintf(fp, "%x ", covram[i+j]);
- }
- fprintf(fp, "\n");
+ for (i = 0; i < RAM_SIZE / 4; i += 32)
+ {
+ k = 0;
+ for (j = 0; j < 32; j++)
+ {
+ k |= covram[i + j];
+ }
+ if (k || state)
+ {
+ fprintf (fp, "%08x : ", ebase.ramstart + i * 4);
+ for (j = 0; j < 32; j++)
+ {
+ if (state)
+ covram[i + j] |= COV_EXEC;
+ if (covram[i + j] & COV_START)
+ state = 1;
+ if (covram[i + j] & (COV_JMP | COV_BT | COV_BNT))
+ state = 0;
+ if ((ebase.ramstart + (i + j) * 4) == sregs[0].pc)
+ state = 0;
+ covram[i + j] &= ~0x6;
+ fprintf (fp, "%x ", covram[i + j]);
+ }
+ fprintf (fp, "\n");
+ }
}
- }
- printf("\nsaved code coverage to %s\n", filename);
- fclose(fp);
+ printf ("\nsaved code coverage to %s\n", filename);
+ fclose (fp);
}
diff --git a/grlib.c b/grlib.c
index 52f78ff..9932360 100644
--- a/grlib.c
+++ b/grlib.c
@@ -104,4 +104,3 @@ grlib_init ()
GRLIB_PP_APBADDR (0x80000200, 0xFFF));
}
-
diff --git a/grlib.h b/grlib.h
index d1ab397..d261b3b 100644
--- a/grlib.h
+++ b/grlib.h
@@ -58,4 +58,4 @@ extern int grlib_ahbspp_add (uint32 id, uint32 addr1, uint32 addr2,
extern uint32 grlib_ahbpnp_read (uint32 addr);
extern uint32 grlib_apbpnp_read (uint32 addr);
extern void grlib_init ();
-extern uint32 rvtimer_read(int address, int cpu);
+extern uint32 rvtimer_read (int address, int cpu);
diff --git a/help.c b/help.c
index d6bf9f3..2593d84 100644
--- a/help.c
+++ b/help.c
@@ -21,36 +21,42 @@
#include "sis.h"
void
-sis_usage()
+sis_usage ()
{
- printf("usage: sis [-uart1 uart_device1] [-uart2 uart_device2]\n");
- printf("[-m <n>] [-dumbio] [-v] \n");
- printf("[-nfp] [-freq frequency] [-c batch_file] [files]\n");
+ printf ("usage: sis [-uart1 uart_device1] [-uart2 uart_device2]\n");
+ printf ("[-m <n>] [-dumbio] [-v] \n");
+ printf ("[-nfp] [-freq frequency] [-c batch_file] [files]\n");
}
void
-gen_help()
+gen_help ()
{
- printf("\n batch <file> execute a batch file of SIS commands\n");
- printf(" +bp <addr> add a breakpoint at <addr>\n");
- printf(" -bp <num> delete breakpoint <num>\n");
- printf(" bp print all breakpoints\n");
- printf(" cont [icnt] continue execution for [icnt] instructions\n");
- printf(" deb <level> set debug level\n");
- printf(" dis [addr] [count] disassemble [count] instructions at address [addr]\n");
- printf(" echo <string> print <string> to the simulator window\n");
- printf(" float print the FPU registers\n");
- printf(" go <addr> [icnt] start execution at <addr> for [icnt] instructions\n");
- printf(" hist [trace_length] enable/show trace history\n");
- printf(" load <file_name> load a file into simulator memory\n");
- printf(" mem [addr] [count] display memory at [addr] for [count] bytes\n");
- printf(" quit exit the simulator\n");
- printf(" perf [reset] show/reset performance statistics\n");
- printf(" reg [w<0-7>] show integer registers (or windows, eg 're w2')\n");
- printf(" run [inst_count] reset and start execution for [icnt] instruction\n");
- printf(" step single step\n");
- printf(" tra [inst_count] trace [inst_count] instructions\n");
- printf("\n type Ctrl-C to interrupt execution\n\n");
+ printf ("\n batch <file> execute a batch file of SIS commands\n");
+ printf (" +bp <addr> add a breakpoint at <addr>\n");
+ printf (" -bp <num> delete breakpoint <num>\n");
+ printf (" bp print all breakpoints\n");
+ printf
+ (" cont [icnt] continue execution for [icnt] instructions\n");
+ printf (" deb <level> set debug level\n");
+ printf
+ (" dis [addr] [count] disassemble [count] instructions at address [addr]\n");
+ printf (" echo <string> print <string> to the simulator window\n");
+ printf (" float print the FPU registers\n");
+ printf
+ (" go <addr> [icnt] start execution at <addr> for [icnt] instructions\n");
+ printf (" hist [trace_length] enable/show trace history\n");
+ printf (" load <file_name> load a file into simulator memory\n");
+ printf
+ (" mem [addr] [count] display memory at [addr] for [count] bytes\n");
+ printf (" quit exit the simulator\n");
+ printf (" perf [reset] show/reset performance statistics\n");
+ printf
+ (" reg [w<0-7>] show integer registers (or windows, eg 're w2')\n");
+ printf
+ (" run [inst_count] reset and start execution for [icnt] instruction\n");
+ printf (" step single step\n");
+ printf (" tra [inst_count] trace [inst_count] instructions\n");
+ printf ("\n type Ctrl-C to interrupt execution\n\n");
}
diff --git a/interf.c b/interf.c
index d1e368b..8062021 100644
--- a/interf.c
+++ b/interf.c
@@ -36,92 +36,95 @@
#define CEBREAK 0x90002
static int
-run_sim_gdb(icount, dis)
- uint64 icount;
- int dis;
+run_sim_gdb (icount, dis)
+ uint64 icount;
+ int dis;
{
- int res;
-
- if ((sregs[cpu].pc != 0) && (ebase.simtime == 0))
- ms->boot_init ();
- res = run_sim(icount, dis);
- ms->sim_halt();
- clearerr(stdin);
- return res;
+ int res;
+
+ if ((sregs[cpu].pc != 0) && (ebase.simtime == 0))
+ ms->boot_init ();
+ res = run_sim (icount, dis);
+ ms->sim_halt ();
+ clearerr (stdin);
+ return res;
}
void
-sim_close(sd, quitting)
+sim_close (sd, quitting)
SIM_DESC sd;
int quitting;
{
- ms->exit_sim ();
+ ms->exit_sim ();
#if defined(F_GETFL) && defined(F_SETFL)
- fcntl(0, F_SETFL, termsave);
+ fcntl (0, F_SETFL, termsave);
#endif
};
void
-sim_create_inferior()
+sim_create_inferior ()
{
- int i;
-
- if (sis_verbose)
- printf("interf: sim_create_inferior()");
- ebase.simtime = 0;
- ebase.simstart = 0;
- reset_all();
- reset_stat(sregs);
- for (i=0; i<ncpu; i++){
- sregs[i].pc = last_load_addr & ~1;
- sregs[i].npc = sregs[i].pc + 4;
+ int i;
+
+ if (sis_verbose)
+ printf ("interf: sim_create_inferior()");
+ ebase.simtime = 0;
+ ebase.simstart = 0;
+ reset_all ();
+ reset_stat (sregs);
+ for (i = 0; i < ncpu; i++)
+ {
+ sregs[i].pc = last_load_addr & ~1;
+ sregs[i].npc = sregs[i].pc + 4;
}
}
int
sim_write (uint32 mem, const char *buf, int length)
{
- int i, len;
+ int i, len;
- for (i = 0; i < length; i++) {
- ms->sis_memory_write ((mem + i) ^ arch->endian, &buf[i], 1);
+ for (i = 0; i < length; i++)
+ {
+ ms->sis_memory_write ((mem + i) ^ arch->endian, &buf[i], 1);
}
- return length;
+ return length;
}
int
sim_read (uint32 mem, char *buf, int length)
{
- int i, len;
+ int i, len;
- for (i = 0; i < length; i++) {
- ms->sis_memory_read ((mem + i) ^ arch->endian, &buf[i], 1);
+ for (i = 0; i < length; i++)
+ {
+ ms->sis_memory_read ((mem + i) ^ arch->endian, &buf[i], 1);
}
- return length;
+ return length;
}
void
-sim_info(sd, verbose)
+sim_info (sd, verbose)
SIM_DESC sd;
int verbose;
{
- show_stat(&sregs[cpu]);
+ show_stat (&sregs[cpu]);
}
-int simstat = OK;
+int simstat = OK;
void
-sim_resume(int step)
+sim_resume (int step)
{
- if (step)
- simstat = run_sim_gdb(1, 0);
- else
- simstat = run_sim_gdb(UINT64_MAX/2, 0);
+ if (step)
+ simstat = run_sim_gdb (1, 0);
+ else
+ simstat = run_sim_gdb (UINT64_MAX / 2, 0);
- if (sis_gdb_break && (cputype != CPU_RISCV))
- flush_windows (&sregs[cpu]);
+ if (sis_gdb_break && (cputype != CPU_RISCV))
+ flush_windows (&sregs[cpu]);
}
int
@@ -132,91 +135,109 @@ sim_stop (SIM_DESC sd)
}
static int
-sis_insert_watchpoint_read(int addr, unsigned char mask)
+sis_insert_watchpoint_read (int addr, unsigned char mask)
{
- if (ebase.wprnum < WPR_MAX) {
- ebase.wprs[ebase.wprnum] = addr;
- ebase.wprm[ebase.wprnum] = mask;
- ebase.wprnum++;
- if (sis_verbose)
- printf ("inserted read watchpoint at %x\n", addr);
- return SIM_RC_OK;
- } else
- return SIM_RC_FAIL;
+ if (ebase.wprnum < WPR_MAX)
+ {
+ ebase.wprs[ebase.wprnum] = addr;
+ ebase.wprm[ebase.wprnum] = mask;
+ ebase.wprnum++;
+ if (sis_verbose)
+ printf ("inserted read watchpoint at %x\n", addr);
+ return SIM_RC_OK;
+ }
+ else
+ return SIM_RC_FAIL;
}
static int
-sis_remove_watchpoint_read(int addr)
+sis_remove_watchpoint_read (int addr)
{
- int i = 0;
-
- while ((i < ebase.wprnum) && (ebase.wprs[i] != addr))
- i++;
- if (addr == ebase.wprs[i]) {
- for (; i < ebase.wprnum - 1; i++)
- ebase.wprs[i] = ebase.wprs[i + 1];
- ebase.wprnum -= 1;
- if (sis_verbose)
- printf ("removed read watchpoint at %x\n", addr);
- return 0;
+ int i = 0;
+
+ while ((i < ebase.wprnum) && (ebase.wprs[i] != addr))
+ i++;
+ if (addr == ebase.wprs[i])
+ {
+ for (; i < ebase.wprnum - 1; i++)
+ ebase.wprs[i] = ebase.wprs[i + 1];
+ ebase.wprnum -= 1;
+ if (sis_verbose)
+ printf ("removed read watchpoint at %x\n", addr);
+ return 0;
}
- return 1;
+ return 1;
}
static int
-sis_insert_watchpoint_write(int32 addr, unsigned char mask)
+sis_insert_watchpoint_write (int32 addr, unsigned char mask)
{
- if (ebase.wpwnum < WPR_MAX) {
- ebase.wpws[ebase.wpwnum] = addr;
- ebase.wpwm[ebase.wpwnum] = mask;
- ebase.wpwnum++;
- if (sis_verbose)
- printf ("sim_insert_watchpoint_write: 0x%08x : %x\n", addr, mask);
- return SIM_RC_OK;
- } else
- return SIM_RC_FAIL;
+ if (ebase.wpwnum < WPR_MAX)
+ {
+ ebase.wpws[ebase.wpwnum] = addr;
+ ebase.wpwm[ebase.wpwnum] = mask;
+ ebase.wpwnum++;
+ if (sis_verbose)
+ printf ("sim_insert_watchpoint_write: 0x%08x : %x\n", addr, mask);
+ return SIM_RC_OK;
+ }
+ else
+ return SIM_RC_FAIL;
}
static int
-sis_remove_watchpoint_write(int addr)
+sis_remove_watchpoint_write (int addr)
{
- int i = 0;
-
- while ((i < ebase.wpwnum) && (ebase.wpws[i] != addr))
- i++;
- if (addr == ebase.wpws[i]) {
- for (; i < ebase.wpwnum - 1; i++)
- ebase.wpws[i] = ebase.wpws[i + 1];
- ebase.wpwnum -= 1;
- if (sis_verbose)
- printf ("removed write watchpoint at %x\n", addr);
- return SIM_RC_OK;
+ int i = 0;
+
+ while ((i < ebase.wpwnum) && (ebase.wpws[i] != addr))
+ i++;
+ if (addr == ebase.wpws[i])
+ {
+ for (; i < ebase.wpwnum - 1; i++)
+ ebase.wpws[i] = ebase.wpws[i + 1];
+ ebase.wpwnum -= 1;
+ if (sis_verbose)
+ printf ("removed write watchpoint at %x\n", addr);
+ return SIM_RC_OK;
}
- return SIM_RC_FAIL;
+ return SIM_RC_FAIL;
}
-int sim_can_use_hw_breakpoint (SIM_DESC sd, int type, int cnt, int othertype)
+int
+sim_can_use_hw_breakpoint (SIM_DESC sd, int type, int cnt, int othertype)
{
- if (type == 2) /* bp_hardware_breakpoint not supported */
- return 0;
- else
- return 1;
+ if (type == 2) /* bp_hardware_breakpoint not supported */
+ return 0;
+ else
+ return 1;
}
-int sim_set_watchpoint (SIM_DESC sd, SIM_ADDR mem, int length, int type)
+int
+sim_set_watchpoint (SIM_DESC sd, SIM_ADDR mem, int length, int type)
{
int res;
unsigned char mask;
- switch (length) {
- case 1: mask = 0; break;
- case 2: mask = 1; break;
- case 4: mask = 3; break;
- default: mask = 7; break;
- }
+ switch (length)
+ {
+ case 1:
+ mask = 0;
+ break;
+ case 2:
+ mask = 1;
+ break;
+ case 4:
+ mask = 3;
+ break;
+ default:
+ mask = 7;
+ break;
+ }
- switch (type) {
+ switch (type)
+ {
case 0:
res = sis_insert_watchpoint_write (mem, mask);
break;
@@ -225,21 +246,23 @@ int sim_set_watchpoint (SIM_DESC sd, SIM_ADDR mem, int length, int type)
break;
case 2:
if ((res = sis_insert_watchpoint_write (mem, mask)) == SIM_RC_OK)
- res = sis_insert_watchpoint_read (mem, mask);
- if (res == SIM_RC_FAIL)
- sis_remove_watchpoint_read (mem);
+ res = sis_insert_watchpoint_read (mem, mask);
+ if (res == SIM_RC_FAIL)
+ sis_remove_watchpoint_read (mem);
break;
default:
res = -1;
- }
+ }
return (res);
}
-int sim_clear_watchpoint (SIM_DESC sd, SIM_ADDR mem, int length, int type)
+int
+sim_clear_watchpoint (SIM_DESC sd, SIM_ADDR mem, int length, int type)
{
int res;
- switch (type) {
+ switch (type)
+ {
case 0:
res = sis_remove_watchpoint_write (mem);
break;
@@ -248,74 +271,85 @@ int sim_clear_watchpoint (SIM_DESC sd, SIM_ADDR mem, int length, int type)
break;
case 2:
if ((res = sis_remove_watchpoint_write (mem)) == SIM_RC_OK)
- res = sis_remove_watchpoint_read (mem);
+ res = sis_remove_watchpoint_read (mem);
else
- sis_remove_watchpoint_read (mem);
+ sis_remove_watchpoint_read (mem);
break;
default:
res = -1;
- }
+ }
return (res);
}
-int sim_stopped_by_watchpoint (SIM_DESC sd)
+int
+sim_stopped_by_watchpoint (SIM_DESC sd)
{
- if (sis_verbose)
- printf ("sim_stopped_by_watchpoint %x\n", ebase.wphit);
- return((ebase.wphit != 0));
+ if (sis_verbose)
+ printf ("sim_stopped_by_watchpoint %x\n", ebase.wphit);
+ return ((ebase.wphit != 0));
}
-int sim_watchpoint_address (SIM_DESC sd)
+int
+sim_watchpoint_address (SIM_DESC sd)
{
- if (sis_verbose)
- printf("sim__watchpoint_address %x\n", ebase.wpaddress);
- return(ebase.wpaddress);
+ if (sis_verbose)
+ printf ("sim__watchpoint_address %x\n", ebase.wpaddress);
+ return (ebase.wpaddress);
}
int
-sim_insert_swbreakpoint(uint32 addr, int len)
+sim_insert_swbreakpoint (uint32 addr, int len)
{
uint32 breakinsn;
- if (ebase.bptnum < BPT_MAX) {
- ebase.bpts[ebase.bptnum] = addr;
- ms->sis_memory_read (addr, (char *) &ebase.bpsave[ebase.bptnum] , len);
- if (len == 4) {
- breakinsn = EBREAK;
- ms->sis_memory_write (addr, (char *) &breakinsn , 4);
- } else {
- breakinsn = CEBREAK;
- ms->sis_memory_write (addr, (char *) &breakinsn , 2);
+ if (ebase.bptnum < BPT_MAX)
+ {
+ ebase.bpts[ebase.bptnum] = addr;
+ ms->sis_memory_read (addr, (char *) &ebase.bpsave[ebase.bptnum], len);
+ if (len == 4)
+ {
+ breakinsn = EBREAK;
+ ms->sis_memory_write (addr, (char *) &breakinsn, 4);
+ }
+ else
+ {
+ breakinsn = CEBREAK;
+ ms->sis_memory_write (addr, (char *) &breakinsn, 2);
+ }
+ if (sis_verbose)
+ printf ("sim_insert_swbreakpoint: added breakpoint %d at 0x%08x\n",
+ ebase.bptnum + 1, addr);
+ ebase.bptnum += 1;
+ return 1;
}
- if (sis_verbose)
- printf("sim_insert_swbreakpoint: added breakpoint %d at 0x%08x\n", ebase.bptnum + 1, addr);
- ebase.bptnum += 1;
- return 1;
- }
- return 0; /* Too many breakpoints */
+ return 0; /* Too many breakpoints */
}
int
-sim_remove_swbreakpoint(uint32 addr, int len)
+sim_remove_swbreakpoint (uint32 addr, int len)
{
int i;
/* find breakpoint to remove */
- for (i=0; i<ebase.bptnum;i++) {
- if (ebase.bpts[i] == addr)
- break;
- }
- if (ebase.bpts[i] == addr) {
- /* write back saved opcode */
- ms->sis_memory_write (addr, (char *) &ebase.bpsave[i] , len);
- if (sis_verbose)
- printf("sim_remove_swbreakpoint: remove breakpoint %d at 0x%08x\n", i, addr);
- /* shift down remaining breakpoints */
- for (; i<ebase.bptnum;i++) {
- ebase.bpts[i] = ebase.bpts[i + 1];
+ for (i = 0; i < ebase.bptnum; i++)
+ {
+ if (ebase.bpts[i] == addr)
+ break;
}
- ebase.bptnum -= 1;
- return 1;
- }
- return 0; /* breakpoint not found */
+ if (ebase.bpts[i] == addr)
+ {
+ /* write back saved opcode */
+ ms->sis_memory_write (addr, (char *) &ebase.bpsave[i], len);
+ if (sis_verbose)
+ printf ("sim_remove_swbreakpoint: remove breakpoint %d at 0x%08x\n",
+ i, addr);
+ /* shift down remaining breakpoints */
+ for (; i < ebase.bptnum; i++)
+ {
+ ebase.bpts[i] = ebase.bpts[i + 1];
+ }
+ ebase.bptnum -= 1;
+ return 1;
+ }
+ return 0; /* breakpoint not found */
}
diff --git a/leon2.c b/leon2.c
index a2f7ebf..6f669a5 100644
--- a/leon2.c
+++ b/leon2.c
@@ -425,7 +425,7 @@ apb_write (uint32 addr, uint32 data)
break;
case POWER_DOWN: /* 0x328 */
- pwd_enter(sregs);
+ pwd_enter (sregs);
break;
case CACHE_CTRL: /* 0x328 */
@@ -620,7 +620,7 @@ grlib_write_uart (uint32 addr, uint32 data)
{
while (wnuma)
{
- wnuma -= fwrite (wbufa, 1, wnuma, f1out);
+ wnuma -= fwrite (wbufa, 1, wnuma, f1out);
}
wbufa[wnuma++] = c;
}
@@ -658,7 +658,7 @@ flush_uart (void)
{
while (wnuma && f1open)
{
- wnuma -= fwrite (wbufa, 1, wnuma, f1out);
+ wnuma -= fwrite (wbufa, 1, wnuma, f1out);
}
}
@@ -667,8 +667,8 @@ uarta_tx (void)
{
while (f1open)
{
- while (fwrite (&uarta_sreg, 1, 1, f1out) != 1)
- continue;
+ while (fwrite (&uarta_sreg, 1, 1, f1out) != 1)
+ continue;
}
if (uart_stat_reg & UARTA_HRE)
{
@@ -791,8 +791,7 @@ timer_ctrl (uint32 val, int i)
2 (one word), or 3 (two words); WS should return the number of wait-states. */
static void
-store_bytes (char *mem, uint32 waddr, uint32 * data, int32 sz,
- int32 * ws)
+store_bytes (char *mem, uint32 waddr, uint32 * data, int32 sz, int32 * ws)
{
switch (sz)
{
diff --git a/leon3.c b/leon3.c
index 4d6ce4a..6b8e2e2 100644
--- a/leon3.c
+++ b/leon3.c
@@ -248,11 +248,12 @@ leon3_reset (void)
int i;
irqmp_ipr = 0;
- for (i=0; i<NCPU; i++) {
- irqmp_imr[i] = 0;
- irqmp_ifr[i] = 0;
- sregs[i].intack = irqmp_intack;
- }
+ for (i = 0; i < NCPU; i++)
+ {
+ irqmp_imr[i] = 0;
+ irqmp_ifr[i] = 0;
+ sregs[i].intack = irqmp_intack;
+ }
wnuma = wnumb = 0;
anum = aind = bnum = bind = 0;
@@ -272,8 +273,8 @@ irqmp_intack (int level, int cpu)
int irq_test;
if ((sis_verbose > 2) && (level != 10))
- printf ("%8" PRIu64 " cpu %d interrupt %d acknowledged\n",
- ebase.simtime, cpu, level);
+ printf ("%8" PRIu64 " cpu %d interrupt %d acknowledged\n",
+ ebase.simtime, cpu, level);
if (irqmp_ifr[cpu] & (1 << level))
irqmp_ifr[cpu] &= ~(1 << level);
else
@@ -288,25 +289,26 @@ chk_irq ()
uint32 itmp;
int old_irl;
- for (cpu = 0; cpu<ncpu; cpu++) {
- old_irl = ext_irl[cpu];
- itmp = ((irqmp_ipr | irqmp_ifr[cpu]) & irqmp_imr[cpu]) & 0x0fffe;
- ext_irl[cpu] = 0;
- if (itmp != 0)
+ for (cpu = 0; cpu < ncpu; cpu++)
{
- for (i = 15; i > 0; i--)
+ old_irl = ext_irl[cpu];
+ itmp = ((irqmp_ipr | irqmp_ifr[cpu]) & irqmp_imr[cpu]) & 0x0fffe;
+ ext_irl[cpu] = 0;
+ if (itmp != 0)
{
- if (((itmp >> i) & 1) != 0)
+ for (i = 15; i > 0; i--)
{
- if ((sis_verbose > 2) && (i != old_irl))
- printf ("%8" PRIu64 " cpu %d irl: %d\n",
- ebase.simtime, cpu, i);
- ext_irl[cpu] = i;
- break;
+ if (((itmp >> i) & 1) != 0)
+ {
+ if ((sis_verbose > 2) && (i != old_irl))
+ printf ("%8" PRIu64 " cpu %d irl: %d\n",
+ ebase.simtime, cpu, i);
+ ext_irl[cpu] = i;
+ break;
+ }
}
}
}
- }
}
static void
@@ -315,7 +317,7 @@ set_irq (int32 level)
int i;
if ((irqmp_ibr >> level) & 1)
- for (i=0; i<ncpu; i++)
+ for (i = 0; i < ncpu; i++)
irqmp_ifr[i] |= (1 << level);
else
irqmp_ipr |= (1 << level);
@@ -326,10 +328,12 @@ static uint32
gpt_counter_read (int i)
{
if (gpt_ctrl[i] & 1)
- return gpt_counter[i] - ((now() - gpt_counter_start[i]) / (gpt_scaler + 1));
+ return gpt_counter[i] -
+ ((now () - gpt_counter_start[i]) / (gpt_scaler + 1));
else
return gpt_counter[i];
}
+
static uint32
gpt_scaler_read ()
{
@@ -362,8 +366,8 @@ apb_read (uint32 addr, uint32 * data)
case IRQMP_ISR: /* 0x210 */
*data = ((ncpu - 1) << 28);
- for (i=0;i<ncpu;i++)
- *data |= (sregs[i].pwd_mode << i);
+ for (i = 0; i < ncpu; i++)
+ *data |= (sregs[i].pwd_mode << i);
break;
case IRQMP_IBR: /* 0x214 */
@@ -403,7 +407,7 @@ apb_read (uint32 addr, uint32 * data)
break;
case GPTIMER_SCALER: /* 0x300 */
- *data = gpt_scaler_read();
+ *data = gpt_scaler_read ();
break;
case GPTIMER_SCLOAD: /* 0x304 */
@@ -415,7 +419,7 @@ apb_read (uint32 addr, uint32 * data)
break;
case GPTIMER_TIMER1: /* 0x310 */
- *data = gpt_counter_read(0);
+ *data = gpt_counter_read (0);
break;
case GPTIMER_RELOAD1: /* 0x314 */
@@ -427,7 +431,7 @@ apb_read (uint32 addr, uint32 * data)
break;
case GPTIMER_TIMER2: /* 0x320 */
- *data = gpt_counter_read(1);
+ *data = gpt_counter_read (1);
break;
case GPTIMER_RELOAD2: /* 0x324 */
@@ -441,15 +445,16 @@ apb_read (uint32 addr, uint32 * data)
default:
*data = 0;
if (sis_verbose > 1)
- printf ("%8" PRIu64 " cpu %d APB read a: %08x, d: %08x unimplemented!\n",
- ebase.simtime, xcpu, addr, *data);
+ printf ("%8" PRIu64
+ " cpu %d APB read a: %08x, d: %08x unimplemented!\n",
+ ebase.simtime, xcpu, addr, *data);
break;
}
if (sis_verbose > 1)
- if ((addr & 0xF00) != 0x100)
- printf ("%8" PRIu64 " cpu %d APB read a: %08x, d: %08x\n",
- ebase.simtime, xcpu, addr, *data);
+ if ((addr & 0xF00) != 0x100)
+ printf ("%8" PRIu64 " cpu %d APB read a: %08x, d: %08x\n",
+ ebase.simtime, xcpu, addr, *data);
return MOK;
}
@@ -460,9 +465,9 @@ apb_write (uint32 addr, uint32 data)
int i;
if (sis_verbose > 1)
- if ((addr & 0xF00) != 0x100)
- printf ("%8" PRIu64 " cpu %d APB write a: %08x, d: %08x\n",
- ebase.simtime, xcpu, addr, data);
+ if ((addr & 0xF00) != 0x100)
+ printf ("%8" PRIu64 " cpu %d APB write a: %08x, d: %08x\n",
+ ebase.simtime, xcpu, addr, data);
switch (addr & 0xfff)
{
@@ -484,17 +489,21 @@ apb_write (uint32 addr, uint32 data)
break;
case IRQMP_ISR: /* 0x210 */
- for (i=0;i<ncpu;i++) {
- if ((data >> i) & 1) {
- if (sregs[i].pwd_mode) {
+ for (i = 0; i < ncpu; i++)
+ {
+ if ((data >> i) & 1)
+ {
+ if (sregs[i].pwd_mode)
+ {
sregs[i].simtime = ebase.simtime;
- if (sis_verbose > 1)
- printf ("%8" PRIu64 " cpu %d starting\n", ebase.simtime, i);
- sregs[i].pwdtime += ebase.simtime - sregs[i].pwdstart;
- }
+ if (sis_verbose > 1)
+ printf ("%8" PRIu64 " cpu %d starting\n", ebase.simtime,
+ i);
+ sregs[i].pwdtime += ebase.simtime - sregs[i].pwdstart;
+ }
sregs[i].pwd_mode = 0;
- }
- }
+ }
+ }
break;
case IRQMP_IBR: /* 0x214 */
@@ -546,9 +555,9 @@ apb_write (uint32 addr, uint32 data)
break;
case GPTIMER_TIMER1: /* 0x310 */
- gpt_counter[0] = data;
- remove_event (gpt_intr, 0);
- gpt_add_intr (0);
+ gpt_counter[0] = data;
+ remove_event (gpt_intr, 0);
+ gpt_add_intr (0);
break;
case GPTIMER_RELOAD1: /* 0x314 */
@@ -561,8 +570,8 @@ apb_write (uint32 addr, uint32 data)
case GPTIMER_TIMER2: /* 0x320 */
gpt_counter[1] = data;
- remove_event (gpt_intr, 1);
- gpt_add_intr (1);
+ remove_event (gpt_intr, 1);
+ gpt_add_intr (1);
break;
case GPTIMER_RELOAD2: /* 0x324 */
@@ -575,8 +584,9 @@ apb_write (uint32 addr, uint32 data)
default:
if (sis_verbose)
- printf ("%8" PRIu64 " cpu %d APB write a: %08x, d: %08x unimplemented!\n",
- ebase.simtime, xcpu, addr, data);
+ printf ("%8" PRIu64
+ " cpu %d APB write a: %08x, d: %08x unimplemented!\n",
+ ebase.simtime, xcpu, addr, data);
break;
}
return MOK;
@@ -620,20 +630,21 @@ port_init (void)
{
f1in = stdin;
f1out = stdout;
- if (uart_dev1[0] != 0) {
- if ((fd1 = open (uart_dev1, O_RDWR | O_NONBLOCK)) < 0)
- {
- printf ("Warning, couldn't open output device %s\n", uart_dev1);
- }
- else
- {
- if (sis_verbose)
- printf ("serial port A on %s\n", uart_dev1);
- f1in = f1out = fdopen (fd1, "r+");
- setbuf (f1out, NULL);
- f1open = 1;
- }
- }
+ if (uart_dev1[0] != 0)
+ {
+ if ((fd1 = open (uart_dev1, O_RDWR | O_NONBLOCK)) < 0)
+ {
+ printf ("Warning, couldn't open output device %s\n", uart_dev1);
+ }
+ else
+ {
+ if (sis_verbose)
+ printf ("serial port A on %s\n", uart_dev1);
+ f1in = f1out = fdopen (fd1, "r+");
+ setbuf (f1out, NULL);
+ f1open = 1;
+ }
+ }
if (f1in)
ifd1 = fileno (f1in);
if (ifd1 == 0)
@@ -772,7 +783,7 @@ grlib_write_uart (uint32 addr, uint32 data)
{
while (wnuma)
{
- wnuma -= fwrite (wbufa, 1, wnuma, f1out);
+ wnuma -= fwrite (wbufa, 1, wnuma, f1out);
}
wbufa[wnuma++] = c;
}
@@ -809,7 +820,7 @@ flush_uart (void)
{
while (wnuma && f1open)
{
- wnuma -= fwrite (wbufa, 1, wnuma, f1out);
+ wnuma -= fwrite (wbufa, 1, wnuma, f1out);
}
}
@@ -818,8 +829,8 @@ uarta_tx (void)
{
while (f1open)
{
- while (fwrite (&uarta_sreg, 1, 1, f1out) != 1)
- continue;
+ while (fwrite (&uarta_sreg, 1, 1, f1out) != 1)
+ continue;
}
if (uart_stat_reg & UARTA_HRE)
{
@@ -885,13 +896,15 @@ uart_irq_start (void)
static void
gpt_add_intr (int i)
{
- if (gpt_ctrl[i] & 1)
- {
- event (gpt_intr, i, (uint64) (gpt_scaler + 1) * (uint64) ((uint64) gpt_counter[i] + (uint64) 1));
- gpt_counter_start[i] = now();
- }
+ if (gpt_ctrl[i] & 1)
+ {
+ event (gpt_intr, i,
+ (uint64) (gpt_scaler + 1) * (uint64) ((uint64) gpt_counter[i] +
+ (uint64) 1));
+ gpt_counter_start[i] = now ();
+ }
}
-
+
static void
gpt_intr (int32 i)
{
@@ -903,7 +916,7 @@ gpt_intr (int32 i)
gpt_counter[i] = gpt_reload[i];
}
if (gpt_ctrl[i] & 8)
- {
+ {
set_irq (GPTIMER_IRQ + i);
}
gpt_add_intr (i);
@@ -938,7 +951,7 @@ gpt_add_intr_all ()
gpt_add_intr (i);
}
}
-
+
static void
gpt_scaler_set (uint32 val)
{
@@ -948,7 +961,7 @@ gpt_scaler_set (uint32 val)
gpt_scaler = val & 0x0ffff;
remove_event (gpt_intr, -1);
gpt_scaler_start = now ();
- gpt_add_intr_all();
+ gpt_add_intr_all ();
}
}
@@ -976,27 +989,26 @@ timer_ctrl (uint32 val, int i)
2 (one word), or 3 (two words); WS should return the number of wait-states. */
static void
-store_bytes (char *mem, uint32 waddr, uint32 * data, int32 sz,
- int32 * ws)
+store_bytes (char *mem, uint32 waddr, uint32 * data, int32 sz, int32 * ws)
{
if (sz == 2)
- memcpy (&mem[waddr], data, 4);
+ memcpy (&mem[waddr], data, 4);
else
switch (sz)
- {
- case 0:
- waddr ^= arch->endian;
- mem[waddr] = *data & 0x0ff;
- break;
- case 1:
- waddr ^= arch->endian & 2;
- memcpy (&mem[waddr], data, 2);
- break;
- case 3:
- memcpy (&mem[waddr], data, 8);
- break;
- }
- *ws = 0;
+ {
+ case 0:
+ waddr ^= arch->endian;
+ mem[waddr] = *data & 0x0ff;
+ break;
+ case 1:
+ waddr ^= arch->endian & 2;
+ memcpy (&mem[waddr], data, 2);
+ break;
+ case 3:
+ memcpy (&mem[waddr], data, 8);
+ break;
+ }
+ *ws = 0;
}
@@ -1134,10 +1146,12 @@ sis_memory_write (uint32 addr, const char *data, uint32 length)
char *mem;
int32 ws;
- if ((mem = get_mem_ptr (addr, length)) != ((char *) -1)) {
- memcpy (mem, data, length);
- return length;
- } else if (length == 4)
+ if ((mem = get_mem_ptr (addr, length)) != ((char *) -1))
+ {
+ memcpy (mem, data, length);
+ return length;
+ }
+ else if (length == 4)
memory_write (addr, (uint32 *) data, 2, &ws);
return 0;
}
@@ -1174,14 +1188,15 @@ boot_init (void)
apb_write (GPTIMER_RELOAD1, -1);
apb_write (GPTIMER_CTRL1, 0x7);
- for (i=0;i<NCPU;i++) {
- sregs[i].wim = 2;
- sregs[i].psr = 0xF30010e0;
- sregs[i].r[30] = RAM_END - (i * 0x20000);
- sregs[i].r[14] = sregs[i].r[30] - 96 * 4;
- sregs[i].cache_ctrl = 0x81000f;
- sregs[i].r[2] = sregs[i].r[30]; /* sp on RISCV-V */
- }
+ for (i = 0; i < NCPU; i++)
+ {
+ sregs[i].wim = 2;
+ sregs[i].psr = 0xF30010e0;
+ sregs[i].r[30] = RAM_END - (i * 0x20000);
+ sregs[i].r[14] = sregs[i].r[30] - 96 * 4;
+ sregs[i].cache_ctrl = 0x81000f;
+ sregs[i].r[2] = sregs[i].r[30]; /* sp on RISCV-V */
+ }
}
const struct memsys leon3 = {
diff --git a/remote.c b/remote.c
index 7cc7344..f18baa8 100644
--- a/remote.c
+++ b/remote.c
@@ -373,10 +373,11 @@ gdb_remote_exec (char *buf)
{
cptr = &buf[6];
mptr = membuf;
- while (*cptr != '#') {
- *mptr = hex (*cptr++) << 4;
- *mptr++ |= hex (*cptr++);
- }
+ while (*cptr != '#')
+ {
+ *mptr = hex (*cptr++) << 4;
+ *mptr++ |= hex (*cptr++);
+ }
*mptr = 0;
exec_cmd (membuf);
strcpy (txbuf, "OK");
diff --git a/riscv.c b/riscv.c
index 7a53659..450283d 100644
--- a/riscv.c
+++ b/riscv.c
@@ -262,7 +262,8 @@ riscv_dispatch_instruction (sregs)
break;
}
mexc =
- ms->memory_write (address, &sregs->fsi[rs2p << 1], 2, &ws);
+ ms->memory_write (address, (uint32 *) & sregs->fsi[rs2p << 1],
+ 2, &ws);
sregs->hold += ws;
if (mexc)
{
@@ -281,7 +282,8 @@ riscv_dispatch_instruction (sregs)
break;
}
mexc =
- ms->memory_write (address, &sregs->fsi[rs2p << 1], 3, &ws);
+ ms->memory_write (address, (uint32 *) & sregs->fsi[rs2p << 1],
+ 3, &ws);
sregs->hold += ws;
if (mexc)
{
@@ -564,7 +566,8 @@ riscv_dispatch_instruction (sregs)
break;
}
mexc =
- ms->memory_write (address, &sregs->fsi[rs2 << 1], 3, &ws);
+ ms->memory_write (address, (uint32 *) & sregs->fsi[rs2 << 1],
+ 3, &ws);
sregs->hold += ws;
if (mexc)
{
@@ -582,7 +585,8 @@ riscv_dispatch_instruction (sregs)
break;
}
mexc =
- ms->memory_write (address, &sregs->fsi[rs2 << 1], 2, &ws);
+ ms->memory_write (address, (uint32 *) & sregs->fsi[rs2 << 1],
+ 2, &ws);
sregs->hold += ws;
if (mexc)
{
@@ -875,7 +879,7 @@ riscv_dispatch_instruction (sregs)
if (ebase.wpwnum)
{
- if (ebase.wphit = check_wpw (sregs, address, funct3 & 3))
+ if ((ebase.wphit = check_wpw (sregs, address, funct3 & 3)))
{
sregs->trap = WPT_TRAP;
break;
@@ -929,8 +933,8 @@ riscv_dispatch_instruction (sregs)
#ifdef ENABLE_L1CACHE
if (ncpu > 1)
{
- l1data_update(address, sregs->cpu);
- l1data_snoop(address, sregs->cpu);
+ l1data_update (address, sregs->cpu);
+ l1data_snoop (address, sregs->cpu);
}
#endif
break;
@@ -941,11 +945,11 @@ riscv_dispatch_instruction (sregs)
#endif
offset = EXTRACT_STYPE_IMM (sregs->inst);
address = op1 + offset;
- wdata = &sregs->fsi[rs2 << 1];
+ wdata = (uint32 *) & sregs->fsi[rs2 << 1];
if (ebase.wpwnum)
{
- if (ebase.wphit = check_wpw (sregs, address, funct3 & 3))
+ if ((ebase.wphit = check_wpw (sregs, address, funct3 & 3)))
{
sregs->trap = WPT_TRAP;
break;
@@ -990,8 +994,8 @@ riscv_dispatch_instruction (sregs)
#ifdef ENABLE_L1CACHE
if (ncpu > 1)
{
- l1data_update(address, sregs->cpu);
- l1data_snoop(address, sregs->cpu);
+ l1data_update (address, sregs->cpu);
+ l1data_snoop (address, sregs->cpu);
}
#endif
break;
@@ -1003,7 +1007,7 @@ riscv_dispatch_instruction (sregs)
address = op1 + offset;
if (ebase.wprnum)
{
- if (ebase.wphit = check_wpr (sregs, address, funct3 & 3))
+ if ((ebase.wphit = check_wpr (sregs, address, funct3 & 3)))
{
sregs->trap = WPT_TRAP;
break;
@@ -1040,7 +1044,7 @@ riscv_dispatch_instruction (sregs)
sregs->trap = TRAP_ILLEG;
break;
}
- mexc = ms->memory_read (address, (uint32 *) &data, &ws);
+ mexc = ms->memory_read (address, (uint32 *) & data, &ws);
sregs->hold += ws;
if (mexc)
{
@@ -1069,7 +1073,7 @@ riscv_dispatch_instruction (sregs)
sregs->wpaddress = address;
break;
}
- mexc = ms->memory_read (address, (uint32 *) &data, &ws);
+ mexc = ms->memory_read (address, (uint32 *) & data, &ws);
sregs->hold += ws;
if (mexc)
{
@@ -1105,7 +1109,7 @@ riscv_dispatch_instruction (sregs)
#ifdef ENABLE_L1CACHE
if (ncpu > 1)
{
- l1data_update(address, sregs->cpu);
+ l1data_update (address, sregs->cpu);
}
#endif
break;
@@ -1191,7 +1195,7 @@ riscv_dispatch_instruction (sregs)
sregs->wpaddress = address;
break;
}
- mexc = ms->memory_read (address, (uint32 *) &data, &ws);
+ mexc = ms->memory_read (address, (uint32 *) & data, &ws);
sregs->hold += ws;
if (mexc)
{
@@ -1338,7 +1342,7 @@ riscv_dispatch_instruction (sregs)
address = op1 + offset;
if (ebase.wprnum)
{
- if (ebase.wphit = check_wpr (sregs, address, funct3 & 3))
+ if ((ebase.wphit = check_wpr (sregs, address, funct3 & 3)))
{
sregs->trap = WPT_TRAP;
break;
@@ -1399,7 +1403,7 @@ riscv_dispatch_instruction (sregs)
#ifdef ENABLE_L1CACHE
if (ncpu > 1)
{
- l1data_update(address, sregs->cpu);
+ l1data_update (address, sregs->cpu);
}
#endif
break;
@@ -1623,18 +1627,18 @@ riscv_dispatch_instruction (sregs)
case 0: /* FSGNJ */
sregs->fsi[frd] = sregs->fsi[frs1];
sregs->fsi[frd + 1] =
- (sregs->
- fsi[frs1 + 1] & 0x7fffffff) | (sregs->fsi[frs2 +
+ (sregs->fsi[frs1 + 1] & 0x7fffffff) | (sregs->
+ fsi[frs2 +
1] &
- 0x80000000);
+ 0x80000000);
break;
case 1: /* FSGNJN */
sregs->fsi[frd] = sregs->fsi[frs1];
sregs->fsi[frd + 1] =
- (sregs->
- fsi[frs1 + 1] & 0x7fffffff) | (~sregs->fsi[frs2 +
- 1] &
- 0x80000000);
+ (sregs->fsi[frs1 + 1] & 0x7fffffff) | (~sregs->
+ fsi[frs2 +
+ 1] &
+ 0x80000000);
break;
case 2: /* FSGNJX */
sregs->fsi[frd] = sregs->fsi[frs1];
diff --git a/riscv.h b/riscv.h
index ff4eb1c..04e99a7 100644
--- a/riscv.h
+++ b/riscv.h
@@ -211,4 +211,3 @@
((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
#define EXTRACT_UJTYPE_IMM(x) \
((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
-
diff --git a/sis.c b/sis.c
index 72466c6..87f75bc 100644
--- a/sis.c
+++ b/sis.c
@@ -37,272 +37,331 @@
#define HIST_LEN 256
int
-main(argc, argv)
- int argc;
- char **argv;
+main (argc, argv)
+ int argc;
+ char **argv;
{
- int cont = 1;
- int stat = 1;
- int freq = 0;
- int copt = 0;
+ int cont = 1;
+ int stat = 1;
+ int freq = 0;
+ int copt = 0;
- char *cfile, *bacmd;
- char *cmdq[HIST_LEN];
- int cmdi = 0;
- int i;
- int lfile = 0;
- char tlim[64] = "";
- int run = 0;
- char prompt[8];
- int gdb = 0;
- int lcputype = 0;
+ char *cfile, *bacmd;
+ char *cmdq[HIST_LEN];
+ int cmdi = 0;
+ int i;
+ int lfile = 0;
+ char tlim[64] = "";
+ int run = 0;
+ char prompt[8];
+ int gdb = 0;
+ int lcputype = 0;
- printf("\n SIS - SPARC/RISCV instruction simulator %s, copyright Jiri Gaisler 2019\n", sis_version);
- printf (" Bug-reports to jiri@gaisler.se\n\n");
+ printf
+ ("\n SIS - SPARC/RISCV instruction simulator %s, copyright Jiri Gaisler 2019\n",
+ sis_version);
+ printf (" Bug-reports to jiri@gaisler.se\n\n");
- /* initialize history buffer */
- for (i = 0; i < HIST_LEN; i++)
- cmdq[i] = 0;
+ /* initialize history buffer */
+ for (i = 0; i < HIST_LEN; i++)
+ cmdq[i] = 0;
- /* if binary name starts with riscv, force RISCV emulation */
- strncpy(uart_dev1, argv[0], 128);
- cfile = basename(uart_dev1);
- if (strncmp(cfile, "riscv", 5) == 0) {
+ /* if binary name starts with riscv, force RISCV emulation */
+ strncpy (uart_dev1, argv[0], 128);
+ cfile = basename (uart_dev1);
+ if (strncmp (cfile, "riscv", 5) == 0)
+ {
lcputype = CPU_RISCV;
- }
+ }
- cfile = 0;
- uart_dev1[0] = 0;
+ cfile = 0;
+ uart_dev1[0] = 0;
- /* parse start-up switches */
- while (stat < argc) {
- if (argv[stat][0] == '-') {
- if (strcmp(argv[stat], "-v") == 0) {
- sis_verbose += 1;
- } else if (strcmp(argv[stat], "-c") == 0) {
- if ((stat + 1) < argc) {
- copt = 1;
- cfile = argv[++stat];
+ /* parse start-up switches */
+ while (stat < argc)
+ {
+ if (argv[stat][0] == '-')
+ {
+ if (strcmp (argv[stat], "-v") == 0)
+ {
+ sis_verbose += 1;
+ }
+ else if (strcmp (argv[stat], "-c") == 0)
+ {
+ if ((stat + 1) < argc)
+ {
+ copt = 1;
+ cfile = argv[++stat];
}
- } else if (strcmp(argv[stat], "-cov") == 0)
- ebase.coven = 1;
- else if (strcmp(argv[stat], "-nfp") == 0)
- nfp = 1;
- else if (strcmp(argv[stat], "-ift") == 0)
- ift = 1;
- else if (strcmp(argv[stat], "-wrp") == 0)
- wrp = 1;
- else if (strcmp(argv[stat], "-rom8") == 0)
- rom8 = 1;
- else if (strcmp(argv[stat], "-uben") == 0)
- uben = 1;
- else if (strcmp(argv[stat], "-uart1") == 0) {
- if ((stat + 1) < argc)
- strcpy(uart_dev1, argv[++stat]);
- } else if (strcmp(argv[stat], "-uart2") == 0) {
- if ((stat + 1) < argc)
- strcpy(uart_dev2, argv[++stat]);
- } else if (strcmp(argv[stat], "-freq") == 0) {
- if ((stat + 1) < argc)
- freq = VAL(argv[++stat]);
- } else if (strcmp(argv[stat], "-dumbio") == 0) {
- dumbio = 1;
- } else if (strcmp(argv[stat], "-gdb") == 0) {
- gdb = 1;
- } else if (strcmp(argv[stat], "-port") == 0) {
- if ((stat + 1) < argc)
- port = VAL(argv[++stat]);
- } else if (strcmp(argv[stat], "-nouartrx") == 0) {
- nouartrx = 1;
- } else if (strcmp(argv[stat], "-r") == 0) {
- run = 1;
- } else if (strcmp (argv[stat], "-erc32") == 0) {
- lcputype = CPU_ERC32;
- } else if (strcmp (argv[stat], "-leon2") == 0) {
- lcputype = CPU_LEON2;
- } else if (strcmp (argv[stat], "-leon3") == 0) {
- lcputype = CPU_LEON3;
- } else if (strcmp (argv[stat], "-riscv") == 0) {
- lcputype = CPU_RISCV;
- } else if (strcmp(argv[stat], "-tlim") == 0) {
- if ((stat + 2) < argc) {
- strcpy(tlim, "tlim ");
- strcat(tlim, argv[++stat]);
- strcat(tlim, " ");
- strcat(tlim, argv[++stat]);
+ }
+ else if (strcmp (argv[stat], "-cov") == 0)
+ ebase.coven = 1;
+ else if (strcmp (argv[stat], "-nfp") == 0)
+ nfp = 1;
+ else if (strcmp (argv[stat], "-ift") == 0)
+ ift = 1;
+ else if (strcmp (argv[stat], "-wrp") == 0)
+ wrp = 1;
+ else if (strcmp (argv[stat], "-rom8") == 0)
+ rom8 = 1;
+ else if (strcmp (argv[stat], "-uben") == 0)
+ uben = 1;
+ else if (strcmp (argv[stat], "-uart1") == 0)
+ {
+ if ((stat + 1) < argc)
+ strcpy (uart_dev1, argv[++stat]);
+ }
+ else if (strcmp (argv[stat], "-uart2") == 0)
+ {
+ if ((stat + 1) < argc)
+ strcpy (uart_dev2, argv[++stat]);
+ }
+ else if (strcmp (argv[stat], "-freq") == 0)
+ {
+ if ((stat + 1) < argc)
+ freq = VAL (argv[++stat]);
+ }
+ else if (strcmp (argv[stat], "-dumbio") == 0)
+ {
+ dumbio = 1;
+ }
+ else if (strcmp (argv[stat], "-gdb") == 0)
+ {
+ gdb = 1;
+ }
+ else if (strcmp (argv[stat], "-port") == 0)
+ {
+ if ((stat + 1) < argc)
+ port = VAL (argv[++stat]);
+ }
+ else if (strcmp (argv[stat], "-nouartrx") == 0)
+ {
+ nouartrx = 1;
+ }
+ else if (strcmp (argv[stat], "-r") == 0)
+ {
+ run = 1;
+ }
+ else if (strcmp (argv[stat], "-erc32") == 0)
+ {
+ lcputype = CPU_ERC32;
+ }
+ else if (strcmp (argv[stat], "-leon2") == 0)
+ {
+ lcputype = CPU_LEON2;
+ }
+ else if (strcmp (argv[stat], "-leon3") == 0)
+ {
+ lcputype = CPU_LEON3;
+ }
+ else if (strcmp (argv[stat], "-riscv") == 0)
+ {
+ lcputype = CPU_RISCV;
+ }
+ else if (strcmp (argv[stat], "-tlim") == 0)
+ {
+ if ((stat + 2) < argc)
+ {
+ strcpy (tlim, "tlim ");
+ strcat (tlim, argv[++stat]);
+ strcat (tlim, " ");
+ strcat (tlim, argv[++stat]);
}
- } else if (strcmp(argv[stat], "-m") == 0) {
- if ((stat + 1) < argc)
- ncpu = VAL(argv[++stat]);
- if ((ncpu < 1) || (ncpu > NCPU)) ncpu = 1;
- } else if (strcmp(argv[stat], "-d") == 0) {
- if ((stat + 1) < argc)
- delta = VAL(argv[++stat]);
- if (delta <= 0) delta = 25;
- } else {
- printf("unknown option %s\n", argv[stat]);
- sis_usage();
- exit(1);
}
- } else {
- lfile = stat;
+ else if (strcmp (argv[stat], "-m") == 0)
+ {
+ if ((stat + 1) < argc)
+ ncpu = VAL (argv[++stat]);
+ if ((ncpu < 1) || (ncpu > NCPU))
+ ncpu = 1;
+ }
+ else if (strcmp (argv[stat], "-d") == 0)
+ {
+ if ((stat + 1) < argc)
+ delta = VAL (argv[++stat]);
+ if (delta <= 0)
+ delta = 25;
+ }
+ else
+ {
+ printf ("unknown option %s\n", argv[stat]);
+ sis_usage ();
+ exit (1);
+ }
}
- stat++;
+ else
+ {
+ lfile = stat;
+ }
+ stat++;
}
- if (lfile) {
- last_load_addr = elf_load(argv[lfile], 0);
- if (ebase.cpu)
- cputype = ebase.cpu;
+ if (lfile)
+ {
+ last_load_addr = elf_load (argv[lfile], 0);
+ if (ebase.cpu)
+ cputype = ebase.cpu;
}
- if (lcputype)
- cputype = lcputype;
+ if (lcputype)
+ cputype = lcputype;
- switch (cputype) {
+ switch (cputype)
+ {
case CPU_LEON2:
- printf (" LEON2 emulation enabled\n");
- ms = &leon2;
- if (!freq) freq = 50;
- break;
+ printf (" LEON2 emulation enabled\n");
+ ms = &leon2;
+ if (!freq)
+ freq = 50;
+ break;
case CPU_LEON3:
- printf (" LEON3 emulation enabled, %d cpus online, delta %d clocks\n",
- ncpu, delta);
- ms = &leon3;
- if (!freq) freq = 50;
- break;
+ printf (" LEON3 emulation enabled, %d cpus online, delta %d clocks\n",
+ ncpu, delta);
+ ms = &leon3;
+ if (!freq)
+ freq = 50;
+ break;
case CPU_RISCV:
- printf (" RISCV emulation enabled, %d cpus online, delta %d clocks\n",
- ncpu, delta);
- ms = &leon3;
- arch = &riscv;
- if (!freq) freq = 50;
- break;
+ printf (" RISCV emulation enabled, %d cpus online, delta %d clocks\n",
+ ncpu, delta);
+ ms = &leon3;
+ arch = &riscv;
+ if (!freq)
+ freq = 50;
+ break;
default:
- printf (" ERC32 emulation enabled\n");
- cputype = CPU_ERC32;
- if (!freq) freq = 14;
+ printf (" ERC32 emulation enabled\n");
+ cputype = CPU_ERC32;
+ if (!freq)
+ freq = 14;
}
#ifdef ENABLE_L1CACHE
- if (ncpu > 1)
- printf(" L1 cache: %dK/%dK, %d bytes/line \n",
- (1 << (L1IBITS - 10)), (1 << (L1DBITS - 10)), (1 << L1ILINEBITS));
+ if (ncpu > 1)
+ printf (" L1 cache: %dK/%dK, %d bytes/line \n",
+ (1 << (L1IBITS - 10)), (1 << (L1DBITS - 10)), (1 << L1ILINEBITS));
#endif
- if (nfp)
- printf(" FPU disabled\n");
- ebase.freq = freq;
- printf("\n");
+ if (nfp)
+ printf (" FPU disabled\n");
+ ebase.freq = freq;
+ printf ("\n");
#ifdef F_GETFL
- termsave = fcntl(0, F_GETFL, 0);
+ termsave = fcntl (0, F_GETFL, 0);
#endif
- using_history();
- init_signals();
- ebase.simtime = 0;
- ebase.simstart = 0;
- reset_all();
- init_bpt(sregs);
- ms->init_sim ();
- if (lfile) {
- last_load_addr = elf_load(argv[lfile], 1);
- daddr = last_load_addr;
+ using_history ();
+ init_signals ();
+ ebase.simtime = 0;
+ ebase.simstart = 0;
+ reset_all ();
+ init_bpt (sregs);
+ ms->init_sim ();
+ if (lfile)
+ {
+ last_load_addr = elf_load (argv[lfile], 1);
+ daddr = last_load_addr;
}
#ifdef STAT
- reset_stat(&sregs);
+ reset_stat (&sregs);
#endif
- if (copt) {
- bacmd = (char *) malloc(256);
- strcpy(bacmd, "batch ");
- strcat(bacmd, cfile);
- exec_cmd(bacmd);
+ if (copt)
+ {
+ bacmd = (char *) malloc (256);
+ strcpy (bacmd, "batch ");
+ strcat (bacmd, cfile);
+ exec_cmd (bacmd);
}
- if (tlim[0]) {
- exec_cmd(tlim);
+ if (tlim[0])
+ {
+ exec_cmd (tlim);
}
- if (gdb)
- gdb_remote(port);
+ if (gdb)
+ gdb_remote (port);
- while (cont) {
+ while (cont)
+ {
- if (cmdq[cmdi] != 0) {
+ if (cmdq[cmdi] != 0)
+ {
#if 0
- remove_history(cmdq[cmdi]);
+ remove_history (cmdq[cmdi]);
#else
- remove_history(cmdi);
+ remove_history (cmdi);
#endif
- free(cmdq[cmdi]);
- cmdq[cmdi] = 0;
+ free (cmdq[cmdi]);
+ cmdq[cmdi] = 0;
}
- if (run) {
- stat = exec_cmd("run");
- cont = 0;
+ if (run)
+ {
+ stat = exec_cmd ("run");
+ cont = 0;
}
- else {
- if (ncpu > 1)
- sprintf(prompt, "cpu%d> ", cpu);
- else
- sprintf(prompt, "sis> ");
- cmdq[cmdi] = readline(prompt);
- if (cmdq[cmdi] && *cmdq[cmdi])
- add_history(cmdq[cmdi]);
- if (cmdq[cmdi])
- stat = exec_cmd(cmdq[cmdi]);
- else {
- puts("\n");
- exit(0);
+ else
+ {
+ if (ncpu > 1)
+ sprintf (prompt, "cpu%d> ", cpu);
+ else
+ sprintf (prompt, "sis> ");
+ cmdq[cmdi] = readline (prompt);
+ if (cmdq[cmdi] && *cmdq[cmdi])
+ add_history (cmdq[cmdi]);
+ if (cmdq[cmdi])
+ stat = exec_cmd (cmdq[cmdi]);
+ else
+ {
+ puts ("\n");
+ exit (0);
}
}
- switch (stat) {
+ switch (stat)
+ {
case OK:
- break;
+ break;
case CTRL_C:
- printf("\b\bInterrupt!\n");
+ printf ("\b\bInterrupt!\n");
case TIME_OUT:
- printf(" Stopped at time %" PRIu64 " (%.3f ms)\n", ebase.simtime,
- ((double) ebase.simtime / (double) ebase.freq) / 1000.0);
- break;
+ printf (" Stopped at time %" PRIu64 " (%.3f ms)\n", ebase.simtime,
+ ((double) ebase.simtime / (double) ebase.freq) / 1000.0);
+ break;
case BPT_HIT:
- printf("cpu %d breakpoint at 0x%08x reached\n",
- ebase.bpcpu, sregs[ebase.bpcpu].pc);
- break;
+ printf ("cpu %d breakpoint at 0x%08x reached\n",
+ ebase.bpcpu, sregs[ebase.bpcpu].pc);
+ break;
case ERROR:
- printf("cpu %d in error mode (tt = 0x%02x)\n",
- ebase.bpcpu, sregs[ebase.bpcpu].trap);
- stat = 0;
- printf(" %8" PRIu64 " ", ebase.simtime);
- dis_mem(sregs[cpu].pc, 1);
- break;
+ printf ("cpu %d in error mode (tt = 0x%02x)\n",
+ ebase.bpcpu, sregs[ebase.bpcpu].trap);
+ stat = 0;
+ printf (" %8" PRIu64 " ", ebase.simtime);
+ dis_mem (sregs[cpu].pc, 1);
+ break;
case WPT_HIT:
- printf("cpu %d watchpoint at 0x%08x reached, pc = 0x%08x\n",
- ebase.bpcpu, ebase.wpaddress, sregs[ebase.bpcpu].pc);
- ebase.wphit = 1;
- break;
+ printf ("cpu %d watchpoint at 0x%08x reached, pc = 0x%08x\n",
+ ebase.bpcpu, ebase.wpaddress, sregs[ebase.bpcpu].pc);
+ ebase.wphit = 1;
+ break;
case NULL_HIT:
- printf("segmentation error, cpu %d halted\n",
- ebase.bpcpu);
- stat = 0;
- printf(" %8" PRIu64 " ", ebase.simtime);
- dis_mem(sregs[cpu].pc, 1);
- break;
+ printf ("segmentation error, cpu %d halted\n", ebase.bpcpu);
+ stat = 0;
+ printf (" %8" PRIu64 " ", ebase.simtime);
+ dis_mem (sregs[cpu].pc, 1);
+ break;
case QUIT:
- cont = 0;
- break;
+ cont = 0;
+ break;
default:
- break;
+ break;
}
- ctrl_c = 0;
- stat = OK;
+ ctrl_c = 0;
+ stat = OK;
- cmdi = (cmdi + 1) & (HIST_LEN - 1);
+ cmdi = (cmdi + 1) & (HIST_LEN - 1);
}
- if (ebase.coven)
- cov_save(argv[lfile]);
- return 0;
+ if (ebase.coven)
+ cov_save (argv[lfile]);
+ return 0;
}
-
diff --git a/sis.h b/sis.h
index 13caddd..a15a83f 100644
--- a/sis.h
+++ b/sis.h
@@ -65,154 +65,160 @@
typedef short int int16; /* 16-bit signed int */
typedef unsigned short int uint16; /* 16-bit unsigned int */
-typedef int int32; /* 32-bit signed int */
+typedef int int32; /* 32-bit signed int */
typedef unsigned int uint32; /* 32-bit unsigned int */
-typedef float float32; /* 32-bit float */
-typedef double float64; /* 64-bit float */
+typedef float float32; /* 32-bit float */
+typedef double float64; /* 64-bit float */
-typedef uint64_t uint64; /* 64-bit unsigned int */
-typedef int64_t int64; /* 64-bit signed int */
+typedef uint64_t uint64; /* 64-bit unsigned int */
+typedef int64_t int64; /* 64-bit signed int */
-struct histype {
- unsigned addr;
- uint64 time;
+struct histype
+{
+ unsigned addr;
+ uint64 time;
};
-struct pstate {
-
- float64 fd[32]; /* FPU registers */
- float32 *fs;
- int32 *fsi;
- uint32 fsr;
- int32 fpstate;
- uint32 fpq[FPUQN * 2];
- uint32 fpqn;
- uint32 ftime;
- uint32 flrd;
- uint32 frd;
- uint32 frs1;
- uint32 frs2;
- uint32 fpu_pres; /* FPU present (0 = No, 1 = Yes) */
-
- uint32 psr; /* IU registers */
- uint32 tbr;
- uint32 wim;
- uint32 g[8];
- uint32 r[128];
- uint32 y;
- uint32 asr17; /* Single vector trapping */
- uint32 pc, npc;
-
-
- uint32 trap; /* Current trap type */
- uint32 data; /* Loaded data */
- uint32 inst; /* Current instruction */
- uint32 asi; /* Current ASI */
- uint32 err_mode; /* IU error mode */
- uint32 pwd_mode; /* IU in power-down mode */
- uint32 breakpoint;
-
- uint32 ltime; /* Load interlock time */
- uint32 hold; /* IU hold cycles in current inst */
- uint32 fhold; /* FPU hold cycles in current inst */
- uint32 icnt; /* Instruction cycles in curr inst */
-
- uint32 histind;
- struct histype *histbuf;
-
-
- uint64 ninst;
- uint64 fholdt;
- uint64 holdt;
- uint64 icntt;
- uint64 finst;
- uint64 pwdtime; /* Cycles in power-down mode */
- uint64 pwdstart; /* Start of power-down mode */
- uint64 nstore; /* Number of store instructions */
- uint64 nload; /* Number of load instructions */
- uint64 nannul; /* Number of annuled instructions */
- uint64 nbranch; /* Number of branch instructions */
- uint32 ildreg; /* Destination of last load instruction */
- uint64 ildtime; /* Last time point for load dependency */
-
- int rett_err; /* IU in jmpl/restore error state (Rev.0) */
- int jmpltime;
- int cpu;
- uint64 simtime; /* local processor time */
- uint32 cache_ctrl; /* Leon3 cache control register */
- void (*intack) (); /* interrupt ack. callback */
-
- uint32 mip;
- uint32 mie;
- uint32 mpp;
- uint32 mode;
- uint32 mstatus;
- uint32 mtvec;
- uint32 epc;
- uint32 wpaddress;
- uint32 mcause;
- uint32 mtval;
- uint32 mscratch;
- uint64 mtimecmp;
- uint32 lrq;
- uint32 lrqa;
-
- uint32 bphit;
- uint32 l1itags[L1ITAGS];
- uint64 l1imiss;
- uint32 l1dtags[L1DTAGS];
- uint64 l1dmiss;
+struct pstate
+{
+
+ float64 fd[32]; /* FPU registers */
+ float32 *fs;
+ int32 *fsi;
+ uint32 fsr;
+ int32 fpstate;
+ uint32 fpq[FPUQN * 2];
+ uint32 fpqn;
+ uint32 ftime;
+ uint32 flrd;
+ uint32 frd;
+ uint32 frs1;
+ uint32 frs2;
+ uint32 fpu_pres; /* FPU present (0 = No, 1 = Yes) */
+
+ uint32 psr; /* IU registers */
+ uint32 tbr;
+ uint32 wim;
+ uint32 g[8];
+ uint32 r[128];
+ uint32 y;
+ uint32 asr17; /* Single vector trapping */
+ uint32 pc, npc;
+
+
+ uint32 trap; /* Current trap type */
+ uint32 data; /* Loaded data */
+ uint32 inst; /* Current instruction */
+ uint32 asi; /* Current ASI */
+ uint32 err_mode; /* IU error mode */
+ uint32 pwd_mode; /* IU in power-down mode */
+ uint32 breakpoint;
+
+ uint32 ltime; /* Load interlock time */
+ uint32 hold; /* IU hold cycles in current inst */
+ uint32 fhold; /* FPU hold cycles in current inst */
+ uint32 icnt; /* Instruction cycles in curr inst */
+
+ uint32 histind;
+ struct histype *histbuf;
+
+
+ uint64 ninst;
+ uint64 fholdt;
+ uint64 holdt;
+ uint64 icntt;
+ uint64 finst;
+ uint64 pwdtime; /* Cycles in power-down mode */
+ uint64 pwdstart; /* Start of power-down mode */
+ uint64 nstore; /* Number of store instructions */
+ uint64 nload; /* Number of load instructions */
+ uint64 nannul; /* Number of annuled instructions */
+ uint64 nbranch; /* Number of branch instructions */
+ uint32 ildreg; /* Destination of last load instruction */
+ uint64 ildtime; /* Last time point for load dependency */
+
+ int rett_err; /* IU in jmpl/restore error state (Rev.0) */
+ int jmpltime;
+ int cpu;
+ uint64 simtime; /* local processor time */
+ uint32 cache_ctrl; /* Leon3 cache control register */
+ void (*intack) (); /* interrupt ack. callback */
+
+ uint32 mip;
+ uint32 mie;
+ uint32 mpp;
+ uint32 mode;
+ uint32 mstatus;
+ uint32 mtvec;
+ uint32 epc;
+ uint32 wpaddress;
+ uint32 mcause;
+ uint32 mtval;
+ uint32 mscratch;
+ uint64 mtimecmp;
+ uint32 lrq;
+ uint32 lrqa;
+
+ uint32 bphit;
+ uint32 l1itags[L1ITAGS];
+ uint64 l1imiss;
+ uint32 l1dtags[L1DTAGS];
+ uint64 l1dmiss;
};
-struct evcell {
- void (*cfunc) ();
- int32 arg;
- uint64 time;
- struct evcell *nxt;
+struct evcell
+{
+ void (*cfunc) ();
+ int32 arg;
+ uint64 time;
+ struct evcell *nxt;
};
-struct cpu_arch {
- int endian;
- int (*dispatch_instruction) (struct pstate *sregs);
- int (*execute_trap) (struct pstate *sregs);
- int (*check_interrupts) (struct pstate *sregs);
- void (*disas) (uint32 addr);
- int (*gdb_get_reg) (char *buf);
- void (*set_register) (struct pstate *sregs, char *reg, uint32 rval, uint32 addr);
- void (*display_registers) (struct pstate *sregs);
- void (*display_ctrl) ( struct pstate *sregs);
- void (*display_special) (struct pstate *sregs);
- void (*display_fpu) ( struct pstate *sregs);
+struct cpu_arch
+{
+ int endian;
+ int (*dispatch_instruction) (struct pstate * sregs);
+ int (*execute_trap) (struct pstate * sregs);
+ int (*check_interrupts) (struct pstate * sregs);
+ void (*disas) (uint32 addr);
+ int (*gdb_get_reg) (char *buf);
+ void (*set_register) (struct pstate * sregs, char *reg, uint32 rval,
+ uint32 addr);
+ void (*display_registers) (struct pstate * sregs);
+ void (*display_ctrl) (struct pstate * sregs);
+ void (*display_special) (struct pstate * sregs);
+ void (*display_fpu) (struct pstate * sregs);
};
-struct estate {
- struct evcell eq;
- struct evcell *freeq;
- uint64 simtime; /* timestamp of last access to event queue */
- uint64 evtime; /* timestamp of next event */
- float32 freq; /* Simulated processor frequency */
- double starttime;
- double tottime;
- uint64 simstart;
- uint64 tlimit; /* Simulation time limit */
- uint32 bptnum;
- uint32 bpts[BPT_MAX]; /* Breakpoints */
- uint32 bpsave[BPT_MAX]; /* Saved opcode */
- uint32 wprnum;
- uint32 wphit;
- uint32 wprs[WPR_MAX]; /* Read Watchpoints */
- unsigned char wprm[WPR_MAX]; /* Read Watchpoint masks*/
- uint32 wpwnum;
- uint32 wpws[WPW_MAX]; /* Write Watchpoints */
- unsigned char wpwm[WPW_MAX]; /* Write Watchpoint masks */
- uint32 wpaddress;
- uint32 histlen;
- uint32 coven; /* coverage enable */
- uint32 ramstart; /* start of RAM */
- uint32 bpcpu; /* cpu that hit breakpoint */
- uint32 bend; /* cpu big endian */
- uint32 cpu; /* cpu typefrom elf file */
+struct estate
+{
+ struct evcell eq;
+ struct evcell *freeq;
+ uint64 simtime; /* timestamp of last access to event queue */
+ uint64 evtime; /* timestamp of next event */
+ float32 freq; /* Simulated processor frequency */
+ double starttime;
+ double tottime;
+ uint64 simstart;
+ uint64 tlimit; /* Simulation time limit */
+ uint32 bptnum;
+ uint32 bpts[BPT_MAX]; /* Breakpoints */
+ uint32 bpsave[BPT_MAX]; /* Saved opcode */
+ uint32 wprnum;
+ uint32 wphit;
+ uint32 wprs[WPR_MAX]; /* Read Watchpoints */
+ unsigned char wprm[WPR_MAX]; /* Read Watchpoint masks */
+ uint32 wpwnum;
+ uint32 wpws[WPW_MAX]; /* Write Watchpoints */
+ unsigned char wpwm[WPW_MAX]; /* Write Watchpoint masks */
+ uint32 wpaddress;
+ uint32 histlen;
+ uint32 coven; /* coverage enable */
+ uint32 ramstart; /* start of RAM */
+ uint32 bpcpu; /* cpu that hit breakpoint */
+ uint32 bend; /* cpu big endian */
+ uint32 cpu; /* cpu typefrom elf file */
};
extern const struct cpu_arch *arch;
@@ -248,103 +254,103 @@ extern const struct memsys erc32sys;
/* func.c */
extern char romb[];
extern char ramb[];
-extern struct pstate sregs[];
-extern struct estate ebase;
-extern struct evcell evbuf[];
-extern int nfp;
-extern int ift;
-extern int ctrl_c;
-extern int sis_verbose;
-extern char *sis_version;
-extern uint32 last_load_addr;
-extern int wrp;
-extern int rom8;
-extern int uben;
-extern int irqpend;
-extern int ext_irl[];
-extern int termsave;
-extern char uart_dev1[];
-extern char uart_dev2[];
-extern void set_regi (struct pstate *sregs, int32 reg,
- uint32 rval);
-extern void get_regi (struct pstate *sregs, int32 reg, char *buf, int length);
-extern int exec_cmd (const char *cmd);
-extern void reset_stat (struct pstate *sregs);
-extern void show_stat (struct pstate *sregs);
-extern void init_bpt (struct pstate *sregs);
-extern void init_signals (void);
-
-void print_insn_sis(uint32 addr);
-extern uint32 dis_mem (uint32 addr, uint32 len);
-extern void event (void (*cfunc) (), int32 arg, uint64 delta);
-extern uint32 now (void);
-extern int check_bpt (struct pstate *sregs);
-extern int check_wpr(struct pstate *sregs, int32 address, unsigned char mask);
-extern int check_wpw(struct pstate *sregs, int32 address, unsigned char mask);
-
-extern void reset_all (void);
-extern void sys_reset (void);
-extern void sys_halt (void);
-extern int elf_load (char *fname, int readsym);
-extern double get_time (void);
-extern int nouartrx;
-//extern host_callback *sim_callback;
-extern int dumbio;
-extern int tty_setup;
-extern int cputype;
-extern int sis_gdb_break;
-extern int cpu; /* active debug cpu */
-extern int ncpu; /* number of online cpus */
-extern int delta; /* time slice for MP simulation */
-extern void pwd_enter(struct pstate *sregs);
-extern void remove_event(void (*cfunc) (), int32 arg);
-extern int run_sim (uint64 icount, int dis);
-void flush_windows (struct pstate *sregs);
-void cov_start(int address);
-void cov_exec(int address);
-void cov_bt(int address1, int address2);
-void cov_bnt(int address);
-void cov_jmp(int address1, int address2);
-void cov_save(char *name);
-extern int port;
-extern int sim_run;
-extern void int_handler(int sig);
-extern uint32 daddr;
-extern void l1data_update(uint32 address, uint32 cpu);
-extern void l1data_snoop(uint32 address, uint32 cpu);
+extern struct pstate sregs[];
+extern struct estate ebase;
+extern struct evcell evbuf[];
+extern int nfp;
+extern int ift;
+extern int ctrl_c;
+extern int sis_verbose;
+extern char *sis_version;
+extern uint32 last_load_addr;
+extern int wrp;
+extern int rom8;
+extern int uben;
+extern int irqpend;
+extern int ext_irl[];
+extern int termsave;
+extern char uart_dev1[];
+extern char uart_dev2[];
+extern void set_regi (struct pstate *sregs, int32 reg, uint32 rval);
+extern void get_regi (struct pstate *sregs, int32 reg, char *buf, int length);
+extern int exec_cmd (const char *cmd);
+extern void reset_stat (struct pstate *sregs);
+extern void show_stat (struct pstate *sregs);
+extern void init_bpt (struct pstate *sregs);
+extern void init_signals (void);
+
+void print_insn_sis (uint32 addr);
+extern uint32 dis_mem (uint32 addr, uint32 len);
+extern void event (void (*cfunc) (), int32 arg, uint64 delta);
+extern uint32 now (void);
+extern int check_bpt (struct pstate *sregs);
+extern int check_wpr (struct pstate *sregs, int32 address,
+ unsigned char mask);
+extern int check_wpw (struct pstate *sregs, int32 address,
+ unsigned char mask);
+
+extern void reset_all (void);
+extern void sys_reset (void);
+extern void sys_halt (void);
+extern int elf_load (char *fname, int readsym);
+extern double get_time (void);
+extern int nouartrx;
+//extern host_callback *sim_callback;
+extern int dumbio;
+extern int tty_setup;
+extern int cputype;
+extern int sis_gdb_break;
+extern int cpu; /* active debug cpu */
+extern int ncpu; /* number of online cpus */
+extern int delta; /* time slice for MP simulation */
+extern void pwd_enter (struct pstate *sregs);
+extern void remove_event (void (*cfunc) (), int32 arg);
+extern int run_sim (uint64 icount, int dis);
+void flush_windows (struct pstate *sregs);
+void cov_start (int address);
+void cov_exec (int address);
+void cov_bt (int address1, int address2);
+void cov_bnt (int address);
+void cov_jmp (int address1, int address2);
+void cov_save (char *name);
+extern int port;
+extern int sim_run;
+extern void int_handler (int sig);
+extern uint32 daddr;
+extern void l1data_update (uint32 address, uint32 cpu);
+extern void l1data_snoop (uint32 address, uint32 cpu);
/* exec.c */
-extern void init_regs (struct pstate *sregs);
-extern void mul64 (uint32 n1, uint32 n2, uint32 *result_hi,
- uint32 *result_lo, int msigned);
-extern void div64 (uint32 n1_hi, uint32 n1_low, uint32 n2,
- uint32 *result, int msigned);
+extern void init_regs (struct pstate *sregs);
+extern void mul64 (uint32 n1, uint32 n2, uint32 * result_hi,
+ uint32 * result_lo, int msigned);
+extern void div64 (uint32 n1_hi, uint32 n1_low, uint32 n2,
+ uint32 * result, int msigned);
/* float.c */
-extern int get_accex (void);
-extern void clear_accex (void);
-extern void set_fsr (uint32 fsr);
+extern int get_accex (void);
+extern void clear_accex (void);
+extern void set_fsr (uint32 fsr);
/* help.c */
-extern void sis_usage (void);
-extern void gen_help (void);
-
-struct memsys {
- void (*init_sim) (void);
- void (*reset) (void);
- void (*error_mode) (uint32 pc);
- void (*sim_halt) (void);
- void (*exit_sim) (void);
- void (*init_stdio) (void);
- void (*restore_stdio) (void);
- int (*memory_iread) (uint32 addr, uint32 *data, int32 *ws);
- int (*memory_read) (uint32 addr, uint32 *data, int32 *ws);
- int (*memory_write) (uint32 addr, uint32 *data, int32 sz, int32 *ws);
- int (*sis_memory_write) (uint32 addr,
- const char *data, uint32 length);
- int (*sis_memory_read) (uint32 addr, char *data,
- uint32 length);
- void (*boot_init) (void);
+extern void sis_usage (void);
+extern void gen_help (void);
+
+struct memsys
+{
+ void (*init_sim) (void);
+ void (*reset) (void);
+ void (*error_mode) (uint32 pc);
+ void (*sim_halt) (void);
+ void (*exit_sim) (void);
+ void (*init_stdio) (void);
+ void (*restore_stdio) (void);
+ int (*memory_iread) (uint32 addr, uint32 * data, int32 * ws);
+ int (*memory_read) (uint32 addr, uint32 * data, int32 * ws);
+ int (*memory_write) (uint32 addr, uint32 * data, int32 sz, int32 * ws);
+ int (*sis_memory_write) (uint32 addr, const char *data, uint32 length);
+ int (*sis_memory_read) (uint32 addr, char *data, uint32 length);
+ void (*boot_init) (void);
};
extern const struct memsys *ms;
@@ -357,18 +363,18 @@ extern const struct memsys leon3;
/* remote.c */
-extern void gdb_remote (int port);
-extern int simstat;
-extern int new_socket;
+extern void gdb_remote (int port);
+extern int simstat;
+extern int new_socket;
/* interf.c */
-extern int sim_read (uint32 mem, char *buf, int length);
-extern int sim_write (uint32 mem, const char *buf, int length);
-extern void sim_create_inferior();
-extern void sim_resume(int step);
-extern int sim_insert_swbreakpoint(uint32 addr, int len);
-extern int sim_remove_swbreakpoint(uint32 addr, int len);
+extern int sim_read (uint32 mem, char *buf, int length);
+extern int sim_write (uint32 mem, const char *buf, int length);
+extern void sim_create_inferior ();
+extern void sim_resume (int step);
+extern int sim_insert_swbreakpoint (uint32 addr, int len);
+extern int sim_remove_swbreakpoint (uint32 addr, int len);
/* FPU timing based on Meiko */
@@ -393,4 +399,3 @@ extern int sim_remove_swbreakpoint(uint32 addr, int len);
#define T_FiTOd 6
#define T_FsTOi 6
#define T_FsTOd 2
-
diff --git a/sparc.c b/sparc.c
index 0daed96..8b49831 100644
--- a/sparc.c
+++ b/sparc.c
@@ -528,7 +528,7 @@ sparc_dispatch_instruction (sregs)
case SMUL:
{
mul64 (rs1, operand2, &sregs->y, rdd, 1);
- sregs->icnt = T_MUL;
+ sregs->icnt = T_MUL;
}
break;
case SMULCC:
@@ -548,13 +548,13 @@ sparc_dispatch_instruction (sregs)
sregs->psr &= ~PSR_Z;
*rdd = result;
- sregs->icnt = T_MUL;
+ sregs->icnt = T_MUL;
}
break;
case UMUL:
{
mul64 (rs1, operand2, &sregs->y, rdd, 0);
- sregs->icnt = T_MUL;
+ sregs->icnt = T_MUL;
}
break;
case UMULCC:
@@ -574,7 +574,7 @@ sparc_dispatch_instruction (sregs)
sregs->psr &= ~PSR_Z;
*rdd = result;
- sregs->icnt = T_MUL;
+ sregs->icnt = T_MUL;
}
break;
case SDIV:
@@ -586,7 +586,7 @@ sparc_dispatch_instruction (sregs)
}
div64 (sregs->y, rs1, operand2, rdd, 1);
- sregs->icnt = T_DIV;
+ sregs->icnt = T_DIV;
}
break;
case SDIVCC:
@@ -615,7 +615,7 @@ sparc_dispatch_instruction (sregs)
sregs->psr &= ~(PSR_C | PSR_V);
*rdd = result;
- sregs->icnt = T_DIV;
+ sregs->icnt = T_DIV;
}
break;
case UDIV:
@@ -627,7 +627,7 @@ sparc_dispatch_instruction (sregs)
}
div64 (sregs->y, rs1, operand2, rdd, 0);
- sregs->icnt = T_DIV;
+ sregs->icnt = T_DIV;
}
break;
case UDIVCC:
@@ -656,7 +656,7 @@ sparc_dispatch_instruction (sregs)
sregs->psr &= ~(PSR_C | PSR_V);
*rdd = result;
- sregs->icnt = T_DIV;
+ sregs->icnt = T_DIV;
}
break;
case IXNOR:
@@ -1402,7 +1402,8 @@ sparc_dispatch_instruction (sregs)
#ifdef HOST_LITTLE_ENDIAN
rd ^= 1;
#endif
- mexc = ms->memory_write (address, &sregs->fsi[rd], 2, &ws);
+ mexc =
+ ms->memory_write (address, (uint32 *) & sregs->fsi[rd], 2, &ws);
sregs->hold += ws;
if (mexc)
{
@@ -1527,14 +1528,14 @@ sparc_dispatch_instruction (sregs)
}
#endif
#ifdef ENABLE_L1CACHE
- if (ncpu > 1)
+ if (ncpu > 1)
{
- l1data_update(address, sregs->cpu);
- if (op3 & 4)
- {
- l1data_snoop(address, sregs->cpu);
- }
- }
+ l1data_update (address, sregs->cpu);
+ if (op3 & 4)
+ {
+ l1data_snoop (address, sregs->cpu);
+ }
+ }
#endif
break;
@@ -1968,11 +1969,11 @@ sparc_disp_regs (struct pstate *sregs, int cwp)
static void
sparc_display_registers (struct pstate *sregs)
{
- sparc_disp_regs(sregs, sregs->psr);
+ sparc_disp_regs (sregs, sregs->psr);
}
static void
-sparc_display_ctrl ( struct pstate *sregs)
+sparc_display_ctrl (struct pstate *sregs)
{
uint32 i;
@@ -2224,9 +2225,9 @@ static void
sparc_set_register (struct pstate *sregs, char *reg, uint32 rval, uint32 addr)
{
if (reg == NULL)
- sparc_set_regi(sregs, addr, rval);
+ sparc_set_regi (sregs, addr, rval);
else
- sparc_set_rega(sregs, reg, rval);
+ sparc_set_rega (sregs, reg, rval);
}
static void
@@ -2603,11 +2604,13 @@ regres (char *st, struct insn_type insn, int hex)
static char brtbl[16][4] =
{ "n", "e", "le", "l", "lue", "cs", "neg", "vs", "a", "ne", "g", "ge", "gu",
-"cc", "pos", "vc" };
+ "cc", "pos", "vc"
+};
static char fbrtbl[16][4] =
{ "n", "ne", "lg", "ul", "l", "ug", "g", "u", "a", "e", "ue", "ge", "uge",
-"le", "ule", "o" };
+ "le", "ule", "o"
+};
char *
branchop (int insn)
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-26 23:30:11 +0000