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authorDaniel Hellstrom <daniel@gaisler.com>2013-03-18 08:29:39 +0100
committerDaniel Hellstrom <daniel@gaisler.com>2013-03-18 08:29:39 +0100
commit944f85f0e00877ca946efda9cd1767c4ce2c449b (patch)
tree179f7d495c6b9c4535839eb4a13da8af5010980b /c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c
parentbdd4c4e15efb54958ca5b0eeb27f7b58a63ca177 (diff)
PCI-RASTA: set GRPCI1 target cache-line-size to avoid poor performancercc-v1.2.8
Diffstat (limited to 'c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c')
-rw-r--r--c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c
index f0716ab3c9..163ccfb98c 100644
--- a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c
+++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c
@@ -247,6 +247,12 @@ int gr_rasta_adcdac_hw_init1(struct gr_rasta_adcdac_priv *priv)
pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data);
pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY));
+ /* Setup cache line size. Default cache line size will result in
+ * poor performance (256 word fetches), 0xff will set it according
+ * to the max size of the PCI FIFO.
+ */
+ pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff);
+
/* Scan AMBA Plug&Play */
/* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */