diff options
| author | Daniel Hellstrom <daniel@gaisler.com> | 2013-03-18 08:29:39 +0100 |
|---|---|---|
| committer | Daniel Hellstrom <daniel@gaisler.com> | 2013-03-18 08:29:39 +0100 |
| commit | 944f85f0e00877ca946efda9cd1767c4ce2c449b (patch) | |
| tree | 179f7d495c6b9c4535839eb4a13da8af5010980b | |
| parent | bdd4c4e15efb54958ca5b0eeb27f7b58a63ca177 (diff) | |
PCI-RASTA: set GRPCI1 target cache-line-size to avoid poor performancercc-v1.2.8
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c | 6 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c | 6 | ||||
| -rw-r--r-- | c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c | 6 |
3 files changed, 18 insertions, 0 deletions
diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c index f0716ab3c9..163ccfb98c 100644 --- a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c +++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_adcdac.c @@ -247,6 +247,12 @@ int gr_rasta_adcdac_hw_init1(struct gr_rasta_adcdac_priv *priv) pci_cfg_r32(priv->pcidev, PCI_COMMAND, &data); pci_cfg_w32(priv->pcidev, PCI_COMMAND, (data|PCI_COMMAND_PARITY)); + /* Setup cache line size. Default cache line size will result in + * poor performance (256 word fetches), 0xff will set it according + * to the max size of the PCI FIFO. + */ + pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff); + /* Scan AMBA Plug&Play */ /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c index 42e7397d65..071636ba45 100644 --- a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c +++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_io.c @@ -264,6 +264,12 @@ int gr_rasta_io_hw_init(struct gr_rasta_io_priv *priv) } #endif + /* Setup cache line size. Default cache line size will result in + * poor performance (256 word fetches), 0xff will set it according + * to the max size of the PCI FIFO. + */ + pci_cfg_w8(priv->pcidev, PCI_CACHE_LINE_SIZE, 0xff); + /* Scan AMBA Plug&Play */ /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ diff --git a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c index 671bcf6d83..8e31b65f0e 100644 --- a/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c +++ b/c/src/lib/libbsp/sparc/shared/pci/gr_rasta_tmtc.c @@ -254,6 +254,12 @@ int gr_rasta_tmtc_hw_init(struct gr_rasta_tmtc_priv *priv) } #endif + /* Setup cache line size. Default cache line size will result in + * poor performance (256 word fetches), 0xff will set it according + * to the max size of the PCI FIFO. + */ + pci_cfg_w8(pcidev, PCI_CACHE_LINE_SIZE, 0xff); + /* Scan AMBA Plug&Play */ /* AMBA MAP bar0 (in CPU) ==> 0x80000000(remote amba address) */ |