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/**
* @file
*
* @ingroup ScoreCPU
*
* @brief RISC-V exception support implementation.
*/
/*
* Copyright (c) 2018 embedded brains GmbH
* Copyright (c) 2015 University of York.
* Hesham Almatary <hesham@alumni.york.ac.uk>
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <rtems/asm.h>
#include <rtems/score/percpu.h>
EXTERN(bsp_start_vector_table_begin)
EXTERN(_Thread_Dispatch)
PUBLIC(ISR_Handler)
.section .text, "ax", @progbits
.align 2
TYPE_FUNC(ISR_Handler)
SYM(ISR_Handler):
addi sp, sp, -CPU_INTERRUPT_FRAME_SIZE
/* Save */
SREG a0, RISCV_INTERRUPT_FRAME_A0(sp)
SREG a1, RISCV_INTERRUPT_FRAME_A1(sp)
SREG a2, RISCV_INTERRUPT_FRAME_A2(sp)
SREG s0, RISCV_INTERRUPT_FRAME_S0(sp)
csrr a0, mcause
csrr a1, mstatus
csrr a2, mepc
GET_SELF_CPU_CONTROL s0
SREG s1, RISCV_INTERRUPT_FRAME_S1(sp)
SREG ra, RISCV_INTERRUPT_FRAME_RA(sp)
SREG a3, RISCV_INTERRUPT_FRAME_A3(sp)
SREG a4, RISCV_INTERRUPT_FRAME_A4(sp)
SREG a5, RISCV_INTERRUPT_FRAME_A5(sp)
SREG a6, RISCV_INTERRUPT_FRAME_A6(sp)
SREG a7, RISCV_INTERRUPT_FRAME_A7(sp)
SREG t0, RISCV_INTERRUPT_FRAME_T0(sp)
SREG t1, RISCV_INTERRUPT_FRAME_T1(sp)
SREG t2, RISCV_INTERRUPT_FRAME_T2(sp)
SREG t3, RISCV_INTERRUPT_FRAME_T3(sp)
SREG t4, RISCV_INTERRUPT_FRAME_T4(sp)
SREG t5, RISCV_INTERRUPT_FRAME_T5(sp)
SREG t6, RISCV_INTERRUPT_FRAME_T6(sp)
SREG a1, RISCV_INTERRUPT_FRAME_MSTATUS(sp)
SREG a2, RISCV_INTERRUPT_FRAME_MEPC(sp)
/* FIXME Only handle interrupts for now (MSB = 1) */
andi a0, a0, 0xf
/* Increment interrupt nest and thread dispatch disable level */
lw t0, PER_CPU_ISR_NEST_LEVEL(s0)
lw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
addi t2, t0, 1
addi t1, t1, 1
sw t2, PER_CPU_ISR_NEST_LEVEL(s0)
sw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
/* Keep sp (Exception frame address) in s1 */
mv s1, sp
/* Call the exception handler from vector table */
/* First function arg for C handler is vector number,
* and the second is a pointer to exception frame.
* a0/mcause/vector number is already loaded above */
mv a1, sp
/* calculate the offset */
la t5, bsp_start_vector_table_begin
#if __riscv_xlen == 32
slli t6, a0, 2
#else /* xlen = 64 */
slli t6, a0, 3
#endif
add t5, t5, t6
LREG t5, (t5)
/* Switch to interrupt stack if necessary */
bnez t0, .Linterrupt_stack_switch_done
LREG sp, PER_CPU_INTERRUPT_STACK_HIGH(s0)
.Linterrupt_stack_switch_done:
jalr t5
/* Load some per-CPU variables */
lw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
lbu t1, PER_CPU_DISPATCH_NEEDED(s0)
lw t2, PER_CPU_ISR_DISPATCH_DISABLE(s0)
lw t3, PER_CPU_ISR_NEST_LEVEL(s0)
/* Restore stack pointer */
mv sp, s1
/* Decrement levels and determine thread dispatch state */
xor t1, t1, t0
addi t0, t0, -1
or t1, t1, t0
or t1, t1, t2
addi t3, t3, -1
/* Store thread dispatch disable and ISR nest levels */
sw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
sw t3, PER_CPU_ISR_NEST_LEVEL(s0)
/*
* Check thread dispatch necessary, ISR dispatch disable and thread
* dispatch disable level.
*/
bnez t1, .Lthread_dispatch_done
.Ldo_thread_dispatch:
/* Set ISR dispatch disable and thread dispatch disable level to one */
li t0, 1
sw t0, PER_CPU_ISR_DISPATCH_DISABLE(s0)
sw t0, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0)
/* Call _Thread_Do_dispatch(), this function will enable interrupts */
mv a0, s0
li a1, RISCV_MSTATUS_MIE
call _Thread_Do_dispatch
/* Disable interrupts */
csrrc zero, mstatus, RISCV_MSTATUS_MIE
#ifdef RTEMS_SMP
GET_SELF_CPU_CONTROL s0
#endif
/* Check if we have to do the thread dispatch again */
lbu t0, PER_CPU_DISPATCH_NEEDED(s0)
bnez t0, .Ldo_thread_dispatch
/* We are done with thread dispatching */
sw zero, PER_CPU_ISR_DISPATCH_DISABLE(s0)
.Lthread_dispatch_done:
/* Restore */
LREG a0, RISCV_INTERRUPT_FRAME_MSTATUS(sp)
LREG a1, RISCV_INTERRUPT_FRAME_MEPC(sp)
LREG a2, RISCV_INTERRUPT_FRAME_A2(sp)
LREG s0, RISCV_INTERRUPT_FRAME_S0(sp)
LREG s1, RISCV_INTERRUPT_FRAME_S1(sp)
LREG ra, RISCV_INTERRUPT_FRAME_RA(sp)
LREG a3, RISCV_INTERRUPT_FRAME_A3(sp)
LREG a4, RISCV_INTERRUPT_FRAME_A4(sp)
LREG a5, RISCV_INTERRUPT_FRAME_A5(sp)
LREG a6, RISCV_INTERRUPT_FRAME_A6(sp)
LREG a7, RISCV_INTERRUPT_FRAME_A7(sp)
LREG t0, RISCV_INTERRUPT_FRAME_T0(sp)
LREG t1, RISCV_INTERRUPT_FRAME_T1(sp)
LREG t2, RISCV_INTERRUPT_FRAME_T2(sp)
LREG t3, RISCV_INTERRUPT_FRAME_T3(sp)
LREG t4, RISCV_INTERRUPT_FRAME_T4(sp)
LREG t5, RISCV_INTERRUPT_FRAME_T5(sp)
LREG t6, RISCV_INTERRUPT_FRAME_T6(sp)
csrw mstatus, a0
csrw mepc, a1
LREG a0, RISCV_INTERRUPT_FRAME_A0(sp)
LREG a1, RISCV_INTERRUPT_FRAME_A1(sp)
addi sp, sp, CPU_INTERRUPT_FRAME_SIZE
mret
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