diff options
Diffstat (limited to 'cpukit/score/cpu/riscv/riscv-exception-handler.S')
| -rw-r--r-- | cpukit/score/cpu/riscv/riscv-exception-handler.S | 140 |
1 files changed, 51 insertions, 89 deletions
diff --git a/cpukit/score/cpu/riscv/riscv-exception-handler.S b/cpukit/score/cpu/riscv/riscv-exception-handler.S index cc47bbb7c1..844d417738 100644 --- a/cpukit/score/cpu/riscv/riscv-exception-handler.S +++ b/cpukit/score/cpu/riscv/riscv-exception-handler.S @@ -50,54 +50,37 @@ PUBLIC(ISR_Handler) TYPE_FUNC(ISR_Handler) SYM(ISR_Handler): - addi sp, sp, -1 * 36 * CPU_SIZEOF_POINTER - - SREG x1, (1 * CPU_SIZEOF_POINTER)(sp) - /* Skip x2/sp */ - SREG x3, (3 * CPU_SIZEOF_POINTER)(sp) - SREG x4, (4 * CPU_SIZEOF_POINTER)(sp) - SREG x5, (5 * CPU_SIZEOF_POINTER)(sp) - SREG x6, (6 * CPU_SIZEOF_POINTER)(sp) - SREG x7, (7 * CPU_SIZEOF_POINTER)(sp) - SREG x8, (8 * CPU_SIZEOF_POINTER)(sp) - SREG x9, (9 * CPU_SIZEOF_POINTER)(sp) - SREG x10, (10 * CPU_SIZEOF_POINTER)(sp) - SREG x11, (11 * CPU_SIZEOF_POINTER)(sp) - SREG x12, (12 * CPU_SIZEOF_POINTER)(sp) - SREG x13, (13 * CPU_SIZEOF_POINTER)(sp) - SREG x14, (14 * CPU_SIZEOF_POINTER)(sp) - SREG x15, (15 * CPU_SIZEOF_POINTER)(sp) - SREG x16, (16 * CPU_SIZEOF_POINTER)(sp) - SREG x17, (17 * CPU_SIZEOF_POINTER)(sp) - SREG x18, (18 * CPU_SIZEOF_POINTER)(sp) - SREG x19, (19 * CPU_SIZEOF_POINTER)(sp) - SREG x20, (20 * CPU_SIZEOF_POINTER)(sp) - SREG x21, (21 * CPU_SIZEOF_POINTER)(sp) - SREG x22, (22 * CPU_SIZEOF_POINTER)(sp) - SREG x23, (23 * CPU_SIZEOF_POINTER)(sp) - SREG x24, (24 * CPU_SIZEOF_POINTER)(sp) - SREG x25, (25 * CPU_SIZEOF_POINTER)(sp) - SREG x26, (26 * CPU_SIZEOF_POINTER)(sp) - SREG x27, (27 * CPU_SIZEOF_POINTER)(sp) - SREG x28, (28 * CPU_SIZEOF_POINTER)(sp) - SREG x29, (29 * CPU_SIZEOF_POINTER)(sp) - SREG x30, (30 * CPU_SIZEOF_POINTER)(sp) - SREG x31, (31 * CPU_SIZEOF_POINTER)(sp) - - /* Exception level related registers */ - csrr a0, mstatus - SREG a0, (32 * CPU_SIZEOF_POINTER)(sp) + addi sp, sp, -CPU_INTERRUPT_FRAME_SIZE + + /* Save */ + SREG a0, RISCV_INTERRUPT_FRAME_A0(sp) + SREG a1, RISCV_INTERRUPT_FRAME_A1(sp) + SREG a2, RISCV_INTERRUPT_FRAME_A2(sp) + SREG s0, RISCV_INTERRUPT_FRAME_S0(sp) csrr a0, mcause - SREG a0, (33 * CPU_SIZEOF_POINTER)(sp) - csrr a1, mepc - SREG a1, (34 * CPU_SIZEOF_POINTER)(sp) + csrr a1, mstatus + csrr a2, mepc + GET_SELF_CPU_CONTROL s0 + SREG s1, RISCV_INTERRUPT_FRAME_S1(sp) + SREG ra, RISCV_INTERRUPT_FRAME_RA(sp) + SREG a3, RISCV_INTERRUPT_FRAME_A3(sp) + SREG a4, RISCV_INTERRUPT_FRAME_A4(sp) + SREG a5, RISCV_INTERRUPT_FRAME_A5(sp) + SREG a6, RISCV_INTERRUPT_FRAME_A6(sp) + SREG a7, RISCV_INTERRUPT_FRAME_A7(sp) + SREG t0, RISCV_INTERRUPT_FRAME_T0(sp) + SREG t1, RISCV_INTERRUPT_FRAME_T1(sp) + SREG t2, RISCV_INTERRUPT_FRAME_T2(sp) + SREG t3, RISCV_INTERRUPT_FRAME_T3(sp) + SREG t4, RISCV_INTERRUPT_FRAME_T4(sp) + SREG t5, RISCV_INTERRUPT_FRAME_T5(sp) + SREG t6, RISCV_INTERRUPT_FRAME_T6(sp) + SREG a1, RISCV_INTERRUPT_FRAME_MSTATUS(sp) + SREG a2, RISCV_INTERRUPT_FRAME_MEPC(sp) /* FIXME Only handle interrupts for now (MSB = 1) */ andi a0, a0, 0xf - /* Get per-CPU control of current processor */ - GET_SELF_CPU_CONTROL s0 - /* Increment interrupt nest and thread dispatch disable level */ lw t0, PER_CPU_ISR_NEST_LEVEL(s0) lw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) @@ -106,10 +89,6 @@ SYM(ISR_Handler): sw t2, PER_CPU_ISR_NEST_LEVEL(s0) sw t1, PER_CPU_THREAD_DISPATCH_DISABLE_LEVEL(s0) - /* Save interrupted task stack pointer */ - addi t4, sp, 36 * CPU_SIZEOF_POINTER - SREG t4, (2 * CPU_SIZEOF_POINTER)(sp) - /* Keep sp (Exception frame address) in s1 */ mv s1, sp @@ -191,47 +170,30 @@ SYM(ISR_Handler): .Lthread_dispatch_done: - LREG x1, (1 * CPU_SIZEOF_POINTER)(sp) - /* Skip sp/x2 */ - LREG x3, (3 * CPU_SIZEOF_POINTER)(sp) - LREG x4, (4 * CPU_SIZEOF_POINTER)(sp) - LREG x5, (5 * CPU_SIZEOF_POINTER)(sp) - LREG x6, (6 * CPU_SIZEOF_POINTER)(sp) - LREG x7, (7 * CPU_SIZEOF_POINTER)(sp) - LREG x8, (8 * CPU_SIZEOF_POINTER)(sp) - LREG x9, (9 * CPU_SIZEOF_POINTER)(sp) - LREG x10, (10 * CPU_SIZEOF_POINTER)(sp) - LREG x11, (11 * CPU_SIZEOF_POINTER)(sp) - LREG x12, (12 * CPU_SIZEOF_POINTER)(sp) - LREG x13, (13 * CPU_SIZEOF_POINTER)(sp) - LREG x14, (14 * CPU_SIZEOF_POINTER)(sp) - LREG x15, (15 * CPU_SIZEOF_POINTER)(sp) - LREG x16, (16 * CPU_SIZEOF_POINTER)(sp) - LREG x17, (17 * CPU_SIZEOF_POINTER)(sp) - LREG x18, (18 * CPU_SIZEOF_POINTER)(sp) - LREG x19, (19 * CPU_SIZEOF_POINTER)(sp) - LREG x20, (20 * CPU_SIZEOF_POINTER)(sp) - LREG x21, (21 * CPU_SIZEOF_POINTER)(sp) - LREG x22, (22 * CPU_SIZEOF_POINTER)(sp) - LREG x23, (23 * CPU_SIZEOF_POINTER)(sp) - LREG x24, (24 * CPU_SIZEOF_POINTER)(sp) - LREG x25, (25 * CPU_SIZEOF_POINTER)(sp) - LREG x26, (26 * CPU_SIZEOF_POINTER)(sp) - LREG x27, (27 * CPU_SIZEOF_POINTER)(sp) - LREG x28, (28 * CPU_SIZEOF_POINTER)(sp) - LREG x29, (29 * CPU_SIZEOF_POINTER)(sp) - LREG x30, (30 * CPU_SIZEOF_POINTER)(sp) - - /* Load mstatus */ - LREG x31, (32 * CPU_SIZEOF_POINTER)(sp) - csrw mstatus, x31 - /* Load mepc */ - LREG x31, (34 * CPU_SIZEOF_POINTER)(sp) - csrw mepc, x31 - - LREG x31, (31 * CPU_SIZEOF_POINTER)(sp) - - /* Unwind exception frame */ - addi sp, sp, 36 * CPU_SIZEOF_POINTER + /* Restore */ + LREG a0, RISCV_INTERRUPT_FRAME_MSTATUS(sp) + LREG a1, RISCV_INTERRUPT_FRAME_MEPC(sp) + LREG a2, RISCV_INTERRUPT_FRAME_A2(sp) + LREG s0, RISCV_INTERRUPT_FRAME_S0(sp) + LREG s1, RISCV_INTERRUPT_FRAME_S1(sp) + LREG ra, RISCV_INTERRUPT_FRAME_RA(sp) + LREG a3, RISCV_INTERRUPT_FRAME_A3(sp) + LREG a4, RISCV_INTERRUPT_FRAME_A4(sp) + LREG a5, RISCV_INTERRUPT_FRAME_A5(sp) + LREG a6, RISCV_INTERRUPT_FRAME_A6(sp) + LREG a7, RISCV_INTERRUPT_FRAME_A7(sp) + LREG t0, RISCV_INTERRUPT_FRAME_T0(sp) + LREG t1, RISCV_INTERRUPT_FRAME_T1(sp) + LREG t2, RISCV_INTERRUPT_FRAME_T2(sp) + LREG t3, RISCV_INTERRUPT_FRAME_T3(sp) + LREG t4, RISCV_INTERRUPT_FRAME_T4(sp) + LREG t5, RISCV_INTERRUPT_FRAME_T5(sp) + LREG t6, RISCV_INTERRUPT_FRAME_T6(sp) + csrw mstatus, a0 + csrw mepc, a1 + LREG a0, RISCV_INTERRUPT_FRAME_A0(sp) + LREG a1, RISCV_INTERRUPT_FRAME_A1(sp) + + addi sp, sp, CPU_INTERRUPT_FRAME_SIZE mret |