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The embedded brains GmbH & Co. KG is the legal successor of embedded
brains GmbH.
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In SMP configurations, check that we run on a configured processor. If not,
then there is not much that can be done since we do not have a stack available
for this processor. Just loop forever in this case. Do this in assemlby to
ensure that no stack memory is used.
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Maybe this helps to ensure that the object is properly aligned.
Update #4658.
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Disable the linker relaxation in start.S to work around an issue described
here:
https://mail.gnu.org/archive/html/bug-binutils/2021-03/msg00164.html
The real issue is probably in the linker command file or the linker itself.
Update #4658.
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The Microchip PolarFire SoC support is implemented as a
riscv BSP variant to boot with any individual hart(cpu core)
or SMP based on the boot HARTID configurable and support
components are 4 CPU Cores (U54), Interrupt controller (PLIC),
Timer (CLINT), UART.
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This is required for ISA 2.0 support, see chapter
"Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
in
RISC-V Instruction Set Manual, Volume I: RISC-V User-Level ISA
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Use a far jump to avoid errors like this:
relocation truncated to fit: R_RISCV_JAL against symbol `boot_card'
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Update #3678.
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