diff options
| -rw-r--r-- | cpukit/score/cpu/riscv/include/rtems/score/cpu.h | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h index 28760f33f6..b2b8d7bf09 100644 --- a/cpukit/score/cpu/riscv/include/rtems/score/cpu.h +++ b/cpukit/score/cpu/riscv/include/rtems/score/cpu.h @@ -220,6 +220,45 @@ extern void _CPU_Fatal_halt(uint32_t source, uint32_t error) RTEMS_NO_RETURN; typedef uint16_t Priority_bit_map_Word; +/* + * See The RISC-V Instruction Set Manual, Volume II: RISC-V Privileged + * Architectures V1.10, Table 3.6: Machine cause register (mcause) values after + * trap. + */ +typedef enum { + RISCV_INTERRUPT_SOFTWARE_USER = 0, + RISCV_INTERRUPT_SOFTWARE_SUPERVISOR = 1, + RISCV_INTERRUPT_SOFTWARE_MACHINE = 3, + RISCV_INTERRUPT_TIMER_USER = 4, + RISCV_INTERRUPT_TIMER_SUPERVISOR = 5, + RISCV_INTERRUPT_TIMER_MACHINE = 7, + RISCV_INTERRUPT_EXTERNAL_USER = 8, + RISCV_INTERRUPT_EXTERNAL_SUPERVISOR = 9, + RISCV_INTERRUPT_EXTERNAL_MACHINE = 11 +} RISCV_Interrupt_code; + +/* + * See The RISC-V Instruction Set Manual, Volume II: RISC-V Privileged + * Architectures V1.10, Table 3.6: Machine cause register (mcause) values after + * trap. + */ +typedef enum { + RISCV_EXCEPTION_INSTRUCTION_ADDRESS_MISALIGNED = 0, + RISCV_EXCEPTION_INSTRUCTION_ACCESS_FAULT = 1, + RISCV_EXCEPTION_ILLEGAL_INSTRUCTION = 2, + RISCV_EXCEPTION_BREAKPOINT = 3, + RISCV_EXCEPTION_LOAD_ADDRESS_MISALIGNED = 4, + RISCV_EXCEPTION_LOAD_ACCESS_FAULT = 5, + RISCV_EXCEPTION_STORE_OR_AMO_ADDRESS_MISALIGNED = 6, + RISCV_EXCEPTION_STORE_OR_AMO_ACCESS_FAULT = 7, + RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_U_MODE = 8, + RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_S_MODE = 9, + RISCV_EXCEPTION_ENVIRONMENT_CALL_FROM_M_MODE = 11, + RISCV_EXCEPTION_INSTRUCTION_PAGE_FAULT = 12, + RISCV_EXCEPTION_LOAD_PAGE_FAULT = 13, + RISCV_EXCEPTION_STORE_OR_AMO_PAGE_FAULT = 15 +} RISCV_Exception_code; + typedef struct { unsigned long x[32];; } CPU_Exception_frame; |