Merge branch 'master' of ssh://git.rtems.org/data/git/rtems

author: Joel Sherrill <joel.sherrill@oarcorp.com> 2013-02-02 15:19:01 -0600
committer: Joel Sherrill <joel.sherrill@oarcorp.com> 2013-02-02 15:19:01 -0600
commit: dd7b83550dfb73f5ec1b7dec3b21d730779ddeb2 (patch)
tree: 3db0eac5b55ed5edcf985baed9f19736c931de47 /cpukit/score/cpu
parent: Merge branch 'master' of ssh://git.rtems.org/data/git/rtems (diff)
parent: fstests/fsrdwr: Free allocated memory (diff)
download: rtems-dd7b83550dfb73f5ec1b7dec3b21d730779ddeb2.tar.bz2
270 files changed, 14172 insertions, 11358 deletions
diff --git a/cpukit/score/cpu/arm/Makefile.am b/cpukit/score/cpu/arm/Makefile.am
index f0ddbd679b..56a5fdd465 100644
--- a/cpukit/score/cpu/arm/Makefile.am
+++ b/cpukit/score/cpu/arm/Makefile.am
@@ -6,6 +6,7 @@ include_rtems_scoredir = $(includedir)/rtems/score
 include_rtems_score_HEADERS = rtems/score/cpu.h
 include_rtems_score_HEADERS += rtems/score/cpu_asm.h
 include_rtems_score_HEADERS += rtems/score/arm.h
+include_rtems_score_HEADERS += rtems/score/armv4.h
 include_rtems_score_HEADERS += rtems/score/armv7m.h
 include_rtems_score_HEADERS += rtems/score/types.h
 
@@ -19,10 +20,12 @@ libscorecpu_a_SOURCES += arm_exc_interrupt.S
 libscorecpu_a_SOURCES += arm_exc_handler_low.S
 libscorecpu_a_SOURCES += arm_exc_handler_high.c
 libscorecpu_a_SOURCES += arm-exception-frame-print.c
+libscorecpu_a_SOURCES += arm-exception-default.c
+libscorecpu_a_SOURCES += armv4-exception-default.S
 libscorecpu_a_SOURCES += armv7m-context-initialize.c
 libscorecpu_a_SOURCES += armv7m-context-restore.c
 libscorecpu_a_SOURCES += armv7m-context-switch.c
-libscorecpu_a_SOURCES += armv7m-exception-frame-print.c
+libscorecpu_a_SOURCES += armv7m-exception-default.c
 libscorecpu_a_SOURCES += armv7m-exception-handler-get.c
 libscorecpu_a_SOURCES += armv7m-exception-handler-set.c
 libscorecpu_a_SOURCES += armv7m-exception-priority-get.c
diff --git a/cpukit/score/cpu/arm/armv7m-exception-frame-print.c b/cpukit/score/cpu/arm/arm-exception-default.c
index 86931b2b24..ec29f23431 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-frame-print.c
+++ b/cpukit/score/cpu/arm/arm-exception-default.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
  *  Obere Lagerstr. 30
@@ -17,12 +17,9 @@
 #endif
 
 #include <rtems/score/cpu.h>
+#include <rtems/fatal.h>
 
-#ifdef ARM_MULTILIB_ARCH_V7M
-
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
+void _ARM_Exception_default( CPU_Exception_frame *frame )
 {
-  /* TODO */
+  rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
 }
-
-#endif /* ARM_MULTILIB_ARCH_V7M */
diff --git a/cpukit/score/cpu/arm/arm-exception-frame-print.c b/cpukit/score/cpu/arm/arm-exception-frame-print.c
index 4d89f69f76..53d31adb73 100644
--- a/cpukit/score/cpu/arm/arm-exception-frame-print.c
+++ b/cpukit/score/cpu/arm/arm-exception-frame-print.c
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2012 embedded brains GmbH.  All rights reserved.
+ * Copyright (c) 2012-2013 embedded brains GmbH.  All rights reserved.
  *
  *  embedded brains GmbH
  *  Obere Lagerstr. 30
@@ -17,12 +17,46 @@
 #endif
 
 #include <rtems/score/cpu.h>
-
-#ifdef ARM_MULTILIB_ARCH_V4
+#include <rtems/bspIo.h>
 
 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame )
 {
-  /* TODO */
+  printk(
+    "\n"
+    "R0   = 0x%08x R8  = 0x%08x\n"
+    "R1   = 0x%08x R9  = 0x%08x\n"
+    "R2   = 0x%08x R10 = 0x%08x\n"
+    "R3   = 0x%08x R11 = 0x%08x\n"
+    "R4   = 0x%08x R12 = 0x%08x\n"
+    "R5   = 0x%08x SP  = 0x%08x\n"
+    "R6   = 0x%08x LR  = 0x%08x\n"
+    "R7   = 0x%08x PC  = 0x%08x\n"
+#if defined(ARM_MULTILIB_ARCH_V4)
+    "CPSR = 0x%08x VEC = 0x%08x\n",
+#elif defined(ARM_MULTILIB_ARCH_V7M)
+    "XPSR = 0x%08x VEC = 0x%08x\n",
+#endif
+    frame->register_r0,
+    frame->register_r1,
+    frame->register_r2,
+    frame->register_r3,
+    frame->register_r4,
+    frame->register_r5,
+    frame->register_r6,
+    frame->register_r7,
+    frame->register_r8,
+    frame->register_r9,
+    frame->register_r10,
+    frame->register_r11,
+    frame->register_r12,
+    frame->register_sp,
+    frame->register_lr,
+    frame->register_pc,
+#if defined(ARM_MULTILIB_ARCH_V4)
+    frame->register_cpsr,
+#elif defined(ARM_MULTILIB_ARCH_V7M)
+    frame->register_xpsr,
+#endif
+    frame->vector
+  );
 }
-
-#endif /* ARM_MULTILIB_ARCH_V4 */
diff --git a/cpukit/score/cpu/arm/arm_exc_abort.S b/cpukit/score/cpu/arm/arm_exc_abort.S
index 59ab5d2988..f4cf6724b8 100644
--- a/cpukit/score/cpu/arm/arm_exc_abort.S
+++ b/cpukit/score/cpu/arm/arm_exc_abort.S
@@ -28,13 +28,13 @@
 
 #ifdef ARM_MULTILIB_ARCH_V4
 
-.extern rtems_fatal_error_occurred
+.extern _ARM_Exception_default
 
-.globl arm_exc_data_abort_set_handler
-.globl arm_exc_data_abort
+.globl _ARMV4_Exception_data_abort_set_handler
+.globl _ARMV4_Exception_data_abort
 
-.globl arm_exc_prefetch_abort_set_handler
-.globl arm_exc_prefetch_abort
+.globl _ARMV4_Exception_prefetch_abort_set_handler
+.globl _ARMV4_Exception_prefetch_abort
 
 .section ".bss"
 
@@ -50,7 +50,7 @@ prefetch_abort_handler:
 	.thumb_func
 #endif
 
-arm_exc_data_abort_set_handler:
+_ARMV4_Exception_data_abort_set_handler:
 	ldr	r1, =data_abort_handler
 	str	r0, [r1]
 #ifdef __thumb__
@@ -63,7 +63,7 @@ arm_exc_data_abort_set_handler:
 	.thumb_func
 #endif
 
-arm_exc_prefetch_abort_set_handler:
+_ARMV4_Exception_prefetch_abort_set_handler:
 	ldr	r1, =prefetch_abort_handler
 	str	r0, [r1]
 #ifdef __thumb__
@@ -74,20 +74,22 @@ arm_exc_prefetch_abort_set_handler:
 
 .arm
 
-arm_exc_prefetch_abort:
+_ARMV4_Exception_prefetch_abort:
 
 	/* Save context and load handler */
-	sub	sp, #16
+	sub	sp, #20
 	stmdb	sp!, {r0-r12}
+	mov	r4, #3
 	ldr	r6, =prefetch_abort_handler
 
 	b	save_more_context
 
-arm_exc_data_abort:
+_ARMV4_Exception_data_abort:
 
 	/* Save context and load handler */
-	sub	sp, #16
+	sub	sp, #20
 	stmdb	sp!, {r0-r12}
+	mov	r4, #4
 	ldr	r6, =data_abort_handler
 
 save_more_context:
@@ -95,22 +97,21 @@ save_more_context:
 	/* Save more context */
 	mov	r2, lr
 	mrs	r3, spsr
-	mrs	r4, cpsr
+	mrs	r7, cpsr
 	orr	r5, r3, #ARM_PSR_I
 	bic	r5, #ARM_PSR_T
 	msr	cpsr, r5
 	mov	r0, sp
 	mov	r1, lr
-	msr	cpsr, r4
-	add	r5, sp, #68
-	stmdb	r5!, {r0-r3}
+	msr	cpsr, r7
+	add	r5, sp, #72
+	stmdb	r5!, {r0-r4}
 
 	/* Call high level handler */
 	ldr	r2, [r6]
 	cmp	r2, #0
-	ldreq	r2, =rtems_fatal_error_occurred
-	movne	r0, sp
-	moveq	r0, #0xaa
+	ldreq	r2, =_ARM_Exception_default
+	mov	r0, sp
 #ifndef __thumb__
 	mov	lr, pc
 	mov	pc, r2
@@ -121,11 +122,11 @@ save_more_context:
 #endif /* __thumb__ */
 
 	/* Restore context */
-	ldmia	r5!, {r0-r3}
+	ldmia	r5!, {r0-r4}
 	mov	lr, r2
 	msr	spsr, r3
 	ldmia	sp!, {r0-r12}
-	add	sp, #16
+	add	sp, #20
 
 	/* Return from interrupt */
 	subs	pc, lr, #8
diff --git a/cpukit/score/cpu/arm/arm_exc_handler_high.c b/cpukit/score/cpu/arm/arm_exc_handler_high.c
index 5f0fdd05f1..9e9449bdd8 100644
--- a/cpukit/score/cpu/arm/arm_exc_handler_high.c
+++ b/cpukit/score/cpu/arm/arm_exc_handler_high.c
@@ -42,7 +42,7 @@ static void _defaultExcHandler (CPU_Exception_frame *ctx)
     printk("----------------------------------------------------------\n\r");
 #if 1
     printk("Exception 0x%x caught at PC 0x%x by thread %d\n",
-           ctx->register_ip, ctx->register_lr - 4,
+           ctx->vector, ctx->register_lr - 4,
            _Thread_Executing->Object.id);
 #endif
     printk("----------------------------------------------------------\n\r");
diff --git a/cpukit/score/cpu/arm/arm_exc_interrupt.S b/cpukit/score/cpu/arm/arm_exc_interrupt.S
index 8d7cfbc1c2..82f3007f5c 100644
--- a/cpukit/score/cpu/arm/arm_exc_interrupt.S
+++ b/cpukit/score/cpu/arm/arm_exc_interrupt.S
@@ -50,8 +50,8 @@
 .extern bsp_interrupt_dispatch
 
 .arm
-.globl arm_exc_interrupt
-arm_exc_interrupt:
+.globl _ARMV4_Exception_interrupt
+_ARMV4_Exception_interrupt:
 
 	/* Save exchange registers to exchange area */
 	stmdb	sp, EXCHANGE_LIST
diff --git a/cpukit/score/cpu/arm/armv4-exception-default.S b/cpukit/score/cpu/arm/armv4-exception-default.S
new file mode 100644
index 0000000000..e5520d5817
--- /dev/null
+++ b/cpukit/score/cpu/arm/armv4-exception-default.S
@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/asm.h>
+#include <rtems/system.h>
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
+.extern _ARM_Exception_default
+
+.globl _ARMV4_Exception_undef_default
+.globl _ARMV4_Exception_swi_default
+.globl _ARMV4_Exception_data_abort_default
+.globl _ARMV4_Exception_pref_abort_default
+.globl _ARMV4_Exception_reserved_default
+.globl _ARMV4_Exception_irq_default
+.globl _ARMV4_Exception_fiq_default
+
+.section ".text"
+
+.arm
+
+_ARMV4_Exception_undef_default:
+
+	/* Save context and load vector */
+	sub	sp, #20
+	stmdb	sp!, {r0-r12}
+	mov	r4, #1
+
+	b	save_more_context
+
+_ARMV4_Exception_swi_default:
+
+	/* Save context and load vector */
+	sub	sp, #20
+	stmdb	sp!, {r0-r12}
+	mov	r4, #2
+
+	b	save_more_context
+
+_ARMV4_Exception_pref_abort_default:
+
+	/* Save context and load vector */
+	sub	sp, #20
+	stmdb	sp!, {r0-r12}
+	mov	r4, #3
+
+	b	save_more_context
+
+_ARMV4_Exception_data_abort_default:
+
+	/* Save context and load vector */
+	sub	sp, #20
+	stmdb	sp!, {r0-r12}
+	mov	r4, #4
+
+_ARMV4_Exception_reserved_default:
+
+	/* Save context and load vector */
+	sub	sp, #20
+	stmdb	sp!, {r0-r12}
+	mov	r4, #5
+
+_ARMV4_Exception_irq_default:
+
+	/* Save context and load vector */
+	sub	sp, #20
+	stmdb	sp!, {r0-r12}
+	mov	r4, #6
+
+_ARMV4_Exception_fiq_default:
+
+	/* Save context and load vector */
+	sub	sp, #20
+	stmdb	sp!, {r0-r12}
+	mov	r4, #7
+
+save_more_context:
+
+	/* Save more context */
+	mov	r2, lr
+	mrs	r3, spsr
+	mrs	r7, cpsr
+	orr	r5, r3, #ARM_PSR_I
+	bic	r5, #ARM_PSR_T
+	msr	cpsr, r5
+	mov	r0, sp
+	mov	r1, lr
+	msr	cpsr, r7
+	add	r5, sp, #72
+	stmdb	r5!, {r0-r4}
+
+	/* Call high level handler */
+	mov	r0, sp
+	SWITCH_FROM_ARM_TO_THUMB	r1
+	bl	_ARM_Exception_default
+
+	/* Just in case */
+twiddle:
+	b	twiddle
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
diff --git a/cpukit/score/cpu/arm/armv7m-context-initialize.c b/cpukit/score/cpu/arm/armv7m-context-initialize.c
index 640adae03d..892df4d8c8 100644
--- a/cpukit/score/cpu/arm/armv7m-context-initialize.c
+++ b/cpukit/score/cpu/arm/armv7m-context-initialize.c
@@ -24,12 +24,11 @@
 
 #include <string.h>
 
+#include <rtems/score/armv7m.h>
 #include <rtems/score/thread.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void _CPU_Context_Initialize(
   Context_Control *context,
   void *stack_area_begin,
diff --git a/cpukit/score/cpu/arm/armv7m-context-restore.c b/cpukit/score/cpu/arm/armv7m-context-restore.c
index 477904953b..a9afdf37e0 100644
--- a/cpukit/score/cpu/arm/armv7m-context-restore.c
+++ b/cpukit/score/cpu/arm/armv7m-context-restore.c
@@ -22,12 +22,11 @@
   #include "config.h"
 #endif
 
+#include <rtems/score/armv7m.h>
 #include <rtems/score/percpu.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void __attribute__((naked)) _CPU_Context_restore(
   Context_Control *heir
 )
diff --git a/cpukit/score/cpu/arm/armv7m-context-switch.c b/cpukit/score/cpu/arm/armv7m-context-switch.c
index 0fd3c206d0..9814ed07a1 100644
--- a/cpukit/score/cpu/arm/armv7m-context-switch.c
+++ b/cpukit/score/cpu/arm/armv7m-context-switch.c
@@ -22,12 +22,11 @@
   #include "config.h"
 #endif
 
+#include <rtems/score/armv7m.h>
 #include <rtems/score/percpu.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void __attribute__((naked)) _CPU_Context_switch(
   Context_Control *executing,
   Context_Control *heir
diff --git a/cpukit/score/cpu/arm/armv7m-exception-default.c b/cpukit/score/cpu/arm/armv7m-exception-default.c
new file mode 100644
index 0000000000..fbd1039028
--- /dev/null
+++ b/cpukit/score/cpu/arm/armv7m-exception-default.c
@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Obere Lagerstr. 30
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifdef HAVE_CONFIG_H
+  #include "config.h"
+#endif
+
+#include <rtems/score/armv7m.h>
+
+#ifdef ARM_MULTILIB_ARCH_V7M
+
+void __attribute__((naked)) _ARMV7M_Exception_default( void )
+{
+  __asm__ volatile (
+    "sub sp, %[cpufsz]\n"
+    "stm sp, {r0-r12}\n"
+    "mov r2, lr\n"
+    "mrs r1, msp\n"
+    "mrs r0, psp\n"
+    "cmn r2, #3\n"
+    "itt ne\n"
+    "movne r0, r1\n"
+    "addne r0, %[cpufsz]\n"
+    "add r2, r0, %[v7mlroff]\n"
+    "add r1, sp, %[cpulroff]\n"
+    "ldm r2, {r3-r5}\n"
+    "stm r1, {r3-r5}\n"
+    "mrs r1, ipsr\n"
+    "str r1, [sp, %[cpuvecoff]]\n"
+    "mov r0, sp\n"
+    "b _ARM_Exception_default\n"
+    :
+    : [cpufsz] "i" (sizeof(CPU_Exception_frame)),
+      [v7mfsz] "i" (sizeof(ARMV7M_Exception_frame)),
+      [cpuspoff] "J" (offsetof(CPU_Exception_frame, register_sp)),
+      [cpulroff] "i" (offsetof(CPU_Exception_frame, register_lr)),
+      [v7mlroff] "i" (offsetof(ARMV7M_Exception_frame, register_lr)),
+      [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector))
+  );
+}
+
+#endif /* ARM_MULTILIB_ARCH_V7M */
diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-get.c b/cpukit/score/cpu/arm/armv7m-exception-handler-get.c
index cf25cafe77..cf100778b8 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-handler-get.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-handler-get.c
@@ -22,12 +22,11 @@
   #include "config.h"
 #endif
 
+#include <rtems/score/armv7m.h>
 #include <rtems/score/cpu.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 ARMV7M_Exception_handler _ARMV7M_Get_exception_handler( int index )
 {
   return _ARMV7M_SCB->vtor [index];
diff --git a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
index ea3fce3ca5..0de3a222c0 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-handler-set.c
@@ -22,12 +22,10 @@
   #include "config.h"
 #endif
 
-#include <rtems/score/cpu.h>
+#include <rtems/score/armv7m.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void _ARMV7M_Set_exception_handler(
   int index,
   ARMV7M_Exception_handler handler
diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-get.c b/cpukit/score/cpu/arm/armv7m-exception-priority-get.c
index 79224e184f..6a1df1df43 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-priority-get.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-priority-get.c
@@ -21,12 +21,10 @@
   #include "config.h"
 #endif
 
-#include <rtems/score/cpu.h>
+#include <rtems/score/armv7m.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 int _ARMV7M_Get_exception_priority( int vector )
 {
   if ( _ARMV7M_Is_vector_an_irq( vector ) ) {
diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c b/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c
index de0b020f23..7b3ff50dbe 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-priority-handler.c
@@ -22,12 +22,10 @@
   #include "config.h"
 #endif
 
-#include <rtems/score/cpu.h>
+#include <rtems/score/armv7m.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void _ARMV7M_Set_exception_priority_and_handler(
   int index,
   int priority,
diff --git a/cpukit/score/cpu/arm/armv7m-exception-priority-set.c b/cpukit/score/cpu/arm/armv7m-exception-priority-set.c
index 085ce2dd96..76dd6d3d7f 100644
--- a/cpukit/score/cpu/arm/armv7m-exception-priority-set.c
+++ b/cpukit/score/cpu/arm/armv7m-exception-priority-set.c
@@ -22,12 +22,10 @@
   #include "config.h"
 #endif
 
-#include <rtems/score/cpu.h>
+#include <rtems/score/armv7m.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void _ARMV7M_Set_exception_priority( int vector, int priority )
 {
   if ( _ARMV7M_Is_vector_an_irq( vector ) ) {
diff --git a/cpukit/score/cpu/arm/armv7m-initialize.c b/cpukit/score/cpu/arm/armv7m-initialize.c
index cb3c19656d..236a0970e9 100644
--- a/cpukit/score/cpu/arm/armv7m-initialize.c
+++ b/cpukit/score/cpu/arm/armv7m-initialize.c
@@ -22,12 +22,10 @@
   #include "config.h"
 #endif
 
-#include <rtems/score/cpu.h>
+#include <rtems/score/armv7m.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void _CPU_Initialize( void )
 {
   /*
diff --git a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
index 7c2cd7370c..3cfe7d7ca5 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-dispatch.c
@@ -22,12 +22,11 @@
   #include "config.h"
 #endif
 
+#include <rtems/score/armv7m.h>
 #include <rtems/score/percpu.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 static void __attribute__((naked)) _ARMV7M_Thread_dispatch( void )
 {
   __asm__ volatile (
diff --git a/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c b/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c
index 1bce10ae77..5af0a8120d 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-enter-leave.c
@@ -22,12 +22,11 @@
   #include "config.h"
 #endif
 
+#include <rtems/score/armv7m.h>
 #include <rtems/score/thread.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void _ARMV7M_Interrupt_service_enter( void )
 {
   ++_Thread_Dispatch_disable_level;
diff --git a/cpukit/score/cpu/arm/armv7m-isr-level-get.c b/cpukit/score/cpu/arm/armv7m-isr-level-get.c
index 887e30843d..7ba13ac111 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-level-get.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-level-get.c
@@ -22,12 +22,10 @@
   #include "config.h"
 #endif
 
-#include <rtems/score/cpu.h>
+#include <rtems/score/armv7m.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 uint32_t _CPU_ISR_Get_level( void )
 {
   return 0;
diff --git a/cpukit/score/cpu/arm/armv7m-isr-level-set.c b/cpukit/score/cpu/arm/armv7m-isr-level-set.c
index 2f4c36312e..81cb9fdbd3 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-level-set.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-level-set.c
@@ -22,12 +22,10 @@
   #include "config.h"
 #endif
 
-#include <rtems/score/cpu.h>
+#include <rtems/score/armv7m.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void _CPU_ISR_Set_level( uint32_t level )
 {
   _ARMV7M_Set_basepri( 0 );
diff --git a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
index 82b8e02e2b..ef813e318b 100644
--- a/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
+++ b/cpukit/score/cpu/arm/armv7m-isr-vector-install.c
@@ -22,12 +22,11 @@
   #include "config.h"
 #endif
 
+#include <rtems/score/armv7m.h>
 #include <rtems/score/isr.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void _CPU_ISR_install_vector(
   uint32_t vector,
   proc_ptr new_handler,
diff --git a/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c b/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c
index d27bf8b009..f3e96e343c 100644
--- a/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c
+++ b/cpukit/score/cpu/arm/armv7m-multitasking-start-stop.c
@@ -22,12 +22,10 @@
   #include "config.h"
 #endif
 
-#include <rtems/score/cpu.h>
+#include <rtems/score/armv7m.h>
 
 #ifdef ARM_MULTILIB_ARCH_V7M
 
-#include <rtems/score/armv7m.h>
-
 void __attribute__((naked)) _ARMV7M_Start_multitasking(
   Context_Control *bsp,
   Context_Control *heir
diff --git a/cpukit/score/cpu/arm/preinstall.am b/cpukit/score/cpu/arm/preinstall.am
index 92ba4687fc..fb8881df93 100644
--- a/cpukit/score/cpu/arm/preinstall.am
+++ b/cpukit/score/cpu/arm/preinstall.am
@@ -39,6 +39,10 @@ $(PROJECT_INCLUDE)/rtems/score/arm.h: rtems/score/arm.h $(PROJECT_INCLUDE)/rtems
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/arm.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/arm.h
 
+$(PROJECT_INCLUDE)/rtems/score/armv4.h: rtems/score/armv4.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
+	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/armv4.h
+PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/armv4.h
+
 $(PROJECT_INCLUDE)/rtems/score/armv7m.h: rtems/score/armv7m.h $(PROJECT_INCLUDE)/rtems/score/$(dirstamp)
 	$(INSTALL_DATA) $< $(PROJECT_INCLUDE)/rtems/score/armv7m.h
 PREINSTALL_FILES += $(PROJECT_INCLUDE)/rtems/score/armv7m.h
diff --git a/cpukit/score/cpu/arm/rtems/asm.h b/cpukit/score/cpu/arm/rtems/asm.h
index e6951dbb28..e0009285da 100644
--- a/cpukit/score/cpu/arm/rtems/asm.h
+++ b/cpukit/score/cpu/arm/rtems/asm.h
@@ -1,21 +1,17 @@
 /**
  * @file
  *
- * @ingroup ScoreCPU
+ * @brief ARM Assembler Support API
  *
- * @brief ARM assembler support API.
- */
-
-/*
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
  *
  *
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
@@ -53,10 +49,9 @@
  *
  * @ingroup ScoreCPU
  *
- * @brief ARM assembler support.
- *
- * @{
+ * @brief ARM Assembler Support
  */
+/**@{**/
 
 /*
  *  Recent versions of GNU cpp define variables which indicate the
diff --git a/cpukit/score/cpu/arm/rtems/score/arm.h b/cpukit/score/cpu/arm/rtems/score/arm.h
index c4f7cf2324..8f8c837b41 100644
--- a/cpukit/score/cpu/arm/rtems/score/arm.h
+++ b/cpukit/score/cpu/arm/rtems/score/arm.h
@@ -1,9 +1,7 @@
 /**
  * @file
  *
- * @ingroup ScoreCPU
- *
- * @brief ARM assembler support API.
+ * @brief ARM Assembler Support API
  */
 
 /*
@@ -28,9 +26,8 @@ extern "C" {
 
 /**
  * @addtogroup ScoreCPU
- *
- * @{
  */
+/**@{**/
 
 /*
  *  This file contains the information required to build
diff --git a/cpukit/score/cpu/arm/rtems/score/armv4.h b/cpukit/score/cpu/arm/rtems/score/armv4.h
new file mode 100644
index 0000000000..dfd57bb3bb
--- /dev/null
+++ b/cpukit/score/cpu/arm/rtems/score/armv4.h
@@ -0,0 +1,98 @@
+/*
+ * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
+ *
+ *  embedded brains GmbH
+ *  Dornierstr. 4
+ *  82178 Puchheim
+ *  Germany
+ *  <rtems@embedded-brains.de>
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rtems.com/license/LICENSE.
+ */
+
+#ifndef RTEMS_SCORE_ARMV4_H
+#define RTEMS_SCORE_ARMV4_H
+
+#include <rtems/score/cpu.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif /* __cplusplus */
+
+#ifdef ARM_MULTILIB_ARCH_V4
+
+void bsp_interrupt_dispatch( void );
+
+void _ARMV4_Exception_interrupt( void );
+
+typedef void ARMV4_Exception_abort_handler( CPU_Exception_frame *frame );
+
+void _ARMV4_Exception_data_abort_set_handler(
+  ARMV4_Exception_abort_handler handler
+);
+
+void _ARMV4_Exception_data_abort( void );
+
+void _ARMV4_Exception_prefetch_abort_set_handler(
+  ARMV4_Exception_abort_handler handler
+);
+
+void _ARMV4_Exception_prefetch_abort( void );
+
+void _ARMV4_Exception_undef_default( void );
+
+void _ARMV4_Exception_swi_default( void );
+
+void _ARMV4_Exception_data_abort_default( void );
+
+void _ARMV4_Exception_pref_abort_default( void );
+
+void _ARMV4_Exception_reserved_default( void );
+
+void _ARMV4_Exception_irq_default( void );
+
+void _ARMV4_Exception_fiq_default( void );
+
+static inline uint32_t _ARMV4_Status_irq_enable( void )
+{
+  uint32_t arm_switch_reg;
+  uint32_t psr;
+
+  RTEMS_COMPILER_MEMORY_BARRIER();
+
+  __asm__ volatile (
+    ARM_SWITCH_TO_ARM
+    "mrs %[psr], cpsr\n"
+    "bic %[arm_switch_reg], %[psr], #0x80\n"
+    "msr cpsr, %[arm_switch_reg]\n"
+    ARM_SWITCH_BACK
+    : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
+  );
+
+  return psr;
+}
+
+static inline void _ARMV4_Status_restore( uint32_t psr )
+{
+  ARM_SWITCH_REGISTERS;
+
+  __asm__ volatile (
+    ARM_SWITCH_TO_ARM
+    "msr cpsr, %[psr]\n"
+    ARM_SWITCH_BACK
+    : ARM_SWITCH_OUTPUT
+    : [psr] "r" (psr)
+  );
+
+  RTEMS_COMPILER_MEMORY_BARRIER();
+}
+
+#endif /* ARM_MULTILIB_ARCH_V4 */
+
+#ifdef __cplusplus
+}
+#endif /* __cplusplus */
+
+#endif /* RTEMS_SCORE_ARMV4_H */
diff --git a/cpukit/score/cpu/arm/rtems/score/armv7m.h b/cpukit/score/cpu/arm/rtems/score/armv7m.h
index 62f69ff490..3a41a0c707 100644
--- a/cpukit/score/cpu/arm/rtems/score/armv7m.h
+++ b/cpukit/score/cpu/arm/rtems/score/armv7m.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief ARMV7M Architecture Support
+ */
+
 /*
  * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
  *
@@ -15,13 +21,14 @@
 #ifndef RTEMS_SCORE_ARMV7M_H
 #define RTEMS_SCORE_ARMV7M_H
 
-#include <stdint.h>
-#include <stdbool.h>
+#include <rtems/score/cpu.h>
 
 #ifdef __cplusplus
 extern "C" {
 #endif /* __cplusplus */
 
+#ifdef ARM_MULTILIB_ARCH_V7M
+
 typedef struct {
   uint32_t reserved_0;
   uint32_t ictr;
@@ -58,6 +65,21 @@ typedef struct {
   uint32_t icsr;
 
   ARMV7M_Exception_handler *vtor;
+
+#define ARMV7M_SCB_AIRCR_VECTKEY (0x05fa << 16)
+#define ARMV7M_SCB_AIRCR_ENDIANESS (1U << 15)
+#define ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT 8
+#define ARMV7M_SCB_AIRCR_PRIGROUP_MASK \
+  ((0x7U) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT)
+#define ARMV7M_SCB_AIRCR_PRIGROUP(val) \
+  (((val) << ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK)
+#define ARMV7M_SCB_AIRCR_PRIGROUP_GET(reg) \
+  (((val) & ARMV7M_SCB_AIRCR_PRIGROUP_MASK) >> ARMV7M_SCB_AIRCR_PRIGROUP_SHIFT)
+#define ARMV7M_SCB_AIRCR_PRIGROUP_SET(reg, val) \
+  (((reg) & ~ARMV7M_SCB_AIRCR_PRIGROUP_MASK) | ARMV7M_SCB_AIRCR_PRIGROUP(val))
+#define ARMV7M_SCB_AIRCR_SYSRESETREQ (1U << 2)
+#define ARMV7M_SCB_AIRCR_VECTCLRACTIVE (1U << 1)
+#define ARMV7M_SCB_AIRCR_VECTRESET (1U << 0)
   uint32_t aircr;
   uint32_t scr;
   uint32_t ccr;
@@ -458,8 +480,7 @@ void _ARMV7M_Set_exception_handler(
 );
 
 /**
- *  @brief ARMV7M Set Exception Priority and Handler
- *
+ * @brief ARMV7M set exception priority and handler.
  */
 void _ARMV7M_Set_exception_priority_and_handler(
   int index,
@@ -467,6 +488,8 @@ void _ARMV7M_Set_exception_priority_and_handler(
   ARMV7M_Exception_handler handler
 );
 
+void _ARMV7M_Exception_default( void );
+
 void _ARMV7M_Interrupt_service_enter( void );
 
 void _ARMV7M_Interrupt_service_leave( void );
@@ -475,6 +498,8 @@ void _ARMV7M_Pendable_service_call( void );
 
 void _ARMV7M_Supervisor_call( void );
 
+#endif /* ARM_MULTILIB_ARCH_V7M */
+
 #ifdef __cplusplus
 }
 #endif /* __cplusplus */
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu.h b/cpukit/score/cpu/arm/rtems/score/cpu.h
index c1ffb0765d..bbcded682c 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu.h
@@ -1,9 +1,7 @@
 /**
  * @file
  *
- * @ingroup ScoreCPU
- *
- * @brief ARM architecture support API.
+ * @brief ARM Architecture Support API
  */
 
 /*
@@ -42,9 +40,8 @@
  * @ingroup ScoreCPU
  *
  * @brief ARM specific support.
- *
- * @{
  */
+/**@{**/
 
 #ifdef __thumb__
   #define ARM_SWITCH_REGISTERS uint32_t arm_switch_reg
@@ -62,9 +59,8 @@
 
 /**
  * @name Program Status Register
- *
- * @{
  */
+/**@{**/
 
 #define ARM_PSR_N (1 << 31)
 #define ARM_PSR_Z (1 << 30)
@@ -97,9 +93,8 @@
 
 /**
  * @addtogroup ScoreCPU
- *
- * @{
  */
+/**@{**/
 
 /* If someone uses THUMB we assume she wants minimal code size */
 #ifdef __thumb__
@@ -227,9 +222,8 @@ extern "C" {
 
 /**
  * @addtogroup ScoreCPU
- *
- * @{
  */
+/**@{**/
 
 typedef struct {
 #if defined(ARM_MULTILIB_ARCH_V4)
@@ -399,8 +393,7 @@ void _CPU_Context_Initialize(
    } while (0);
 
 /**
- *  @brief CPU Initialize
- *
+ * @brief CPU initialization.
  */
 void _CPU_Initialize( void );
 
@@ -411,8 +404,7 @@ void _CPU_ISR_install_vector(
 );
 
 /**
- *  @brief CPU Context Switch
- *
+ * @brief CPU switch context.
  */
 void _CPU_Context_switch( Context_Control *run, Context_Control *heir );
 
@@ -482,35 +474,12 @@ static inline uint16_t CPU_swap_u16( uint16_t value )
 
 /** @} */
 
-#if defined(ARM_MULTILIB_ARCH_V4)
-
 /**
  * @addtogroup ScoreCPUARM
- *
- * @{
  */
+/**@{**/
 
-typedef struct {
-  uint32_t r0;
-  uint32_t r1;
-  uint32_t r2;
-  uint32_t r3;
-  uint32_t r4;
-  uint32_t r5;
-  uint32_t r6;
-  uint32_t r7;
-  uint32_t r8;
-  uint32_t r9;
-  uint32_t r10;
-  uint32_t r11;
-  uint32_t r12;
-  uint32_t sp;
-  uint32_t lr;
-  uint32_t pc;
-  uint32_t cpsr;
-} arm_cpu_context;
-
-typedef void arm_exc_abort_handler( arm_cpu_context *context );
+#if defined(ARM_MULTILIB_ARCH_V4)
 
 typedef enum {
   ARM_EXCEPTION_RESET = 0,
@@ -521,81 +490,45 @@ typedef enum {
   ARM_EXCEPTION_RESERVED = 5,
   ARM_EXCEPTION_IRQ = 6,
   ARM_EXCEPTION_FIQ = 7,
-  MAX_EXCEPTIONS = 8
+  MAX_EXCEPTIONS = 8,
+  ARM_EXCEPTION_MAKE_ENUM_32_BIT = 0xffffffff
 } Arm_symbolic_exception_name;
 
-static inline uint32_t arm_status_irq_enable( void )
-{
-  uint32_t arm_switch_reg;
-  uint32_t psr;
-
-  RTEMS_COMPILER_MEMORY_BARRIER();
-
-  __asm__ volatile (
-    ARM_SWITCH_TO_ARM
-    "mrs %[psr], cpsr\n"
-    "bic %[arm_switch_reg], %[psr], #0x80\n"
-    "msr cpsr, %[arm_switch_reg]\n"
-    ARM_SWITCH_BACK
-    : [arm_switch_reg] "=&r" (arm_switch_reg), [psr] "=&r" (psr)
-  );
-
-  return psr;
-}
-
-static inline void arm_status_restore( uint32_t psr )
-{
-  ARM_SWITCH_REGISTERS;
-
-  __asm__ volatile (
-    ARM_SWITCH_TO_ARM
-    "msr cpsr, %[psr]\n"
-    ARM_SWITCH_BACK
-    : ARM_SWITCH_OUTPUT
-    : [psr] "r" (psr)
-  );
-
-  RTEMS_COMPILER_MEMORY_BARRIER();
-}
-
-void arm_exc_data_abort_set_handler( arm_exc_abort_handler handler );
-
-void arm_exc_data_abort( void );
-
-void arm_exc_prefetch_abort_set_handler( arm_exc_abort_handler handler );
-
-void arm_exc_prefetch_abort( void );
-
-void bsp_interrupt_dispatch( void );
-
-void arm_exc_interrupt( void );
-
-void arm_exc_undefined( void );
-
-/** @} */
+#endif /* defined(ARM_MULTILIB_ARCH_V4) */
 
-/* XXX This is out of date */
 typedef struct {
   uint32_t register_r0;
   uint32_t register_r1;
   uint32_t register_r2;
   uint32_t register_r3;
-  uint32_t register_ip;
-  uint32_t register_lr;
+  uint32_t register_r4;
+  uint32_t register_r5;
+  uint32_t register_r6;
+  uint32_t register_r7;
+  uint32_t register_r8;
+  uint32_t register_r9;
+  uint32_t register_r10;
+  uint32_t register_r11;
+  uint32_t register_r12;
+  uint32_t register_sp;
+  void *register_lr;
+  void *register_pc;
+#if defined(ARM_MULTILIB_ARCH_V4)
+  uint32_t register_cpsr;
+  Arm_symbolic_exception_name vector;
+#elif defined(ARM_MULTILIB_ARCH_V7M)
+  uint32_t register_xpsr;
+  uint32_t vector;
+#endif
 } CPU_Exception_frame;
 
 typedef CPU_Exception_frame CPU_Interrupt_frame;
 
-#else /* !defined(ARM_MULTILIB_ARCH_V4) */
-
-typedef void CPU_Interrupt_frame;
-
-/* FIXME */
-typedef CPU_Interrupt_frame CPU_Exception_frame;
+void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
 
-#endif /* !defined(ARM_MULTILIB_ARCH_V4) */
+void _ARM_Exception_default( CPU_Exception_frame *frame );
 
-void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
+/** @} */
 
 #ifdef __cplusplus
 }
diff --git a/cpukit/score/cpu/arm/rtems/score/cpu_asm.h b/cpukit/score/cpu/arm/rtems/score/cpu_asm.h
index 16c40125ec..59bfae079f 100644
--- a/cpukit/score/cpu/arm/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/arm/rtems/score/cpu_asm.h
@@ -3,7 +3,7 @@
  *
  * @ingroup ScoreCPU
  *
- * @brief ARM assembler support API.
+ * @brief ARM Assembler Support API
  */
 
 /*
diff --git a/cpukit/score/cpu/arm/rtems/score/types.h b/cpukit/score/cpu/arm/rtems/score/types.h
index f6de605b89..8e7195304b 100644
--- a/cpukit/score/cpu/arm/rtems/score/types.h
+++ b/cpukit/score/cpu/arm/rtems/score/types.h
@@ -1,9 +1,7 @@
 /**
  * @file
  *
- * @ingroup ScoreCPU
- *
- * @brief ARM architecture types API.
+ * @brief ARM Architecture Types API
  */
 
 /*
@@ -32,9 +30,8 @@ extern "C" {
 
 /**
  * @addtogroup ScoreCPU
- *
- * @{
  */
+/**@{**/
 
 /*
  *  This section defines the basic types for this processor.
diff --git a/cpukit/score/cpu/avr/avr/boot.h b/cpukit/score/cpu/avr/avr/boot.h
index 96453b5bfd..863143b226 100644
--- a/cpukit/score/cpu/avr/avr/boot.h
+++ b/cpukit/score/cpu/avr/avr/boot.h
@@ -1,104 +1,114 @@
-/* Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009  Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
+/**
+ * @file
+ *
+ * @brief Bootloader Support Utilities
+ *
+ *  The macros in this module provide a C language interface to the
+ *  bootloader support functionality of certain AVR processors. These
+ *  macros are designed to work with all sizes of flash memory.
+ *
+ *  Global interrupts are not automatically disabled for these macros. It
+ *  is left up to the programmer to do this. See the code example below.
+ *  Also see the processor datasheet for caveats on having global interrupts
+ *  enabled during writing of the Flash.
+ *
+ *  \note Not all AVR processors provide bootloader support. See your
+ *  processor datasheet to see if it provides bootloader support.
+ *
+ *  From email with Marek: On smaller devices (all except ATmega64/128),
+ *  __SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
+ *  instructions - since the boot loader has a limited size, this could be an
+ *  important optimization.
+ *
+ *  API Usage Example
+ *  The following code shows typical usage of the boot API.
+ *
+ *
+ *  #include <inttypes.h>
+ *  #include <avr/interrupt.h>
+ *  #include <avr/pgmspace.h>
+ *
+ *  void boot_program_page (uint32_t page, uint8_t *buf)
+ *  {
+ *      uint16_t i;
+ *      uint8_t sreg;
+ *
+ *      // Disable interrupts.
+ *
+ *      sreg = SREG;
+ *      cli();
+ *
+ *      eeprom_busy_wait ();
+ *
+ *      boot_page_erase (page);
+ *      boot_spm_busy_wait ();      // Wait until the memory is erased.
+ *
+ *      for (i=0; i<SPM_PAGESIZE; i+=2)
+ *      {
+ *          // Set up little-endian word.
+ *
+ *          uint16_t w = *buf++;
+ *          w += (*buf++) << 8;
+ *
+ *          boot_page_fill (page + i, w);
+ *      }
+ *
+ *      boot_page_write (page);     // Store buffer in flash page.
+ *      boot_spm_busy_wait();       // Wait until the memory is written.
+ *
+ *      // Reenable RWW-section again. We need this if we want to jump back
+ *      // to the application after bootloading.
+ *
+ *      boot_rww_enable ();
+ *
+ *      // Re-enable interrupts (if they were ever enabled).
+ *
+ *      SREG = sreg;
+ *  }
+ */
+
+/*
+ *   Copyright (c) 2002,2003,2004,2005,2006,2007,2008,2009  Eric B. Weddington
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 
 #ifndef _AVR_BOOT_H_
 #define _AVR_BOOT_H_    1
 
-/** \file */
-/** \defgroup avr_boot <avr/boot.h>: Bootloader Support Utilities
-    \code
-    #include <avr/io.h>
-    #include <avr/boot.h>
-    \endcode
-
-    The macros in this module provide a C language interface to the
-    bootloader support functionality of certain AVR processors. These
-    macros are designed to work with all sizes of flash memory.
-
-    Global interrupts are not automatically disabled for these macros. It
-    is left up to the programmer to do this. See the code example below. 
-    Also see the processor datasheet for caveats on having global interrupts 
-    enabled during writing of the Flash.
-
-    \note Not all AVR processors provide bootloader support. See your
-    processor datasheet to see if it provides bootloader support.
-
-    \todo From email with Marek: On smaller devices (all except ATmega64/128),
-    __SPM_REG is in the I/O space, accessible with the shorter "in" and "out"
-    instructions - since the boot loader has a limited size, this could be an
-    important optimization.
-
-    \par API Usage Example
-    The following code shows typical usage of the boot API.
-
-    \code
-    #include <inttypes.h>
-    #include <avr/interrupt.h>
-    #include <avr/pgmspace.h>
-    
-    void boot_program_page (uint32_t page, uint8_t *buf)
-    {
-        uint16_t i;
-        uint8_t sreg;
-
-        // Disable interrupts.
-
-        sreg = SREG;
-        cli();
-    
-        eeprom_busy_wait ();
-
-        boot_page_erase (page);
-        boot_spm_busy_wait ();      // Wait until the memory is erased.
-
-        for (i=0; i<SPM_PAGESIZE; i+=2)
-        {
-            // Set up little-endian word.
-
-            uint16_t w = *buf++;
-            w += (*buf++) << 8;
-        
-            boot_page_fill (page + i, w);
-        }
-
-        boot_page_write (page);     // Store buffer in flash page.
-        boot_spm_busy_wait();       // Wait until the memory is written.
-
-        // Reenable RWW-section again. We need this if we want to jump back
-        // to the application after bootloading.
-
-        boot_rww_enable ();
-
-        // Re-enable interrupts (if they were ever enabled).
-
-        SREG = sreg;
-    }\endcode */
+/**
+ *  @defgroup avr_boot Bootloader Support Utilities
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #include <avr/eeprom.h>
 #include <avr/io.h>
@@ -382,11 +392,11 @@
 
      If bits 5..2 in R0 are cleared (zero), the corresponding Boot Lock bit
      will be programmed if an SPM instruction is executed within four cycles
-     after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is 
-     don't care during this operation, but for future compatibility it is 
-     recommended to load the Z-pointer with $0001 (same as used for reading the 
-     Lock bits). For future compatibility It is also recommended to set bits 7, 
-     6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the 
+     after BLBSET and SPMEN (or SELFPRGEN) are set in SPMCR. The Z-pointer is
+     don't care during this operation, but for future compatibility it is
+     recommended to load the Z-pointer with $0001 (same as used for reading the
+     Lock bits). For future compatibility It is also recommended to set bits 7,
+     6, 1, and 0 in R0 to 1 when writing the Lock bits. When programming the
      Lock bits the entire Flash can be read during the operation. */
 
 #define __boot_lock_bits_set(lock_bits)                    \
@@ -430,8 +440,8 @@
 /*
    Reading lock and fuse bits:
 
-     Similarly to writing the lock bits above, set BLBSET and SPMEN (or 
-     SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an 
+     Similarly to writing the lock bits above, set BLBSET and SPMEN (or
+     SELFPRGEN) bits in __SPMREG, and then (within four clock cycles) issue an
      LPM instruction.
 
      Z address:       contents:
@@ -525,13 +535,13 @@
 /** \ingroup avr_boot
     \def boot_page_fill(address, data)
 
-    Fill the bootloader temporary page buffer for flash 
-    address with data word. 
+    Fill the bootloader temporary page buffer for flash
+    address with data word.
 
-    \note The address is a byte address. The data is a word. The AVR 
+    \note The address is a byte address. The data is a word. The AVR
     writes data to the buffer a word at a time, but addresses the buffer
     per byte! So, increment your address by 2 between calls, and send 2
-    data bytes in a word format! The LSB of the data is written to the lower 
+    data bytes in a word format! The LSB of the data is written to the lower
     address; the MSB of the data is written to the higher address.*/
 
 /** \ingroup avr_boot
@@ -544,9 +554,9 @@
 /** \ingroup avr_boot
     \def boot_page_write(address)
 
-    Write the bootloader temporary page buffer 
+    Write the bootloader temporary page buffer
     to flash page that contains address.
-    
+
     \note address is a byte address in flash, not a word address. */
 
 /** \ingroup avr_boot
@@ -581,7 +591,7 @@
    instruction sequences after LPM.
 
    FLASHEND is defined in the ioXXXX.h file.
-   USHRT_MAX is defined in <limits.h>. */ 
+   USHRT_MAX is defined in <limits.h>. */
 
 #if defined(__AVR_ATmega161__) || defined(__AVR_ATmega163__) \
     || defined(__AVR_ATmega323__)
@@ -673,4 +683,5 @@ do { \
     boot_lock_bits_set (lock_bits);             \
 } while (0)
 
+/**@}*/
 #endif /* _AVR_BOOT_H_ */
diff --git a/cpukit/score/cpu/avr/avr/common.h b/cpukit/score/cpu/avr/avr/common.h
index 0901a6c741..1acfe26889 100644
--- a/cpukit/score/cpu/avr/avr/common.h
+++ b/cpukit/score/cpu/avr/avr/common.h
@@ -1,53 +1,65 @@
-/* Copyright (c) 2007 Eric B. Weddington
-   All rights reserved.
+/**
+ * @file
+ *
+ * @brief Common Symbols and Define Undefined Registers
+ *
+ * This purpose of this header is to define registers that have not been
+ * previously defined in the individual device IO header files, and to define
+ * other symbols that are common across AVR device families.
+ *
+ * This file is designed to be included in <avr/io.h> after the individual
+ * device IO header files, and after <avr/sfr_defs.h>
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
+/*
+ *  Copyright (c) 2007 Eric B. Weddington
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 
 
 #ifndef _AVR_COMMON_H
 #define _AVR_COMMON_H
 
-#include <avr/sfr_defs.h>
-
-/* 
-This purpose of this header is to define registers that have not been 
-previously defined in the individual device IO header files, and to define 
-other symbols that are common across AVR device families.
-
-This file is designed to be included in <avr/io.h> after the individual
-device IO header files, and after <avr/sfr_defs.h>
+/**
+ *  @defgroup Avr_common Common Data
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
-*/
+#include <avr/sfr_defs.h>
 
 /*------------ Registers Not Previously Defined ------------*/
 
-/* 
+/*
 These are registers that are not previously defined in the individual
 IO header files, OR they are defined here because they are used in parts of
 avr-libc even if a device is not selected but a general architecture has
@@ -58,7 +70,7 @@ been selected.
 /*
 Stack pointer register.
 
-AVR architecture 1 has no RAM, thus no stack pointer. 
+AVR architecture 1 has no RAM, thus no stack pointer.
 
 All other architectures do have a stack pointer.  Some devices have only
 less than 256 bytes of possible RAM locations (128 Bytes of SRAM
@@ -75,7 +87,7 @@ for them.
 #  ifndef SP
 #    define SP _SFR_MEM16(0x3D)
 #  endif
-#elif __AVR_ARCH__ != 1 
+#elif __AVR_ARCH__ != 1
 #  ifndef SPL
 #    define SPL _SFR_IO8(0x3D)
 #  endif
@@ -192,7 +204,7 @@ keep the EEPROM-related definitions here.
 
 /*------------ Common Symbols ------------*/
 
-/* 
+/*
 Generic definitions for registers that are common across multiple AVR devices
 and families.
 */
@@ -319,4 +331,5 @@ and families.
 # endif
 #endif
 
+/**@}*/
 #endif /* _AVR_COMMON_H */
diff --git a/cpukit/score/cpu/avr/avr/crc16.h b/cpukit/score/cpu/avr/avr/crc16.h
index 63e043b7a8..fe6dfd4346 100644
--- a/cpukit/score/cpu/avr/avr/crc16.h
+++ b/cpukit/score/cpu/avr/avr/crc16.h
@@ -1,38 +1,54 @@
-/* Copyright (c) 2005 Joerg Wunsch
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
+/**
+ * @file
+ *
+ * @brief Moved to <util/crc16.h>
+ */
+
+/*
+ *  Copyright (c) 2005 Joerg Wunsch
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 
 #ifndef _AVR_CRC16_H_
 #define _AVR_CRC16_H_
 
+/**
+ *  @defgroup Avr_crc16 crc16
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #warning "This file has been moved to <util/crc16.h>."
 #include <util/crc16.h>
 
+/**@}*/
 #endif /* _AVR_CRC16_H_ */
diff --git a/cpukit/score/cpu/avr/avr/delay.h b/cpukit/score/cpu/avr/avr/delay.h
index 42f10c1912..ad9db108eb 100644
--- a/cpukit/score/cpu/avr/avr/delay.h
+++ b/cpukit/score/cpu/avr/avr/delay.h
@@ -1,38 +1,55 @@
-/* Copyright (c) 2005 Joerg Wunsch
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
+/**
+ * @file
+ *
+ * @brief Moved to <util/delay.h>
+ */
+
+/*
+ * Copyright (c) 2005 Joerg Wunsch
+ * All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 
 #ifndef _AVR_DELAY_H_
 #define _AVR_DELAY_H_
 
+/**
+ * @defgroup AvrDelay Delay
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 #warning "This file has been moved to <util/delay.h>."
 #include <util/delay.h>
 
+/** @} */
 #endif /* _AVR_DELAY_H_ */
diff --git a/cpukit/score/cpu/avr/avr/eeprom.h b/cpukit/score/cpu/avr/avr/eeprom.h
index ab21d2dbe0..448248dc37 100644
--- a/cpukit/score/cpu/avr/avr/eeprom.h
+++ b/cpukit/score/cpu/avr/avr/eeprom.h
@@ -1,34 +1,78 @@
-/* Copyright (c) 2002, 2003, 2004, 2007 Marek Michalkiewicz
-   Copyright (c) 2005, 2006 Bjoern Haase
-   Copyright (c) 2008 Atmel Corporation
-   Copyright (c) 2008 Wouter van Gulik
-   Copyright (c) 2009 Dmitry Xmelkov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
+/**
+ * @file
+ *
+ * @brief Data EEPROM Contained in the AVR Microcontrollers
+ *
+ * This header file declares the interface to some simple library
+ * routines suitable for handling the data EEPROM contained in the
+ * AVR microcontrollers.  The implementation uses a simple polled
+ * mode interface.  Applications that require interrupt-controlled
+ * EEPROM access to ensure that no time will be wasted in spinloops
+ * will have to deploy their own implementation.
+ *
+ *  \par Notes:
+ *
+ *  - In addition to the write functions there is a set of update ones.
+ *  This functions read each byte first and skip the burning if the
+ *  old value is the same with new.  The scaning direction is from
+ *  high address to low, to obtain quick return in common cases.
+ *
+ *  - All of the read/write functions first make sure the EEPROM is
+ *  ready to be accessed.  Since this may cause long delays if a
+ *  write operation is still pending, time-critical applications
+ *  should first poll the EEPROM e. g. using eeprom_is_ready() before
+ *  attempting any actual I/O.  But this functions are not wait until
+ *  SELFPRGEN in SPMCSR becomes zero.  Do this manually, if your
+ *  softwate contains the Flash burning.
+ *
+ *  - As these functions modify IO registers, they are known to be
+ *  non-reentrant.  If any of these functions are used from both,
+ *  standard and interrupt context, the applications must ensure
+ *  proper protection (e.g. by disabling interrupts before accessing
+ *  them).
+ *
+ *  - All write functions force erase_and_write programming mode.
+ *
+ *  - For Xmega the EEPROM start address is 0, like other architectures.
+ *  The reading functions add the 0x2000 value to use EEPROM mapping into
+ *  data space.
+ */
+
+/*
+ * Copyright (c) 2002, 2003, 2004, 2007 Marek Michalkiewicz
+ * Copyright (c) 2005, 2006 Bjoern Haase
+ * Copyright (c) 2008 Atmel Corporation
+ * Copyright (c) 2008 Wouter van Gulik
+ * Copyright (c) 2009 Dmitry Xmelkov
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 
 #ifndef _AVR_EEPROM_H_
@@ -409,43 +453,12 @@
 #include <stddef.h>	/* size_t */
 #include <stdint.h>
 
-/** \defgroup avr_eeprom <avr/eeprom.h>: EEPROM handling
-    \code #include <avr/eeprom.h> \endcode
-
-    This header file declares the interface to some simple library
-    routines suitable for handling the data EEPROM contained in the
-    AVR microcontrollers.  The implementation uses a simple polled
-    mode interface.  Applications that require interrupt-controlled
-    EEPROM access to ensure that no time will be wasted in spinloops
-    will have to deploy their own implementation.
-
-    \par Notes:
-
-    - In addition to the write functions there is a set of update ones.
-    This functions read each byte first and skip the burning if the
-    old value is the same with new.  The scaning direction is from
-    high address to low, to obtain quick return in common cases.
-
-    - All of the read/write functions first make sure the EEPROM is
-    ready to be accessed.  Since this may cause long delays if a
-    write operation is still pending, time-critical applications
-    should first poll the EEPROM e. g. using eeprom_is_ready() before
-    attempting any actual I/O.  But this functions are not wait until
-    SELFPRGEN in SPMCSR becomes zero.  Do this manually, if your
-    softwate contains the Flash burning.
-
-    - As these functions modify IO registers, they are known to be
-    non-reentrant.  If any of these functions are used from both,
-    standard and interrupt context, the applications must ensure
-    proper protection (e.g. by disabling interrupts before accessing
-    them).
-
-    - All write functions force erase_and_write programming mode.
-    
-    - For Xmega the EEPROM start address is 0, like other architectures.
-    The reading functions add the 0x2000 value to use EEPROM mapping into
-    data space.
+/**
+ *  @defgroup avr_eeprom EEPROM handling
+ *
+ *  @ingroup avr
  */
+/**@{*/
 
 #ifdef __cplusplus
 extern "C" {
@@ -486,7 +499,7 @@ extern "C" {
     \ingroup avr_eeprom
     Loops until the eeprom is no longer busy.
     \returns Nothing.
- */ 	 
+ */
 #define eeprom_busy_wait() do {} while (!eeprom_is_ready())
 
 
@@ -602,4 +615,6 @@ void eeprom_update_block (const void *__src, void *__dst, size_t __n);
 
 #endif	/* !__ASSEMBLER__ */
 #endif	/* E2END || defined(__DOXYGEN__) || defined(__COMPILING_AVR_LIBC__) */
+
+/**@}*/
 #endif	/* !_AVR_EEPROM_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io.h b/cpukit/score/cpu/avr/avr/io.h
index d4198f14ae..22ac57d84f 100644
--- a/cpukit/score/cpu/avr/avr/io.h
+++ b/cpukit/score/cpu/avr/avr/io.h
@@ -1,100 +1,109 @@
-/* Copyright (c) 2002,2003,2005,2006,2007 Marek Michalkiewicz, Joerg Wunsch
-   Copyright (c) 2007 Eric B. Weddington
-   All rights reserved.
+/**
+ * @file
+ *
+ * @brief AVR device-specific IO Definitions
+ *
+ * This header file includes the apropriate IO definitions for the
+ * device that has been specified by the <tt>-mmcu=</tt> compiler
+ *  command-line switch.  This is done by diverting to the appropriate
+ *  file <tt>&lt;avr/io</tt><em>XXXX</em><tt>.h&gt;</tt> which should
+ *  never be included directly.  Some register names common to all
+ *  AVR devices are defined directly within <tt>&lt;avr/common.h&gt;</tt>,
+ *  which is included in <tt>&lt;avr/io.h&gt;</tt>,
+ *  but most of the details come from the respective include file.
+ *
+ *  Note that this file always includes the following files:
+ *  \code
+ *  #include <avr/sfr_defs.h>
+ *  #include <avr/portpins.h>
+ *  #include <avr/common.h>
+ *  #include <avr/version.h>
+ *  \endcode
+ *  See \ref avr_sfr for more details about that header file.
+ *
+ *  Included are definitions of the IO register set and their
+ *  respective bit values as specified in the Atmel documentation.
+ *  Note that inconsistencies in naming conventions,
+ *  so even identical functions sometimes get different names on
+ *  different devices.
+ *
+ *  Also included are the specific names useable for interrupt
+ *  function definitions as documented
+ *  \ref avr_signames "here".
+ *
+ *  Finally, the following macros are defined:
+ *
+ *  - \b RAMEND
+ *  <br>
+ *  The last on-chip RAM address.
+ *  <br>
+ *  - \b XRAMEND
+ *  <br>
+ *  The last possible RAM location that is addressable. This is equal to
+ *  RAMEND for devices that do not allow for external RAM. For devices
+ *  that allow external RAM, this will be larger than RAMEND.
+ *  <br>
+ *  - \b E2END
+ *  <br>
+ *  The last EEPROM address.
+ *  <br>
+ *  - \b FLASHEND
+ *  <br>
+ *  The last byte address in the Flash program space.
+ *  <br>
+ *  - \b SPM_PAGESIZE
+ *  <br>
+ *  For devices with bootloader support, the flash pagesize
+ *  (in bytes) to be used for the \c SPM instruction.
+ *  - \b E2PAGESIZE
+ *  <br>
+ *  The size of the EEPROM page.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/** \file */
-/** \defgroup avr_io <avr/io.h>: AVR device-specific IO definitions
-    \code #include <avr/io.h> \endcode
-
-    This header file includes the apropriate IO definitions for the
-    device that has been specified by the <tt>-mmcu=</tt> compiler
-    command-line switch.  This is done by diverting to the appropriate
-    file <tt>&lt;avr/io</tt><em>XXXX</em><tt>.h&gt;</tt> which should
-    never be included directly.  Some register names common to all
-    AVR devices are defined directly within <tt>&lt;avr/common.h&gt;</tt>,
-    which is included in <tt>&lt;avr/io.h&gt;</tt>,
-    but most of the details come from the respective include file.
-
-    Note that this file always includes the following files:
-    \code 
-    #include <avr/sfr_defs.h>
-    #include <avr/portpins.h>
-    #include <avr/common.h>
-    #include <avr/version.h>
-    \endcode
-    See \ref avr_sfr for more details about that header file.
-
-    Included are definitions of the IO register set and their
-    respective bit values as specified in the Atmel documentation.
-    Note that inconsistencies in naming conventions,
-    so even identical functions sometimes get different names on
-    different devices.
-
-    Also included are the specific names useable for interrupt
-    function definitions as documented
-    \ref avr_signames "here".
-
-    Finally, the following macros are defined:
-
-    - \b RAMEND
-    <br>
-    The last on-chip RAM address.
-    <br>
-    - \b XRAMEND
-    <br>
-    The last possible RAM location that is addressable. This is equal to 
-    RAMEND for devices that do not allow for external RAM. For devices 
-    that allow external RAM, this will be larger than RAMEND.
-    <br>
-    - \b E2END
-    <br>
-    The last EEPROM address.
-    <br>
-    - \b FLASHEND
-    <br>
-    The last byte address in the Flash program space.
-    <br>
-    - \b SPM_PAGESIZE
-    <br>
-    For devices with bootloader support, the flash pagesize
-    (in bytes) to be used for the \c SPM instruction. 
-    - \b E2PAGESIZE
-    <br>
-    The size of the EEPROM page.
-    
-*/
+/*
+ *  Copyright (c) 2002,2003,2005,2006,2007 Marek Michalkiewicz, Joerg Wunsch
+ *  Copyright (c) 2007 Eric B. Weddington
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #define _AVR_IO_H_
 
+/**
+ * @defgroup avr_io Input Output
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 #include <avr/sfr_defs.h>
 
 #if defined (__AVR_AT94K__)
@@ -416,4 +425,5 @@
 /* Include lock.h after individual IO header files. */
 #include <avr/lock.h>
 
+/** @} */
 #endif /* _AVR_IO_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io1200.h b/cpukit/score/cpu/avr/avr/io1200.h
index fdb934ff4e..ae2aa17542 100644
--- a/cpukit/score/cpu/avr/avr/io1200.h
+++ b/cpukit/score/cpu/avr/avr/io1200.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file avr/io1200.h
+ *
+ * @brief Definitions for AT90S1200
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-/* avr/io1200.h - definitions for AT90S1200 */
+/*
+ *   Copyright (c) 2002, Marek Michalkiewicz
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO1200_H_
 #define _AVR_IO1200_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_io1200 AT90S1200 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "io1200.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 #ifndef __ASSEMBLER__
 #  warning "MCU not supported by the C compiler"
@@ -266,4 +278,5 @@
 #define SIGNATURE_2 0x01
 
 
+/**@}*/
 #endif  /* _AVR_IO1200_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io2333.h b/cpukit/score/cpu/avr/avr/io2333.h
index 044f5a6b8b..63c7fab337 100644
--- a/cpukit/score/cpu/avr/avr/io2333.h
+++ b/cpukit/score/cpu/avr/avr/io2333.h
@@ -46,8 +46,11 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
-/* I/O registers */
-
+/**
+ * @name I/O Registers
+ * 
+ */
+/**@{**/
 /* UART Baud Rate Register high */
 #define UBRRH	_SFR_IO8(0x03)
 
@@ -171,9 +174,13 @@
 
 /* General Interrupt MaSK register */
 #define GIMSK	_SFR_IO8(0x3B)
+/** @} */
 
-/* Interrupt vectors */
-
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 /* External Interrupt 0 */
 #define INT0_vect			_VECTOR(1)
 #define SIG_INTERRUPT0			_VECTOR(1)
@@ -227,6 +234,7 @@
 #define SIG_COMPARATOR			_VECTOR(13)
 
 #define _VECTORS_SIZE 28
+/** @} */
 
 /*
    The Register Bit names are represented by their bit number (0-7).
@@ -434,10 +442,15 @@
 #define    EEWE      1
 #define    EERE      0
 
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define    RAMEND   0xDF    /*Last On-Chip SRAM location*/
 #define    XRAMEND  RAMEND
 #define    E2END    0x7F
 #define    FLASHEND 0x7FF
+/** @} */
 
 #endif /* _AVR_IO2333_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io2343.h b/cpukit/score/cpu/avr/avr/io2343.h
index bb193917c5..bee4ad4fa7 100644
--- a/cpukit/score/cpu/avr/avr/io2343.h
+++ b/cpukit/score/cpu/avr/avr/io2343.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file avr/io2343.h
+ *
+ * @brief Definitions for AT90S2343
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-/* avr/io2343.h - definitions for AT90S2343 */
+/*
+ *   Copyright (c) 2002, Marek Michalkiewicz
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO2343_H_
 #define _AVR_IO2343_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_io2343 AT90S2343 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "io2343.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -205,4 +217,5 @@
 #define SIGNATURE_2 0x03
 
 
+/**@}*/
 #endif /* _AVR_IO2343_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io43u32x.h b/cpukit/score/cpu/avr/avr/io43u32x.h
index c31a187d94..ed36ff1010 100644
--- a/cpukit/score/cpu/avr/avr/io43u32x.h
+++ b/cpukit/score/cpu/avr/avr/io43u32x.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2003,2005 Keith Gudger
-   All rights reserved.
+/**
+ * @file avr/io43u32x.h
+ *
+ * @brief Definitions for AT43USB32x
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io43u32x.h - definitions for AT43USB32x */
+/*
+ *  Copyright (c) 2003,2005 Keith Gudger
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO43U32X_H_
 #define _AVR_IO43U32X_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_io43u32x AT43USB32x Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "io43u32x.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -70,7 +82,7 @@
 #define DDRE	_SFR_IO8(0x02)
 
 /* Data Register, Port E */
-#define PORTE	_SFR_IO8(0x03) 
+#define PORTE	_SFR_IO8(0x03)
 
 /* SPI Control Register */
 #define SPCR	_SFR_IO8(0x0D)
@@ -432,4 +444,5 @@
    but no RAMPZ causes gcrt1.S build to fail, so assume 64K for now...  */
 #define    FLASHEND 0x0FFFF
 
+/**@}*/
 #endif /* _AVR_43USB32X_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io43u35x.h b/cpukit/score/cpu/avr/avr/io43u35x.h
index d803fa99c0..66a06d867a 100644
--- a/cpukit/score/cpu/avr/avr/io43u35x.h
+++ b/cpukit/score/cpu/avr/avr/io43u35x.h
@@ -46,8 +46,11 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
-/* I/O registers */
-
+/**
+ * @name I/O Registers
+ * 
+ */
+/**@{**/
 /* ADC Data Register */
 #ifndef __ASSEMBLER__
 #define ADC 	_SFR_IO16(0x02)
@@ -179,9 +182,13 @@
 
 /* General Interrupt Mask register */
 #define GIMSK	_SFR_IO8(0x3B)
+/** @} */
 
-/* Interrupt vectors */
-
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 #define SIG_INTERRUPT0		_VECTOR(1)  /* suspend/resume */
 #define SIG_INTERRUPT1		_VECTOR(2)
 #define SIG_TIMER1_CAPT1	_VECTOR(3)
@@ -196,10 +203,11 @@
 #define SIG_USB_INT         _VECTOR(12)
 
 #define _VECTORS_SIZE 52
+/** @} */
 
 /*
-   The Register Bit names are represented by their bit number (0-7).
-*/
+ * The Register Bit names are represented by their bit number (0-7).
+ */
 
 /* Timer/Counter Interrupt MaSK register */
 #define    TICIE1       3
@@ -418,10 +426,15 @@
 #define    ADPS1    1
 #define    ADPS0    0  
 
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define    RAMEND   0x045F     /*Last On-Chip SRAM Location*/
 #define    XRAMEND  RAMEND
 #define    E2END    0x0000
 #define    FLASHEND 0x5FFF
+/** @} */
 
 #endif /* _AVR_43USB355_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io4414.h b/cpukit/score/cpu/avr/avr/io4414.h
index 9c8362c061..96c400030d 100644
--- a/cpukit/score/cpu/avr/avr/io4414.h
+++ b/cpukit/score/cpu/avr/avr/io4414.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for AT90S4414
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2002, Marek Michalkiewicz
    All rights reserved.
 
@@ -46,6 +54,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_io4414 AT90S4414 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 /* Analog Comparator Control and Status Register */
@@ -480,5 +496,6 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x01
 
+/** @} */
 
 #endif /* _AVR_IO4414_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io4433.h b/cpukit/score/cpu/avr/avr/io4433.h
index d0a57e3075..62cbb00cd3 100644
--- a/cpukit/score/cpu/avr/avr/io4433.h
+++ b/cpukit/score/cpu/avr/avr/io4433.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
+/**
+ * @file avr/io4433.h
+ *
+ * @brief Definitions for AT90S4433
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io4433.h - definitions for AT90S4433 */
+/*
+ *   Copyright (c) 2002, Marek Michalkiewicz
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO4433_H_
 #define _AVR_IO4433_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_io4433 AT90S4433 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "io4433.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -468,5 +480,5 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x03
 
-
+/**@}*/
 #endif /* _AVR_IO4433_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io4434.h b/cpukit/score/cpu/avr/avr/io4434.h
index d3719f8fcb..72bc72680d 100644
--- a/cpukit/score/cpu/avr/avr/io4434.h
+++ b/cpukit/score/cpu/avr/avr/io4434.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
+/**
+ * @file avr/io4434.h
+ *
+ * @brief Definitions for AT90S4434
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io4434.h - definitions for AT90S4434 */
+/*
+ *  Copyright (c) 2002 Marek Michalkiewicz
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO4434_H_
 #define _AVR_IO4434_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_io4434 AT90S4434 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "io4434.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -562,5 +574,5 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x03
 
-
+/**@}*/
 #endif /* _AVR_IO4434_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io76c711.h b/cpukit/score/cpu/avr/avr/io76c711.h
index 60e3b744a3..e0c68e2267 100644
--- a/cpukit/score/cpu/avr/avr/io76c711.h
+++ b/cpukit/score/cpu/avr/avr/io76c711.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for AT76C711
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2002, Marek Michalkiewicz
    All rights reserved.
 
@@ -46,6 +54,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_io76c711 AT76C711 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 /* 0x00-0x0C reserved */
@@ -489,4 +505,7 @@
    0x8000 - 0xBFFF - program SRAM (read/write), would be nice if other
                      AVR devices did that as well (no need to use LPM!)
  */
+
+/** @} */
+
 #endif /* _AVR_IO76C711_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io8534.h b/cpukit/score/cpu/avr/avr/io8534.h
index f25cfd269f..c873a71430 100644
--- a/cpukit/score/cpu/avr/avr/io8534.h
+++ b/cpukit/score/cpu/avr/avr/io8534.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for AT90C8534
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2002, Marek Michalkiewicz
    All rights reserved.
 
@@ -46,6 +54,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_io8534 AT90C8534 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 /* 0x00..0x03 reserved */
@@ -212,4 +228,6 @@
 #define E2END		0x1FF
 #define FLASHEND	0x1FFF
 
+/** @} */
+
 #endif /* _AVR_IO8534_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io8535.h b/cpukit/score/cpu/avr/avr/io8535.h
index f0c419b8f5..cf31f00c32 100644
--- a/cpukit/score/cpu/avr/avr/io8535.h
+++ b/cpukit/score/cpu/avr/avr/io8535.h
@@ -1,41 +1,46 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
+/**
+ * @file avr/io8535.h
+ *
+ * @brief Definitions for AT90S8535
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io8535.h - definitions for AT90S8535 */
+/*
+ *  Copyright (c) 2002, Marek Michalkiewicz
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO8535_H_
 #define _AVR_IO8535_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
-
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
 #endif
@@ -44,7 +49,15 @@
 #  define _AVR_IOXXX_H_ "io8535.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
+
+/**
+ * @defgroup AvrDef_io8535 AT90S8535 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* I/O registers */
 
@@ -563,5 +576,5 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x03
 
-
+/** @} */
 #endif /* _AVR_IO8535_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io86r401.h b/cpukit/score/cpu/avr/avr/io86r401.h
index 5fa29c25b4..56f2d568f3 100644
--- a/cpukit/score/cpu/avr/avr/io86r401.h
+++ b/cpukit/score/cpu/avr/avr/io86r401.h
@@ -1,39 +1,52 @@
-/* Copyright (c) 2002, Colin O'Flynn
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/io86r401.h - definitions for AT86RF401 */
+/**
+ * @file avr/io86r401.h
+ *
+ * @brief Definitions for AT86RF401
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2002, Colin O'Flynn
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO86RF401_H_
 #define _AVR_IO86RF401_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_io86r401 AT86RF401 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -83,7 +96,7 @@
 
 #define BTCNT           _SFR_IO8(0x20)
 
-/* 
+/*
 NOTE: EEPROM name's changed to have D in front on them, per datasheet, but
 you may want to remove the leading D.
 */
@@ -304,5 +317,5 @@ you may want to remove the leading D.
 #define SIGNATURE_1 0x91
 #define SIGNATURE_2 0x81
 
-
+/**@}*/
 #endif  /* _AVR_IO86RF401_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm1.h b/cpukit/score/cpu/avr/avr/io90pwm1.h
index ccf77afd07..6c3aad03a5 100644
--- a/cpukit/score/cpu/avr/avr/io90pwm1.h
+++ b/cpukit/score/cpu/avr/avr/io90pwm1.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for AT90PWM1
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2005, Andrey Pashchenko
    Copyright (c) 2007, Anatoly Sokolov
    All rights reserved.
@@ -47,6 +55,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_io90pwm1 AT90PWM1 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 /* Reserved [0x00..0x02] */
@@ -1116,5 +1132,6 @@
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
 
+/** @} */
 
 #endif /* _AVR_IOPWM1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm216.h b/cpukit/score/cpu/avr/avr/io90pwm216.h
index 70682e7bcd..c6befa4081 100644
--- a/cpukit/score/cpu/avr/avr/io90pwm216.h
+++ b/cpukit/score/cpu/avr/avr/io90pwm216.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for AT90PWM216
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2007, Atmel Corporation
    All rights reserved.
 
@@ -46,6 +54,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_io90pwm216 AT90PWM216 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 /* Port B Input Pins Address */
@@ -1176,5 +1192,6 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x83
 
+/** @} */
 
 #endif /* _AVR_IO90PWM216_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm2b.h b/cpukit/score/cpu/avr/avr/io90pwm2b.h
index 14a3893366..22d0c1c379 100644
--- a/cpukit/score/cpu/avr/avr/io90pwm2b.h
+++ b/cpukit/score/cpu/avr/avr/io90pwm2b.h
@@ -1,38 +1,42 @@
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/io90pwm2b.h - definitions for AT90PWM2B */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/io90pwm2b.h
+ *
+ * @brief Definitions for AT90PWM2B
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2007 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *
+ *   * Neither the name of the copyright holders nor the names of
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -42,12 +46,20 @@
 #  define _AVR_IOXXX_H_ "io90pwm2b.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_IO90PWM2B_H_
 #define _AVR_IO90PWM2B_H_ 1
 
+/**
+ * @defgroup Avr_io90pwm2b AT90PWM2B Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Registers and associated bit numbers */
 
 #define PINB _SFR_IO8(0x03)
@@ -79,7 +91,7 @@
 #define PORTB5 5
 #define PORTB6 6
 #define PORTB7 7
-      
+
 #define PINC _SFR_IO8(0x06)
 #define PINC0 0
 #define PINC1 1
@@ -817,7 +829,7 @@
 #define STP0 0
 #define STP1 1
 #define F1617 2
-#define FEM 3 
+#define FEM 3
 
 #define MUBRR _SFR_MEM16(0xCC)
 
@@ -1362,7 +1374,7 @@
 #define FUSE_SPIEN     (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
 #define FUSE_DWEN      (unsigned char)~_BV(6)  /* debugWIRE Enable */
 #define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)    
+#define HFUSE_DEFAULT (FUSE_SPIEN)
 
 
 /* Extended Fuse Byte */
@@ -1379,7 +1391,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -1388,4 +1400,5 @@
 #define SIGNATURE_2 0x83
 
 
+/** @} */
 #endif /* _AVR_IO90PWM2B_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm3b.h b/cpukit/score/cpu/avr/avr/io90pwm3b.h
index 0d648fb47d..5b1a7537cb 100644
--- a/cpukit/score/cpu/avr/avr/io90pwm3b.h
+++ b/cpukit/score/cpu/avr/avr/io90pwm3b.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for AT90PWM3B
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2007 Atmel Corporation
    All rights reserved.
 
@@ -48,6 +56,14 @@
 #ifndef _AVR_IO90PWM3B_H_
 #define _AVR_IO90PWM3B_H_ 1
 
+/**
+ * @defgroup AvrDef_io90pwm3b AT90PWM3B Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Registers and associated bit numbers */
 
 #define PINB _SFR_IO8(0x03)
@@ -1387,5 +1403,6 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x83
 
+/** @} */
 
 #endif /* _AVR_IO90PWM3B_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90pwm81.h b/cpukit/score/cpu/avr/avr/io90pwm81.h
index cc013b96b0..b2faea85f6 100644
--- a/cpukit/score/cpu/avr/avr/io90pwm81.h
+++ b/cpukit/score/cpu/avr/avr/io90pwm81.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for AT90PWM81
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2009 Atmel Corporation
    All rights reserved.
 
@@ -43,6 +51,13 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_io90pwm81 AT90PWM81 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 #ifndef _AVR_AT90PWM81_H_
 #define _AVR_AT90PWM81_H_ 1
@@ -1019,6 +1034,7 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x88
 
+/** @} */
 
 #endif /* _AVR_AT90PWM81_H_ */
 
diff --git a/cpukit/score/cpu/avr/avr/io90pwmx.h b/cpukit/score/cpu/avr/avr/io90pwmx.h
index f2db6097f7..b66b65c541 100644
--- a/cpukit/score/cpu/avr/avr/io90pwmx.h
+++ b/cpukit/score/cpu/avr/avr/io90pwmx.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for AT90PWM2(B) and AT90PWM3(B)
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2005, Andrey Pashchenko
    All rights reserved.
 
@@ -46,6 +54,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup io90pwmx AT90PWM2(B) and AT90PWM3(B) Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 /* Port B Input Pins Address */
@@ -1366,5 +1382,6 @@
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
 
+/** @} */
 
 #endif /* _AVR_IO90PWMX_H_ */
diff --git a/cpukit/score/cpu/avr/avr/io90scr100.h b/cpukit/score/cpu/avr/avr/io90scr100.h
index 4451ec8b5d..cb9f59247a 100644
--- a/cpukit/score/cpu/avr/avr/io90scr100.h
+++ b/cpukit/score/cpu/avr/avr/io90scr100.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/io90scr100.h - definitions for AT90SCR100 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/io90scr100.h
+ *
+ * @brief Definitions for AT90SCR100
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "io90scr100.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_AT90SCR100_H_
 #define _AVR_AT90SCR100_H_ 1
 
+/**
+ *  @defgroup Avr_io90scr100 AT90SCR100 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -1693,5 +1704,5 @@
 #define SIGNATURE_2 0xC1
 
 
+/**@}*/
 #endif /* _AVR_AT90SCR100_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/ioa6289.h b/cpukit/score/cpu/avr/avr/ioa6289.h
index b5bde6ae40..d51e3a965a 100644
--- a/cpukit/score/cpu/avr/avr/ioa6289.h
+++ b/cpukit/score/cpu/avr/avr/ioa6289.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2008 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/ioa6289.h - definitions for ATA6289 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/ioa6289.h
+ *
+ * @brief Definitions for ATA6289
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2008 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *
+ *   * Neither the name of the copyright holders nor the names of
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,19 @@
 #  define _AVR_IOXXX_H_ "ioa6289.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATA6289_H_
 #define _AVR_ATA6289_H_ 1
 
+/**
+ * @defgroup Avr_ioa6289 ATA6289 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* Registers and associated bit numbers. */
 
@@ -839,5 +851,5 @@
 #define SIGNATURE_2 0x82
 
 
+/** @} */
 #endif /* _AVR_ATA6289_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/ioat94k.h b/cpukit/score/cpu/avr/avr/ioat94k.h
index 68a9fe2cf5..dc0cab6890 100644
--- a/cpukit/score/cpu/avr/avr/ioat94k.h
+++ b/cpukit/score/cpu/avr/avr/ioat94k.h
@@ -1,41 +1,46 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file avr/ioat94k.h
+ *
+ * @brief Definitions for AT94K Series FPSLIC(tm)
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-/* avr/ioat94k.h - definitions for AT94K series FPSLIC(tm) */
+/*
+ *  Copyright (c) 2002 Marek Michalkiewicz
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOAT94K_H_
 #define _AVR_IOAT94K_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
-
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
 #endif
@@ -44,7 +49,14 @@
 #  define _AVR_IOXXX_H_ "ioat94k.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
+
+/**
+ *  @defgroup Avr_ioat94k AT94K Series FPSLIC(tm) Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* I/O registers */
 
@@ -209,33 +221,33 @@
 
 /* Interrupt vectors */
 
-#define SIG_FPGA_INTERRUPT0     _VECTOR(1)   /* FPGA_INT0  */        
+#define SIG_FPGA_INTERRUPT0     _VECTOR(1)   /* FPGA_INT0  */
 #define SIG_INTERRUPT0          _VECTOR(2)   /* EXT_INT0   */
-#define SIG_FPGA_INTERRUPT1     _VECTOR(3)   /* FPGA_INT1  */        
+#define SIG_FPGA_INTERRUPT1     _VECTOR(3)   /* FPGA_INT1  */
 #define SIG_INTERRUPT1          _VECTOR(4)   /* EXT_INT1   */
-#define SIG_FPGA_INTERRUPT2     _VECTOR(5)   /* FPGA_INT2  */        
+#define SIG_FPGA_INTERRUPT2     _VECTOR(5)   /* FPGA_INT2  */
 #define SIG_INTERRUPT2          _VECTOR(6)   /* EXT_INT2   */
-#define SIG_FPGA_INTERRUPT3     _VECTOR(7)   /* FPGA_INT3  */        
+#define SIG_FPGA_INTERRUPT3     _VECTOR(7)   /* FPGA_INT3  */
 #define SIG_INTERRUPT3          _VECTOR(8)   /* EXT_INT3   */
-#define SIG_OUTPUT_COMPARE2     _VECTOR(9)   /* TIM2_COMP  */        
-#define SIG_OVERFLOW2           _VECTOR(10)  /* TIM2_OVF   */        
-#define SIG_INPUT_CAPTURE1      _VECTOR(11)  /* TIM1_CAPT  */        
-#define SIG_OUTPUT_COMPARE1A    _VECTOR(12)  /* TIM1_COMPA */        
-#define SIG_OUTPUT_COMPARE1B    _VECTOR(13)  /* TIM1_COMPB */        
-#define SIG_OVERFLOW1           _VECTOR(14)  /* TIM1_OVF   */        
-#define SIG_OUTPUT_COMPARE0     _VECTOR(15)  /* TIM0_COMP  */        
-#define SIG_OVERFLOW0           _VECTOR(16)  /* TIM0_OVF   */        
-#define SIG_FPGA_INTERRUPT4     _VECTOR(17)  /* FPGA_INT4  */        
-#define SIG_FPGA_INTERRUPT5     _VECTOR(18)  /* FPGA_INT5  */        
-#define SIG_FPGA_INTERRUPT6     _VECTOR(19)  /* FPGA_INT6  */        
-#define SIG_FPGA_INTERRUPT7     _VECTOR(20)  /* FPGA_INT7  */        
+#define SIG_OUTPUT_COMPARE2     _VECTOR(9)   /* TIM2_COMP  */
+#define SIG_OVERFLOW2           _VECTOR(10)  /* TIM2_OVF   */
+#define SIG_INPUT_CAPTURE1      _VECTOR(11)  /* TIM1_CAPT  */
+#define SIG_OUTPUT_COMPARE1A    _VECTOR(12)  /* TIM1_COMPA */
+#define SIG_OUTPUT_COMPARE1B    _VECTOR(13)  /* TIM1_COMPB */
+#define SIG_OVERFLOW1           _VECTOR(14)  /* TIM1_OVF   */
+#define SIG_OUTPUT_COMPARE0     _VECTOR(15)  /* TIM0_COMP  */
+#define SIG_OVERFLOW0           _VECTOR(16)  /* TIM0_OVF   */
+#define SIG_FPGA_INTERRUPT4     _VECTOR(17)  /* FPGA_INT4  */
+#define SIG_FPGA_INTERRUPT5     _VECTOR(18)  /* FPGA_INT5  */
+#define SIG_FPGA_INTERRUPT6     _VECTOR(19)  /* FPGA_INT6  */
+#define SIG_FPGA_INTERRUPT7     _VECTOR(20)  /* FPGA_INT7  */
 #define SIG_UART0_RECV          _VECTOR(21)  /* UART0_RXC  */
 #define SIG_UART0_DATA          _VECTOR(22)  /* UART0_DRE  */
 #define SIG_UART0_TRANS         _VECTOR(23)  /* UART0_TXC  */
-#define SIG_FPGA_INTERRUPT8     _VECTOR(24)  /* FPGA_INT8  */        
-#define SIG_FPGA_INTERRUPT9     _VECTOR(25)  /* FPGA_INT9  */        
-#define SIG_FPGA_INTERRUPT10    _VECTOR(26)  /* FPGA_INT10 */        
-#define SIG_FPGA_INTERRUPT11    _VECTOR(27)  /* FPGA_INT11 */        
+#define SIG_FPGA_INTERRUPT8     _VECTOR(24)  /* FPGA_INT8  */
+#define SIG_FPGA_INTERRUPT9     _VECTOR(25)  /* FPGA_INT9  */
+#define SIG_FPGA_INTERRUPT10    _VECTOR(26)  /* FPGA_INT10 */
+#define SIG_FPGA_INTERRUPT11    _VECTOR(27)  /* FPGA_INT11 */
 #define SIG_UART1_RECV          _VECTOR(28)  /* UART1_RXC  */
 #define SIG_UART1_DATA          _VECTOR(29)  /* UART1_DRE  */
 #define SIG_UART1_TRANS         _VECTOR(30)  /* UART1_TXC  */
@@ -553,4 +565,5 @@
 #define FLASHEND 0x7FFF
 #endif
 
+/**@}*/
 #endif /* _AVR_IOAT94K_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iocan32.h b/cpukit/score/cpu/avr/avr/iocan32.h
index 8833f653f0..512b45d7b5 100644
--- a/cpukit/score/cpu/avr/avr/iocan32.h
+++ b/cpukit/score/cpu/avr/avr/iocan32.h
@@ -1,39 +1,54 @@
-/* Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iocan32.h - definitions for CAN32 */
+/**
+ * @file iocan32.h
+ *
+ * @brief Definitions for CAN32
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2004,2005, Anatoly Sokolov <aesok@pautinka.net>
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOCAN32_H_
 #define _AVR_IOCAN32_H_ 1
 
+/**
+ * @defgroup AvrDef_CAN32 CAN32 Defintions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 #include <avr/iocanxx.h>
 
 /* Constants */
@@ -81,7 +96,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -90,4 +105,5 @@
 #define SIGNATURE_2 0x81
 
 
+/** @} */
 #endif  /* _AVR_IOCAN32_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iocanxx.h b/cpukit/score/cpu/avr/avr/iocanxx.h
index 70c073a640..a593539cb1 100644
--- a/cpukit/score/cpu/avr/avr/iocanxx.h
+++ b/cpukit/score/cpu/avr/avr/iocanxx.h
@@ -1,48 +1,60 @@
-/* Copyright (c) 2004,2005,2006 Colin O'Flynn <coflynn@newae.com>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* This file is based largely on:
-   - iom128.h by Peter Jansen (bit defines)
-   - iom169.h by Juergen Schilling <juergen.schilling@honeywell.com>
-     (register addresses)
-   - AT90CAN128 Datasheet (bit defines and register addresses)
-   - Appnote on Mega128 --> AT90Can128 Conversion (for what registers I need
-     to change) */
-
-/* iocanxx.h - definitions for AT90CAN32, AT90CAN64 and AT90CAN128 */
+/**
+ * @file iocanxx.h
+ *
+ * @brief Definitions for AT90CAN32, AT90CAN64 and AT90CAN128
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ *
+ * This file is based largely on:
+ * - iom128.h by Peter Jansen (bit defines)
+ * - iom169.h by Juergen Schilling <juergen.schilling@honeywell.com>
+ *   (register addresses)
+ * - AT90CAN128 Datasheet (bit defines and register addresses)
+ * - Appnote on Mega128 --> AT90Can128 Conversion (for what registers I need
+ *   to change)
+ */
+
+/*
+ *   Copyright (c) 2004,2005,2006 Colin O'Flynn <coflynn@newae.com>
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOCANXX_H_
 #define _AVR_IOCANXX_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iocanxx AT90CAN32, AT90CAN64, AT90CAN128 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -52,7 +64,7 @@
 #  define _AVR_IOXXX_H_ "iocanxx.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers and bit definitions. */
 
@@ -951,9 +963,9 @@
 #define    ADPS0        0
 /* End Register Bits */
 
-/* 
-   The ADHSM bit has been removed from all documentation, 
-   as being not needed at all since the comparator has proven 
+/*
+   The ADHSM bit has been removed from all documentation,
+   as being not needed at all since the comparator has proven
    to be fast enough even without feeding it more power.
 */
 
@@ -1974,4 +1986,5 @@
 
 /* End Verbatim */
 
+/**@}*/
 #endif  /* _AVR_IOCANXX_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom103.h b/cpukit/score/cpu/avr/avr/iom103.h
index 0f4816ff07..6ca791b100 100644
--- a/cpukit/score/cpu/avr/avr/iom103.h
+++ b/cpukit/score/cpu/avr/avr/iom103.h
@@ -1,41 +1,46 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
+/**
+ * @file avr/iom103.h
+ *
+ * @brief Definitions for ATmega103
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom103.h - definitions for ATmega103 */
+/*
+ *  Copyright (c) 2002, Marek Michalkiewicz
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM103_H_
 #define _AVR_IOM103_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
-
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
 #endif
@@ -44,7 +49,15 @@
 #  define _AVR_IOXXX_H_ "iom103.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
+
+/**
+ * @defgroup AvrDef_iom103 ATmega103 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* I/O registers */
 
@@ -670,5 +683,5 @@
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x01
 
-
+/** @} */
 #endif /* _AVR_IOM103_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom128.h b/cpukit/score/cpu/avr/avr/iom128.h
index 0a41879f23..7eeb3f57e6 100644
--- a/cpukit/score/cpu/avr/avr/iom128.h
+++ b/cpukit/score/cpu/avr/avr/iom128.h
@@ -1,44 +1,56 @@
-/* Copyright (c) 2002, Peter Jansen
-   Copyright (c) 2007, Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iom128.h
+ *
+ * @brief Definitions for ATmega128
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ *
+ *  As of 2002-08-27:
+ *  - This should be up to date with data sheet 2467E-AVR-05/02
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom128.h - defines for ATmega128 
-
-   As of 2002-08-27:
-   - This should be up to date with data sheet 2467E-AVR-05/02 */
+/*
+ *  Copyright (c) 2002, Peter Jansen
+ *  Copyright (c) 2007, Atmel Corporation
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM128_H_
 #define _AVR_IOM128_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom128 ATmega128 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -48,7 +60,7 @@
 #  define _AVR_IOXXX_H_ "iom128.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -793,9 +805,9 @@
 #define    WDP1         1
 #define    WDP0         0
 
-/* 
-   The ADHSM bit has been removed from all documentation, 
-   as being not needed at all since the comparator has proven 
+/*
+   The ADHSM bit has been removed from all documentation,
+   as being not needed at all since the comparator has proven
    to be fast enough even without feeding it more power.
 */
 
@@ -965,7 +977,7 @@
 #define    PINA5        5
 #define    PINA4        4
 #define    PINA3        3
-#define    PINA2        2 
+#define    PINA2        2
 #define    PINA1        1
 #define    PINA0        0
 
@@ -995,7 +1007,7 @@
 #define    PINB5        5
 #define    PINB4        4
 #define    PINB3        3
-#define    PINB2        2 
+#define    PINB2        2
 #define    PINB1        1
 #define    PINB0        0
 
@@ -1025,7 +1037,7 @@
 #define    PINC5        5
 #define    PINC4        4
 #define    PINC3        3
-#define    PINC2        2 
+#define    PINC2        2
 #define    PINC1        1
 #define    PINC0        0
 
@@ -1055,7 +1067,7 @@
 #define    PIND5        5
 #define    PIND4        4
 #define    PIND3        3
-#define    PIND2        2 
+#define    PIND2        2
 #define    PIND1        1
 #define    PIND0        0
 
@@ -1085,7 +1097,7 @@
 #define    PINE5        5
 #define    PINE4        4
 #define    PINE3        3
-#define    PINE2        2 
+#define    PINE2        2
 #define    PINE1        1
 #define    PINE0        0
 
@@ -1115,7 +1127,7 @@
 #define    PINF5        5
 #define    PINF4        4
 #define    PINF3        3
-#define    PINF2        2 
+#define    PINF2        2
 #define    PINF1        1
 #define    PINF0        0
 
@@ -1136,7 +1148,7 @@
 /* Port G Input Pins - PING */
 #define    PING4        4
 #define    PING3        3
-#define    PING2        2 
+#define    PING2        2
 #define    PING1        1
 #define    PING0        0
 
@@ -1190,7 +1202,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -1199,4 +1211,5 @@
 #define SIGNATURE_2 0x02
 
 
+/**@}*/
 #endif /* _AVR_IOM128_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom1280.h b/cpukit/score/cpu/avr/avr/iom1280.h
index 5bed7c9a43..a6aff362b8 100644
--- a/cpukit/score/cpu/avr/avr/iom1280.h
+++ b/cpukit/score/cpu/avr/avr/iom1280.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega1280
+ */
+
 /* Copyright (c) 2005 Anatoly Sokolov 
    All rights reserved.
 
@@ -36,6 +42,14 @@
 
 #include <avr/iomxx0_1.h>
 
+/**
+ * @defgroup AvrDef_iom1280 ATmega1280 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Constants */
 #define SPM_PAGESIZE    256
 #define RAMEND          0x21FF
@@ -89,5 +103,6 @@
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x03
 
+/** @} */
 
 #endif /* _AVR_IOM1280_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom1281.h b/cpukit/score/cpu/avr/avr/iom1281.h
index 39f6916ed1..8b764c675e 100644
--- a/cpukit/score/cpu/avr/avr/iom1281.h
+++ b/cpukit/score/cpu/avr/avr/iom1281.h
@@ -1,39 +1,52 @@
-/* Copyright (c) 2005 Anatoly Sokolov 
-   All rights reserved.
+/**
+ * @file avr/iom1281.h
+ *
+ * @brief Definitions for ATmega1281
+ */
+
+/*
+ *  Copyright (c) 2005 Anatoly Sokolov
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom1281.h - definitions for ATmega1281 */
 
 #ifndef _AVR_IOM1281_H_
 #define _AVR_IOM1281_H_ 1
 
+/**
+ *  @defgroup Avr_iom1281 ATmega1281 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #include <avr/iomxx0_1.h>
 
 /* Constants */
@@ -81,7 +94,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -89,5 +102,5 @@
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x04
 
-
+/**@}*/
 #endif /* _AVR_IOM1281_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom1284p.h b/cpukit/score/cpu/avr/avr/iom1284p.h
index 0e5a6f5cd6..3076de21c6 100644
--- a/cpukit/score/cpu/avr/avr/iom1284p.h
+++ b/cpukit/score/cpu/avr/avr/iom1284p.h
@@ -1,1131 +1,1141 @@
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iom1284p.h - definitions for ATmega1284P. */
-
-/* This file should only be included from <avr/io.h>, never directly. */
-
-#ifndef _AVR_IO_H_
-#  error "Include <avr/io.h> instead of this file."
-#endif
-
-#ifndef _AVR_IOXXX_H_
-#  define _AVR_IOXXX_H_ "iom1284p.h"
-#else
-#  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
-
-
-#ifndef _AVR_IOM1284P_H_
-#define _AVR_IOM1284P_H_ 1
-
-
-/* Registers and associated bit numbers */
-
-#define PINA _SFR_IO8(0x00)
-#define PINA0 0
-#define PINA1 1
-#define PINA2 2
-#define PINA3 3
-#define PINA4 4
-#define PINA5 5
-#define PINA6 6
-#define PINA7 7
-
-#define DDRA _SFR_IO8(0x01)
-#define DDA0 0
-#define DDA1 1
-#define DDA2 2
-#define DDA3 3
-#define DDA4 4
-#define DDA5 5
-#define DDA6 6
-#define DDA7 7
-
-#define PORTA _SFR_IO8(0x02)
-#define PORTA0 0
-#define PORTA1 1
-#define PORTA2 2
-#define PORTA3 3
-#define PORTA4 4
-#define PORTA5 5
-#define PORTA6 6
-#define PORTA7 7
-
-#define PINB _SFR_IO8(0x03)
-#define PINB0 0
-#define PINB1 1
-#define PINB2 2
-#define PINB3 3
-#define PINB4 4
-#define PINB5 5
-#define PINB6 6
-#define PINB7 7
-
-#define DDRB _SFR_IO8(0x04)
-#define DDB0 0
-#define DDB1 1
-#define DDB2 2
-#define DDB3 3
-#define DDB4 4
-#define DDB5 5
-#define DDB6 6
-#define DDB7 7
-
-#define PORTB _SFR_IO8(0x05)
-#define PORTB0 0
-#define PORTB1 1
-#define PORTB2 2
-#define PORTB3 3
-#define PORTB4 4
-#define PORTB5 5
-#define PORTB6 6
-#define PORTB7 7
-
-#define PINC _SFR_IO8(0x06)
-#define PINC0 0
-#define PINC1 1
-#define PINC2 2
-#define PINC3 3
-#define PINC4 4
-#define PINC5 5
-#define PINC6 6
-#define PINC7 7
-
-#define DDRC _SFR_IO8(0x07)
-#define DDC0 0
-#define DDC1 1
-#define DDC2 2
-#define DDC3 3
-#define DDC4 4
-#define DDC5 5
-#define DDC6 6
-#define DDC7 7
-
-#define PORTC _SFR_IO8(0x08)
-#define PORTC0 0
-#define PORTC1 1
-#define PORTC2 2
-#define PORTC3 3
-#define PORTC4 4
-#define PORTC5 5
-#define PORTC6 6
-#define PORTC7 7
-
-#define PIND _SFR_IO8(0x09)
-#define PIND0 0
-#define PIND1 1
-#define PIND2 2
-#define PIND3 3
-#define PIND4 4
-#define PIND5 5
-#define PIND6 6
-#define PIND7 7
-
-#define DDRD _SFR_IO8(0x0A)
-#define DDD0 0
-#define DDD1 1
-#define DDD2 2
-#define DDD3 3
-#define DDD4 4
-#define DDD5 5
-#define DDD6 6
-#define DDD7 7
-
-#define PORTD _SFR_IO8(0x0B)
-#define PORTD0 0
-#define PORTD1 1
-#define PORTD2 2
-#define PORTD3 3
-#define PORTD4 4
-#define PORTD5 5
-#define PORTD6 6
-#define PORTD7 7
-
-#define TIFR0 _SFR_IO8(0x15)
-#define TOV0 0
-#define OCF0A 1
-#define OCF0B 2
-
-#define TIFR1 _SFR_IO8(0x16)
-#define TOV1 0
-#define OCF1A 1
-#define OCF1B 2
-#define ICF1 5
-
-#define TIFR2 _SFR_IO8(0x17)
-#define TOV2 0
-#define OCF2A 1
-#define OCF2B 2
-
-#define TIFR3 _SFR_IO8(0x18)
-#define TOV3 0
-#define OCF3A 1
-#define OCF3B 2
-#define ICF3 5
-
-#define PCIFR _SFR_IO8(0x1B)
-#define PCIF0 0
-#define PCIF1 1
-#define PCIF2 2
-#define PCIF3 3
-
-#define EIFR _SFR_IO8(0x1C)
-#define INTF0 0
-#define INTF1 1
-#define INTF2 2
-
-#define EIMSK _SFR_IO8(0x1D)
-#define INT0 0
-#define INT1 1
-#define INT2 2
-
-#define GPIOR0 _SFR_IO8(0x1E)
-#define GPIOR00 0
-#define GPIOR01 1
-#define GPIOR02 2
-#define GPIOR03 3
-#define GPIOR04 4
-#define GPIOR05 5
-#define GPIOR06 6
-#define GPIOR07 7
-
-#define EECR _SFR_IO8(0x1F)
-#define EERE 0
-#define EEPE 1
-#define EEMPE 2
-#define EERIE 3
-#define EEPM0 4
-#define EEPM1 5
-
-#define EEDR _SFR_IO8(0x20)
-#define EEDR0 0
-#define EEDR1 1
-#define EEDR2 2
-#define EEDR3 3
-#define EEDR4 4
-#define EEDR5 5
-#define EEDR6 6
-#define EEDR7 7
-
-#define EEAR _SFR_IO16(0x21)
-
-#define EEARL _SFR_IO8(0x21)
-#define EEAR0 0
-#define EEAR1 1
-#define EEAR2 2
-#define EEAR3 3
-#define EEAR4 4
-#define EEAR5 5
-#define EEAR6 6
-#define EEAR7 7
-
-#define EEARH _SFR_IO8(0x22)
-#define EEAR8 0
-#define EEAR9 1
-#define EEAR10 2
-#define EEAR11 3
-
-#define GTCCR _SFR_IO8(0x23)
-#define PSRSYNC 0
-#define PSRASY 1
-#define TSM 7
-
-#define TCCR0A _SFR_IO8(0x24)
-#define WGM00 0
-#define WGM01 1
-#define COM0B0 4
-#define COM0B1 5
-#define COM0A0 6
-#define COM0A1 7
-
-#define TCCR0B _SFR_IO8(0x25)
-#define CS00 0
-#define CS01 1
-#define CS02 2
-#define WGM02 3
-#define FOC0B 6
-#define FOC0A 7
-
-#define TCNT0 _SFR_IO8(0x26)
-#define TCNT0_0 0
-#define TCNT0_1 1
-#define TCNT0_2 2
-#define TCNT0_3 3
-#define TCNT0_4 4
-#define TCNT0_5 5
-#define TCNT0_6 6
-#define TCNT0_7 7
-
-#define OCR0A _SFR_IO8(0x27)
-#define OCR0A_0 0
-#define OCR0A_1 1
-#define OCR0A_2 2
-#define OCR0A_3 3
-#define OCR0A_4 4
-#define OCR0A_5 5
-#define OCR0A_6 6
-#define OCR0A_7 7
-
-#define OCR0B _SFR_IO8(0x28)
-#define OCR0B_0 0
-#define OCR0B_1 1
-#define OCR0B_2 2
-#define OCR0B_3 3
-#define OCR0B_4 4
-#define OCR0B_5 5
-#define OCR0B_6 6
-#define OCR0B_7 7
-
-#define GPIOR1 _SFR_IO8(0x2A)
-#define GPIOR10 0
-#define GPIOR11 1
-#define GPIOR12 2
-#define GPIOR13 3
-#define GPIOR14 4
-#define GPIOR15 5
-#define GPIOR16 6
-#define GPIOR17 7
-
-#define GPIOR2 _SFR_IO8(0x2B)
-#define GPIOR20 0
-#define GPIOR21 1
-#define GPIOR22 2
-#define GPIOR23 3
-#define GPIOR24 4
-#define GPIOR25 5
-#define GPIOR26 6
-#define GPIOR27 7
-
-#define SPCR _SFR_IO8(0x2C)
-#define SPR0 0
-#define SPR1 1
-#define CPHA 2
-#define CPOL 3
-#define MSTR 4
-#define DORD 5
-#define SPE 6
-#define SPIE 7
-
-#define SPSR _SFR_IO8(0x2D)
-#define SPI2X 0
-#define WCOL 6
-#define SPIF 7
-
-#define SPDR _SFR_IO8(0x2E)
-#define SPDR0 0
-#define SPDR1 1
-#define SPDR2 2
-#define SPDR3 3
-#define SPDR4 4
-#define SPDR5 5
-#define SPDR6 6
-#define SPDR7 7
-
-#define ACSR _SFR_IO8(0x30)
-#define ACIS0 0
-#define ACIS1 1
-#define ACIC 2
-#define ACIE 3
-#define ACI 4
-#define ACO 5
-#define ACBG 6
-#define ACD 7
-
-#define OCDR _SFR_IO8(0x31)
-#define OCDR0 0
-#define OCDR1 1
-#define OCDR2 2
-#define OCDR3 3
-#define OCDR4 4
-#define OCDR5 5
-#define OCDR6 6
-#define OCDR7 7
-
-#define SMCR _SFR_IO8(0x33)
-#define SE 0
-#define SM0 1
-#define SM1 2
-#define SM2 3
-
-#define MCUSR _SFR_IO8(0x34)
-#define PORF 0
-#define EXTRF 1
-#define BORF 2
-#define WDRF 3
-#define JTRF 4
-
-#define MCUCR _SFR_IO8(0x35)
-#define IVCE 0
-#define IVSEL 1
-#define PUD 4
-#define BODSE 5
-#define BODS 6
-#define JTD 7
-
-#define SPMCSR _SFR_IO8(0x37)
-#define SPMEN 0
-#define PGERS 1
-#define PGWRT 2
-#define BLBSET 3
-#define RWWSRE 4
-#define SIGRD 5
-#define RWWSB 6
-#define SPMIE 7
-
-#define RAMPZ _SFR_IO8(0x3B)
-#define RAMPZ0 0
-
-#define WDTCSR _SFR_MEM8(0x60)
-#define WDP0 0
-#define WDP1 1
-#define WDP2 2
-#define WDE 3
-#define WDCE 4
-#define WDP3 5
-#define WDIE 6
-#define WDIF 7
-
-#define CLKPR _SFR_MEM8(0x61)
-#define CLKPS0 0
-#define CLKPS1 1
-#define CLKPS2 2
-#define CLKPS3 3
-#define CLKPCE 7
-
-#define PRR0 _SFR_MEM8(0x64)
-#define PRADC 0
-#define PRUSART0 1
-#define PRSPI 2
-#define PRTIM1 3
-#define PRUSART1 4
-#define PRTIM0 5
-#define PRTIM2 6
-#define PRTWI 7
-
-#define PRR1 _SFR_MEM8(0x65)
-#define PRTIM3 0
-
-#define OSCCAL _SFR_MEM8(0x66)
-#define CAL0 0
-#define CAL1 1
-#define CAL2 2
-#define CAL3 3
-#define CAL4 4
-#define CAL5 5
-#define CAL6 6
-#define CAL7 7
-
-#define PCICR _SFR_MEM8(0x68)
-#define PCIE0 0
-#define PCIE1 1
-#define PCIE2 2
-#define PCIE3 3
-
-#define EICRA _SFR_MEM8(0x69)
-#define ISC00 0
-#define ISC01 1
-#define ISC10 2
-#define ISC11 3
-#define ISC20 4
-#define ISC21 5
-
-#define PCMSK0 _SFR_MEM8(0x6B)
-#define PCINT0 0
-#define PCINT1 1
-#define PCINT2 2
-#define PCINT3 3
-#define PCINT4 4
-#define PCINT5 5
-#define PCINT6 6
-#define PCINT7 7
-
-#define PCMSK1 _SFR_MEM8(0x6C)
-#define PCINT8 0
-#define PCINT9 1
-#define PCINT10 2
-#define PCINT11 3
-#define PCINT12 4
-#define PCINT13 5
-#define PCINT14 6
-#define PCINT15 7
-
-#define PCMSK2 _SFR_MEM8(0x6D)
-#define PCINT16 0
-#define PCINT17 1
-#define PCINT18 2
-#define PCINT19 3
-#define PCINT20 4
-#define PCINT21 5
-#define PCINT22 6
-#define PCINT23 7
-
-#define TIMSK0 _SFR_MEM8(0x6E)
-#define TOIE0 0
-#define OCIE0A 1
-#define OCIE0B 2
-
-#define TIMSK1 _SFR_MEM8(0x6F)
-#define TOIE1 0
-#define OCIE1A 1
-#define OCIE1B 2
-#define ICIE1 5
-
-#define TIMSK2 _SFR_MEM8(0x70)
-#define TOIE2 0
-#define OCIE2A 1
-#define OCIE2B 2
-
-#define TIMSK3 _SFR_MEM8(0x71)
-#define TOIE3 0
-#define OCIE3A 1
-#define OCIE3B 2
-#define ICIE3 5
-
-#define PCMSK3 _SFR_MEM8(0x73)
-#define PCINT24 0
-#define PCINT25 1
-#define PCINT26 2
-#define PCINT27 3
-#define PCINT28 4
-#define PCINT29 5
-#define PCINT30 6
-#define PCINT31 7
-
-#ifndef __ASSEMBLER__
-#define ADC     _SFR_MEM16(0x78)
-#endif
-#define ADCW    _SFR_MEM16(0x78)
-
-#define ADCL _SFR_MEM8(0x78)
-#define ADCL0 0
-#define ADCL1 1
-#define ADCL2 2
-#define ADCL3 3
-#define ADCL4 4
-#define ADCL5 5
-#define ADCL6 6
-#define ADCL7 7
-
-#define ADCH _SFR_MEM8(0x79)
-#define ADCH0 0
-#define ADCH1 1
-#define ADCH2 2
-#define ADCH3 3
-#define ADCH4 4
-#define ADCH5 5
-#define ADCH6 6
-#define ADCH7 7
-
-#define ADCSRA _SFR_MEM8(0x7A)
-#define ADPS0 0
-#define ADPS1 1
-#define ADPS2 2
-#define ADIE 3
-#define ADIF 4
-#define ADATE 5
-#define ADSC 6
-#define ADEN 7
-
-#define ADCSRB _SFR_MEM8(0x7B)
-#define ADTS0 0
-#define ADTS1 1
-#define ADTS2 2
-#define ACME 6
-
-#define ADMUX _SFR_MEM8(0x7C)
-#define MUX0 0
-#define MUX1 1
-#define MUX2 2
-#define MUX3 3
-#define MUX4 4
-#define ADLAR 5
-#define REFS0 6
-#define REFS1 7
-
-#define DIDR0 _SFR_MEM8(0x7E)
-#define ADC0D 0
-#define ADC1D 1
-#define ADC2D 2
-#define ADC3D 3
-#define ADC4D 4
-#define ADC5D 5
-#define ADC6D 6
-#define ADC7D 7
-
-#define DIDR1 _SFR_MEM8(0x7F)
-#define AIN0D 0
-#define AIN1D 1
-
-#define TCCR1A _SFR_MEM8(0x80)
-#define WGM10 0
-#define WGM11 1
-#define COM1B0 4
-#define COM1B1 5
-#define COM1A0 6
-#define COM1A1 7
-
-#define TCCR1B _SFR_MEM8(0x81)
-#define CS10 0
-#define CS11 1
-#define CS12 2
-#define WGM12 3
-#define WGM13 4
-#define ICES1 6
-#define ICNC1 7
-
-#define TCCR1C _SFR_MEM8(0x82)
-#define FOC1B 6
-#define FOC1A 7
-
-#define TCNT1 _SFR_MEM16(0x84)
-
-#define TCNT1L _SFR_MEM8(0x84)
-#define TCNT1L0 0
-#define TCNT1L1 1
-#define TCNT1L2 2
-#define TCNT1L3 3
-#define TCNT1L4 4
-#define TCNT1L5 5
-#define TCNT1L6 6
-#define TCNT1L7 7
-
-#define TCNT1H _SFR_MEM8(0x85)
-#define TCNT1H0 0
-#define TCNT1H1 1
-#define TCNT1H2 2
-#define TCNT1H3 3
-#define TCNT1H4 4
-#define TCNT1H5 5
-#define TCNT1H6 6
-#define TCNT1H7 7
-
-#define ICR1 _SFR_MEM16(0x86)
-
-#define ICR1L _SFR_MEM8(0x86)
-#define ICR1L0 0
-#define ICR1L1 1
-#define ICR1L2 2
-#define ICR1L3 3
-#define ICR1L4 4
-#define ICR1L5 5
-#define ICR1L6 6
-#define ICR1L7 7
-
-#define ICR1H _SFR_MEM8(0x87)
-#define ICR1H0 0
-#define ICR1H1 1
-#define ICR1H2 2
-#define ICR1H3 3
-#define ICR1H4 4
-#define ICR1H5 5
-#define ICR1H6 6
-#define ICR1H7 7
-
-#define OCR1A _SFR_MEM16(0x88)
-
-#define OCR1AL _SFR_MEM8(0x88)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1AH _SFR_MEM8(0x89)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define OCR1B _SFR_MEM16(0x8A)
-
-#define OCR1BL _SFR_MEM8(0x8A)
-#define OCR1AL0 0
-#define OCR1AL1 1
-#define OCR1AL2 2
-#define OCR1AL3 3
-#define OCR1AL4 4
-#define OCR1AL5 5
-#define OCR1AL6 6
-#define OCR1AL7 7
-
-#define OCR1BH _SFR_MEM8(0x8B)
-#define OCR1AH0 0
-#define OCR1AH1 1
-#define OCR1AH2 2
-#define OCR1AH3 3
-#define OCR1AH4 4
-#define OCR1AH5 5
-#define OCR1AH6 6
-#define OCR1AH7 7
-
-#define TCCR3A _SFR_MEM8(0x90)
-#define WGM30 0
-#define WGM31 1
-#define COM3B0 4
-#define COM3B1 5
-#define COM3A0 6
-#define COM3A1 7
-
-#define TCCR3B _SFR_MEM8(0x91)
-#define CS30 0
-#define CS31 1
-#define CS32 2
-#define WGM32 3
-#define WGM33 4
-#define ICES3 6
-#define ICNC3 7
-
-#define TCCR3C _SFR_MEM8(0x92)
-#define FOC3B 6
-#define FOC3A 7
-
-#define TCNT3 _SFR_MEM16(0x94)
-
-#define TCNT3L _SFR_MEM8(0x94)
-#define TCNT3L0 0
-#define TCNT3L1 1
-#define TCNT3L2 2
-#define TCNT3L3 3
-#define TCNT3L4 4
-#define TCNT3L5 5
-#define TCNT3L6 6
-#define TCNT3L7 7
-
-#define TCNT3H _SFR_MEM8(0x95)
-#define TCNT3H0 0
-#define TCNT3H1 1
-#define TCNT3H2 2
-#define TCNT3H3 3
-#define TCNT3H4 4
-#define TCNT3H5 5
-#define TCNT3H6 6
-#define TCNT3H7 7
-
-#define ICR3 _SFR_MEM16(0x96)
-
-#define ICR3L _SFR_MEM8(0x96)
-#define ICR3L0 0
-#define ICR3L1 1
-#define ICR3L2 2
-#define ICR3L3 3
-#define ICR3L4 4
-#define ICR3L5 5
-#define ICR3L6 6
-#define ICR3L7 7
-
-#define ICR3H _SFR_MEM8(0x97)
-#define ICR3H0 0
-#define ICR3H1 1
-#define ICR3H2 2
-#define ICR3H3 3
-#define ICR3H4 4
-#define ICR3H5 5
-#define ICR3H6 6
-#define ICR3H7 7
-
-#define OCR3A _SFR_MEM16(0x98)
-
-#define OCR3AL _SFR_MEM8(0x98)
-#define OCR3AL0 0
-#define OCR3AL1 1
-#define OCR3AL2 2
-#define OCR3AL3 3
-#define OCR3AL4 4
-#define OCR3AL5 5
-#define OCR3AL6 6
-#define OCR3AL7 7
-
-#define OCR3AH _SFR_MEM8(0x99)
-#define OCR3AH0 0
-#define OCR3AH1 1
-#define OCR3AH2 2
-#define OCR3AH3 3
-#define OCR3AH4 4
-#define OCR3AH5 5
-#define OCR3AH6 6
-#define OCR3AH7 7
-
-#define OCR3B _SFR_MEM16(0x9A)
-
-#define OCR3BL _SFR_MEM8(0x9A)
-#define OCR3AL0 0
-#define OCR3AL1 1
-#define OCR3AL2 2
-#define OCR3AL3 3
-#define OCR3AL4 4
-#define OCR3AL5 5
-#define OCR3AL6 6
-#define OCR3AL7 7
-
-#define OCR3BH _SFR_MEM8(0x9B)
-#define OCR3AH0 0
-#define OCR3AH1 1
-#define OCR3AH2 2
-#define OCR3AH3 3
-#define OCR3AH4 4
-#define OCR3AH5 5
-#define OCR3AH6 6
-#define OCR3AH7 7
-
-#define TCCR2A _SFR_MEM8(0xB0)
-#define WGM20 0
-#define WGM21 1
-#define COM2B0 4
-#define COM2B1 5
-#define COM2A0 6
-#define COM2A1 7
-
-#define TCCR2B _SFR_MEM8(0xB1)
-#define CS20 0
-#define CS21 1
-#define CS22 2
-#define WGM22 3
-#define FOC2B 6
-#define FOC2A 7
-
-#define TCNT2 _SFR_MEM8(0xB2)
-#define TCNT2_0 0
-#define TCNT2_1 1
-#define TCNT2_2 2
-#define TCNT2_3 3
-#define TCNT2_4 4
-#define TCNT2_5 5
-#define TCNT2_6 6
-#define TCNT2_7 7
-
-#define OCR2A _SFR_MEM8(0xB3)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define OCR2B _SFR_MEM8(0xB4)
-#define OCR2_0 0
-#define OCR2_1 1
-#define OCR2_2 2
-#define OCR2_3 3
-#define OCR2_4 4
-#define OCR2_5 5
-#define OCR2_6 6
-#define OCR2_7 7
-
-#define ASSR _SFR_MEM8(0xB6)
-#define TCR2BUB 0
-#define TCR2AUB 1
-#define OCR2BUB 2
-#define OCR2AUB 3
-#define TCN2UB 4
-#define AS2 5
-#define EXCLK 6
-
-#define TWBR _SFR_MEM8(0xB8)
-#define TWBR0 0
-#define TWBR1 1
-#define TWBR2 2
-#define TWBR3 3
-#define TWBR4 4
-#define TWBR5 5
-#define TWBR6 6
-#define TWBR7 7
-
-#define TWSR _SFR_MEM8(0xB9)
-#define TWPS0 0
-#define TWPS1 1
-#define TWS3 3
-#define TWS4 4
-#define TWS5 5
-#define TWS6 6
-#define TWS7 7
-
-#define TWAR _SFR_MEM8(0xBA)
-#define TWGCE 0
-#define TWA0 1
-#define TWA1 2
-#define TWA2 3
-#define TWA3 4
-#define TWA4 5
-#define TWA5 6
-#define TWA6 7
-
-#define TWDR _SFR_MEM8(0xBB)
-#define TWD0 0
-#define TWD1 1
-#define TWD2 2
-#define TWD3 3
-#define TWD4 4
-#define TWD5 5
-#define TWD6 6
-#define TWD7 7
-
-#define TWCR _SFR_MEM8(0xBC)
-#define TWIE 0
-#define TWEN 2
-#define TWWC 3
-#define TWSTO 4
-#define TWSTA 5
-#define TWEA 6
-#define TWINT 7
-
-#define TWAMR _SFR_MEM8(0xBD)
-#define TWAM0 1
-#define TWAM1 2
-#define TWAM2 3
-#define TWAM3 4
-#define TWAM4 5
-#define TWAM5 6
-#define TWAM6 7
-
-#define UCSR0A _SFR_MEM8(0xC0)
-#define MPCM0 0
-#define U2X0 1
-#define UPE0 2
-#define DOR0 3
-#define FE0 4
-#define UDRE0 5
-#define TXC0 6
-#define RXC0 7
-
-#define UCSR0B _SFR_MEM8(0xC1)
-#define TXB80 0
-#define RXB80 1
-#define UCSZ02 2
-#define TXEN0 3
-#define RXEN0 4
-#define UDRIE0 5
-#define TXCIE0 6
-#define RXCIE0 7
-
-#define UCSR0C _SFR_MEM8(0xC2)
-#define UCPOL0 0
-#define UCSZ00 1
-#define UCSZ01 2
-#define USBS0 3
-#define UPM00 4
-#define UPM01 5
-#define UMSEL00 6
-#define UMSEL01 7
-
-#define UBRR0 _SFR_MEM16(0xC4)
-
-#define UBRR0L _SFR_MEM8(0xC4)
-#define UBRR0_0 0
-#define UBRR0_1 1
-#define UBRR0_2 2
-#define UBRR0_3 3
-#define UBRR0_4 4
-#define UBRR0_5 5
-#define UBRR0_6 6
-#define UBRR0_7 7
-
-#define UBRR0H _SFR_MEM8(0xC5)
-#define UBRR0_8 0
-#define UBRR0_9 1
-#define UBRR0_10 2
-#define UBRR0_11 3
-
-#define UDR0 _SFR_MEM8(0xC6)
-#define UDR0_0 0
-#define UDR0_1 1
-#define UDR0_2 2
-#define UDR0_3 3
-#define UDR0_4 4
-#define UDR0_5 5
-#define UDR0_6 6
-#define UDR0_7 7
-
-#define UCSR1A _SFR_MEM8(0xC8)
-#define MPCM1 0
-#define U2X1 1
-#define UPE1 2
-#define DOR1 3
-#define FE1 4
-#define UDRE1 5
-#define TXC1 6
-#define RXC1 7
-
-#define UCSR1B _SFR_MEM8(0xC9)
-#define TXB81 0
-#define RXB81 1
-#define UCSZ12 2
-#define TXEN1 3
-#define RXEN1 4
-#define UDRIE1 5
-#define TXCIE1 6
-#define RXCIE1 7
-
-#define UCSR1C _SFR_MEM8(0xCA)
-#define UCPOL1 0
-#define UCSZ10 1
-#define UCSZ11 2
-#define USBS1 3
-#define UPM10 4
-#define UPM11 5
-#define UMSEL10 6
-#define UMSEL11 7
-
-#define UBRR1 _SFR_MEM16(0xCC)
-
-#define UBRR1L _SFR_MEM8(0xCC)
-#define UBRR1_0 0
-#define UBRR1_1 1
-#define UBRR1_2 2
-#define UBRR1_3 3
-#define UBRR1_4 4
-#define UBRR1_5 5
-#define UBRR1_6 6
-#define UBRR1_7 7
-
-#define UBRR1H _SFR_MEM8(0xCD)
-#define UBRR1_8 0
-#define UBRR1_9 1
-#define UBRR1_10 2
-#define UBRR1_11 3
-
-#define UDR1 _SFR_MEM8(0xCE)
-#define UDR1_0 0
-#define UDR1_1 1
-#define UDR1_2 2
-#define UDR1_3 3
-#define UDR1_4 4
-#define UDR1_5 5
-#define UDR1_6 6
-#define UDR1_7 7
-
-
-/* Interrupt Vectors */
-/* Interrupt Vector 0 is the reset vector. */
-
-#define INT0_vect         _VECTOR(1)  /* External Interrupt Request 0 */
-#define INT1_vect         _VECTOR(2)  /* External Interrupt Request 1 */
-#define INT2_vect         _VECTOR(3)  /* External Interrupt Request 2 */
-#define PCINT0_vect       _VECTOR(4)  /* Pin Change Interrupt Request 0 */
-#define PCINT1_vect       _VECTOR(5)  /* Pin Change Interrupt Request 1 */
-#define PCINT2_vect       _VECTOR(6)  /* Pin Change Interrupt Request 2 */
-#define PCINT3_vect       _VECTOR(7)  /* Pin Change Interrupt Request 3 */
-#define WDT_vect          _VECTOR(8)  /* Watchdog Time-out Interrupt */
-#define TIMER2_COMPA_vect _VECTOR(9)  /* Timer/Counter2 Compare Match A */
-#define TIMER2_COMPB_vect _VECTOR(10)  /* Timer/Counter2 Compare Match B */
-#define TIMER2_OVF_vect   _VECTOR(11)  /* Timer/Counter2 Overflow */
-#define TIMER1_CAPT_vect  _VECTOR(12)  /* Timer/Counter1 Capture Event */
-#define TIMER1_COMPA_vect _VECTOR(13)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(14)  /* Timer/Counter1 Compare Match B */
-#define TIMER1_OVF_vect   _VECTOR(15)  /* Timer/Counter1 Overflow */
-#define TIMER0_COMPA_vect _VECTOR(16)  /* Timer/Counter0 Compare Match A */
-#define TIMER0_COMPB_vect _VECTOR(17)  /* Timer/Counter0 Compare Match B */
-#define TIMER0_OVF_vect   _VECTOR(18)  /* Timer/Counter0 Overflow */
-#define SPI_STC_vect      _VECTOR(19)  /* SPI Serial Transfer Complete */
-#define USART0_RX_vect    _VECTOR(20)  /* USART0, Rx Complete */
-#define USART0_UDRE_vect  _VECTOR(21)  /* USART0 Data register Empty */
-#define USART0_TX_vect    _VECTOR(22)  /* USART0, Tx Complete */
-#define ANALOG_COMP_vect  _VECTOR(23)  /* Analog Comparator */
-#define ADC_vect          _VECTOR(24)  /* ADC Conversion Complete */
-#define EE_READY_vect     _VECTOR(25)  /* EEPROM Ready */
-#define TWI_vect          _VECTOR(26)  /* 2-wire Serial Interface */
-#define SPM_READY_vect    _VECTOR(27)  /* Store Program Memory Read */
-#define USART1_RX_vect    _VECTOR(28)  /* USART1 RX complete */
-#define USART1_UDRE_vect  _VECTOR(29)  /* USART1 Data Register Empty */
-#define USART1_TX_vect    _VECTOR(30)  /* USART1 TX complete */
-#define TIMER3_CAPT_vect  _VECTOR(31)  /* Timer/Counter3 Capture Event */
-#define TIMER3_COMPA_vect _VECTOR(32)  /* Timer/Counter3 Compare Match A */
-#define TIMER3_COMPB_vect _VECTOR(33)  /* Timer/Counter3 Compare Match B */
-#define TIMER3_OVF_vect   _VECTOR(34)  /* Timer/Counter3 Overflow */
-
-#define _VECTORS_SIZE (35 * 4)
-
-
-/* Constants */
-#define SPM_PAGESIZE 256
-#define RAMEND       0x40FF    /* Last On-Chip SRAM Location */
-#define XRAMSIZE     0
-#define XRAMEND      RAMEND
-#define E2END        0xFFF
-#define E2PAGESIZE   8
-#define FLASHEND     0x1FFFF
-
-
-/* Fuses */
-#define FUSE_MEMORY_SIZE 3
-
-/* Low Fuse Byte */
-#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
-#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
-#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
-#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
-#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
-#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
-#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
-#define FUSE_CKDIV8 (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
-
-/* High Fuse Byte */
-#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
-#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
-#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
-#define FUSE_WDTON   (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN   (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
-#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
-#define FUSE_OCDEN   (unsigned char)~_BV(7)  /* Enable OCD */
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN & FUSE_JTAGEN)
-
-/* Extended Fuse Byte */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
-#define EFUSE_DEFAULT (0xFF)
-
-
-/* Lock Bits */
-#define __LOCK_BITS_EXIST
-#define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
-
-
-/* Signature */
-#define SIGNATURE_0 0x1E
-#define SIGNATURE_1 0x97
-#define SIGNATURE_2 0x05
-
-
-#endif  /* _AVR_IOM1284P_H_ */
+/**
+ * @file avr/iom1284p.h
+ *
+ * @brief Definitions for ATmega1284P
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2007 Atmel Corporation
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _AVR_IO_H_
+#  error "Include <avr/io.h> instead of this file."
+#endif
+
+#ifndef _AVR_IOXXX_H_
+#  define _AVR_IOXXX_H_ "iom1284p.h"
+#else
+#  error "Attempt to include more than one <avr/ioXXX.h> file."
+#endif
+
+
+#ifndef _AVR_IOM1284P_H_
+#define _AVR_IOM1284P_H_ 1
+
+/**
+ *  @defgroup Avr_iom1284p ATmega1284P Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
+/* Registers and associated bit numbers */
+
+#define PINA _SFR_IO8(0x00)
+#define PINA0 0
+#define PINA1 1
+#define PINA2 2
+#define PINA3 3
+#define PINA4 4
+#define PINA5 5
+#define PINA6 6
+#define PINA7 7
+
+#define DDRA _SFR_IO8(0x01)
+#define DDA0 0
+#define DDA1 1
+#define DDA2 2
+#define DDA3 3
+#define DDA4 4
+#define DDA5 5
+#define DDA6 6
+#define DDA7 7
+
+#define PORTA _SFR_IO8(0x02)
+#define PORTA0 0
+#define PORTA1 1
+#define PORTA2 2
+#define PORTA3 3
+#define PORTA4 4
+#define PORTA5 5
+#define PORTA6 6
+#define PORTA7 7
+
+#define PINB _SFR_IO8(0x03)
+#define PINB0 0
+#define PINB1 1
+#define PINB2 2
+#define PINB3 3
+#define PINB4 4
+#define PINB5 5
+#define PINB6 6
+#define PINB7 7
+
+#define DDRB _SFR_IO8(0x04)
+#define DDB0 0
+#define DDB1 1
+#define DDB2 2
+#define DDB3 3
+#define DDB4 4
+#define DDB5 5
+#define DDB6 6
+#define DDB7 7
+
+#define PORTB _SFR_IO8(0x05)
+#define PORTB0 0
+#define PORTB1 1
+#define PORTB2 2
+#define PORTB3 3
+#define PORTB4 4
+#define PORTB5 5
+#define PORTB6 6
+#define PORTB7 7
+
+#define PINC _SFR_IO8(0x06)
+#define PINC0 0
+#define PINC1 1
+#define PINC2 2
+#define PINC3 3
+#define PINC4 4
+#define PINC5 5
+#define PINC6 6
+#define PINC7 7
+
+#define DDRC _SFR_IO8(0x07)
+#define DDC0 0
+#define DDC1 1
+#define DDC2 2
+#define DDC3 3
+#define DDC4 4
+#define DDC5 5
+#define DDC6 6
+#define DDC7 7
+
+#define PORTC _SFR_IO8(0x08)
+#define PORTC0 0
+#define PORTC1 1
+#define PORTC2 2
+#define PORTC3 3
+#define PORTC4 4
+#define PORTC5 5
+#define PORTC6 6
+#define PORTC7 7
+
+#define PIND _SFR_IO8(0x09)
+#define PIND0 0
+#define PIND1 1
+#define PIND2 2
+#define PIND3 3
+#define PIND4 4
+#define PIND5 5
+#define PIND6 6
+#define PIND7 7
+
+#define DDRD _SFR_IO8(0x0A)
+#define DDD0 0
+#define DDD1 1
+#define DDD2 2
+#define DDD3 3
+#define DDD4 4
+#define DDD5 5
+#define DDD6 6
+#define DDD7 7
+
+#define PORTD _SFR_IO8(0x0B)
+#define PORTD0 0
+#define PORTD1 1
+#define PORTD2 2
+#define PORTD3 3
+#define PORTD4 4
+#define PORTD5 5
+#define PORTD6 6
+#define PORTD7 7
+
+#define TIFR0 _SFR_IO8(0x15)
+#define TOV0 0
+#define OCF0A 1
+#define OCF0B 2
+
+#define TIFR1 _SFR_IO8(0x16)
+#define TOV1 0
+#define OCF1A 1
+#define OCF1B 2
+#define ICF1 5
+
+#define TIFR2 _SFR_IO8(0x17)
+#define TOV2 0
+#define OCF2A 1
+#define OCF2B 2
+
+#define TIFR3 _SFR_IO8(0x18)
+#define TOV3 0
+#define OCF3A 1
+#define OCF3B 2
+#define ICF3 5
+
+#define PCIFR _SFR_IO8(0x1B)
+#define PCIF0 0
+#define PCIF1 1
+#define PCIF2 2
+#define PCIF3 3
+
+#define EIFR _SFR_IO8(0x1C)
+#define INTF0 0
+#define INTF1 1
+#define INTF2 2
+
+#define EIMSK _SFR_IO8(0x1D)
+#define INT0 0
+#define INT1 1
+#define INT2 2
+
+#define GPIOR0 _SFR_IO8(0x1E)
+#define GPIOR00 0
+#define GPIOR01 1
+#define GPIOR02 2
+#define GPIOR03 3
+#define GPIOR04 4
+#define GPIOR05 5
+#define GPIOR06 6
+#define GPIOR07 7
+
+#define EECR _SFR_IO8(0x1F)
+#define EERE 0
+#define EEPE 1
+#define EEMPE 2
+#define EERIE 3
+#define EEPM0 4
+#define EEPM1 5
+
+#define EEDR _SFR_IO8(0x20)
+#define EEDR0 0
+#define EEDR1 1
+#define EEDR2 2
+#define EEDR3 3
+#define EEDR4 4
+#define EEDR5 5
+#define EEDR6 6
+#define EEDR7 7
+
+#define EEAR _SFR_IO16(0x21)
+
+#define EEARL _SFR_IO8(0x21)
+#define EEAR0 0
+#define EEAR1 1
+#define EEAR2 2
+#define EEAR3 3
+#define EEAR4 4
+#define EEAR5 5
+#define EEAR6 6
+#define EEAR7 7
+
+#define EEARH _SFR_IO8(0x22)
+#define EEAR8 0
+#define EEAR9 1
+#define EEAR10 2
+#define EEAR11 3
+
+#define GTCCR _SFR_IO8(0x23)
+#define PSRSYNC 0
+#define PSRASY 1
+#define TSM 7
+
+#define TCCR0A _SFR_IO8(0x24)
+#define WGM00 0
+#define WGM01 1
+#define COM0B0 4
+#define COM0B1 5
+#define COM0A0 6
+#define COM0A1 7
+
+#define TCCR0B _SFR_IO8(0x25)
+#define CS00 0
+#define CS01 1
+#define CS02 2
+#define WGM02 3
+#define FOC0B 6
+#define FOC0A 7
+
+#define TCNT0 _SFR_IO8(0x26)
+#define TCNT0_0 0
+#define TCNT0_1 1
+#define TCNT0_2 2
+#define TCNT0_3 3
+#define TCNT0_4 4
+#define TCNT0_5 5
+#define TCNT0_6 6
+#define TCNT0_7 7
+
+#define OCR0A _SFR_IO8(0x27)
+#define OCR0A_0 0
+#define OCR0A_1 1
+#define OCR0A_2 2
+#define OCR0A_3 3
+#define OCR0A_4 4
+#define OCR0A_5 5
+#define OCR0A_6 6
+#define OCR0A_7 7
+
+#define OCR0B _SFR_IO8(0x28)
+#define OCR0B_0 0
+#define OCR0B_1 1
+#define OCR0B_2 2
+#define OCR0B_3 3
+#define OCR0B_4 4
+#define OCR0B_5 5
+#define OCR0B_6 6
+#define OCR0B_7 7
+
+#define GPIOR1 _SFR_IO8(0x2A)
+#define GPIOR10 0
+#define GPIOR11 1
+#define GPIOR12 2
+#define GPIOR13 3
+#define GPIOR14 4
+#define GPIOR15 5
+#define GPIOR16 6
+#define GPIOR17 7
+
+#define GPIOR2 _SFR_IO8(0x2B)
+#define GPIOR20 0
+#define GPIOR21 1
+#define GPIOR22 2
+#define GPIOR23 3
+#define GPIOR24 4
+#define GPIOR25 5
+#define GPIOR26 6
+#define GPIOR27 7
+
+#define SPCR _SFR_IO8(0x2C)
+#define SPR0 0
+#define SPR1 1
+#define CPHA 2
+#define CPOL 3
+#define MSTR 4
+#define DORD 5
+#define SPE 6
+#define SPIE 7
+
+#define SPSR _SFR_IO8(0x2D)
+#define SPI2X 0
+#define WCOL 6
+#define SPIF 7
+
+#define SPDR _SFR_IO8(0x2E)
+#define SPDR0 0
+#define SPDR1 1
+#define SPDR2 2
+#define SPDR3 3
+#define SPDR4 4
+#define SPDR5 5
+#define SPDR6 6
+#define SPDR7 7
+
+#define ACSR _SFR_IO8(0x30)
+#define ACIS0 0
+#define ACIS1 1
+#define ACIC 2
+#define ACIE 3
+#define ACI 4
+#define ACO 5
+#define ACBG 6
+#define ACD 7
+
+#define OCDR _SFR_IO8(0x31)
+#define OCDR0 0
+#define OCDR1 1
+#define OCDR2 2
+#define OCDR3 3
+#define OCDR4 4
+#define OCDR5 5
+#define OCDR6 6
+#define OCDR7 7
+
+#define SMCR _SFR_IO8(0x33)
+#define SE 0
+#define SM0 1
+#define SM1 2
+#define SM2 3
+
+#define MCUSR _SFR_IO8(0x34)
+#define PORF 0
+#define EXTRF 1
+#define BORF 2
+#define WDRF 3
+#define JTRF 4
+
+#define MCUCR _SFR_IO8(0x35)
+#define IVCE 0
+#define IVSEL 1
+#define PUD 4
+#define BODSE 5
+#define BODS 6
+#define JTD 7
+
+#define SPMCSR _SFR_IO8(0x37)
+#define SPMEN 0
+#define PGERS 1
+#define PGWRT 2
+#define BLBSET 3
+#define RWWSRE 4
+#define SIGRD 5
+#define RWWSB 6
+#define SPMIE 7
+
+#define RAMPZ _SFR_IO8(0x3B)
+#define RAMPZ0 0
+
+#define WDTCSR _SFR_MEM8(0x60)
+#define WDP0 0
+#define WDP1 1
+#define WDP2 2
+#define WDE 3
+#define WDCE 4
+#define WDP3 5
+#define WDIE 6
+#define WDIF 7
+
+#define CLKPR _SFR_MEM8(0x61)
+#define CLKPS0 0
+#define CLKPS1 1
+#define CLKPS2 2
+#define CLKPS3 3
+#define CLKPCE 7
+
+#define PRR0 _SFR_MEM8(0x64)
+#define PRADC 0
+#define PRUSART0 1
+#define PRSPI 2
+#define PRTIM1 3
+#define PRUSART1 4
+#define PRTIM0 5
+#define PRTIM2 6
+#define PRTWI 7
+
+#define PRR1 _SFR_MEM8(0x65)
+#define PRTIM3 0
+
+#define OSCCAL _SFR_MEM8(0x66)
+#define CAL0 0
+#define CAL1 1
+#define CAL2 2
+#define CAL3 3
+#define CAL4 4
+#define CAL5 5
+#define CAL6 6
+#define CAL7 7
+
+#define PCICR _SFR_MEM8(0x68)
+#define PCIE0 0
+#define PCIE1 1
+#define PCIE2 2
+#define PCIE3 3
+
+#define EICRA _SFR_MEM8(0x69)
+#define ISC00 0
+#define ISC01 1
+#define ISC10 2
+#define ISC11 3
+#define ISC20 4
+#define ISC21 5
+
+#define PCMSK0 _SFR_MEM8(0x6B)
+#define PCINT0 0
+#define PCINT1 1
+#define PCINT2 2
+#define PCINT3 3
+#define PCINT4 4
+#define PCINT5 5
+#define PCINT6 6
+#define PCINT7 7
+
+#define PCMSK1 _SFR_MEM8(0x6C)
+#define PCINT8 0
+#define PCINT9 1
+#define PCINT10 2
+#define PCINT11 3
+#define PCINT12 4
+#define PCINT13 5
+#define PCINT14 6
+#define PCINT15 7
+
+#define PCMSK2 _SFR_MEM8(0x6D)
+#define PCINT16 0
+#define PCINT17 1
+#define PCINT18 2
+#define PCINT19 3
+#define PCINT20 4
+#define PCINT21 5
+#define PCINT22 6
+#define PCINT23 7
+
+#define TIMSK0 _SFR_MEM8(0x6E)
+#define TOIE0 0
+#define OCIE0A 1
+#define OCIE0B 2
+
+#define TIMSK1 _SFR_MEM8(0x6F)
+#define TOIE1 0
+#define OCIE1A 1
+#define OCIE1B 2
+#define ICIE1 5
+
+#define TIMSK2 _SFR_MEM8(0x70)
+#define TOIE2 0
+#define OCIE2A 1
+#define OCIE2B 2
+
+#define TIMSK3 _SFR_MEM8(0x71)
+#define TOIE3 0
+#define OCIE3A 1
+#define OCIE3B 2
+#define ICIE3 5
+
+#define PCMSK3 _SFR_MEM8(0x73)
+#define PCINT24 0
+#define PCINT25 1
+#define PCINT26 2
+#define PCINT27 3
+#define PCINT28 4
+#define PCINT29 5
+#define PCINT30 6
+#define PCINT31 7
+
+#ifndef __ASSEMBLER__
+#define ADC     _SFR_MEM16(0x78)
+#endif
+#define ADCW    _SFR_MEM16(0x78)
+
+#define ADCL _SFR_MEM8(0x78)
+#define ADCL0 0
+#define ADCL1 1
+#define ADCL2 2
+#define ADCL3 3
+#define ADCL4 4
+#define ADCL5 5
+#define ADCL6 6
+#define ADCL7 7
+
+#define ADCH _SFR_MEM8(0x79)
+#define ADCH0 0
+#define ADCH1 1
+#define ADCH2 2
+#define ADCH3 3
+#define ADCH4 4
+#define ADCH5 5
+#define ADCH6 6
+#define ADCH7 7
+
+#define ADCSRA _SFR_MEM8(0x7A)
+#define ADPS0 0
+#define ADPS1 1
+#define ADPS2 2
+#define ADIE 3
+#define ADIF 4
+#define ADATE 5
+#define ADSC 6
+#define ADEN 7
+
+#define ADCSRB _SFR_MEM8(0x7B)
+#define ADTS0 0
+#define ADTS1 1
+#define ADTS2 2
+#define ACME 6
+
+#define ADMUX _SFR_MEM8(0x7C)
+#define MUX0 0
+#define MUX1 1
+#define MUX2 2
+#define MUX3 3
+#define MUX4 4
+#define ADLAR 5
+#define REFS0 6
+#define REFS1 7
+
+#define DIDR0 _SFR_MEM8(0x7E)
+#define ADC0D 0
+#define ADC1D 1
+#define ADC2D 2
+#define ADC3D 3
+#define ADC4D 4
+#define ADC5D 5
+#define ADC6D 6
+#define ADC7D 7
+
+#define DIDR1 _SFR_MEM8(0x7F)
+#define AIN0D 0
+#define AIN1D 1
+
+#define TCCR1A _SFR_MEM8(0x80)
+#define WGM10 0
+#define WGM11 1
+#define COM1B0 4
+#define COM1B1 5
+#define COM1A0 6
+#define COM1A1 7
+
+#define TCCR1B _SFR_MEM8(0x81)
+#define CS10 0
+#define CS11 1
+#define CS12 2
+#define WGM12 3
+#define WGM13 4
+#define ICES1 6
+#define ICNC1 7
+
+#define TCCR1C _SFR_MEM8(0x82)
+#define FOC1B 6
+#define FOC1A 7
+
+#define TCNT1 _SFR_MEM16(0x84)
+
+#define TCNT1L _SFR_MEM8(0x84)
+#define TCNT1L0 0
+#define TCNT1L1 1
+#define TCNT1L2 2
+#define TCNT1L3 3
+#define TCNT1L4 4
+#define TCNT1L5 5
+#define TCNT1L6 6
+#define TCNT1L7 7
+
+#define TCNT1H _SFR_MEM8(0x85)
+#define TCNT1H0 0
+#define TCNT1H1 1
+#define TCNT1H2 2
+#define TCNT1H3 3
+#define TCNT1H4 4
+#define TCNT1H5 5
+#define TCNT1H6 6
+#define TCNT1H7 7
+
+#define ICR1 _SFR_MEM16(0x86)
+
+#define ICR1L _SFR_MEM8(0x86)
+#define ICR1L0 0
+#define ICR1L1 1
+#define ICR1L2 2
+#define ICR1L3 3
+#define ICR1L4 4
+#define ICR1L5 5
+#define ICR1L6 6
+#define ICR1L7 7
+
+#define ICR1H _SFR_MEM8(0x87)
+#define ICR1H0 0
+#define ICR1H1 1
+#define ICR1H2 2
+#define ICR1H3 3
+#define ICR1H4 4
+#define ICR1H5 5
+#define ICR1H6 6
+#define ICR1H7 7
+
+#define OCR1A _SFR_MEM16(0x88)
+
+#define OCR1AL _SFR_MEM8(0x88)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1AH _SFR_MEM8(0x89)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define OCR1B _SFR_MEM16(0x8A)
+
+#define OCR1BL _SFR_MEM8(0x8A)
+#define OCR1AL0 0
+#define OCR1AL1 1
+#define OCR1AL2 2
+#define OCR1AL3 3
+#define OCR1AL4 4
+#define OCR1AL5 5
+#define OCR1AL6 6
+#define OCR1AL7 7
+
+#define OCR1BH _SFR_MEM8(0x8B)
+#define OCR1AH0 0
+#define OCR1AH1 1
+#define OCR1AH2 2
+#define OCR1AH3 3
+#define OCR1AH4 4
+#define OCR1AH5 5
+#define OCR1AH6 6
+#define OCR1AH7 7
+
+#define TCCR3A _SFR_MEM8(0x90)
+#define WGM30 0
+#define WGM31 1
+#define COM3B0 4
+#define COM3B1 5
+#define COM3A0 6
+#define COM3A1 7
+
+#define TCCR3B _SFR_MEM8(0x91)
+#define CS30 0
+#define CS31 1
+#define CS32 2
+#define WGM32 3
+#define WGM33 4
+#define ICES3 6
+#define ICNC3 7
+
+#define TCCR3C _SFR_MEM8(0x92)
+#define FOC3B 6
+#define FOC3A 7
+
+#define TCNT3 _SFR_MEM16(0x94)
+
+#define TCNT3L _SFR_MEM8(0x94)
+#define TCNT3L0 0
+#define TCNT3L1 1
+#define TCNT3L2 2
+#define TCNT3L3 3
+#define TCNT3L4 4
+#define TCNT3L5 5
+#define TCNT3L6 6
+#define TCNT3L7 7
+
+#define TCNT3H _SFR_MEM8(0x95)
+#define TCNT3H0 0
+#define TCNT3H1 1
+#define TCNT3H2 2
+#define TCNT3H3 3
+#define TCNT3H4 4
+#define TCNT3H5 5
+#define TCNT3H6 6
+#define TCNT3H7 7
+
+#define ICR3 _SFR_MEM16(0x96)
+
+#define ICR3L _SFR_MEM8(0x96)
+#define ICR3L0 0
+#define ICR3L1 1
+#define ICR3L2 2
+#define ICR3L3 3
+#define ICR3L4 4
+#define ICR3L5 5
+#define ICR3L6 6
+#define ICR3L7 7
+
+#define ICR3H _SFR_MEM8(0x97)
+#define ICR3H0 0
+#define ICR3H1 1
+#define ICR3H2 2
+#define ICR3H3 3
+#define ICR3H4 4
+#define ICR3H5 5
+#define ICR3H6 6
+#define ICR3H7 7
+
+#define OCR3A _SFR_MEM16(0x98)
+
+#define OCR3AL _SFR_MEM8(0x98)
+#define OCR3AL0 0
+#define OCR3AL1 1
+#define OCR3AL2 2
+#define OCR3AL3 3
+#define OCR3AL4 4
+#define OCR3AL5 5
+#define OCR3AL6 6
+#define OCR3AL7 7
+
+#define OCR3AH _SFR_MEM8(0x99)
+#define OCR3AH0 0
+#define OCR3AH1 1
+#define OCR3AH2 2
+#define OCR3AH3 3
+#define OCR3AH4 4
+#define OCR3AH5 5
+#define OCR3AH6 6
+#define OCR3AH7 7
+
+#define OCR3B _SFR_MEM16(0x9A)
+
+#define OCR3BL _SFR_MEM8(0x9A)
+#define OCR3AL0 0
+#define OCR3AL1 1
+#define OCR3AL2 2
+#define OCR3AL3 3
+#define OCR3AL4 4
+#define OCR3AL5 5
+#define OCR3AL6 6
+#define OCR3AL7 7
+
+#define OCR3BH _SFR_MEM8(0x9B)
+#define OCR3AH0 0
+#define OCR3AH1 1
+#define OCR3AH2 2
+#define OCR3AH3 3
+#define OCR3AH4 4
+#define OCR3AH5 5
+#define OCR3AH6 6
+#define OCR3AH7 7
+
+#define TCCR2A _SFR_MEM8(0xB0)
+#define WGM20 0
+#define WGM21 1
+#define COM2B0 4
+#define COM2B1 5
+#define COM2A0 6
+#define COM2A1 7
+
+#define TCCR2B _SFR_MEM8(0xB1)
+#define CS20 0
+#define CS21 1
+#define CS22 2
+#define WGM22 3
+#define FOC2B 6
+#define FOC2A 7
+
+#define TCNT2 _SFR_MEM8(0xB2)
+#define TCNT2_0 0
+#define TCNT2_1 1
+#define TCNT2_2 2
+#define TCNT2_3 3
+#define TCNT2_4 4
+#define TCNT2_5 5
+#define TCNT2_6 6
+#define TCNT2_7 7
+
+#define OCR2A _SFR_MEM8(0xB3)
+#define OCR2_0 0
+#define OCR2_1 1
+#define OCR2_2 2
+#define OCR2_3 3
+#define OCR2_4 4
+#define OCR2_5 5
+#define OCR2_6 6
+#define OCR2_7 7
+
+#define OCR2B _SFR_MEM8(0xB4)
+#define OCR2_0 0
+#define OCR2_1 1
+#define OCR2_2 2
+#define OCR2_3 3
+#define OCR2_4 4
+#define OCR2_5 5
+#define OCR2_6 6
+#define OCR2_7 7
+
+#define ASSR _SFR_MEM8(0xB6)
+#define TCR2BUB 0
+#define TCR2AUB 1
+#define OCR2BUB 2
+#define OCR2AUB 3
+#define TCN2UB 4
+#define AS2 5
+#define EXCLK 6
+
+#define TWBR _SFR_MEM8(0xB8)
+#define TWBR0 0
+#define TWBR1 1
+#define TWBR2 2
+#define TWBR3 3
+#define TWBR4 4
+#define TWBR5 5
+#define TWBR6 6
+#define TWBR7 7
+
+#define TWSR _SFR_MEM8(0xB9)
+#define TWPS0 0
+#define TWPS1 1
+#define TWS3 3
+#define TWS4 4
+#define TWS5 5
+#define TWS6 6
+#define TWS7 7
+
+#define TWAR _SFR_MEM8(0xBA)
+#define TWGCE 0
+#define TWA0 1
+#define TWA1 2
+#define TWA2 3
+#define TWA3 4
+#define TWA4 5
+#define TWA5 6
+#define TWA6 7
+
+#define TWDR _SFR_MEM8(0xBB)
+#define TWD0 0
+#define TWD1 1
+#define TWD2 2
+#define TWD3 3
+#define TWD4 4
+#define TWD5 5
+#define TWD6 6
+#define TWD7 7
+
+#define TWCR _SFR_MEM8(0xBC)
+#define TWIE 0
+#define TWEN 2
+#define TWWC 3
+#define TWSTO 4
+#define TWSTA 5
+#define TWEA 6
+#define TWINT 7
+
+#define TWAMR _SFR_MEM8(0xBD)
+#define TWAM0 1
+#define TWAM1 2
+#define TWAM2 3
+#define TWAM3 4
+#define TWAM4 5
+#define TWAM5 6
+#define TWAM6 7
+
+#define UCSR0A _SFR_MEM8(0xC0)
+#define MPCM0 0
+#define U2X0 1
+#define UPE0 2
+#define DOR0 3
+#define FE0 4
+#define UDRE0 5
+#define TXC0 6
+#define RXC0 7
+
+#define UCSR0B _SFR_MEM8(0xC1)
+#define TXB80 0
+#define RXB80 1
+#define UCSZ02 2
+#define TXEN0 3
+#define RXEN0 4
+#define UDRIE0 5
+#define TXCIE0 6
+#define RXCIE0 7
+
+#define UCSR0C _SFR_MEM8(0xC2)
+#define UCPOL0 0
+#define UCSZ00 1
+#define UCSZ01 2
+#define USBS0 3
+#define UPM00 4
+#define UPM01 5
+#define UMSEL00 6
+#define UMSEL01 7
+
+#define UBRR0 _SFR_MEM16(0xC4)
+
+#define UBRR0L _SFR_MEM8(0xC4)
+#define UBRR0_0 0
+#define UBRR0_1 1
+#define UBRR0_2 2
+#define UBRR0_3 3
+#define UBRR0_4 4
+#define UBRR0_5 5
+#define UBRR0_6 6
+#define UBRR0_7 7
+
+#define UBRR0H _SFR_MEM8(0xC5)
+#define UBRR0_8 0
+#define UBRR0_9 1
+#define UBRR0_10 2
+#define UBRR0_11 3
+
+#define UDR0 _SFR_MEM8(0xC6)
+#define UDR0_0 0
+#define UDR0_1 1
+#define UDR0_2 2
+#define UDR0_3 3
+#define UDR0_4 4
+#define UDR0_5 5
+#define UDR0_6 6
+#define UDR0_7 7
+
+#define UCSR1A _SFR_MEM8(0xC8)
+#define MPCM1 0
+#define U2X1 1
+#define UPE1 2
+#define DOR1 3
+#define FE1 4
+#define UDRE1 5
+#define TXC1 6
+#define RXC1 7
+
+#define UCSR1B _SFR_MEM8(0xC9)
+#define TXB81 0
+#define RXB81 1
+#define UCSZ12 2
+#define TXEN1 3
+#define RXEN1 4
+#define UDRIE1 5
+#define TXCIE1 6
+#define RXCIE1 7
+
+#define UCSR1C _SFR_MEM8(0xCA)
+#define UCPOL1 0
+#define UCSZ10 1
+#define UCSZ11 2
+#define USBS1 3
+#define UPM10 4
+#define UPM11 5
+#define UMSEL10 6
+#define UMSEL11 7
+
+#define UBRR1 _SFR_MEM16(0xCC)
+
+#define UBRR1L _SFR_MEM8(0xCC)
+#define UBRR1_0 0
+#define UBRR1_1 1
+#define UBRR1_2 2
+#define UBRR1_3 3
+#define UBRR1_4 4
+#define UBRR1_5 5
+#define UBRR1_6 6
+#define UBRR1_7 7
+
+#define UBRR1H _SFR_MEM8(0xCD)
+#define UBRR1_8 0
+#define UBRR1_9 1
+#define UBRR1_10 2
+#define UBRR1_11 3
+
+#define UDR1 _SFR_MEM8(0xCE)
+#define UDR1_0 0
+#define UDR1_1 1
+#define UDR1_2 2
+#define UDR1_3 3
+#define UDR1_4 4
+#define UDR1_5 5
+#define UDR1_6 6
+#define UDR1_7 7
+
+
+/* Interrupt Vectors */
+/* Interrupt Vector 0 is the reset vector. */
+
+#define INT0_vect         _VECTOR(1)  /* External Interrupt Request 0 */
+#define INT1_vect         _VECTOR(2)  /* External Interrupt Request 1 */
+#define INT2_vect         _VECTOR(3)  /* External Interrupt Request 2 */
+#define PCINT0_vect       _VECTOR(4)  /* Pin Change Interrupt Request 0 */
+#define PCINT1_vect       _VECTOR(5)  /* Pin Change Interrupt Request 1 */
+#define PCINT2_vect       _VECTOR(6)  /* Pin Change Interrupt Request 2 */
+#define PCINT3_vect       _VECTOR(7)  /* Pin Change Interrupt Request 3 */
+#define WDT_vect          _VECTOR(8)  /* Watchdog Time-out Interrupt */
+#define TIMER2_COMPA_vect _VECTOR(9)  /* Timer/Counter2 Compare Match A */
+#define TIMER2_COMPB_vect _VECTOR(10)  /* Timer/Counter2 Compare Match B */
+#define TIMER2_OVF_vect   _VECTOR(11)  /* Timer/Counter2 Overflow */
+#define TIMER1_CAPT_vect  _VECTOR(12)  /* Timer/Counter1 Capture Event */
+#define TIMER1_COMPA_vect _VECTOR(13)  /* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPB_vect _VECTOR(14)  /* Timer/Counter1 Compare Match B */
+#define TIMER1_OVF_vect   _VECTOR(15)  /* Timer/Counter1 Overflow */
+#define TIMER0_COMPA_vect _VECTOR(16)  /* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPB_vect _VECTOR(17)  /* Timer/Counter0 Compare Match B */
+#define TIMER0_OVF_vect   _VECTOR(18)  /* Timer/Counter0 Overflow */
+#define SPI_STC_vect      _VECTOR(19)  /* SPI Serial Transfer Complete */
+#define USART0_RX_vect    _VECTOR(20)  /* USART0, Rx Complete */
+#define USART0_UDRE_vect  _VECTOR(21)  /* USART0 Data register Empty */
+#define USART0_TX_vect    _VECTOR(22)  /* USART0, Tx Complete */
+#define ANALOG_COMP_vect  _VECTOR(23)  /* Analog Comparator */
+#define ADC_vect          _VECTOR(24)  /* ADC Conversion Complete */
+#define EE_READY_vect     _VECTOR(25)  /* EEPROM Ready */
+#define TWI_vect          _VECTOR(26)  /* 2-wire Serial Interface */
+#define SPM_READY_vect    _VECTOR(27)  /* Store Program Memory Read */
+#define USART1_RX_vect    _VECTOR(28)  /* USART1 RX complete */
+#define USART1_UDRE_vect  _VECTOR(29)  /* USART1 Data Register Empty */
+#define USART1_TX_vect    _VECTOR(30)  /* USART1 TX complete */
+#define TIMER3_CAPT_vect  _VECTOR(31)  /* Timer/Counter3 Capture Event */
+#define TIMER3_COMPA_vect _VECTOR(32)  /* Timer/Counter3 Compare Match A */
+#define TIMER3_COMPB_vect _VECTOR(33)  /* Timer/Counter3 Compare Match B */
+#define TIMER3_OVF_vect   _VECTOR(34)  /* Timer/Counter3 Overflow */
+
+#define _VECTORS_SIZE (35 * 4)
+
+
+/* Constants */
+#define SPM_PAGESIZE 256
+#define RAMEND       0x40FF    /* Last On-Chip SRAM Location */
+#define XRAMSIZE     0
+#define XRAMEND      RAMEND
+#define E2END        0xFFF
+#define E2PAGESIZE   8
+#define FLASHEND     0x1FFFF
+
+
+/* Fuses */
+#define FUSE_MEMORY_SIZE 3
+
+/* Low Fuse Byte */
+#define FUSE_CKSEL0 (unsigned char)~_BV(0)  /* Select Clock Source */
+#define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
+#define FUSE_CKSEL2 (unsigned char)~_BV(2)  /* Select Clock Source */
+#define FUSE_CKSEL3 (unsigned char)~_BV(3)  /* Select Clock Source */
+#define FUSE_SUT0   (unsigned char)~_BV(4)  /* Select start-up time */
+#define FUSE_SUT1   (unsigned char)~_BV(5)  /* Select start-up time */
+#define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Clock output */
+#define FUSE_CKDIV8 (unsigned char)~_BV(7)  /* Divide clock by 8 */
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
+
+/* High Fuse Byte */
+#define FUSE_BOOTRST (unsigned char)~_BV(0)  /* Select Reset Vector */
+#define FUSE_BOOTSZ0 (unsigned char)~_BV(1)  /* Select Boot Size */
+#define FUSE_BOOTSZ1 (unsigned char)~_BV(2)  /* Select Boot Size */
+#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
+#define FUSE_WDTON   (unsigned char)~_BV(4)  /* Watchdog timer always on */
+#define FUSE_SPIEN   (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
+#define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
+#define FUSE_OCDEN   (unsigned char)~_BV(7)  /* Enable OCD */
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_SPIEN & FUSE_JTAGEN)
+
+/* Extended Fuse Byte */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2 (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
+#define EFUSE_DEFAULT (0xFF)
+
+
+/* Lock Bits */
+#define __LOCK_BITS_EXIST
+#define __BOOT_LOCK_BITS_0_EXIST
+#define __BOOT_LOCK_BITS_1_EXIST
+
+
+/* Signature */
+#define SIGNATURE_0 0x1E
+#define SIGNATURE_1 0x97
+#define SIGNATURE_2 0x05
+
+/**@}*/
+#endif  /* _AVR_IOM1284P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom16.h b/cpukit/score/cpu/avr/avr/iom16.h
index a9ac82b42f..6d6e9e3e2c 100644
--- a/cpukit/score/cpu/avr/avr/iom16.h
+++ b/cpukit/score/cpu/avr/avr/iom16.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2004 Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom16.h - definitions for ATmega16 */
+/**
+ * @file avr/iom16.h
+ *
+ * @brief Definitions for ATmega16
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2004 Eric B. Weddington
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM16_H_
 #define _AVR_IOM16_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom16 ATmega16 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iom16.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* Registers and associated bit numbers */
 
@@ -368,9 +380,9 @@
 #define COM1A0  6
 #define COM1A1  7
 
-/* 
-   The ADHSM bit has been removed from all documentation, 
-   as being not needed at all since the comparator has proven 
+/*
+   The ADHSM bit has been removed from all documentation,
+   as being not needed at all since the comparator has proven
    to be fast enough even without feeding it more power.
 */
 
@@ -601,7 +613,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -609,5 +621,5 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x03
 
-
+/**@}*/
 #endif /* _AVR_IOM16_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom161.h b/cpukit/score/cpu/avr/avr/iom161.h
index 8a12acf428..af7bebeec1 100644
--- a/cpukit/score/cpu/avr/avr/iom161.h
+++ b/cpukit/score/cpu/avr/avr/iom161.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file avr/iom161.h
+ *
+ * @brief Definitions for ATmega161
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-/* avr/iom161.h - definitions for ATmega161 */
+/*
+ * Copyright (c) 2002, Marek Michalkiewicz
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM161_H_
 #define _AVR_IOM161_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom161 ATmega161 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iom161.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -660,7 +672,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -669,4 +681,5 @@
 #define SIGNATURE_2 0x01
 
 
+/**@}*/
 #endif /* _AVR_IOM161_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom162.h b/cpukit/score/cpu/avr/avr/iom162.h
index bdd90de0c9..d10a59aff7 100644
--- a/cpukit/score/cpu/avr/avr/iom162.h
+++ b/cpukit/score/cpu/avr/avr/iom162.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002, Nils Kristian Strom <nilsst@omegav.ntnu.no>
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iom162.h - definitions for ATmega162 */
+/**
+ * @file iom162.h
+ *
+ * @brief Definitions for ATmega162
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2002, Nils Kristian Strom <nilsst@omegav.ntnu.no>
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM162_H_
 #define _AVR_IOM162_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom162 ATmega162 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iom162.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* Memory mapped I/O registers */
 
@@ -163,7 +175,7 @@
 #define UCSR1A	_SFR_IO8(0x02)	/* USART 1 Control and Status Register A */
 #define UCSR1B	_SFR_IO8(0x01)	/* USART 1 Control and Status Register B */
 #define	UBRR1L  _SFR_IO8(0x00)  /* USART 0 Baud Rate Register High Byte */
- 
+
 
 /* Interrupt vectors (byte addresses) */
 
@@ -456,7 +468,7 @@
 
 
 
-/* SPMCR bit definitions */ 
+/* SPMCR bit definitions */
 
 #define SPMIE	7
 #define RWWSB	6
@@ -939,7 +951,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -948,4 +960,5 @@
 #define SIGNATURE_2 0x04
 
 
+/**@}*/
 #endif  /* _AVR_IOM162_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom163.h b/cpukit/score/cpu/avr/avr/iom163.h
index 276c7423fc..2dabcd8d40 100644
--- a/cpukit/score/cpu/avr/avr/iom163.h
+++ b/cpukit/score/cpu/avr/avr/iom163.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file avr/iom163.h
+ *
+ * @brief Definitions for ATmega163
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-/* avr/iom163.h - definitions for ATmega163 */
+/*
+ *   Copyright (c) 2007 Anatoly Sokolov
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM163_H_
 #define _AVR_IOM163_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom163 ATmega163 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iom163.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -626,7 +638,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -635,4 +647,5 @@
 #define SIGNATURE_2 0x02
 
 
+/**@}*/
 #endif /* _AVR_IOM163_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom164.h b/cpukit/score/cpu/avr/avr/iom164.h
index 9b97f21df6..160663da88 100644
--- a/cpukit/score/cpu/avr/avr/iom164.h
+++ b/cpukit/score/cpu/avr/avr/iom164.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega164
+ */
+
 /* Copyright (c) 2005, 2006 Anatoly Sokolov
    All rights reserved.
 
@@ -36,6 +42,14 @@
 
 #include <avr/iomxx4.h>
 
+/**
+ * @defgroup AvrDef_iom164 ATmega164 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Constants */
 #define SPM_PAGESIZE    128
 #define RAMEND          0x04FF
@@ -89,5 +103,6 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x0A 
 
+/** @} */
 
 #endif /* _AVR_IOM164_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom165.h b/cpukit/score/cpu/avr/avr/iom165.h
index a15eea43c2..72cbc39fec 100644
--- a/cpukit/score/cpu/avr/avr/iom165.h
+++ b/cpukit/score/cpu/avr/avr/iom165.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega165
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2004,2005,2006 Eric B. Weddington
    All rights reserved.
 
@@ -46,6 +54,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_iom165 ATmega165 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Registers and associated bit numbers */
 
 #define PINA    _SFR_IO8(0x00)
@@ -815,5 +831,6 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x07
 
+/** @} */
 
 #endif /* _AVR_IOM165_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom168.h b/cpukit/score/cpu/avr/avr/iom168.h
index 9470d22a39..7f1dee2345 100644
--- a/cpukit/score/cpu/avr/avr/iom168.h
+++ b/cpukit/score/cpu/avr/avr/iom168.h
@@ -1,37 +1,51 @@
-/* Copyright (c) 2004, Theodore A. Roth
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file
+ *
+ * @brief Definitions for iom168
+ */
+
+/*
+ *  Copyright (c) 2004, Theodore A. Roth
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM168_H_
 #define _AVR_IOM168_H_ 1
 
+/**
+ *  @defgroup Avr_iom168 iom168 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #include <avr/iomx8.h>
 
 /* Constants */
@@ -78,7 +92,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -86,5 +100,5 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x06
 
-
+/**@}*/
 #endif /* _AVR_IOM168_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom168p.h b/cpukit/score/cpu/avr/avr/iom168p.h
index 7c62bc3a29..987d489434 100644
--- a/cpukit/score/cpu/avr/avr/iom168p.h
+++ b/cpukit/score/cpu/avr/avr/iom168p.h
@@ -1,38 +1,43 @@
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iom168p.h
+ *
+ * @brief Definitions for ATmega168P
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2007 Atmel Corporation
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iom168p.h - definitions for ATmega168P. */
-
-/* This file should only be included from <avr/io.h>, never directly. */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -42,12 +47,19 @@
 #  define _AVR_IOXXX_H_ "iom168p.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_IOM168P_H_
 #define _AVR_IOM168P_H_ 1
 
+/**
+ *  @defgroup Avr_iom168p ATmega168P Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 /* Registers and associated bit numbers */
 
 #define PINB _SFR_IO8(0x03)
@@ -330,7 +342,7 @@
 #define WDRF 3
 
 #define MCUCR _SFR_IO8(0x35)
-#define IVCE 0 
+#define IVCE 0
 #define IVSEL 1
 #define PUD 4
 #define BODSE 5
@@ -795,7 +807,7 @@
 #define TIMER2_OVF_vect   _VECTOR(9)   /* Timer/Counter2 Overflow */
 #define TIMER1_CAPT_vect  _VECTOR(10)  /* Timer/Counter1 Capture Event */
 #define TIMER1_COMPA_vect _VECTOR(11)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */ 
+#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */
 #define TIMER1_OVF_vect   _VECTOR(13)  /* Timer/Counter1 Overflow */
 #define TIMER0_COMPA_vect _VECTOR(14)  /* TimerCounter0 Compare Match A */
 #define TIMER0_COMPB_vect _VECTOR(15)  /* TimerCounter0 Compare Match B */
@@ -861,7 +873,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -869,5 +881,5 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x0B
 
-
+/**@}*/
 #endif  /* _AVR_IOM168P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom169.h b/cpukit/score/cpu/avr/avr/iom169.h
index 88a757e2ec..64910dd115 100644
--- a/cpukit/score/cpu/avr/avr/iom169.h
+++ b/cpukit/score/cpu/avr/avr/iom169.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega169
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2002, 2003, 2004, 2005 
    Juergen Schilling <juergen.schilling@honeywell.com>
    Eric B. Weddington
@@ -50,6 +58,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_iom169 ATmega169 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 /* Port A */
@@ -1102,5 +1118,6 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x05
 
+/** @} */
 
 #endif  /* _AVR_IOM169_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom169p.h b/cpukit/score/cpu/avr/avr/iom169p.h
index 6aad286fc7..3d7995a3f5 100644
--- a/cpukit/score/cpu/avr/avr/iom169p.h
+++ b/cpukit/score/cpu/avr/avr/iom169p.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega169P
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2002, 2003, 2004, 2005, 2006
    Juergen Schilling <juergen.schilling@honeywell.com>
    Eric B. Weddington <ericw@evcohs.com>
@@ -49,6 +57,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_iom169p ATmega169P Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 /* Port A */
@@ -1025,5 +1041,6 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x05
 
+/** @} */
 
 #endif  /* _AVR_IOM169P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom169pa.h b/cpukit/score/cpu/avr/avr/iom169pa.h
index a2403f0546..4f457db5dd 100644
--- a/cpukit/score/cpu/avr/avr/iom169pa.h
+++ b/cpukit/score/cpu/avr/avr/iom169pa.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom169pa.h - definitions for ATmega169PA */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom169pa.h
+ *
+ * @brief Definitions for ATmega169PA
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *
+ *   * Neither the name of the copyright holders nor the names of
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,8 +46,15 @@
 #  define _AVR_IOXXX_H_ "iom169pa.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
+/**
+ * @defgroup AvrDef_iom169pa ATmega169PA Defintions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 #ifndef _AVR_ATmega169PA_H_
 #define _AVR_ATmega169PA_H_ 1
@@ -1467,5 +1479,5 @@
 #define ADC0_PIN   PINF
 #define ADC0_BIT   0
 
+/** @} */
 #endif /* _AVR_ATmega169PA_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom16a.h b/cpukit/score/cpu/avr/avr/iom16a.h
index 707c3b1803..ddfb220b99 100644
--- a/cpukit/score/cpu/avr/avr/iom16a.h
+++ b/cpukit/score/cpu/avr/avr/iom16a.h
@@ -47,9 +47,11 @@
 #ifndef _AVR_ATmega16A_H_
 #define _AVR_ATmega16A_H_ 1
 
-
-/* Registers and associated bit numbers. */
-
+/**
+ * @name Registers and Associated Bit Numbers
+ * 
+ */
+/**@{**/
 #define TWBR _SFR_IO8(0x00)
 #define TWBR0 0
 #define TWBR1 1
@@ -654,8 +656,13 @@
 #define OCR0_6 6
 #define OCR0_7 7
 
+/** @} */
 
-/* Interrupt vectors */
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 /* Vector 0 is the reset vector */
 #define INT0_vect_num  1
 #define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
@@ -668,9 +675,11 @@
 #define TIMER1_CAPT_vect_num  5
 #define TIMER1_CAPT_vect      _VECTOR(5)  /* Timer/Counter1 Capture Event */
 #define TIMER1_COMPA_vect_num  6
-#define TIMER1_COMPA_vect      _VECTOR(6)  /* Timer/Counter1 Compare Match A */
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect      _VECTOR(6)  
 #define TIMER1_COMPB_vect_num  7
-#define TIMER1_COMPB_vect      _VECTOR(7)  /* Timer/Counter1 Compare Match B */
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect      _VECTOR(7)  
 #define TIMER1_OVF_vect_num  8
 #define TIMER1_OVF_vect      _VECTOR(8)  /* Timer/Counter1 Overflow */
 #define TIMER0_OVF_vect_num  9
@@ -700,9 +709,13 @@
 
 #define _VECTOR_SIZE 4 /* Size of individual vector. */
 #define _VECTORS_SIZE (21 * _VECTOR_SIZE)
+/** @} */
 
-
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define SPM_PAGESIZE (128)
 #define RAMSTART     (0x60)
 #define RAMSIZE      (1024)
@@ -713,9 +726,13 @@
 #define E2END        (0x1FF)
 #define E2PAGESIZE   (4)
 #define FLASHEND     (0x3FFF)
+/** @} */
 
-
-/* Fuses */
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 2
 
 /* Low Fuse Byte */
@@ -726,34 +743,50 @@
 #define FUSE_SUT0  (unsigned char)~_BV(4)  /* Select start-up time */
 #define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
 #define FUSE_BODEN  (unsigned char)~_BV(6)  /* Brown out detector enable */
-#define FUSE_BODLEVEL  (unsigned char)~_BV(7)  /* Brown out detector trigger level */
-#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
+/* Brown out detector trigger level */
+#define FUSE_BODLEVEL  (unsigned char)~_BV(7)  
+#define LFUSE_DEFAULT (FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & \
+                       FUSE_CKSEL2 & FUSE_CKSEL1)
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
 #define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
 #define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
+/* EEPROM memory is preserved through chip erase */
+#define FUSE_EESAVE  (unsigned char)~_BV(3)  
 #define FUSE_CKOPT  (unsigned char)~_BV(4)  /* Oscillator Options */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
+/* Enable Serial programming and Data Downloading */
+#define FUSE_SPIEN  (unsigned char)~_BV(5)  
 #define FUSE_JTAGEN  (unsigned char)~_BV(6)  /* Enable JTAG */
 #define FUSE_OCDEN  (unsigned char)~_BV(7)  /* Enable OCD */
 #define HFUSE_DEFAULT (FUSE_JTAGEN & FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x03
+/** @} */
 
-
-/* Device Pin Definitions */
+/**
+ * @name Device Pin Definitions
+ * 
+ */
+/**@{**/
 #define MOSI_DDR   DDRB
 #define MOSI_PORT  PORTB
 #define MOSI_PIN   PINB
@@ -898,6 +931,7 @@
 #define SS_PORT  PORTB
 #define SS_PIN   PINB
 #define SS_BIT   4
+/** @} */
 
 #endif /* _AVR_ATmega16A_H_ */
 
diff --git a/cpukit/score/cpu/avr/avr/iom16hva.h b/cpukit/score/cpu/avr/avr/iom16hva.h
index cae9194539..7dcad90e37 100644
--- a/cpukit/score/cpu/avr/avr/iom16hva.h
+++ b/cpukit/score/cpu/avr/avr/iom16hva.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega16HVA
+ */
+
 /* Copyright (c) 2007, Anatoly Sokolov 
    All rights reserved.
 
@@ -36,6 +42,14 @@
 
 #include <avr/iomxxhva.h>
 
+/**
+ * @defgroup AvrDef_iom16hva ATmega16HVA Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Constants */
 #define SPM_PAGESIZE 128
 #define RAMEND      0x2FF
@@ -70,5 +84,6 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x0C
 
+/** @} */
 
 #endif /* _AVR_IOM16HVA_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom16hva2.h b/cpukit/score/cpu/avr/avr/iom16hva2.h
index 2f1893ff20..bca3d20d87 100644
--- a/cpukit/score/cpu/avr/avr/iom16hva2.h
+++ b/cpukit/score/cpu/avr/avr/iom16hva2.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom16hva2.h - definitions for ATmega16HVA2 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom16hva2.h
+ *
+ * @brief Definitions for ATmega16HVA2
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iom16hva2.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega16HVA2_H_
 #define _AVR_ATmega16HVA2_H_ 1
 
+/**
+ *  @defgroup Avr_iom16hva2 ATmega16HVA2 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -809,7 +820,7 @@
 #define PI_DDR   DDRI
 #define PI_PORT  PORTI
 #define PI_PIN   PINI
-#define PI_BIT   
+#define PI_BIT
 
 #define NI_DDR   DDRNI
 #define NI_PORT  PORTNI
@@ -866,5 +877,5 @@
 #define OC_PIN   PINOC
 #define OC_BIT   OC
 
+/**@}*/
 #endif /* _AVR_ATmega16HVA2_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom16hvb.h b/cpukit/score/cpu/avr/avr/iom16hvb.h
index ea3ab57001..ad6720eb45 100644
--- a/cpukit/score/cpu/avr/avr/iom16hvb.h
+++ b/cpukit/score/cpu/avr/avr/iom16hvb.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom16hvb.h - definitions for ATmega16HVB */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom16hvb.h
+ *
+ * @brief Definitions for ATmega16HVB
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *   Copyright (c) 2009 Atmel Corporation
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iom16hvb.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega16HVB_H_
 #define _AVR_ATmega16HVB_H_ 1
 
+/**
+ *  @defgroup Avr_iom16hvb ATmega16HVB Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -977,7 +988,7 @@
 #define PI_DDR   DDRI
 #define PI_PORT  PORTI
 #define PI_PIN   PINI
-#define PI_BIT   
+#define PI_BIT
 
 #define NI_DDR   DDRNI
 #define NI_PORT  PORTNI
@@ -1034,5 +1045,5 @@
 #define OC_PIN   PINOC
 #define OC_BIT   OC
 
+/**@}*/
 #endif /* _AVR_ATmega16HVB_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom16m1.h b/cpukit/score/cpu/avr/avr/iom16m1.h
index a7cb85e16a..4ca8f1e40c 100644
--- a/cpukit/score/cpu/avr/avr/iom16m1.h
+++ b/cpukit/score/cpu/avr/avr/iom16m1.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom16m1.h - definitions for ATmega16M1 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom16m1.h
+ *
+ * @brief Definitions for ATmega16M1
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iom16m1.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega16M1_H_
 #define _AVR_ATmega16M1_H_ 1
 
+/**
+ *  @defgroup Avr_iom16m1 ATmega16M1 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -1542,6 +1553,5 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x84
 
-
+/**@}*/
 #endif /* _AVR_ATmega16M1_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom16u2.h b/cpukit/score/cpu/avr/avr/iom16u2.h
index 346dda6d85..bae63fa594 100644
--- a/cpukit/score/cpu/avr/avr/iom16u2.h
+++ b/cpukit/score/cpu/avr/avr/iom16u2.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom16u2.h - definitions for ATmega16U2 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom16u2.h
+ *
+ * @brief Definitions for ATmega16U2
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iom16u2.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega16U2_H_
 #define _AVR_ATmega16U2_H_ 1
 
+/**
+ *  @defgroup Avr_iom16u2 ATmega16U2 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -973,7 +984,7 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x89
 
+/**@}*/
 
 /* Device Pin Definitions */
 #endif /* _AVR_ATmega16U2_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom16u4.h b/cpukit/score/cpu/avr/avr/iom16u4.h
index d87bfd2a7a..79e577919b 100644
--- a/cpukit/score/cpu/avr/avr/iom16u4.h
+++ b/cpukit/score/cpu/avr/avr/iom16u4.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom16u4.h - definitions for ATmega16U4 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file aavr/iom16u4.h
+ *
+ * @brief Definitions for ATmega16U4
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iom16u4.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega16U4_H_
 #define _AVR_ATmega16U4_H_ 1
 
+/**
+ *  @defgroup Avr_iom16u4 ATmega16U4 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -1351,6 +1362,5 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x88
 
-
+/**@}*/
 #endif /* _AVR_ATmega16U4_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom2560.h b/cpukit/score/cpu/avr/avr/iom2560.h
index 99cfca51e6..461f93611f 100644
--- a/cpukit/score/cpu/avr/avr/iom2560.h
+++ b/cpukit/score/cpu/avr/avr/iom2560.h
@@ -36,17 +36,24 @@
 
 #include <avr/iomxx0_1.h>
 
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define SPM_PAGESIZE    256
 #define RAMEND          0x21FF
 #define XRAMEND         0xFFFF
 #define E2END           0xFFF
 #define E2PAGESIZE      8
 #define FLASHEND        0x3FFFF
+/** @} */
 
-
-/* Fuses */
-
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 3
 
 /* Low Fuse Byte */
@@ -58,7 +65,8 @@
 #define FUSE_SUT1        (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
+                       FUSE_SUT0 & FUSE_CKDIV8)
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -76,18 +84,26 @@
 #define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
 #define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
 #define EFUSE_DEFAULT (0xFF)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x98
 #define SIGNATURE_2 0x01
-
+/** @} */
 
 #endif /* _AVR_IOM2560_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom32.h b/cpukit/score/cpu/avr/avr/iom32.h
index 7338261d75..88465252d6 100644
--- a/cpukit/score/cpu/avr/avr/iom32.h
+++ b/cpukit/score/cpu/avr/avr/iom32.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002, Steinar Haugen
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file avr/iom32.h
+ *
+ * @brief Definitions for ATmega32
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-/* avr/iom32.h - definitions for ATmega32 */
+/*
+ *  Copyright (c) 2002, Steinar Haugen
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM32_H_
 #define _AVR_IOM32_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom32 ATmega32 Definitons
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iom32.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -683,7 +695,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -691,5 +703,5 @@
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x02
 
-
+/**@}*/
 #endif /* _AVR_IOM32_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom323.h b/cpukit/score/cpu/avr/avr/iom323.h
index 8f6a4d1516..d631ab5e06 100644
--- a/cpukit/score/cpu/avr/avr/iom323.h
+++ b/cpukit/score/cpu/avr/avr/iom323.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002, Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file avr/iom323.h
+ *
+ * @brief Definitions for ATmega323
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-/* avr/iom323.h - definitions for ATmega323 */
+/*
+ *  Copyright (c) 2002 Marek Michalkiewicz
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM323_H_
 #define _AVR_IOM323_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom323 ATmega323 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iom323.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -675,7 +687,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -683,5 +695,5 @@
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x01
 
-
+/**@}*/
 #endif /* _AVR_IOM323_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom324.h b/cpukit/score/cpu/avr/avr/iom324.h
index 788113fd5f..09fbd51f66 100644
--- a/cpukit/score/cpu/avr/avr/iom324.h
+++ b/cpukit/score/cpu/avr/avr/iom324.h
@@ -1,39 +1,51 @@
-/* Copyright (c) 2005, 2006 Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/iom324.h - definitions for ATmega324 */
-
+/**
+ * @file avr/iom324.h
+ *
+ * @brief Definitions for ATmega324
+ */
+
+/*
+ *   Copyright (c) 2005, 2006 Anatoly Sokolov
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM324_H_
 #define _AVR_IOM324_H_ 1
 
+/**
+ *  @defgroup Avr_iom324 ATmega324 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #include <avr/iomxx4.h>
 
 /* Constants */
@@ -81,13 +93,13 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature (ATmega324P) */
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x95
-#define SIGNATURE_2 0x08 
-
+#define SIGNATURE_2 0x08
 
+/**@}*/
 #endif /* _AVR_IOM324_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom325.h b/cpukit/score/cpu/avr/avr/iom325.h
index d22911c8e9..7d4f582aaf 100644
--- a/cpukit/score/cpu/avr/avr/iom325.h
+++ b/cpukit/score/cpu/avr/avr/iom325.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega325 and ATmega325P
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2004, 2005, 2006, 2007 Eric B. Weddington
    All rights reserved.
 
@@ -46,6 +54,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_iom325  ATmega325 and ATmega325P Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Registers and associated bit numbers */
 
 #define PINA    _SFR_IO8(0x00)
@@ -816,5 +832,6 @@
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x05
 
+/** @} */
 
 #endif /* _AVR_IOM325_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom3250.h b/cpukit/score/cpu/avr/avr/iom3250.h
index 21d0ad123e..6c3cb35a0f 100644
--- a/cpukit/score/cpu/avr/avr/iom3250.h
+++ b/cpukit/score/cpu/avr/avr/iom3250.h
@@ -46,8 +46,11 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
-/* Registers and associated bit numbers */
-
+/**
+ * @name Registers and Associated Bit Numbers
+ * 
+ */
+/**@{**/
 #define PINA    _SFR_IO8(0x00)
 #define PINA7   7
 #define PINA6   6
@@ -295,12 +298,15 @@
 #define EEARL   _SFR_IO8(0x21)
 #define EEARH   _SFR_IO8(0X22)
 
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
+/*
+ * 6-char sequence denoting where to find the EEPROM registers in 
+ * memory space.
+ * Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+ * subroutines.
+ * First two letters:  EECR address.
+ * Second two letters: EEDR address.
+ * Last two letters:   EEAR address.  
+ */
 #define __EEPROM_REG_LOCATIONS__ 1F2021
 
 #define GTCCR   _SFR_IO8(0x23)
@@ -751,9 +757,13 @@
 #define PJ0     0
 
 /* Reserved [0xDE..0xFF] */
+/** @} */
 
-
-/* Interrupt vectors */
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
 #define INT0_vect			_VECTOR(1)
@@ -851,19 +861,26 @@
 #define SIG_PIN_CHANGE3			_VECTOR(24)
 
 #define _VECTORS_SIZE 100
+/** @} */
 
-
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define SPM_PAGESIZE    128
 #define RAMEND          0x8FF
 #define XRAMEND         RAMEND
 #define E2END           0x3FF
 #define E2PAGESIZE      4
 #define FLASHEND        0x7FFF
+/** @} */
 
-
-/* Fuses */
-
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 3
 
 /* Low Fuse Byte */
@@ -875,7 +892,8 @@
 #define FUSE_SUT1        (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
+                       FUSE_SUT0 & FUSE_CKDIV8)
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -893,18 +911,26 @@
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
 #define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
 #define EFUSE_DEFAULT (0xFF)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x06
-
+/** @} */
 
 #endif /* _AVR_IOM3250_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom328p.h b/cpukit/score/cpu/avr/avr/iom328p.h
index 179f0a5e2d..b2bb6b58bf 100644
--- a/cpukit/score/cpu/avr/avr/iom328p.h
+++ b/cpukit/score/cpu/avr/avr/iom328p.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega328P
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2007 Atmel Corporation
    All rights reserved.
 
@@ -48,6 +56,14 @@
 #ifndef _AVR_IOM328P_H_
 #define _AVR_IOM328P_H_ 1
 
+/**
+ * @defgroup AvrDef_iom328p ATmega328P Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Registers and associated bit numbers */
 
 #define PINB _SFR_IO8(0x03)
@@ -870,5 +886,6 @@
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x0F
 
+/** @} */
 
 #endif  /* _AVR_IOM328P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom329.h b/cpukit/score/cpu/avr/avr/iom329.h
index fc96d00a7e..a7b5efdfd1 100644
--- a/cpukit/score/cpu/avr/avr/iom329.h
+++ b/cpukit/score/cpu/avr/avr/iom329.h
@@ -46,8 +46,11 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
-/* Registers and associated bit numbers */
-
+/**
+ * @name Registers and Associated Bit Numbers
+ * 
+ */
+/**@{**/
 #define PINA    _SFR_IO8(0x00)
 #define PINA7   7
 #define PINA6   6
@@ -291,12 +294,15 @@
 #define EEARL  _SFR_IO8(0x21)
 #define EEARH  _SFR_IO8(0X22)
 
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
+/* 
+ * 6-char sequence denoting where to find the EEPROM registers in 
+ * memory space.
+ * Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+ * subroutines.
+ * First two letters:  EECR address.
+ * Second two letters: EEDR address.
+ * Last two letters:   EEAR address.  
+ */
 #define __EEPROM_REG_LOCATIONS__ 1F2021
 
 #define GTCCR   _SFR_IO8(0x23)
@@ -852,8 +858,13 @@
 #define SEG324  0
 
 /* Reserved [0xFF] */
+/** @} */
 
-/* Interrupt vectors */
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 /* Vector 0 is the reset vector */
 /* External Interrupt Request 0 */
 #define INT0_vect			_VECTOR(1)
@@ -944,19 +955,26 @@
 #define SIG_LCD				_VECTOR(22)
 
 #define _VECTORS_SIZE 92
+/** @} */
 
-
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define SPM_PAGESIZE    128
 #define RAMEND          0x8FF
 #define XRAMEND         RAMEND
 #define E2END           0x3FF
 #define E2PAGESIZE      4
 #define FLASHEND        0x7FFF
+/** @} */
 
-
-/* Fuses */
-
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 3
 
 /* Low Fuse Byte */
@@ -968,7 +986,8 @@
 #define FUSE_SUT1        (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
+                       FUSE_SUT0 & FUSE_CKDIV8)
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -979,25 +998,34 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_JTAGEN      (unsigned char)~_BV(6)
 #define FUSE_OCDEN       (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN & FUSE_JTAGEN)
+#define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & \
+                       FUSE_SPIEN & FUSE_JTAGEN)
 
 /* Extended Fuse Byte */
 #define FUSE_RSTDISBL    (unsigned char)~_BV(0)
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(1)
 #define FUSE_BODLEVEL1   (unsigned char)~_BV(2)
 #define EFUSE_DEFAULT (0xFF)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x03
-
+/** @} */
 
 #endif /* _AVR_IOM329_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom3290.h b/cpukit/score/cpu/avr/avr/iom3290.h
index b8ddf19cc6..f349821f77 100644
--- a/cpukit/score/cpu/avr/avr/iom3290.h
+++ b/cpukit/score/cpu/avr/avr/iom3290.h
@@ -1,35 +1,41 @@
-/* Copyright (c) 2004 Eric B. Weddington
-   Copyright (c) 2005, 2006, 2007 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/iom3290.h - definitions for ATmega3290 and ATmega3290P.  */
+/**
+ * @file avr/iom3290.h
+ *
+ * @brief Definitions for ATmega3290 and ATmega3290P
+ */
+
+/*
+ *   Copyright (c) 2004 Eric B. Weddington
+ *   Copyright (c) 2005, 2006, 2007 Anatoly Sokolov
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *
+ *   * Neither the name of the copyright holders nor the names of
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM3290_H_
 #define _AVR_IOM3290_H_ 1
@@ -44,7 +50,15 @@
 #  define _AVR_IOXXX_H_ "iom3290.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
+
+/**
+ * @defgroup AvrDef_iom3290 ATmega3290, ATmega3290P Defintions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* Registers and associated bit numbers */
 
@@ -1143,7 +1157,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -1151,5 +1165,5 @@
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x04
 
-
+/** @} */
 #endif /* _AVR_IOM3290_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom32c1.h b/cpukit/score/cpu/avr/avr/iom32c1.h
index 0147aee979..a0d4017026 100644
--- a/cpukit/score/cpu/avr/avr/iom32c1.h
+++ b/cpukit/score/cpu/avr/avr/iom32c1.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom32c1.h - definitions for ATmega32C1 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom32c1.h
+ *
+ * @brief Definitions for ATmega32C1
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *
+ *   * Neither the name of the copyright holders nor the names of
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,19 @@
 #  define _AVR_IOXXX_H_ "iom32c1.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega32C1_H_
 #define _AVR_ATmega32C1_H_ 1
 
+/**
+ * @defgroup Avr_iom32c1 ATmega32C1 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* Registers and associated bit numbers. */
 
@@ -1292,5 +1304,5 @@
 #define SIGNATURE_2 0x86
 
 
+/** @} */
 #endif /* _AVR_ATmega32C1_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom32m1.h b/cpukit/score/cpu/avr/avr/iom32m1.h
index bf12d9f513..f8bf88396e 100644
--- a/cpukit/score/cpu/avr/avr/iom32m1.h
+++ b/cpukit/score/cpu/avr/avr/iom32m1.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2008-2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom32m1.h - definitions for ATmega32M1 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom32m1.h
+ *
+ * @brief Definitions for ATmega32M1
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2008-2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,19 @@
 #  define _AVR_IOXXX_H_ "iom32m1.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega32M1_H_
 #define _AVR_ATmega32M1_H_ 1
 
+/**
+ * @defgroup AvrDef_iom32m1 ATmega32M1 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* Registers and associated bit numbers. */
 
@@ -1566,5 +1578,5 @@
 #define SIGNATURE_2 0x84
 
 
+/** @} */
 #endif /* _AVR_ATmega32M1_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom32u2.h b/cpukit/score/cpu/avr/avr/iom32u2.h
index 5859281230..10e835e6ed 100644
--- a/cpukit/score/cpu/avr/avr/iom32u2.h
+++ b/cpukit/score/cpu/avr/avr/iom32u2.h
@@ -47,9 +47,11 @@
 #ifndef _AVR_ATmega32U2_H_
 #define _AVR_ATmega32U2_H_ 1
 
-
-/* Registers and associated bit numbers. */
-
+/**
+ * @name Registers and Associated Bit Numbers
+ * 
+ */
+/**@{**/
 #define PINB _SFR_IO8(0x03)
 #define PINB0 0
 #define PINB1 1
@@ -851,9 +853,13 @@
 #define UPDRV1 5
 #define UPWE0 6
 #define UPWE1 7
+/** @} */
 
-
-/* Interrupt vectors */
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 /* Vector 0 is the reset vector */
 #define INT0_vect_num  1
 #define INT0_vect      _VECTOR(1)  /* External Interrupt Request 0 */
@@ -878,17 +884,21 @@
 #define USB_GEN_vect_num  11
 #define USB_GEN_vect      _VECTOR(11)  /* USB General Interrupt Request */
 #define USB_COM_vect_num  12
-#define USB_COM_vect      _VECTOR(12)  /* USB Endpoint/Pipe Interrupt Communication Request */
+/* USB Endpoint/Pipe Interrupt Communication Request */
+#define USB_COM_vect      _VECTOR(12)  
 #define WDT_vect_num  13
 #define WDT_vect      _VECTOR(13)  /* Watchdog Time-out Interrupt */
 #define TIMER1_CAPT_vect_num  14
 #define TIMER1_CAPT_vect      _VECTOR(14)  /* Timer/Counter2 Capture Event */
 #define TIMER1_COMPA_vect_num  15
-#define TIMER1_COMPA_vect      _VECTOR(15)  /* Timer/Counter2 Compare Match B */
+/* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPA_vect      _VECTOR(15)  
 #define TIMER0_COMPA_vect_num  19
-#define TIMER0_COMPA_vect      _VECTOR(19)  /* Timer/Counter0 Compare Match A */
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect      _VECTOR(19)  
 #define TIMER0_COMPB_vect_num  20
-#define TIMER0_COMPB_vect      _VECTOR(20)  /* Timer/Counter0 Compare Match B */
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect      _VECTOR(20)  
 #define TIMER0_OVF_vect_num  21
 #define TIMER0_OVF_vect      _VECTOR(21)  /* Timer/Counter0 Overflow */
 #define SPI_STC_vect_num  22
@@ -906,15 +916,17 @@
 #define SPM_READY_vect_num  28
 #define SPM_READY_vect      _VECTOR(28)  /* Store Program Memory Read */
 #define TIMER1_COMPB_vect_num  16
-#define TIMER1_COMPB_vect      _VECTOR(16)  /* Timer/Counter2 Compare Match B */
+/* Timer/Counter2 Compare Match B */
+#define TIMER1_COMPB_vect      _VECTOR(16)  
 #define TIMER1_COMPC_vect_num  17
-#define TIMER1_COMPC_vect      _VECTOR(17)  /* Timer/Counter2 Compare Match C */
+/* Timer/Counter2 Compare Match C */
+#define TIMER1_COMPC_vect      _VECTOR(17)  
 #define TIMER1_OVF_vect_num  18
 #define TIMER1_OVF_vect      _VECTOR(18)  /* Timer/Counter1 Overflow */
 
 #define _VECTOR_SIZE 4 /* Size of individual vector. */
 #define _VECTORS_SIZE (38 * _VECTOR_SIZE)
-
+/** @} */
 
 /* Constants */
 #define SPM_PAGESIZE (128)
@@ -927,9 +939,13 @@
 #define E2END        (0x3FF)
 #define E2PAGESIZE   (4)
 #define FLASHEND     (0x7FFF)
+/** @} */
 
-
-/* Fuses */
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 3
 
 /* Low Fuse Byte */
@@ -941,38 +957,52 @@
 #define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
 #define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator options */
 #define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & \
+                       FUSE_CKSEL2 & FUSE_CKSEL1)
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
 #define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
 #define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
+/* EEPROM memory is preserved through chip erase */
+#define FUSE_EESAVE  (unsigned char)~_BV(3)
 #define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
+/* Enable Serial programming and Data Downloading */
+#define FUSE_SPIEN  (unsigned char)~_BV(5)  
 #define FUSE_RSTDISBL  (unsigned char)~_BV(6)  /* External Reset Disable */
 #define FUSE_DWEN  (unsigned char)~_BV(7)  /* dwbugWIRE Enable */
 #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
 
 /* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector trigger level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector trigger level */
+/* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  
+/* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  
+/* Brown-out Detector trigger level */
+#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  
 #define FUSE_HWBE  (unsigned char)~_BV(3)  /* Hardware Boot Enable */
 #define EFUSE_DEFAULT (0xFF)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x8A
-
+/** @} */
 
 /* Device Pin Definitions */
 #endif /* _AVR_ATmega32U2_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom32u4.h b/cpukit/score/cpu/avr/avr/iom32u4.h
index 87f3b360ad..263d40f9b2 100644
--- a/cpukit/score/cpu/avr/avr/iom32u4.h
+++ b/cpukit/score/cpu/avr/avr/iom32u4.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega32U4
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2008 Atmel Corporation
    All rights reserved.
 
@@ -48,6 +56,13 @@
 #ifndef _AVR_IOM32U4_H_
 #define _AVR_IOM32U4_H_ 1
 
+/**
+ * @defgroup AvrDef_iom32u4 ATmega32U4 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* Registers and associated bit numbers */
 
@@ -1498,6 +1513,6 @@
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x87
 
-
+/** @} */
 
 #endif  /* _AVR_IOM32U4_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom32u6.h b/cpukit/score/cpu/avr/avr/iom32u6.h
index a8b7f566f1..9f4211dd80 100644
--- a/cpukit/score/cpu/avr/avr/iom32u6.h
+++ b/cpukit/score/cpu/avr/avr/iom32u6.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2008 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom32u6.h - definitions for ATmega32U6 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom32u6.h
+ *
+ * @brief Definitions for ATmega32U6
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2008 Atmel Corporation
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iom32u6.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega32U6_H_
 #define _AVR_ATmega32U6_H_ 1
 
+/**
+ *  @defgroup Avr_iom32u6 ATmega32U6 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -1406,5 +1417,5 @@
 #define SIGNATURE_2 0x88
 
 
+/**@}*/
 #endif /* _AVR_ATmega32U6_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom406.h b/cpukit/score/cpu/avr/avr/iom406.h
index a349ff369c..b0baafd024 100644
--- a/cpukit/score/cpu/avr/avr/iom406.h
+++ b/cpukit/score/cpu/avr/avr/iom406.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2006, Pieter Conradie
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom406.h - definitions for ATmega406 */
+/**
+ * @file avr/iom406.h
+ *
+ * @brief Definitions for ATmega406
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2006, Pieter Conradie
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM406_H_
 #define _AVR_IOM406_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom406 ATmega406 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iom406.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -348,13 +360,13 @@
 
 /* Pin Change Mask Register 1 */
 #define PCMSK1  _SFR_MEM8(0x6C)
-#define PCINT15 7 
-#define PCINT14 6 
-#define PCINT13 5 
-#define PCINT12 4 
-#define PCINT11 3 
-#define PCINT10 2 
-#define PCINT9  1 
+#define PCINT15 7
+#define PCINT14 6
+#define PCINT13 5
+#define PCINT12 4
+#define PCINT11 3
+#define PCINT10 2
+#define PCINT9  1
 #define PCINT8  0
 
 /* Reserved [0x6D] */
@@ -755,7 +767,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -764,4 +776,5 @@
 #define SIGNATURE_2 0x07
 
 
+/**@}*/
 #endif /* _AVR_IOM406_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom48.h b/cpukit/score/cpu/avr/avr/iom48.h
index 57d345e23b..2840dff539 100644
--- a/cpukit/score/cpu/avr/avr/iom48.h
+++ b/cpukit/score/cpu/avr/avr/iom48.h
@@ -1,37 +1,51 @@
-/* Copyright (c) 2004, Theodore A. Roth
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file
+ *
+ * @brief Definitions for iom48
+ */
+
+/*
+ *  Copyright (c) 2004, Theodore A. Roth
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM48_H_
 #define _AVR_IOM48_H_ 1
 
+/**
+ *  @defgroup Avr_iom48 iom48 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #include <avr/iomx8.h>
 
 /* Constants */
@@ -82,5 +96,5 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x05
 
-
+/**@}*/
 #endif /* _AVR_IOM48_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom48p.h b/cpukit/score/cpu/avr/avr/iom48p.h
index 2ced5dc8a9..db48949ae3 100644
--- a/cpukit/score/cpu/avr/avr/iom48p.h
+++ b/cpukit/score/cpu/avr/avr/iom48p.h
@@ -1,38 +1,42 @@
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iom48p.h - definitions for ATmega48P. */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom48p.h
+ *
+ * @brief Definitions for ATmega48P
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *   Copyright (c) 2007 Atmel Corporation
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -42,12 +46,19 @@
 #  define _AVR_IOXXX_H_ "iom48p.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_IOM48P_H_
 #define _AVR_IOM48P_H_ 1
 
+/**
+ *  @defgroup Avr_iom48p ATmega48P Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 /* Registers and associated bit numbers */
 
 #define PINB _SFR_IO8(0x03)
@@ -791,7 +802,7 @@
 #define TIMER2_OVF_vect   _VECTOR(9)   /* Timer/Counter2 Overflow */
 #define TIMER1_CAPT_vect  _VECTOR(10)  /* Timer/Counter1 Capture Event */
 #define TIMER1_COMPA_vect _VECTOR(11)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */ 
+#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */
 #define TIMER1_OVF_vect   _VECTOR(13)  /* Timer/Counter1 Overflow */
 #define TIMER0_COMPA_vect _VECTOR(14)  /* TimerCounter0 Compare Match A */
 #define TIMER0_COMPB_vect _VECTOR(15)  /* TimerCounter0 Compare Match B */
@@ -855,7 +866,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -864,4 +875,5 @@
 #define SIGNATURE_2 0x0A
 
 
+/**@}*/
 #endif  /* _AVR_IOM48P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom640.h b/cpukit/score/cpu/avr/avr/iom640.h
index f3fe369042..d542d2eed5 100644
--- a/cpukit/score/cpu/avr/avr/iom640.h
+++ b/cpukit/score/cpu/avr/avr/iom640.h
@@ -1,39 +1,52 @@
-/* Copyright (c) 2005 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom640.h - definitions for ATmega640 */
+/**
+ * @file avr/iom640.h
+ *
+ * @brief Definitions for ATmega640
+ */
+
+/*
+ * Copyright (c) 2005 Anatoly Sokolov
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM640_H_
 #define _AVR_IOM640_H_ 1
 
+/**
+ * @defgroup Avr_iom640 ATmega640 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 #include <avr/iomxx0_1.h>
 
 /* Constants */
@@ -81,7 +94,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -89,5 +102,5 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x08
 
-
+/** @} */
 #endif /* _AVR_IOM640_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom644.h b/cpukit/score/cpu/avr/avr/iom644.h
index 2ad996c647..dcfab293ef 100644
--- a/cpukit/score/cpu/avr/avr/iom644.h
+++ b/cpukit/score/cpu/avr/avr/iom644.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega644
+ */
+
 /* Copyright (c) 2005 Anatoly Sokolov
    All rights reserved.
 
@@ -36,6 +42,14 @@
 
 #include <avr/iomxx4.h>
 
+/**
+ * @defgroup AvrDef_iom644 ATmega644 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Constants */
 #define SPM_PAGESIZE 256
 #define RAMEND       0x10FF
@@ -89,5 +103,6 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x09
 
+/** @} */
 
 #endif /* _AVR_IOM644_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom644p.h b/cpukit/score/cpu/avr/avr/iom644p.h
index 21b19d4392..5c42b09c6d 100644
--- a/cpukit/score/cpu/avr/avr/iom644p.h
+++ b/cpukit/score/cpu/avr/avr/iom644p.h
@@ -36,17 +36,24 @@
 
 #include <avr/iomxx4.h>
 
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define SPM_PAGESIZE 256
 #define RAMEND       0x10FF
 #define XRAMEND      RAMEND
 #define E2END        0x7FF
 #define E2PAGESIZE   8
 #define FLASHEND     0xFFFF
+/** @} */
 
-
-/* Fuses */
-
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 3
 
 /* Low Fuse Byte */
@@ -58,7 +65,8 @@
 #define FUSE_SUT1        (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
+                       FUSE_SUT0 & FUSE_SUT1 & FUSE_CKDIV8)
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -76,18 +84,26 @@
 #define FUSE_BODLEVEL1   (unsigned char)~_BV(1)
 #define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
 #define EFUSE_DEFAULT (0xFF)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x0A
-
+/** @} */
 
 #endif /* _AVR_IOM644P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom644pa.h b/cpukit/score/cpu/avr/avr/iom644pa.h
index 0bcf3e6e50..e794e089a5 100644
--- a/cpukit/score/cpu/avr/avr/iom644pa.h
+++ b/cpukit/score/cpu/avr/avr/iom644pa.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom644PA.h - definitions for ATmega644PA */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom644PA.h
+ *
+ * @brief Definitions for ATmega644PA
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iom644PA.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega644PA_H_
 #define _AVR_ATmega644PA_H_ 1
 
+/**
+ *  @defgroup Avr_iom644PA ATmega644PA Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -1365,5 +1376,5 @@
 #define PCINT12_PIN   PINB
 #define PCINT12_BIT   4
 
+/**@}*/
 #endif /* _AVR_ATmega644PA_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom645.h b/cpukit/score/cpu/avr/avr/iom645.h
index 1b73f2be69..991ff821fd 100644
--- a/cpukit/score/cpu/avr/avr/iom645.h
+++ b/cpukit/score/cpu/avr/avr/iom645.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2004,2005,2006 Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom645.h - definitions for ATmega645 */
+/**
+ * @file avr/iom645.h
+ *
+ * @brief Definitions for ATmega645
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *   Copyright (c) 2004,2005,2006 Eric B. Weddington
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM645_H_
 #define _AVR_IOM645_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom645 ATmega645 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iom645.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* Registers and associated bit numbers */
 
@@ -803,7 +815,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -811,5 +823,5 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x05
 
-
+/**@}*/
 #endif /* _AVR_IOM645_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom6450.h b/cpukit/score/cpu/avr/avr/iom6450.h
index 8317f18013..fa2203e527 100644
--- a/cpukit/score/cpu/avr/avr/iom6450.h
+++ b/cpukit/score/cpu/avr/avr/iom6450.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega6450
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2004,2005,2006 Eric B. Weddington
    All rights reserved.
 
@@ -46,6 +54,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_iom6450 ATmega6450 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Registers and associated bit numbers */
 
 #define PINA    _SFR_IO8(0x00)
@@ -902,5 +918,6 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x06
 
+/** @} */
 
 #endif /* _AVR_IOM6450_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom649.h b/cpukit/score/cpu/avr/avr/iom649.h
index c9d5058a24..2064573933 100644
--- a/cpukit/score/cpu/avr/avr/iom649.h
+++ b/cpukit/score/cpu/avr/avr/iom649.h
@@ -1,40 +1,53 @@
-/* Copyright (c) 2004 Eric B. Weddington
-   Copyright (c) 2005,2006 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/iom649.h - definitions for ATmega649 */
+/**
+ * @file avr/iom649.h
+ *
+ * @brief Definitions for ATmega649
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2004 Eric B. Weddington
+ *  Copyright (c) 2005,2006 Anatoly Sokolov
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM649_H_
 #define _AVR_IOM649_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom649 ATmega649 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +57,7 @@
 #  define _AVR_IOXXX_H_ "iom649.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* Registers and associated bit numbers */
 
@@ -980,7 +993,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -988,5 +1001,5 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x03
 
-
+/**@}*/
 #endif /* _AVR_IOM649_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom6490.h b/cpukit/score/cpu/avr/avr/iom6490.h
index f678acf30f..10334d7677 100644
--- a/cpukit/score/cpu/avr/avr/iom6490.h
+++ b/cpukit/score/cpu/avr/avr/iom6490.h
@@ -1,40 +1,53 @@
-/* Copyright (c) 2004 Eric B. Weddington
-   Copyright (c) 2005,2006 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/iom6490.h - definitions for ATmega6490 */
+/**
+ * @file avr/iom6490.h
+ *
+ * @brief Definitions for ATmega6490
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2004 Eric B. Weddington
+ *  Copyright (c) 2005,2006 Anatoly Sokolov
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM6490_H_
 #define _AVR_IOM6490_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom6490 ATmega6490 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +57,7 @@
 #  define _AVR_IOXXX_H_ "iom6490.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* Registers and associated bit numbers */
 
@@ -1132,7 +1145,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -1141,4 +1154,5 @@
 #define SIGNATURE_2 0x04
 
 
+/**@}*/
 #endif /* _AVR_IOM6490_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom64c1.h b/cpukit/score/cpu/avr/avr/iom64c1.h
index a30aee0d98..5895fe9857 100644
--- a/cpukit/score/cpu/avr/avr/iom64c1.h
+++ b/cpukit/score/cpu/avr/avr/iom64c1.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega64C1
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2009 Atmel Corporation
    All rights reserved.
 
@@ -47,6 +55,13 @@
 #ifndef _AVR_ATmega64C1_H_
 #define _AVR_ATmega64C1_H_ 1
 
+/**
+ * @defgroup AvrDef_iom64c1 ATmega64C1 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* Registers and associated bit numbers. */
 
@@ -1292,6 +1307,7 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x86
 
+/** @} */
 
 #endif /* _AVR_ATmega64C1_H_ */
 
diff --git a/cpukit/score/cpu/avr/avr/iom64hve.h b/cpukit/score/cpu/avr/avr/iom64hve.h
index 2e2debc19f..913697de98 100644
--- a/cpukit/score/cpu/avr/avr/iom64hve.h
+++ b/cpukit/score/cpu/avr/avr/iom64hve.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom64hve.h - definitions for ATmega64HVE */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom64hve.h
+ *
+ * @brief Definitions for ATmega64HVE
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iom64hve.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATmega64HVE_H_
 #define _AVR_ATmega64HVE_H_ 1
 
+/**
+ *  @defgroup Avr_iom64hve ATmega64HVE Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -958,7 +969,7 @@
 #define PI_DDR   DDRI
 #define PI_PORT  PORTI
 #define PI_PIN   PINI
-#define PI_BIT   
+#define PI_BIT
 
 #define NI_DDR   DDRNI
 #define NI_PORT  PORTNI
@@ -1015,5 +1026,5 @@
 #define OC_PIN   PINOC
 #define OC_BIT   OC
 
+/**@}*/
 #endif /* _AVR_ATmega64HVE_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iom64m1.h b/cpukit/score/cpu/avr/avr/iom64m1.h
index 6a97062440..492e524185 100644
--- a/cpukit/score/cpu/avr/avr/iom64m1.h
+++ b/cpukit/score/cpu/avr/avr/iom64m1.h
@@ -48,8 +48,11 @@
 #define _AVR_ATmega64M1_H_ 1
 
 
-/* Registers and associated bit numbers. */
-
+/**
+ * @name Registers and Associated Bit Numbers
+ * 
+ */
+/**@{**/
 #define PINB _SFR_IO8(0x03)
 #define PINB0 0
 #define PINB1 1
@@ -1415,9 +1418,13 @@
 #define MSG5 5
 #define MSG6 6
 #define MSG7 7
+/** @} */
 
-
-/* Interrupt vectors */
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 /* Vector 0 is the reset vector */
 #define ANACOMP0_vect_num  1
 #define ANACOMP0_vect      _VECTOR(1)  /* Analog Comparator 0 */
@@ -1442,15 +1449,19 @@
 #define TIMER1_CAPT_vect_num  11
 #define TIMER1_CAPT_vect      _VECTOR(11)  /* Timer/Counter1 Capture Event */
 #define TIMER1_COMPA_vect_num  12
-#define TIMER1_COMPA_vect      _VECTOR(12)  /* Timer/Counter1 Compare Match A */
+/* Timer/Counter1 Compare Match A */
+#define TIMER1_COMPA_vect      _VECTOR(12)  
 #define TIMER1_COMPB_vect_num  13
-#define TIMER1_COMPB_vect      _VECTOR(13)  /* Timer/Counter1 Compare Match B */
+/* Timer/Counter1 Compare Match B */
+#define TIMER1_COMPB_vect      _VECTOR(13)  
 #define TIMER1_OVF_vect_num  14
 #define TIMER1_OVF_vect      _VECTOR(14)  /* Timer1/Counter1 Overflow */
 #define TIMER0_COMPA_vect_num  15
-#define TIMER0_COMPA_vect      _VECTOR(15)  /* Timer/Counter0 Compare Match A */
+/* Timer/Counter0 Compare Match A */
+#define TIMER0_COMPA_vect      _VECTOR(15)  
 #define TIMER0_COMPB_vect_num  16
-#define TIMER0_COMPB_vect      _VECTOR(16)  /* Timer/Counter0 Compare Match B */
+/* Timer/Counter0 Compare Match B */
+#define TIMER0_COMPB_vect      _VECTOR(16)  
 #define TIMER0_OVF_vect_num  17
 #define TIMER0_OVF_vect      _VECTOR(17)  /* Timer/Counter0 Overflow */
 #define CAN_INT_vect_num  18
@@ -1482,9 +1493,13 @@
 
 #define _VECTOR_SIZE 4 /* Size of individual vector. */
 #define _VECTORS_SIZE (31 * _VECTOR_SIZE)
+/** @} */
 
-
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define SPM_PAGESIZE (256)
 #define RAMSTART     (0x0100)
 #define RAMSIZE      (4096)
@@ -1495,9 +1510,13 @@
 #define E2END        (0x7FF)
 #define E2PAGESIZE   (8)
 #define FLASHEND     (0xFFFF)
+/** @} */
 
-
-/* Fuses */
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 3
 
 /* Low Fuse Byte */
@@ -1509,40 +1528,54 @@
 #define FUSE_SUT1  (unsigned char)~_BV(5)  /* Select start-up time */
 #define FUSE_CKOUT  (unsigned char)~_BV(6)  /* Oscillator output option */
 #define FUSE_CKDIV8  (unsigned char)~_BV(7)  /* Divide clock by 8 */
-#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
+#define LFUSE_DEFAULT (FUSE_CKDIV8 & FUSE_SUT1 & FUSE_SUT0 & \
+                       FUSE_CKSEL3 & FUSE_CKSEL2 & FUSE_CKSEL1)
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST  (unsigned char)~_BV(0)  /* Select Reset Vector */
 #define FUSE_BOOTSZ0  (unsigned char)~_BV(1)  /* Select Boot Size */
 #define FUSE_BOOTSZ1  (unsigned char)~_BV(2)  /* Select Boot Size */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* EEPROM memory is preserved through chip erase */
+/* EEPROM memory is preserved through chip erase */
+#define FUSE_EESAVE  (unsigned char)~_BV(3)  
 #define FUSE_WDTON  (unsigned char)~_BV(4)  /* Watchdog timer always on */
-#define FUSE_SPIEN  (unsigned char)~_BV(5)  /* Enable Serial programming and Data Downloading */
+/* Enable Serial programming and Data Downloading */
+#define FUSE_SPIEN  (unsigned char)~_BV(5)  
 #define FUSE_DWEN  (unsigned char)~_BV(6)  /* DebugWIRE Enable */
 #define FUSE_RSTDISBL  (unsigned char)~_BV(7)  /* External Reset Disable */
 #define HFUSE_DEFAULT (FUSE_SPIEN & FUSE_BOOTSZ1 & FUSE_BOOTSZ0)
 
 /* Extended Fuse Byte */
-#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  /* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  /* Brown-out Detector Trigger Level */
-#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  /* Brown-out Detector Trigger Level */
+/* Brown-out Detector Trigger Level */
+#define FUSE_BODLEVEL0  (unsigned char)~_BV(0)  
+/* Brown-out Detector Trigger Level */
+#define FUSE_BODLEVEL1  (unsigned char)~_BV(1)  
+/* Brown-out Detector Trigger Level */
+#define FUSE_BODLEVEL2  (unsigned char)~_BV(2)  
 #define FUSE_PSCRVB  (unsigned char)~_BV(3)  /* PSC Outputs xB Reset Value */
 #define FUSE_PSCRVA  (unsigned char)~_BV(4)  /* PSC Outputs xA Reset Value */
 #define FUSE_PSCRB  (unsigned char)~_BV(5)  /* PSC Reset Behavior */
 #define EFUSE_DEFAULT (FUSE_BODLEVEL2 & FUSE_BODLEVEL1)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x84
-
+/** @} */
 
 #endif /* _AVR_ATmega64M1_H_ */
 
diff --git a/cpukit/score/cpu/avr/avr/iom8.h b/cpukit/score/cpu/avr/avr/iom8.h
index 02ad8e1ac3..c918b43dfb 100644
--- a/cpukit/score/cpu/avr/avr/iom8.h
+++ b/cpukit/score/cpu/avr/avr/iom8.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega8
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2002, Marek Michalkiewicz
    All rights reserved.
 
@@ -46,6 +54,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_iom8 ATmega8 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
@@ -609,5 +625,6 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x07
 
+/** @} */
 
 #endif /* _AVR_IOM8_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom8515.h b/cpukit/score/cpu/avr/avr/iom8515.h
index 0516670064..7576f8df4e 100644
--- a/cpukit/score/cpu/avr/avr/iom8515.h
+++ b/cpukit/score/cpu/avr/avr/iom8515.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002, Steinar Haugen
-   All rights reserved.
+/**
+ * @file avr/iom8515.h
+ *
+ * @brief Definitions for ATmega8515
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iom8515.h - definitions for ATmega8515 */
+/*
+ *  Copyright (c) 2002, Steinar Haugen
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOM8515_H_
 #define _AVR_IOM8515_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iom8515 ATmega8515 Definitons
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iom8515.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -623,7 +635,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -631,5 +643,5 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x06
 
-
+/**@}*/
 #endif /* _AVR_IOM8515_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom8535.h b/cpukit/score/cpu/avr/avr/iom8535.h
index 035587103e..061a0fce6b 100644
--- a/cpukit/score/cpu/avr/avr/iom8535.h
+++ b/cpukit/score/cpu/avr/avr/iom8535.h
@@ -46,8 +46,11 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
-/* I/O registers */
-
+/**
+ * @name I/O Registers
+ * 
+ */
+/**@{**/
 /* TWI stands for "Two Wire Interface" or "TWI Was I2C(tm)" */
 #define TWBR    _SFR_IO8(0x00)
 #define TWSR    _SFR_IO8(0x01)
@@ -227,9 +230,13 @@
 /* 0x3D..0x3E SP */
 
 /* 0x3F SREG */
+/** @} */
 
-/* Interrupt vectors */
-
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 /* External Interrupt 0 */
 #define INT0_vect			_VECTOR(1)
 #define SIG_INTERRUPT0			_VECTOR(1)
@@ -311,10 +318,10 @@
 #define SIG_SPM_READY			_VECTOR(20)
 
 #define _VECTORS_SIZE 42
-
+/** @} */
 /*
-   The Register Bit names are represented by their bit number (0-7).
-*/
+ * The Register Bit names are represented by their bit number (0-7).
+ */
 
 /* General Interrupt Control Register */
 #define    INT1         7
@@ -394,10 +401,10 @@
 #define    CS00         0
 
 /* 
-   The ADHSM bit has been removed from all documentation, 
-   as being not needed at all since the comparator has proven 
-   to be fast enough even without feeding it more power.
-*/
+ * The ADHSM bit has been removed from all documentation, 
+ * as being not needed at all since the comparator has proven 
+ * to be fast enough even without feeding it more power.
+ */
 
 /* Special Function IO Register */
 #define    ADTS2        7
@@ -663,17 +670,24 @@
 #define    EEWE         1
 #define    EERE         0
 
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define SPM_PAGESIZE 64
 #define RAMEND       0x25F    /* Last On-Chip SRAM Location */
 #define XRAMEND      RAMEND
 #define E2END        0x1FF
 #define E2PAGESIZE   4
 #define FLASHEND     0x1FFF
+/** @} */
 
-
-/* Fuses */
-
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 2
 
 /* Low Fuse Byte */
@@ -685,7 +699,8 @@
 #define FUSE_SUT1        (unsigned char)~_BV(5)
 #define FUSE_BODEN       (unsigned char)~_BV(6)
 #define FUSE_BODLEVEL    (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_SUT1)
+#define LFUSE_DEFAULT (FUSE_CKSEL1 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
+                       FUSE_SUT0 & FUSE_SUT1)
 
 /* High Fuse Byte */
 #define FUSE_BOOTRST     (unsigned char)~_BV(0)
@@ -697,18 +712,26 @@
 #define FUSE_WDTON       (unsigned char)~_BV(6)
 #define FUSE_S8535C      (unsigned char)~_BV(7)
 #define HFUSE_DEFAULT (FUSE_BOOTSZ0 & FUSE_BOOTSZ1 & FUSE_SPIEN)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x08
-
+/** @} */
 
 #endif /* _AVR_IOM8535_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom88.h b/cpukit/score/cpu/avr/avr/iom88.h
index 063b1faecc..f3e5e64c45 100644
--- a/cpukit/score/cpu/avr/avr/iom88.h
+++ b/cpukit/score/cpu/avr/avr/iom88.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega88
+ */
+
 /* Copyright (c) 2004, Theodore A. Roth
    All rights reserved.
 
@@ -32,6 +38,14 @@
 #ifndef _AVR_IOM88_H_
 #define _AVR_IOM88_H_ 1
 
+/**
+ * @defgroup AvrDef_iom88 ATmega88 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 #include <avr/iomx8.h>
 
 /* Constants */
@@ -86,5 +100,6 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x0A
 
+/** @} */
 
 #endif /* _AVR_IOM88_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom88p.h b/cpukit/score/cpu/avr/avr/iom88p.h
index a95fad464b..0c98183d58 100644
--- a/cpukit/score/cpu/avr/avr/iom88p.h
+++ b/cpukit/score/cpu/avr/avr/iom88p.h
@@ -1,38 +1,42 @@
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iom88p.h - definitions for ATmega88P. */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iom88p.h
+ *
+ * @brief Definitions for ATmega88P
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2007 Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -42,12 +46,19 @@
 #  define _AVR_IOXXX_H_ "iom88p.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_IOM88P_H_
 #define _AVR_IOM88P_H_ 1
 
+/**
+ *  @defgroup Avr_iom88p ATmega88P Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 /* Registers and associated bit numbers */
 
 #define PINB _SFR_IO8(0x03)
@@ -330,7 +341,7 @@
 #define WDRF 3
 
 #define MCUCR _SFR_IO8(0x35)
-#define IVCE 0 
+#define IVCE 0
 #define IVSEL 1
 #define PUD 4
 #define BODSE 5
@@ -795,7 +806,7 @@
 #define TIMER2_OVF_vect   _VECTOR(9)   /* Timer/Counter2 Overflow */
 #define TIMER1_CAPT_vect  _VECTOR(10)  /* Timer/Counter1 Capture Event */
 #define TIMER1_COMPA_vect _VECTOR(11)  /* Timer/Counter1 Compare Match A */
-#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */ 
+#define TIMER1_COMPB_vect _VECTOR(12)  /* Timer/Counter1 Compare Match B */
 #define TIMER1_OVF_vect   _VECTOR(13)  /* Timer/Counter1 Overflow */
 #define TIMER0_COMPA_vect _VECTOR(14)  /* TimerCounter0 Compare Match A */
 #define TIMER0_COMPB_vect _VECTOR(15)  /* TimerCounter0 Compare Match B */
@@ -861,7 +872,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -869,5 +880,5 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x0F
 
-
+/**@}*/
 #endif  /* _AVR_IOM88P_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iom8hva.h b/cpukit/score/cpu/avr/avr/iom8hva.h
index 804ff526bf..fc36eabb25 100644
--- a/cpukit/score/cpu/avr/avr/iom8hva.h
+++ b/cpukit/score/cpu/avr/avr/iom8hva.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega8HVA
+ */
+
 /* Copyright (c) 2007, Anatoly Sokolov 
    All rights reserved.
 
@@ -36,6 +42,14 @@
 
 #include <avr/iomxxhva.h>
 
+/**
+ * @defgroup AvrDef_iom8hva ATmega8HVA Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Constants */
 #define SPM_PAGESIZE 128
 #define RAMEND      0x2FF
@@ -64,6 +78,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 
+/** @} */
 
 #endif /* _AVR_IOM8HVA_H_ */
 
diff --git a/cpukit/score/cpu/avr/avr/iom8u2.h b/cpukit/score/cpu/avr/avr/iom8u2.h
index 24c8ff12d8..c3ee0ba211 100644
--- a/cpukit/score/cpu/avr/avr/iom8u2.h
+++ b/cpukit/score/cpu/avr/avr/iom8u2.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATmega8U2
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2009 Atmel Corporation
    All rights reserved.
 
@@ -47,6 +55,13 @@
 #ifndef _AVR_ATmega8U2_H_
 #define _AVR_ATmega8U2_H_ 1
 
+/**
+ * @defgroup AvrDef_iom8u2 ATmega8U2 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* Registers and associated bit numbers. */
 
@@ -960,7 +975,9 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x89
 
-
 /* Device Pin Definitions */
+
+/** @} */
+
 #endif /* _AVR_ATmega8U2_H_ */
 
diff --git a/cpukit/score/cpu/avr/avr/iomx8.h b/cpukit/score/cpu/avr/avr/iomx8.h
index 46ffc47589..f145d9d27d 100644
--- a/cpukit/score/cpu/avr/avr/iomx8.h
+++ b/cpukit/score/cpu/avr/avr/iomx8.h
@@ -46,8 +46,11 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
-/* I/O registers */
-
+/**
+ * @name I/O Registers
+ * 
+ */
+/**@{**/
 /* Port B */
 
 #define PINB    _SFR_IO8 (0x03)
@@ -203,16 +206,19 @@
 #define EEARL   _SFR_IO8(0x21)
 #define EEARH   _SFR_IO8(0X22)
 /* 
-Even though EEARH is not used by the mega48, the EEAR8 bit in the register
-must be written to 0, according to the datasheet, hence the EEARH register
-must be defined for the mega48.
-*/
-/* 6-char sequence denoting where to find the EEPROM registers in memory space.
-   Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
-   subroutines.
-   First two letters:  EECR address.
-   Second two letters: EEDR address.
-   Last two letters:   EEAR address.  */
+ * Even though EEARH is not used by the mega48, the EEAR8 bit in the register
+ * must be written to 0, according to the datasheet, hence the EEARH register
+ * must be defined for the mega48.
+ */
+/*
+ * 6-char sequence denoting where to find the EEPROM registers in 
+ * memory space.
+ * Adresses denoted in hex syntax with uppercase letters. Used by the EEPROM
+ * subroutines.
+ * First two letters:  EECR address.
+ * Second two letters: EEDR address.
+ * Last two letters:   EEAR address.  
+ */
 #define __EEPROM_REG_LOCATIONS__ 1F2021
 
 
@@ -617,9 +623,13 @@ must be defined for the mega48.
 #define UBRR0L  _SFR_MEM8 (0xC4)
 #define UBRR0H  _SFR_MEM8 (0xC5)
 #define UDR0    _SFR_MEM8 (0xC6)
+/** @} */
 
-/* Interrupt vectors */
-
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 /* External Interrupt Request 0 */
 #define INT0_vect			_VECTOR(1)
 #define SIG_INTERRUPT0			_VECTOR(1)
@@ -721,14 +731,17 @@ must be defined for the mega48.
 #define SPM_READY_vect			_VECTOR(25)
 #define SIG_SPM_READY			_VECTOR(25)
 
-/* The mega48 and mega88 vector tables are single instruction entries (16 bits
-   per entry for an RJMP) while the mega168 table has double instruction
-   entries (32 bits per entry for a JMP). */
+/* 
+ * The mega48 and mega88 vector tables are single instruction entries (16 bits
+ * per entry for an RJMP) while the mega168 table has double instruction
+ * entries (32 bits per entry for a JMP). 
+ */
 
 #if defined (__AVR_ATmega168__)
 #  define _VECTORS_SIZE 104
 #else
 #  define _VECTORS_SIZE 52
 #endif
+/** @} */
 
 #endif /* _AVR_IOM8_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iomxx0_1.h b/cpukit/score/cpu/avr/avr/iomxx0_1.h
index 3abc5cb0ea..2e62117ce9 100644
--- a/cpukit/score/cpu/avr/avr/iomxx0_1.h
+++ b/cpukit/score/cpu/avr/avr/iomxx0_1.h
@@ -1,41 +1,52 @@
-/* Copyright (c) 2005 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iomxx0_1.h - definitions for ATmega640, Atmega1280, ATmega1281,
-   ATmega2560 and ATmega2561. */
+/**
+ * @file avr/iomxx0_1.h
+ *
+ * @brief Definitions for ATmega640/1280/1281/2560/2561
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2005, Anatoly Sokolov
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOMXX0_1_H_
 #define _AVR_IOMXX0_1_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iomxx0_1 ATmega640/1280/1281/2560/2561 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -45,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iomxx0_1.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 #if defined(__AVR_ATmega640__) || defined(__AVR_ATmega1280__) || defined(__AVR_ATmega2560__)
 # define __ATmegaxx0__
@@ -298,7 +309,7 @@
 #define TOV5    0
 
 #define PCIFR   _SFR_IO8(0x1B)
-#if defined(__ATmegaxx0__) 
+#if defined(__ATmegaxx0__)
 # define PCIF2  2
 #endif /* __ATmegaxx0__ */
 #define PCIF1   1
@@ -321,7 +332,7 @@
 #define INT4    4
 #define INT3    3
 #define INT2    2
-#define INT1    1 
+#define INT1    1
 #define INT0    0
 
 #define GPIOR0  _SFR_IO8(0x1E)
@@ -555,7 +566,7 @@
 #define PCINT9  1
 #define PCINT8  0
 
-#if defined(__ATmegaxx0__) 
+#if defined(__ATmegaxx0__)
 # define PCMSK2 _SFR_MEM8(0x6D)
 # define PCINT23 7
 # define PCINT22 6
@@ -1250,7 +1261,7 @@
 
 /* Reserved [0x12E..0x12F] */
 
-#if defined(__ATmegaxx0__) 
+#if defined(__ATmegaxx0__)
 
 # define UCSR3A _SFR_MEM8(0x130)
 # define RXC3   7
@@ -1549,4 +1560,5 @@
 # undef __ATmegaxx1__
 #endif
 
+/**@}*/
 #endif /* _AVR_IOMXX0_1_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iomxx4.h b/cpukit/score/cpu/avr/avr/iomxx4.h
index 4b88642f74..9dd64d875d 100644
--- a/cpukit/score/cpu/avr/avr/iomxx4.h
+++ b/cpukit/score/cpu/avr/avr/iomxx4.h
@@ -1,40 +1,53 @@
-/* Copyright (c) 2005, 2006, 2007 Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-/* avr/iomXX4.h - definitions for ATmega164P/324P/644P and ATmega644 */
+/**
+ * @file avr/iomXX4.h
+ *
+ * @brief Definitions for ATmega164P/324P/644P and ATmega644
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
+/*
+ *  Copyright (c) 2005, 2006, 2007 Anatoly Sokolov
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOMXX4_H_
 #define _AVR_IOMXX4_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @defgroup AvrDef_iomXX4 ATmega164P/324P/644P , ATmega644 Defintions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -865,4 +878,5 @@
 #endif /* defined(__AVR_ATmega644__) */
 
 
+/** @} */
 #endif /* _AVR_IOMXX4_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iomxxhva.h b/cpukit/score/cpu/avr/avr/iomxxhva.h
index 5b6bfdd7ed..2f62e18a0b 100644
--- a/cpukit/score/cpu/avr/avr/iomxxhva.h
+++ b/cpukit/score/cpu/avr/avr/iomxxhva.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2007, Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iomxxhva.h - definitions for ATmega8HVA and ATmega16HVA.  */
+/**
+ * @file iomxxhva.h
+ *
+ * @brief Definitions for ATmega8HVA and ATmega16HVA
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *   Copyright (c) 2007 Anatoly Sokolov
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOMXXHVA_H_
 #define _AVR_IOMXXHVA_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly.  */
+/**
+ *  @defgroup Avr_iomxxhva ATmega8HVA, ATmega16HVA Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iomxxhva.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* Registers and associated bit numbers */
 
@@ -114,7 +126,7 @@
 
 #define EIMSK   _SFR_IO8(0x1D)
 #define INT2    2
-#define INT1    1 
+#define INT1    1
 #define INT0    0
 
 #define GPIOR0  _SFR_IO8(0x1E)
@@ -518,5 +530,5 @@
 #  define _VECTORS_SIZE 42
 #endif
 
-
+/**@}*/
 #endif  /* _AVR_IOMXXHVA_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn11.h b/cpukit/score/cpu/avr/avr/iotn11.h
index 176b2dd0d3..8310f560ed 100644
--- a/cpukit/score/cpu/avr/avr/iotn11.h
+++ b/cpukit/score/cpu/avr/avr/iotn11.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002,2005 Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file avr/iotn11.h
+ *
+ * @brief Definitions for ATtiny10/11
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-/* avr/iotn11.h - definitions for ATtiny10/11 */
+/*
+ * Copyright (c) 2002, 2005 Marek Michalkiewicz
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOTN11_H_
 #define _AVR_IOTN11_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iotn11 ATtiny10/11 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iotn11.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 #ifndef __ASSEMBLER__
 #  warning "MCU not supported by the C compiler"
@@ -230,4 +242,5 @@
 #define SIGNATURE_2 0x04
 
 
+/**@}*/
 #endif /* _AVR_IOTN11_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn12.h b/cpukit/score/cpu/avr/avr/iotn12.h
index 7762ec0169..5851dee68b 100644
--- a/cpukit/score/cpu/avr/avr/iotn12.h
+++ b/cpukit/score/cpu/avr/avr/iotn12.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2002,2005 Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file avr/iotn12.h
+ *
+ * @brief Definitions for ATtiny12
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-/* avr/iotn12.h - definitions for ATtiny12 */
+/*
+ *  Copyright (c) 2002,2005 Marek Michalkiewicz
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOTN12_H_
 #define _AVR_IOTN12_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iotn12 ATtiny12 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iotn12.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 #ifndef __ASSEMBLER__
 #  warning "MCU not supported by the C compiler"
@@ -260,5 +272,5 @@
 #define SIGNATURE_1 0x90
 #define SIGNATURE_2 0x05
 
-
+/**@}*/
 #endif /* _AVR_IOTN12_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn13.h b/cpukit/score/cpu/avr/avr/iotn13.h
index ae13f703b9..3f491fa914 100644
--- a/cpukit/score/cpu/avr/avr/iotn13.h
+++ b/cpukit/score/cpu/avr/avr/iotn13.h
@@ -1,42 +1,54 @@
-/* Copyright (c) 2004, Theodore A. Roth
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn13.h - definitions for ATtiny13 */
-
-/* Verified 5/20/04 by Bruce Graham */
+/**
+ * @file avr/iotn13.h
+ *
+ * @brief Definitions for ATtiny13
+ *
+ * Verified 5/20/04 by Bruce Graham
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2004, Theodore A. Roth
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOTN13_H_
 #define _AVR_IOTN13_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iotn13 ATtiny13 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -46,7 +58,7 @@
 #  define _AVR_IOXXX_H_ "iotn13.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers and bit names */
 
@@ -360,4 +372,5 @@
 #define SIGNATURE_2 0x07
 
 
+/**@}*/
 #endif /* _AVR_IOTN13_H_*/
diff --git a/cpukit/score/cpu/avr/avr/iotn13a.h b/cpukit/score/cpu/avr/avr/iotn13a.h
index 4ca5b0751a..689f4032d6 100644
--- a/cpukit/score/cpu/avr/avr/iotn13a.h
+++ b/cpukit/score/cpu/avr/avr/iotn13a.h
@@ -47,9 +47,11 @@
 #ifndef _AVR_ATTINY13A_H_
 #define _AVR_ATTINY13A_H_ 1
 
-
-/* Registers and associated bit numbers. */
-
+/**
+ * @name Registers and Associated Bit Numbers
+ * 
+ */
+/**@{**/
 #define ADCSRB _SFR_IO8(0x03)
 #define ADTS0 0
 #define ADTS1 1
@@ -306,9 +308,13 @@
 #define GIMSK _SFR_IO8(0x3B)
 #define PCIE 5
 #define INT0 6
+/** @} */
 
-
-/* Interrupt vectors */
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 /* Vector 0 is the reset vector */
 #define INT0_vect_num  1
 #define INT0_vect      _VECTOR(1)  /* External Interrupt 0 */
@@ -331,9 +337,13 @@
 
 #define _VECTOR_SIZE 2 /* Size of individual vector. */
 #define _VECTORS_SIZE (10 * _VECTOR_SIZE)
+/** @} */
 
-
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define SPM_PAGESIZE (32)
 #define RAMSTART     (0x60)
 #define RAMSIZE      (64)
@@ -344,9 +354,13 @@
 #define E2END        (64 - 1)
 #define E2PAGESIZE   (4)
 #define FLASHEND     (1024 - 1)
+/** @} */
 
-
-/* Fuses */
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 2
 
 /* Low Fuse Byte */
@@ -354,30 +368,42 @@
 #define FUSE_CKSEL1 (unsigned char)~_BV(1)  /* Select Clock Source */
 #define FUSE_SUT0 (unsigned char)~_BV(2)  /* Select start-up time */
 #define FUSE_SUT1 (unsigned char)~_BV(3)  /* Select start-up time */
-#define FUSE_CKDIV8 (unsigned char)~_BV(4)  /* Start up with system clock divided by 8 */
+/* Start up with system clock divided by 8 */
+#define FUSE_CKDIV8 (unsigned char)~_BV(4)  
 #define FUSE_WDTON (unsigned char)~_BV(5)  /* Watch dog timer always on */
-#define FUSE_EESAVE (unsigned char)~_BV(6)  /* Keep EEprom contents during chip erase */
+/* Keep EEprom contents during chip erase */
+#define FUSE_EESAVE (unsigned char)~_BV(6)  
 #define FUSE_SPIEN (unsigned char)~_BV(7)  /* SPI programming enable */
 #define LFUSE_DEFAULT (FUSE_SPIEN & FUSE_CKDIV8 & FUSE_SUT0 & FUSE_CKSEL0)
 
 /* High Fuse Byte */
 #define FUSE_RSTDISBL (unsigned char)~_BV(0)  /* Disable external reset */
-#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)  /* Enable BOD and select level */
-#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)  /* Enable BOD and select level */
+/* Enable BOD and select level */
+#define FUSE_BODLEVEL0 (unsigned char)~_BV(1)  
+/* Enable BOD and select level */
+#define FUSE_BODLEVEL1 (unsigned char)~_BV(2)  
 #define FUSE_DWEN (unsigned char)~_BV(3)  /* DebugWire Enable */
 #define FUSE_SELFPRGEN (unsigned char)~_BV(4)  /* Self Programming Enable */
 #define HFUSE_DEFAULT (0xFF)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x90
 #define SIGNATURE_2 0x07
-
+/** @} */
 
 #endif /* _AVR_ATTINY13A_H_ */
 
diff --git a/cpukit/score/cpu/avr/avr/iotn15.h b/cpukit/score/cpu/avr/avr/iotn15.h
index ffffee1798..3e7ac81487 100644
--- a/cpukit/score/cpu/avr/avr/iotn15.h
+++ b/cpukit/score/cpu/avr/avr/iotn15.h
@@ -1,40 +1,53 @@
-/* Copyright (c) 2002,2005 Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file avr/iotn15.h
+ *
+ * @brief Definitions for ATtiny15
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-/* avr/iotn15.h - definitions for ATtiny15 */
+/*
+ *  Copyright (c) 2002,2005 Marek Michalkiewicz
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *   * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOTN15_H_
 #define _AVR_IOTN15_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @defgroup AvrDef_iotn15 ATtiny15 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +57,7 @@
 #  define _AVR_IOXXX_H_ "iotn15.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 #ifndef __ASSEMBLER__
 #  warning "MCU not supported by the C compiler"
@@ -328,5 +341,5 @@
 #define SIGNATURE_1 0x90
 #define SIGNATURE_2 0x06
 
-
+/** @} */
 #endif /* _AVR_IOTN15_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn167.h b/cpukit/score/cpu/avr/avr/iotn167.h
index 0717faaada..53202b33a2 100644
--- a/cpukit/score/cpu/avr/avr/iotn167.h
+++ b/cpukit/score/cpu/avr/avr/iotn167.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATtiny167
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2008 Atmel Corporation
    All rights reserved.
 
@@ -48,6 +56,13 @@
 #ifndef _AVR_IOTN167_H_
 #define _AVR_IOTN167_H_ 1
 
+/**
+ * @defgroup AvrDef_iotn167 ATtiny167 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* Registers and associated bit numbers */
 
@@ -826,6 +841,6 @@
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x87
 
-
+/** @} */
 
 #endif  /* _AVR_IOTN167_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn2313.h b/cpukit/score/cpu/avr/avr/iotn2313.h
index 9495acabb6..21a00522a3 100644
--- a/cpukit/score/cpu/avr/avr/iotn2313.h
+++ b/cpukit/score/cpu/avr/avr/iotn2313.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATtiny2313
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2004, 2005, 2006 Bob Paddock
    All rights reserved.
 
@@ -71,6 +79,14 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif
 
+/**
+ * @defgroup AvrDef_iotn2313 ATtiny2313 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 /*
@@ -628,5 +644,6 @@
 #define SIGNATURE_1 0x91
 #define SIGNATURE_2 0x0A
 
+/** @} */
 
 #endif  /* _AVR_IOTN2313_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn2313a.h b/cpukit/score/cpu/avr/avr/iotn2313a.h
index eb3da33fd2..a84e4ee3a3 100644
--- a/cpukit/score/cpu/avr/avr/iotn2313a.h
+++ b/cpukit/score/cpu/avr/avr/iotn2313a.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn2313a.h - definitions for ATtiny2313A */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iotn2313a.h
+ *
+ * @brief Definitions for ATtiny2313A
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iotn2313a.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATtiny2313A_H_
 #define _AVR_ATtiny2313A_H_ 1
 
+/**
+ *  @defgroup Avr_io4434 AT90S4434 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -764,5 +775,5 @@
 #define SCL_PIN   PINB
 #define SCL_BIT   7
 
+/**@}*/
 #endif /* _AVR_ATtiny2313A_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iotn24.h b/cpukit/score/cpu/avr/avr/iotn24.h
index 57baa1d1c6..2fc94b10da 100644
--- a/cpukit/score/cpu/avr/avr/iotn24.h
+++ b/cpukit/score/cpu/avr/avr/iotn24.h
@@ -1,39 +1,51 @@
-/* Copyright (c) 2005, Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn24.h - definitions for ATtiny24 */
+/**
+ * @file avr/iotn24.h
+ *
+ * @brief Definitions for ATtiny24
+ */
+
+/*
+ * Copyright (c) 2005 Anatoly Sokolov
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOTN24_H_
 #define _AVR_IOTN24_H_ 1
 
+/**
+ *  @defgroup Avr_iotn24 ATtiny24 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #include <avr/iotnx4.h>
 
 #define SPM_PAGESIZE 32
@@ -85,4 +97,5 @@
 #define SIGNATURE_2 0x0B
 
 
+/**@}*/
 #endif /* _AVR_IOTN24_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn24a.h b/cpukit/score/cpu/avr/avr/iotn24a.h
index a413c405a0..266bc94db8 100644
--- a/cpukit/score/cpu/avr/avr/iotn24a.h
+++ b/cpukit/score/cpu/avr/avr/iotn24a.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn24a.h - definitions for ATtiny24A */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iotn24a.h
+ *
+ * @brief Definitions for ATtiny24A
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *   Copyright (c) 2009 Atmel Corporation
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iotn24a.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATtiny24A_H_
 #define _AVR_ATtiny24A_H_ 1
 
+/**
+ *  @defgroup Avr_iotn24a ATtiny24A Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -826,5 +837,5 @@
 #define PCINT5_PIN   PINA
 #define PCINT5_BIT   5
 
+/**@}*/
 #endif /* _AVR_ATtiny24A_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iotn26.h b/cpukit/score/cpu/avr/avr/iotn26.h
index 068d7f98f8..7fcf2a3b59 100644
--- a/cpukit/score/cpu/avr/avr/iotn26.h
+++ b/cpukit/score/cpu/avr/avr/iotn26.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATtiny26
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2004,2005 Eric B. Weddington
    All rights reserved.
 
@@ -46,6 +54,14 @@
 #ifndef _AVR_IOTN26_H_
 #define _AVR_IOTN26_H_ 1
 
+/**
+ * @defgroup AvrDef_iotn26 ATtiny26 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Registers and associated bit numbers */
 
 /* Reserved [0x00..0x03] */
@@ -380,5 +396,6 @@
 #define SIGNATURE_1 0x91
 #define SIGNATURE_2 0x09
 
+/** @} */
 
 #endif  /* _AVR_IOTN26_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn261.h b/cpukit/score/cpu/avr/avr/iotn261.h
index 6e18069b5b..129e595a34 100644
--- a/cpukit/score/cpu/avr/avr/iotn261.h
+++ b/cpukit/score/cpu/avr/avr/iotn261.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATtiny261
+ */
+
 /* Copyright (c) 2006, Anatoly Sokolov
    All rights reserved.
 
@@ -34,6 +40,14 @@
 #ifndef _AVR_IOTN261_H_
 #define _AVR_IOTN261_H_ 1
 
+/**
+ * @defgroup AvrDef_iotn261 ATtiny261 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 #include <avr/iotnx61.h>
 
 #define SPM_PAGESIZE 32
@@ -83,5 +97,6 @@
 #define SIGNATURE_1 0x91
 #define SIGNATURE_2 0x0C
 
+/** @} */
 
 #endif /* _AVR_IOTN261_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn261a.h b/cpukit/score/cpu/avr/avr/iotn261a.h
index 2d7169b8c8..607642fe88 100644
--- a/cpukit/score/cpu/avr/avr/iotn261a.h
+++ b/cpukit/score/cpu/avr/avr/iotn261a.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn261a.h - definitions for ATtiny261A */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iotn261a.h
+ *
+ * @brief Definitions for ATtiny261A
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iotn261a.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATtiny261A_H_
 #define _AVR_ATtiny261A_H_ 1
 
+/**
+ *  @defgroup Avr_iotn261a ATtiny261A Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -971,5 +982,5 @@
 #define PA0_PIN   PINADC
 #define PA0_BIT   ADC0
 
+/**@}*/
 #endif /* _AVR_ATtiny261A_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iotn28.h b/cpukit/score/cpu/avr/avr/iotn28.h
index e91d67ae11..28a68e5ca2 100644
--- a/cpukit/score/cpu/avr/avr/iotn28.h
+++ b/cpukit/score/cpu/avr/avr/iotn28.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATtiny28
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2002, Marek Michalkiewicz
    All rights reserved.
 
@@ -50,6 +58,14 @@
 #  warning "MCU not supported by the C compiler"
 #endif
 
+/**
+ * @defgroup AvrDef_iotn28 ATtiny28 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* I/O registers */
 
 #define OSCCAL	_SFR_IO8(0x00)
@@ -270,5 +286,6 @@
 #define SIGNATURE_1 0x91
 #define SIGNATURE_2 0x07
 
+/** @} */
 
 #endif /* _AVR_IOTN28_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn4313.h b/cpukit/score/cpu/avr/avr/iotn4313.h
index 43719da625..f3744853fd 100644
--- a/cpukit/score/cpu/avr/avr/iotn4313.h
+++ b/cpukit/score/cpu/avr/avr/iotn4313.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn4313.h - definitions for ATtiny4313 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iotn4313.h
+ *
+ * @brief Definitions for ATtiny4313
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *   Copyright (c) 2009 Atmel Corporation
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iotn4313.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATtiny4313_H_
 #define _AVR_ATtiny4313_H_ 1
 
+/**
+ *  @defgroup Avr_iotn4313 ATtiny4313 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -764,5 +775,5 @@
 #define SCL_PIN   PINB
 #define SCL_BIT   7
 
+/**@}*/
 #endif /* _AVR_ATtiny4313_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iotn43u.h b/cpukit/score/cpu/avr/avr/iotn43u.h
index 060cff9898..52038673ad 100644
--- a/cpukit/score/cpu/avr/avr/iotn43u.h
+++ b/cpukit/score/cpu/avr/avr/iotn43u.h
@@ -1,38 +1,42 @@
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iotn43u.h - definitions for ATtiny43U */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iotn43u.h
+ *
+ * @brief Definitions for ATtiny43U
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *   Copyright (c) 2007 Atmel Corporation
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -42,12 +46,19 @@
 #  define _AVR_IOXXX_H_ "iotn43u.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_IOTN43U_H_
 #define _AVR_IOTN43U_H_ 1
 
+/**
+ *  @defgroup Avr_iotn43u ATtiny43U Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 /* Registers and associated bit numbers */
 
 #define PRR _SFR_IO8(0x00)
@@ -554,7 +565,7 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5)
 #define FUSE_DWEN        (unsigned char)~_BV(6)
 #define FUSE_RSTDISBL    (unsigned char)~_BV(7)
-#define HFUSE_DEFAULT (FUSE_SPIEN)    
+#define HFUSE_DEFAULT (FUSE_SPIEN)
 
 /* Extended Fuse Byte */
 #define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
@@ -571,4 +582,5 @@
 #define SIGNATURE_2 0x0C
 
 
+/**@}*/
 #endif /* _AVR_IOTN43U_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn44.h b/cpukit/score/cpu/avr/avr/iotn44.h
index 7a49d39e13..5c41ef5484 100644
--- a/cpukit/score/cpu/avr/avr/iotn44.h
+++ b/cpukit/score/cpu/avr/avr/iotn44.h
@@ -1,39 +1,52 @@
-/* Copyright (c) 2005, Anatoly Sokolov
-   All rights reserved.
+/**
+ * @file avr/iotn44.h
+ *
+ * @brief Definitions for ATtiny44
+ */
+
+/*
+ *  Copyright (c) 2005, Anatoly Sokolov
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn44.h - definitions for ATtiny44 */
 
 #ifndef _AVR_IOTN44_H_
 #define _AVR_IOTN44_H_ 1
 
+/**
+ *  @defgroup Avr_iotn44 ATtiny44 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #include <avr/iotnx4.h>
 
 /* Constants */
@@ -84,5 +97,5 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x07
 
-
+/**@}*/
 #endif /* _AVR_IOTN44_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn45.h b/cpukit/score/cpu/avr/avr/iotn45.h
index f368f9ecd7..b8351210b0 100644
--- a/cpukit/score/cpu/avr/avr/iotn45.h
+++ b/cpukit/score/cpu/avr/avr/iotn45.h
@@ -1,39 +1,51 @@
-/* Copyright (c) 2005, Joerg Wunsch
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn45.h - definitions for ATtiny45 */
+/**
+ * @file avr/iotn45.h
+ *
+ * @brief Definitions for ATtiny45
+ */
+
+/*
+ *   Copyright (c) 2005, Joerg Wunsch
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOTN45_H_
 #define _AVR_IOTN45_H_ 1
 
+/**
+ *  @defgroup Avr_iotn45 ATtiny45 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #include <avr/iotnx5.h>
 
 /* Constants */
@@ -85,4 +97,5 @@
 #define SIGNATURE_2 0x06
 
 
+/**@}*/
 #endif /* _AVR_IOTN45_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn461.h b/cpukit/score/cpu/avr/avr/iotn461.h
index 2867e3e41a..0b14646486 100644
--- a/cpukit/score/cpu/avr/avr/iotn461.h
+++ b/cpukit/score/cpu/avr/avr/iotn461.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATtiny461
+ */
+
 /* Copyright (c) 2006, Anatoly Sokolov
    All rights reserved.
 
@@ -36,6 +42,14 @@
 
 #include <avr/iotnx61.h>
 
+/**
+ * @defgroup AvrDef_iotn461 ATtiny461 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Constants */
 #define SPM_PAGESIZE 64
 #define RAMEND       0x15F
@@ -84,5 +98,6 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x08
 
+/** @} */
 
 #endif /* _AVR_IOTN461_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn461a.h b/cpukit/score/cpu/avr/avr/iotn461a.h
index f92ef46d1b..8aac4fbba9 100644
--- a/cpukit/score/cpu/avr/avr/iotn461a.h
+++ b/cpukit/score/cpu/avr/avr/iotn461a.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn461a.h - definitions for ATtiny461A */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iotn461a.h
+ *
+ * @brief Definitions for ATtiny461A
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *   Copyright (c) 2009 Atmel Corporation
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iotn461a.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATtiny461A_H_
 #define _AVR_ATtiny461A_H_ 1
 
+/**
+ *  @defgroup Avr_iotn461a ATtiny461A Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -971,5 +982,5 @@
 #define PA0_PIN   PINADC
 #define PA0_BIT   ADC0
 
+/**@}*/
 #endif /* _AVR_ATtiny461A_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iotn48.h b/cpukit/score/cpu/avr/avr/iotn48.h
index b9204a562c..d878e98305 100644
--- a/cpukit/score/cpu/avr/avr/iotn48.h
+++ b/cpukit/score/cpu/avr/avr/iotn48.h
@@ -1,38 +1,42 @@
-/* Copyright (c) 2007 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. 
-*/
-
-
-/* avr/iotn48.h - definitions for ATtiny48 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iotn48.h
+ *
+ * @brief Definitions for ATtiny48
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2007 Atmel Corporation
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -42,12 +46,19 @@
 #  define _AVR_IOXXX_H_ "iotn48.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_IOTN48_H_
 #define _AVR_IOTN48_H_ 1
 
+/**
+ *  @defgroup Avr_iotn48 ATtiny48 Definitons
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 /* Registers and associated bit numbers */
 
 #define PINB _SFR_IO8(0x03)
@@ -736,7 +747,7 @@
 #define FUSE_SPIEN       (unsigned char)~_BV(5) /* Enable Serial programming and Data Downloading */
 #define FUSE_DWEN        (unsigned char)~_BV(6) /* debugWIRE Enable */
 #define FUSE_RSTDISBL    (unsigned char)~_BV(7) /* External reset disable */
-#define HFUSE_DEFAULT (FUSE_SPIEN)    
+#define HFUSE_DEFAULT (FUSE_SPIEN)
 
 /* Extended Fuse Byte */
 #define FUSE_SELFPRGEN   (unsigned char)~_BV(0) /* Self Programming Enable */
@@ -752,5 +763,5 @@
 #define SIGNATURE_1 0x92
 #define SIGNATURE_2 0x09
 
-
+/**@}*/
 #endif /* _AVR_IOTN48_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn85.h b/cpukit/score/cpu/avr/avr/iotn85.h
index 34cf692eb3..2fa4d3f0b1 100644
--- a/cpukit/score/cpu/avr/avr/iotn85.h
+++ b/cpukit/score/cpu/avr/avr/iotn85.h
@@ -1,39 +1,52 @@
-/* Copyright (c) 2005, Joerg Wunsch
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn85.h - definitions for ATtiny85 */
+/**
+ * @file avr/iotn85.h
+ *
+ * @brief Definitions for ATtiny85
+ */
+
+/*
+ * Copyright (c) 2005, Joerg Wunsch
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *
+ *   * Neither the name of the copyright holders nor the names of
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOTN85_H_
 #define _AVR_IOTN85_H_ 1
 
+/**
+ * @defgroup Avr_iotn85 ATtiny85 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 #include <avr/iotnx5.h>
 
 /* Constants */
@@ -84,5 +97,5 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x0B
 
-
+/** @} */
 #endif /* _AVR_IOTN85_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn861.h b/cpukit/score/cpu/avr/avr/iotn861.h
index 8226d2b254..54c86570c0 100644
--- a/cpukit/score/cpu/avr/avr/iotn861.h
+++ b/cpukit/score/cpu/avr/avr/iotn861.h
@@ -36,16 +36,24 @@
 
 #include <avr/iotnx61.h>
 
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define SPM_PAGESIZE 64
 #define RAMEND       0x25F
 #define XRAMEND      RAMEND
 #define E2END        0x1FF
 #define E2PAGESIZE   4
 #define FLASHEND     0x1FFF
+/** @} */
 
-
-/* Fuses */
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 3
 
 /* Low Fuse Byte */
@@ -57,7 +65,8 @@
 #define FUSE_SUT1        (unsigned char)~_BV(5)
 #define FUSE_CKOUT       (unsigned char)~_BV(6)
 #define FUSE_CKDIV8      (unsigned char)~_BV(7)
-#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & FUSE_SUT0 & FUSE_CKDIV8)
+#define LFUSE_DEFAULT (FUSE_CKSEL0 & FUSE_CKSEL2 & FUSE_CKSEL3 & \
+                       FUSE_SUT0 & FUSE_CKDIV8)
 
 /* High Fuse Byte */
 #define FUSE_BODLEVEL0   (unsigned char)~_BV(0)
@@ -73,16 +82,24 @@
 /* Extended Fuse Byte */
 #define FUSE_SELFPRGEN   (unsigned char)~_BV(0)
 #define EFUSE_DEFAULT (0xFF)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits 
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x0D
-
+/** @} */
 
 #endif /* _AVR_IOTN861_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotn861a.h b/cpukit/score/cpu/avr/avr/iotn861a.h
index 0177134bdd..654f0959fd 100644
--- a/cpukit/score/cpu/avr/avr/iotn861a.h
+++ b/cpukit/score/cpu/avr/avr/iotn861a.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn861a.h - definitions for ATtiny861A */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iotn861a.h
+ *
+ * @brief Definitions for ATtiny861A
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iotn861a.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATtiny861A_H_
 #define _AVR_ATtiny861A_H_ 1
 
+/**
+ *  @defgroup Avr_iotn861a ATtiny861A Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -971,5 +982,5 @@
 #define PA0_PIN   PINADC
 #define PA0_BIT   ADC0
 
+/**@}*/
 #endif /* _AVR_ATtiny861A_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iotn87.h b/cpukit/score/cpu/avr/avr/iotn87.h
index b8affdfa12..099d81c05f 100644
--- a/cpukit/score/cpu/avr/avr/iotn87.h
+++ b/cpukit/score/cpu/avr/avr/iotn87.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotn87.h - definitions for ATtiny87 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iotn87.h
+ *
+ * @brief Definitions for ATtiny87
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iotn87.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATtiny87_H_
 #define _AVR_ATtiny87_H_ 1
 
+/**
+ *  @defgroup Avr_iotn87 ATtiny87 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Registers and associated bit numbers. */
 
@@ -841,6 +852,5 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x87
 
-
+/**@}*/
 #endif /* _AVR_ATtiny87_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iotn88.h b/cpukit/score/cpu/avr/avr/iotn88.h
index 427fc8fd4d..829d13f283 100644
--- a/cpukit/score/cpu/avr/avr/iotn88.h
+++ b/cpukit/score/cpu/avr/avr/iotn88.h
@@ -1,3 +1,11 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATtiny88
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2007 Atmel Corporation
    All rights reserved.
 
@@ -44,6 +52,13 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
+/**
+ * @defgroup AvrDef_iotn88 ATtiny88 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 #ifndef _AVR_IOTN88_H_
 #define _AVR_IOTN88_H_ 1
@@ -752,5 +767,6 @@
 #define SIGNATURE_1 0x93
 #define SIGNATURE_2 0x11
 
+/** @} */
 
 #endif /* _AVR_IOTN88_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotnx4.h b/cpukit/score/cpu/avr/avr/iotnx4.h
index cc1ed9d263..8bb310ba13 100644
--- a/cpukit/score/cpu/avr/avr/iotnx4.h
+++ b/cpukit/score/cpu/avr/avr/iotnx4.h
@@ -46,8 +46,11 @@
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
 #endif 
 
-/* I/O registers */
-
+/**
+ * @name I/O Registers
+ * 
+ */
+/**@{**/
 #define PRR     _SFR_IO8 (0x00)
 #define PRTIM1  3
 #define PRTIM0  2
@@ -378,9 +381,13 @@
 /* 0x3D..0x3E SP  [defined in <avr/io.h>] */
 /* 0x3F SREG      [defined in <avr/io.h>] */
 
-///---
+/** @} */
 
-/* Interrupt vectors */
+/**
+ * @name Interrupt Vectors
+ * 
+ */
+/**@{**/
 /* Interrupt vector 0 is the reset vector. */
 /* External Interrupt Request 0 */
 #define INT0_vect			_VECTOR(1)
@@ -452,4 +459,6 @@
 
 #define _VECTORS_SIZE 34
 
+/** @} */
+
 #endif /* _AVR_IOTNX4_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotnx5.h b/cpukit/score/cpu/avr/avr/iotnx5.h
index 57863b10ae..34edf06e8b 100644
--- a/cpukit/score/cpu/avr/avr/iotnx5.h
+++ b/cpukit/score/cpu/avr/avr/iotnx5.h
@@ -1,40 +1,52 @@
-/* Copyright (c) 2005, 2007, 2009 Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotnx5.h - definitions for ATtiny25, ATtiny45 and ATtiny85 */
+/**
+ * @file avr/iotnx5.h
+ *
+ * @brief Definitions for ATtiny25, ATtiny45 and ATtiny85
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *   Copyright (c) 2005, 2007, 2009 Anatoly Sokolov
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOTNX5_H_
 #define _AVR_IOTNX5_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iotnx5 ATtiny25, ATtiny45, ATtiny85 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iotnx5.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* I/O registers */
 
@@ -107,7 +119,7 @@
 #define USITC   0
 
 #define USISR   _SFR_IO8(0x0E)
-#define USISIF  7 
+#define USISIF  7
 #define USIOIF  6
 #define USIPF   5
 #define USIDC   4
@@ -128,7 +140,7 @@
 #define ADC2D   4
 #define ADC3D   3
 #define ADC1D   2
-#define AIN1D   1 
+#define AIN1D   1
 #define AIN0D   0
 
 #define PCMSK   _SFR_IO8(0x15)
@@ -412,4 +424,5 @@
 
 #define _VECTORS_SIZE 30
 
+/**@}*/
 #endif /* _AVR_IOTNX5_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iotnx61.h b/cpukit/score/cpu/avr/avr/iotnx61.h
index 6a4bd87553..58cba5c493 100644
--- a/cpukit/score/cpu/avr/avr/iotnx61.h
+++ b/cpukit/score/cpu/avr/avr/iotnx61.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2006, 2007 Anatoly Sokolov
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iotnx61.h - definitions for ATtiny261, ATtiny461 and ATtiny861 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @file avr/iotnx61.h
+ *
+ * @brief Definitions for ATtiny261, ATtiny461 and ATtiny861
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2006, 2007 Anatoly Sokolov
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,11 +46,19 @@
 #  define _AVR_IOXXX_H_ "iotnx61.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 #ifndef _AVR_IOTNx61_H_
 #define _AVR_IOTNx61_H_ 1
 
+/**
+ * @defgroup AvrDef_iotnx61 ATtiny261, ATtiny461, ATtiny861 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Registers and associated bit numbers */
 
 #define TCCR1E  _SFR_IO8(0x00)
@@ -511,4 +524,5 @@
 
 #define _VECTORS_SIZE 38
 
+/** @} */
 #endif  /* _AVR_IOTNx61_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb1286.h b/cpukit/score/cpu/avr/avr/iousb1286.h
index b245b95b05..5f9411daff 100644
--- a/cpukit/score/cpu/avr/avr/iousb1286.h
+++ b/cpukit/score/cpu/avr/avr/iousb1286.h
@@ -1,39 +1,51 @@
-/* Copyright (c) 2006 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iousb1286.h - definitions for AT90USB1286 */
+/**
+ * @file avr/iousb1286.h
+ *
+ * @brief Definitions for AT90USB1286
+ */
+
+/*
+ *  Copyright (c) 2006 Anatoly Sokolov
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_AT90USB1286_H_
 #define _AVR_AT90USB1286_H_ 1
 
+/**
+ *  @defgroup Avr_iousb1286 AT90USB1286 Definitons
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #include <avr/iousbxx6_7.h>
 
 /* Constants */
@@ -81,7 +93,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -89,5 +101,5 @@
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x82
 
-
+/**@}*/
 #endif /* _AVR_AT90USB1286_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb1287.h b/cpukit/score/cpu/avr/avr/iousb1287.h
index 4a1db39670..f75894bdbc 100644
--- a/cpukit/score/cpu/avr/avr/iousb1287.h
+++ b/cpukit/score/cpu/avr/avr/iousb1287.h
@@ -1,39 +1,51 @@
-/* Copyright (c) 2006 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iousb1287.h - definitions for AT90USB1287 */
+/**
+ * @file avr/iousb1287.h
+ *
+ * @brief Definitions for AT90USB1287
+ */
+
+/*
+ * Copyright (c) 2006 Anatoly Sokolov
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_AT90USB1287_H_
 #define _AVR_AT90USB1287_H_ 1
 
+/**
+ *  @defgroup Avr_iousb1287 AT90USB1287 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #include <avr/iousbxx6_7.h>
 
 /* Constants */
@@ -81,7 +93,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -90,4 +102,5 @@
 #define SIGNATURE_2 0x82
 
 
+/**@}*/
 #endif /* _AVR_AT90USB1287_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb162.h b/cpukit/score/cpu/avr/avr/iousb162.h
index c9094be89d..89709a7279 100644
--- a/cpukit/score/cpu/avr/avr/iousb162.h
+++ b/cpukit/score/cpu/avr/avr/iousb162.h
@@ -36,16 +36,24 @@
 
 #include <avr/iousbxx2.h>
 
-/* Constants */
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define SPM_PAGESIZE 128
 #define RAMEND       0x2FF
 #define XRAMEND      RAMEND
 #define E2END        0x1FF
 #define E2PAGESIZE   4
 #define FLASHEND     0x3FFF
+/** @} */
 
-
-/* Fuses */
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 3
 
 /* Low Fuse Byte */
@@ -76,18 +84,26 @@
 #define FUSE_BODLEVEL2   (unsigned char)~_BV(2)
 #define FUSE_HWBE        (unsigned char)~_BV(3)
 #define EFUSE_DEFAULT (BODLEVEL0 & BODLEVEL1 & HWBE)
+/** @} */
 
-
-/* Lock Bits */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
+/** @} */
 
-
-/* Signature */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x94
 #define SIGNATURE_2 0x82
-
+/** @} */
 
 #endif /* _AVR_AT90USB162_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb646.h b/cpukit/score/cpu/avr/avr/iousb646.h
index d7a1d3a0f1..035cbcd2bc 100644
--- a/cpukit/score/cpu/avr/avr/iousb646.h
+++ b/cpukit/score/cpu/avr/avr/iousb646.h
@@ -1,39 +1,51 @@
-/* Copyright (c) 2006 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iousb646.h - definitions for AT90USB646 */
+/**
+ * @file avr/iousb646.h
+ *
+ * @brief Definitions for AT90USB646
+ */
+
+/*
+ * Copyright (c) 2006 Anatoly Sokolov
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_AT90USB646_H_
 #define _AVR_AT90USB646_H_ 1
 
+/**
+ *  @defgroup Avr_iousb646 AT90USB646 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #include <avr/iousbxx6_7.h>
 
 /* Constants */
@@ -81,7 +93,7 @@
 /* Lock Bits */
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_BITS_0_EXIST
-#define __BOOT_LOCK_BITS_1_EXIST 
+#define __BOOT_LOCK_BITS_1_EXIST
 
 
 /* Signature */
@@ -90,4 +102,5 @@
 #define SIGNATURE_2 0x82
 
 
+/**@}*/
 #endif /* _AVR_AT90USB646_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb647.h b/cpukit/score/cpu/avr/avr/iousb647.h
index 3b93048149..2e1288accb 100644
--- a/cpukit/score/cpu/avr/avr/iousb647.h
+++ b/cpukit/score/cpu/avr/avr/iousb647.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Definitions for AT90USB647
+ */
+
 /* Copyright (c) 2006 Anatoly Sokolov 
    All rights reserved.
 
@@ -36,6 +42,14 @@
 
 #include <avr/iousbxx6_7.h>
 
+/**
+ * @defgroup AvrDef_iousb647 AT90USB647 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Constants */
 #define SPM_PAGESIZE 256
 #define RAMEND       0x10FF
@@ -89,5 +103,6 @@
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x82
 
+/** @} */
 
 #endif /* _AVR_AT90USB647_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousb82.h b/cpukit/score/cpu/avr/avr/iousb82.h
index 428ed9b566..2d66bd5d70 100644
--- a/cpukit/score/cpu/avr/avr/iousb82.h
+++ b/cpukit/score/cpu/avr/avr/iousb82.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Ddefinitions for AT90USB82
+ */
+
 /* Copyright (c) 2007 Anatoly Sokolov 
    All rights reserved.
 
@@ -36,6 +42,14 @@
 
 #include <avr/iousbxx2.h>
 
+/**
+ * @defgroup AvrDef_iousb82 AT90USB82 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 /* Constants */
 #define SPM_PAGESIZE 128
 #define RAMEND       0x2FF
@@ -83,5 +97,6 @@
 #define __BOOT_LOCK_BITS_0_EXIST
 #define __BOOT_LOCK_BITS_1_EXIST 
 
+/** @} */
 
 #endif /* _AVR_AT90USB82_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousbxx2.h b/cpukit/score/cpu/avr/avr/iousbxx2.h
index cf1840c557..3dcbc76262 100644
--- a/cpukit/score/cpu/avr/avr/iousbxx2.h
+++ b/cpukit/score/cpu/avr/avr/iousbxx2.h
@@ -1,40 +1,53 @@
-/* Copyright (c) 2007 Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iousbxx2.h - definitions for AT90USB82 and AT90USB162.  */
+/**
+ * @file iousbxx2.h
+ *
+ * @brief Definitions for AT90USB82 and AT90USB162
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ * Copyright (c) 2007 Anatoly Sokolov
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOUSBXX2_H_
 #define _AVR_IOUSBXX2_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ * @defgroup AvrDef_iousbxx2 AT90USB82, AT90USB162 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -44,7 +57,7 @@
 #  define _AVR_IOXXX_H_ "iousbxx2.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 /* Registers and associated bit numbers */
 
@@ -174,7 +187,7 @@
 #define INT4    4
 #define INT3    3
 #define INT2    2
-#define INT1    1 
+#define INT1    1
 #define INT0    0
 
 #define GPIOR0  _SFR_IO8(0x1E)
@@ -762,4 +775,5 @@
 
 #define _VECTORS_SIZE 116
 
+/** @} */
 #endif  /* _AVR_IOUSBXX2_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iousbxx6_7.h b/cpukit/score/cpu/avr/avr/iousbxx6_7.h
index ee4fe1e6a2..c923c22c82 100644
--- a/cpukit/score/cpu/avr/avr/iousbxx6_7.h
+++ b/cpukit/score/cpu/avr/avr/iousbxx6_7.h
@@ -1,41 +1,52 @@
-/* Copyright (c) 2006, Anatoly Sokolov 
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* iousbxx6_7.h - definitions for AT90USB646, AT90USB647, AT90USB1286 
-   and AT90USB1287 */
+/**
+ * @file iousbxx6_7.h
+ *
+ * @brief Definitions for AT90USB646, AT90USB647, AT90USB1286, AT90USB1287
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
+/*
+ *  Copyright (c) 2006, Anatoly Sokolov
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IOUSBXX6_7_H_
 #define _AVR_IOUSBXX6_7_H_ 1
 
-/* This file should only be included from <avr/io.h>, never directly. */
+/**
+ *  @defgroup Avr_iomxx0_1 AT90USB-646/647/1286/1287 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -45,7 +56,7 @@
 #  define _AVR_IOXXX_H_ "iousbxx6_7.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 #if defined(__AVR_AT90USB646__) || defined(__AVR_AT90USB1286__)
 #  define __AT90USBxx6__ 1
@@ -283,7 +294,7 @@
 #define INT4    4
 #define INT3    3
 #define INT2    2
-#define INT1    1 
+#define INT1    1
 #define INT0    0
 
 #define GPIOR0  _SFR_IO8(0x1E)
@@ -1281,4 +1292,5 @@
 # undef __AT90USBxx7__
 #endif /* __AT90USBxx7__ */
 
+/**@}*/
 #endif  /* _AVR_IOUSBXX6_7_H_ */
diff --git a/cpukit/score/cpu/avr/avr/iox128a1.h b/cpukit/score/cpu/avr/avr/iox128a1.h
index 9feffd4f38..4ce4c47e64 100644
--- a/cpukit/score/cpu/avr/avr/iox128a1.h
+++ b/cpukit/score/cpu/avr/avr/iox128a1.h
@@ -117,13 +117,11 @@ typedef volatile uint32_t register32_t;
         }; \
     }
 
-
-/*
-==========================================================================
-IO Module Structures
-==========================================================================
-*/
-
+/**
+ * @name IO Module Structures
+ * 
+ */
+/**@{**/
 
 /*
 --------------------------------------------------------------------------
@@ -186,7 +184,8 @@ typedef enum CLK_SCLKSEL_enum
     CLK_SCLKSEL_RC2M_gc = (0x00<<0),  /* Internal 2MHz RC Oscillator */
     CLK_SCLKSEL_RC32M_gc = (0x01<<0),  /* Internal 32MHz RC Oscillator */
     CLK_SCLKSEL_RC32K_gc = (0x02<<0),  /* Internal 32kHz RC Oscillator */
-    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  /* External Crystal Oscillator or Clock */
+    /* External Crystal Oscillator or Clock */
+    CLK_SCLKSEL_XOSC_gc = (0x03<<0),  
     CLK_SCLKSEL_PLL_gc = (0x04<<0),  /* Phase Locked Loop */
 } CLK_SCLKSEL_t;
 
@@ -218,9 +217,12 @@ typedef enum CLK_PSBCDIV_enum
 typedef enum CLK_RTCSRC_enum
 {
     CLK_RTCSRC_ULP_gc = (0x00<<1),  /* 1kHz from internal 32kHz ULP */
-    CLK_RTCSRC_TOSC_gc = (0x01<<1),  /* 1kHz from 32kHz crystal oscillator on TOSC */
-    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  /* 1kHz from internal 32kHz RC oscillator */
-    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  /* 32kHz from 32kHz crystal oscillator on TOSC */
+    /* 1kHz from 32kHz crystal oscillator on TOSC */
+    CLK_RTCSRC_TOSC_gc = (0x01<<1),  
+    /* 1kHz from internal 32kHz RC oscillator */
+    CLK_RTCSRC_RCOSC_gc = (0x02<<1),  
+    /* 32kHz from 32kHz crystal oscillator on TOSC */
+    CLK_RTCSRC_TOSC32_gc = (0x05<<1),  
 } CLK_RTCSRC_t;
 
 
@@ -259,8 +261,10 @@ typedef struct OSC_struct
     register8_t CTRL;  /* Control Register */
     register8_t STATUS;  /* Status Register */
     register8_t XOSCCTRL;  /* External Oscillator Control Register */
-    register8_t XOSCFAIL;  /* External Oscillator Failure Detection Register */
-    register8_t RC32KCAL;  /* 32kHz Internal Oscillator Calibration Register */
+    /* External Oscillator Failure Detection Register */
+    register8_t XOSCFAIL;  
+    /* 32kHz Internal Oscillator Calibration Register */
+    register8_t RC32KCAL;  
     register8_t PLLCTRL;  /* PLL Control REgister */
     register8_t DFLLCTRL;  /* DFLL Control Register */
 } OSC_t;
@@ -484,7 +488,8 @@ typedef enum DMA_CH_SRCRELOAD_enum
     DMA_CH_SRCRELOAD_NONE_gc = (0x00<<6),  /* No reload */
     DMA_CH_SRCRELOAD_BLOCK_gc = (0x01<<6),  /* Reload at end of block */
     DMA_CH_SRCRELOAD_BURST_gc = (0x02<<6),  /* Reload at end of burst */
-    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  /* Reload at end of transaction */
+    /* Reload at end of transaction */
+    DMA_CH_SRCRELOAD_TRANSACTION_gc = (0x03<<6),  
 } DMA_CH_SRCRELOAD_t;
 
 /* Source addressing mode */
@@ -501,7 +506,8 @@ typedef enum DMA_CH_DESTRELOAD_enum
     DMA_CH_DESTRELOAD_NONE_gc = (0x00<<2),  /* No reload */
     DMA_CH_DESTRELOAD_BLOCK_gc = (0x01<<2),  /* Reload at end of block */
     DMA_CH_DESTRELOAD_BURST_gc = (0x02<<2),  /* Reload at end of burst */
-    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2),  /* Reload at end of transaction */
+    /* Reload at end of transaction */
+    DMA_CH_DESTRELOAD_TRANSACTION_gc = (0x03<<2), 
 } DMA_CH_DESTRELOAD_t;
 
 /* Destination adressing mode */
@@ -523,94 +529,142 @@ typedef enum DMA_CH_TRIGSRC_enum
     DMA_CH_TRIGSRC_ADCA_CH1_gc = (0x11<<0),  /* ADCA Channel 1 */
     DMA_CH_TRIGSRC_ADCA_CH2_gc = (0x12<<0),  /* ADCA Channel 2 */
     DMA_CH_TRIGSRC_ADCA_CH3_gc = (0x13<<0),  /* ADCA Channel 3 */
-    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  /* ADCA Channel 0,1,2,3 combined */
+    /* ADCA Channel 0,1,2,3 combined */
+    DMA_CH_TRIGSRC_ADCA_CH4_gc = (0x14<<0),  
     DMA_CH_TRIGSRC_DACA_CH0_gc = (0x15<<0),  /* DACA Channel 0 */
     DMA_CH_TRIGSRC_DACA_CH1_gc = (0x16<<0),  /* DACA Channel 1 */
     DMA_CH_TRIGSRC_ADCB_CH0_gc = (0x20<<0),  /* ADCB Channel 0 */
     DMA_CH_TRIGSRC_ADCB_CH1_gc = (0x21<<0),  /* ADCB Channel 1 */
     DMA_CH_TRIGSRC_ADCB_CH2_gc = (0x22<<0),  /* ADCB Channel 2 */
     DMA_CH_TRIGSRC_ADCB_CH3_gc = (0x23<<0),  /* ADCB Channel 3 */
-    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  /* ADCB Channel 0,1,2,3 combined */
+    /* ADCB Channel 0,1,2,3 combined */
+    DMA_CH_TRIGSRC_ADCB_CH4_gc = (0x24<<0),  
     DMA_CH_TRIGSRC_DACB_CH0_gc = (0x25<<0),  /* DACB Channel 0 */
     DMA_CH_TRIGSRC_DACB_CH1_gc = (0x26<<0),  /* DACB Channel 1 */
     DMA_CH_TRIGSRC_TCC0_OVF_gc = (0x40<<0),  /* Timer/Counter C0 Overflow */
     DMA_CH_TRIGSRC_TCC0_ERR_gc = (0x41<<0),  /* Timer/Counter C0 Error */
-    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0),  /* Timer/Counter C0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  /* Timer/Counter C0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  /* Timer/Counter C0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  /* Timer/Counter C0 Compare or Capture D */
+     /* Timer/Counter C0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCC0_CCA_gc = (0x42<<0), 
+    /* Timer/Counter C0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCC0_CCB_gc = (0x43<<0),  
+    /* Timer/Counter C0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCC0_CCC_gc = (0x44<<0),  
+    /* Timer/Counter C0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCC0_CCD_gc = (0x45<<0),  
     DMA_CH_TRIGSRC_TCC1_OVF_gc = (0x46<<0),  /* Timer/Counter C1 Overflow */
     DMA_CH_TRIGSRC_TCC1_ERR_gc = (0x47<<0),  /* Timer/Counter C1 Error */
-    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  /* Timer/Counter C1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  /* Timer/Counter C1 Compare or Capture B */
+    /* Timer/Counter C1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCC1_CCA_gc = (0x48<<0),  
+    /* Timer/Counter C1 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCC1_CCB_gc = (0x49<<0),  
     DMA_CH_TRIGSRC_SPIC_gc = (0x4A<<0),  /* SPI C Transfer Complete */
-    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  /* USART C0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  /* USART C0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  /* USART C1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  /* USART C1 Data Register Empty */
+    /* USART C0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTC0_RXC_gc = (0x4B<<0),  
+    /* USART C0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTC0_DRE_gc = (0x4C<<0),  
+    /* USART C1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTC1_RXC_gc = (0x4E<<0),  
+    /* USART C1 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTC1_DRE_gc = (0x4F<<0),  
     DMA_CH_TRIGSRC_TCD0_OVF_gc = (0x60<<0),  /* Timer/Counter D0 Overflow */
     DMA_CH_TRIGSRC_TCD0_ERR_gc = (0x61<<0),  /* Timer/Counter D0 Error */
-    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  /* Timer/Counter D0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  /* Timer/Counter D0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  /* Timer/Counter D0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  /* Timer/Counter D0 Compare or Capture D */
+    /* Timer/Counter D0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCD0_CCA_gc = (0x62<<0),  
+    /* Timer/Counter D0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCD0_CCB_gc = (0x63<<0),  
+    /* Timer/Counter D0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCD0_CCC_gc = (0x64<<0),  
+    /* Timer/Counter D0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCD0_CCD_gc = (0x65<<0),  
     DMA_CH_TRIGSRC_TCD1_OVF_gc = (0x66<<0),  /* Timer/Counter D1 Overflow */
     DMA_CH_TRIGSRC_TCD1_ERR_gc = (0x67<<0),  /* Timer/Counter D1 Error */
-    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  /* Timer/Counter D1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  /* Timer/Counter D1 Compare or Capture B */
+    /* Timer/Counter D1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCD1_CCA_gc = (0x68<<0),  
+    /* Timer/Counter D1 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCD1_CCB_gc = (0x69<<0),  
     DMA_CH_TRIGSRC_SPID_gc = (0x6A<<0),  /* SPI D Transfer Complete */
-    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  /* USART D0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  /* USART D0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  /* USART D1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  /* USART D1 Data Register Empty */
+    /* USART D0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTD0_RXC_gc = (0x6B<<0),  
+    /* USART D0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTD0_DRE_gc = (0x6C<<0),  
+    /* USART D1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTD1_RXC_gc = (0x6E<<0),  
+    /* USART D1 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTD1_DRE_gc = (0x6F<<0),  
     DMA_CH_TRIGSRC_TCE0_OVF_gc = (0x80<<0),  /* Timer/Counter E0 Overflow */
     DMA_CH_TRIGSRC_TCE0_ERR_gc = (0x81<<0),  /* Timer/Counter E0 Error */
-    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  /* Timer/Counter E0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  /* Timer/Counter E0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  /* Timer/Counter E0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0),  /* Timer/Counter E0 Compare or Capture D */
+    /* Timer/Counter E0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCE0_CCA_gc = (0x82<<0),  
+    /* Timer/Counter E0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCE0_CCB_gc = (0x83<<0),  
+    /* Timer/Counter E0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCE0_CCC_gc = (0x84<<0),  
+    /* Timer/Counter E0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCE0_CCD_gc = (0x85<<0), 
     DMA_CH_TRIGSRC_TCE1_OVF_gc = (0x86<<0),  /* Timer/Counter E1 Overflow */
     DMA_CH_TRIGSRC_TCE1_ERR_gc = (0x87<<0),  /* Timer/Counter E1 Error */
-    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  /* Timer/Counter E1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  /* Timer/Counter E1 Compare or Capture B */
+    /* Timer/Counter E1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCE1_CCA_gc = (0x88<<0),  
+    /* Timer/Counter E1 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCE1_CCB_gc = (0x89<<0),  
     DMA_CH_TRIGSRC_SPIE_gc = (0x8A<<0),  /* SPI E Transfer Complete */
-    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0),  /* USART E0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  /* USART E0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  /* USART E1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  /* USART E1 Data Register Empty */
+    /* USART E0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTE0_RXC_gc = (0x8B<<0), 
+    /* USART E0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTE0_DRE_gc = (0x8C<<0),  
+    /* USART E1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTE1_RXC_gc = (0x8E<<0),  
+    /* USART E1 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTE1_DRE_gc = (0x8F<<0),  
     DMA_CH_TRIGSRC_TCF0_OVF_gc = (0xA0<<0),  /* Timer/Counter F0 Overflow */
     DMA_CH_TRIGSRC_TCF0_ERR_gc = (0xA1<<0),  /* Timer/Counter F0 Error */
-    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  /* Timer/Counter F0 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  /* Timer/Counter F0 Compare or Capture B */
-    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  /* Timer/Counter F0 Compare or Capture C */
-    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  /* Timer/Counter F0 Compare or Capture D */
+    /* Timer/Counter F0 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCF0_CCA_gc = (0xA2<<0),  
+    /* Timer/Counter F0 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCF0_CCB_gc = (0xA3<<0),  
+    /* Timer/Counter F0 Compare or Capture C */
+    DMA_CH_TRIGSRC_TCF0_CCC_gc = (0xA4<<0),  
+    /* Timer/Counter F0 Compare or Capture D */
+    DMA_CH_TRIGSRC_TCF0_CCD_gc = (0xA5<<0),  
     DMA_CH_TRIGSRC_TCF1_OVF_gc = (0xA6<<0),  /* Timer/Counter F1 Overflow */
     DMA_CH_TRIGSRC_TCF1_ERR_gc = (0xA7<<0),  /* Timer/Counter F1 Error */
-    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  /* Timer/Counter F1 Compare or Capture A */
-    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  /* Timer/Counter F1 Compare or Capture B */
+    /* Timer/Counter F1 Compare or Capture A */
+    DMA_CH_TRIGSRC_TCF1_CCA_gc = (0xA8<<0),  
+    /* Timer/Counter F1 Compare or Capture B */
+    DMA_CH_TRIGSRC_TCF1_CCB_gc = (0xA9<<0),  
     DMA_CH_TRIGSRC_SPIF_gc = (0xAA<<0),  /* SPI F Transfer Complete */
-    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  /* USART F0 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  /* USART F0 Data Register Empty */
-    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  /* USART F1 Receive Complete */
-    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  /* USART F1 Data Register Empty */
+    /* USART F0 Receive Complete */
+    DMA_CH_TRIGSRC_USARTF0_RXC_gc = (0xAB<<0),  
+    /* USART F0 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTF0_DRE_gc = (0xAC<<0),  
+    /* USART F1 Receive Complete */
+    DMA_CH_TRIGSRC_USARTF1_RXC_gc = (0xAE<<0),  
+    /* USART F1 Data Register Empty */
+    DMA_CH_TRIGSRC_USARTF1_DRE_gc = (0xAF<<0),  
 } DMA_CH_TRIGSRC_t;
 
 /* Double buffering mode */
 typedef enum DMA_DBUFMODE_enum
 {
     DMA_DBUFMODE_DISABLED_gc = (0x00<<2),  /* Double buffering disabled */
-    DMA_DBUFMODE_CH01_gc = (0x01<<2),  /* Double buffering enabled on channel 0/1 */
-    DMA_DBUFMODE_CH23_gc = (0x02<<2),  /* Double buffering enabled on channel 2/3 */
-    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
+    /* Double buffering enabled on channel 0/1 */
+    DMA_DBUFMODE_CH01_gc = (0x01<<2),  
+    /* Double buffering enabled on channel 2/3 */
+    DMA_DBUFMODE_CH23_gc = (0x02<<2),  
+    /* Double buffering enabled on ch. 0/1 and ch. 2/3 */
+    DMA_DBUFMODE_CH01CH23_gc = (0x03<<2),  
 } DMA_DBUFMODE_t;
 
 /* Priority mode */
 typedef enum DMA_PRIMODE_enum
 {
     DMA_PRIMODE_RR0123_gc = (0x00<<0),  /* Round Robin */
-    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  /* Channel 0 > Round Robin on channel 1/2/3 */
-    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
-    DMA_PRIMODE_CH0123_gc = (0x03<<0),  /* Channel 0 > channel 1 > channel 2 > channel 3 */
+    /* Channel 0 > Round Robin on channel 1/2/3 */
+    DMA_PRIMODE_CH0RR123_gc = (0x01<<0),  
+    /* Channel 0 > channel 1 > Round Robin on channel 2/3 */
+    DMA_PRIMODE_CH01RR23_gc = (0x02<<0),  
+    /* Channel 0 > channel 1 > channel 2 > channel 3 */
+    DMA_PRIMODE_CH0123_gc = (0x03<<0),  
 } DMA_PRIMODE_t;
 
 /* Interrupt level */
@@ -761,52 +815,82 @@ typedef enum EVSYS_CHMUX_enum
     EVSYS_CHMUX_PRESCALER_128_gc = (0x87<<0),  /* Prescaler, divide by 128 */
     EVSYS_CHMUX_PRESCALER_256_gc = (0x88<<0),  /* Prescaler, divide by 256 */
     EVSYS_CHMUX_PRESCALER_512_gc = (0x89<<0),  /* Prescaler, divide by 512 */
-    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  /* Prescaler, divide by 1024 */
-    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  /* Prescaler, divide by 2048 */
-    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  /* Prescaler, divide by 4096 */
-    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  /* Prescaler, divide by 8192 */
-    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  /* Prescaler, divide by 16384 */
-    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  /* Prescaler, divide by 32768 */
+    /* Prescaler, divide by 1024 */
+    EVSYS_CHMUX_PRESCALER_1024_gc = (0x8A<<0),  
+    /* Prescaler, divide by 2048 */
+    EVSYS_CHMUX_PRESCALER_2048_gc = (0x8B<<0),  
+    /* Prescaler, divide by 4096 */
+    EVSYS_CHMUX_PRESCALER_4096_gc = (0x8C<<0),  
+    /* Prescaler, divide by 8192 */
+    EVSYS_CHMUX_PRESCALER_8192_gc = (0x8D<<0),  
+    /* Prescaler, divide by 16384 */
+    EVSYS_CHMUX_PRESCALER_16384_gc = (0x8E<<0),  
+    /* Prescaler, divide by 32768 */
+    EVSYS_CHMUX_PRESCALER_32768_gc = (0x8F<<0),  
     EVSYS_CHMUX_TCC0_OVF_gc = (0xC0<<0),  /* Timer/Counter C0 Overflow */
     EVSYS_CHMUX_TCC0_ERR_gc = (0xC1<<0),  /* Timer/Counter C0 Error */
-    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  /* Timer/Counter C0 Compare or Capture A */
-    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  /* Timer/Counter C0 Compare or Capture B */
-    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  /* Timer/Counter C0 Compare or Capture C */
-    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  /* Timer/Counter C0 Compare or Capture D */
+    /* Timer/Counter C0 Compare or Capture A */
+    EVSYS_CHMUX_TCC0_CCA_gc = (0xC4<<0),  
+    /* Timer/Counter C0 Compare or Capture B */
+    EVSYS_CHMUX_TCC0_CCB_gc = (0xC5<<0),  
+    /* Timer/Counter C0 Compare or Capture C */
+    EVSYS_CHMUX_TCC0_CCC_gc = (0xC6<<0),  
+    /* Timer/Counter C0 Compare or Capture D */
+    EVSYS_CHMUX_TCC0_CCD_gc = (0xC7<<0),  
     EVSYS_CHMUX_TCC1_OVF_gc = (0xC8<<0),  /* Timer/Counter C1 Overflow */
     EVSYS_CHMUX_TCC1_ERR_gc = (0xC9<<0),  /* Timer/Counter C1 Error */
-    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  /* Timer/Counter C1 Compare or Capture A */
-    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  /* Timer/Counter C1 Compare or Capture B */
+    /* Timer/Counter C1 Compare or Capture A */
+    EVSYS_CHMUX_TCC1_CCA_gc = (0xCC<<0),  
+    /* Timer/Counter C1 Compare or Capture B */
+    EVSYS_CHMUX_TCC1_CCB_gc = (0xCD<<0),  
     EVSYS_CHMUX_TCD0_OVF_gc = (0xD0<<0),  /* Timer/Counter D0 Overflow */
     EVSYS_CHMUX_TCD0_ERR_gc = (0xD1<<0),  /* Timer/Counter D0 Error */
-    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  /* Timer/Counter D0 Compare or Capture A */
-    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  /* Timer/Counter D0 Compare or Capture B */
-    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  /* Timer/Counter D0 Compare or Capture C */
-    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  /* Timer/Counter D0 Compare or Capture D */
+    /* Timer/Counter D0 Compare or Capture A */
+    EVSYS_CHMUX_TCD0_CCA_gc = (0xD4<<0),  
+    /* Timer/Counter D0 Compare or Capture B */
+    EVSYS_CHMUX_TCD0_CCB_gc = (0xD5<<0),  
+    /* Timer/Counter D0 Compare or Capture C */
+    EVSYS_CHMUX_TCD0_CCC_gc = (0xD6<<0),  
+    /* Timer/Counter D0 Compare or Capture D */
+    EVSYS_CHMUX_TCD0_CCD_gc = (0xD7<<0),  
     EVSYS_CHMUX_TCD1_OVF_gc = (0xD8<<0),  /* Timer/Counter D1 Overflow */
     EVSYS_CHMUX_TCD1_ERR_gc = (0xD9<<0),  /* Timer/Counter D1 Error */
-    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  /* Timer/Counter D1 Compare or Capture A */
-    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  /* Timer/Counter D1 Compare or Capture B */
+    /* Timer/Counter D1 Compare or Capture A */
+    EVSYS_CHMUX_TCD1_CCA_gc = (0xDC<<0),  
+    /* Timer/Counter D1 Compare or Capture B */
+    EVSYS_CHMUX_TCD1_CCB_gc = (0xDD<<0),  
     EVSYS_CHMUX_TCE0_OVF_gc = (0xE0<<0),  /* Timer/Counter E0 Overflow */
     EVSYS_CHMUX_TCE0_ERR_gc = (0xE1<<0),  /* Timer/Counter E0 Error */
-    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  /* Timer/Counter E0 Compare or Capture A */
-    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  /* Timer/Counter E0 Compare or Capture B */
-    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  /* Timer/Counter E0 Compare or Capture C */
-    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  /* Timer/Counter E0 Compare or Capture D */
+    /* Timer/Counter E0 Compare or Capture A */
+    EVSYS_CHMUX_TCE0_CCA_gc = (0xE4<<0),  
+    /* Timer/Counter E0 Compare or Capture B */
+    EVSYS_CHMUX_TCE0_CCB_gc = (0xE5<<0),  
+    /* Timer/Counter E0 Compare or Capture C */
+    EVSYS_CHMUX_TCE0_CCC_gc = (0xE6<<0),  
+    /* Timer/Counter E0 Compare or Capture D */
+    EVSYS_CHMUX_TCE0_CCD_gc = (0xE7<<0),  
     EVSYS_CHMUX_TCE1_OVF_gc = (0xE8<<0),  /* Timer/Counter E1 Overflow */
     EVSYS_CHMUX_TCE1_ERR_gc = (0xE9<<0),  /* Timer/Counter E1 Error */
-    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  /* Timer/Counter E1 Compare or Capture A */
-    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  /* Timer/Counter E1 Compare or Capture B */
+    /* Timer/Counter E1 Compare or Capture A */
+    EVSYS_CHMUX_TCE1_CCA_gc = (0xEC<<0),  
+    /* Timer/Counter E1 Compare or Capture B */
+    EVSYS_CHMUX_TCE1_CCB_gc = (0xED<<0),  
     EVSYS_CHMUX_TCF0_OVF_gc = (0xF0<<0),  /* Timer/Counter F0 Overflow */
     EVSYS_CHMUX_TCF0_ERR_gc = (0xF1<<0),  /* Timer/Counter F0 Error */
-    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  /* Timer/Counter F0 Compare or Capture A */
-    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  /* Timer/Counter F0 Compare or Capture B */
-    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  /* Timer/Counter F0 Compare or Capture C */
-    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  /* Timer/Counter F0 Compare or Capture D */
+    /* Timer/Counter F0 Compare or Capture A */
+    EVSYS_CHMUX_TCF0_CCA_gc = (0xF4<<0),  
+    /* Timer/Counter F0 Compare or Capture B */
+    EVSYS_CHMUX_TCF0_CCB_gc = (0xF5<<0),  
+    /* Timer/Counter F0 Compare or Capture C */
+    EVSYS_CHMUX_TCF0_CCC_gc = (0xF6<<0),  
+    /* Timer/Counter F0 Compare or Capture D */
+    EVSYS_CHMUX_TCF0_CCD_gc = (0xF7<<0),  
     EVSYS_CHMUX_TCF1_OVF_gc = (0xF8<<0),  /* Timer/Counter F1 Overflow */
     EVSYS_CHMUX_TCF1_ERR_gc = (0xF9<<0),  /* Timer/Counter F1 Error */
-    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  /* Timer/Counter F1 Compare or Capture A */
-    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  /* Timer/Counter F1 Compare or Capture B */
+    /* Timer/Counter F1 Compare or Capture A */
+    EVSYS_CHMUX_TCF1_CCA_gc = (0xFC<<0),  
+    /* Timer/Counter F1 Compare or Capture B */
+    EVSYS_CHMUX_TCF1_CCB_gc = (0xFD<<0),  
 } EVSYS_CHMUX_t;
 
 
@@ -953,20 +1037,27 @@ typedef enum NVM_CMD_enum
     NVM_CMD_ERASE_USER_SIG_ROW_gc = (0x18<<0),  /* Erase user signature row */
     NVM_CMD_WRITE_USER_SIG_ROW_gc = (0x1A<<0),  /* Write user signature row */
     NVM_CMD_ERASE_APP_gc = (0x20<<0),  /* Erase Application Section */
-    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  /* Erase Application Section page */
+    /* Erase Application Section page */
+    NVM_CMD_ERASE_APP_PAGE_gc = (0x22<<0),  
     NVM_CMD_LOAD_FLASH_BUFFER_gc = (0x23<<0),  /* Load Flash page buffer */
-    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  /* Write Application Section page */
-    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  /* Erase-and-write Application Section page */
-    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  /* Erase/flush Flash page buffer */
+    /* Write Application Section page */
+    NVM_CMD_WRITE_APP_PAGE_gc = (0x24<<0),  
+    /* Erase-and-write Application Section page */
+    NVM_CMD_ERASE_WRITE_APP_PAGE_gc = (0x25<<0),  
+    /* Erase/flush Flash page buffer */
+    NVM_CMD_ERASE_FLASH_BUFFER_gc = (0x26<<0),  
     NVM_CMD_ERASE_BOOT_PAGE_gc = (0x2A<<0),  /* Erase Boot Section page */
     NVM_CMD_WRITE_BOOT_PAGE_gc = (0x2C<<0),  /* Write Boot Section page */
-    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  /* Erase-and-write Boot Section page */
+    /* Erase-and-write Boot Section page */
+    NVM_CMD_ERASE_WRITE_BOOT_PAGE_gc = (0x2D<<0),  
     NVM_CMD_ERASE_EEPROM_gc = (0x30<<0),  /* Erase EEPROM */
     NVM_CMD_ERASE_EEPROM_PAGE_gc = (0x32<<0),  /* Erase EEPROM page */
     NVM_CMD_LOAD_EEPROM_BUFFER_gc = (0x33<<0),  /* Load EEPROM page buffer */
     NVM_CMD_WRITE_EEPROM_PAGE_gc = (0x34<<0),  /* Write EEPROM page */
-    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  /* Erase-and-write EEPROM page */
-    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  /* Erase/flush EEPROM page buffer */
+    /* Erase-and-write EEPROM page */
+    NVM_CMD_ERASE_WRITE_EEPROM_PAGE_gc = (0x35<<0),  
+    /* Erase/flush EEPROM page buffer */
+    NVM_CMD_ERASE_EEPROM_BUFFER_gc = (0x36<<0),  
     NVM_CMD_APP_CRC_gc = (0x38<<0),  /* Generate Application section CRC */
     NVM_CMD_BOOT_CRC_gc = (0x39<<0),  /* Generate Boot Section CRC */
     NVM_CMD_FLASH_RANGE_CRC_gc = (0x3A<<0),  /* Generate Flash Range CRC */
@@ -1272,9 +1363,11 @@ typedef enum ADC_CH_MUXNEG_enum
 typedef enum ADC_CH_INPUTMODE_enum
 {
     ADC_CH_INPUTMODE_INTERNAL_gc = (0x00<<0),  /* Internal inputs, no gain */
-    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  /* Single-ended input, no gain */
+    /* Single-ended input, no gain */
+    ADC_CH_INPUTMODE_SINGLEENDED_gc = (0x01<<0),  
     ADC_CH_INPUTMODE_DIFF_gc = (0x02<<0),  /* Differential input, no gain */
-    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  /* Differential input, with gain */
+    /* Differential input, with gain */
+    ADC_CH_INPUTMODE_DIFFWGAIN_gc = (0x03<<0),  
 } ADC_CH_INPUTMODE_t;
 
 /* Gain factor */
@@ -1294,7 +1387,8 @@ typedef enum ADC_RESOLUTION_enum
 {
     ADC_RESOLUTION_12BIT_gc = (0x00<<1),  /* 12-bit right-adjusted result */
     ADC_RESOLUTION_8BIT_gc = (0x02<<1),  /* 8-bit right-adjusted result */
-    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),  /* 12-bit left-adjusted result */
+    /* 12-bit left-adjusted result */
+    ADC_RESOLUTION_LEFT12BIT_gc = (0x03<<1),
 } ADC_RESOLUTION_t;
 
 /* Voltage reference selection */
@@ -1334,18 +1428,23 @@ typedef enum ADC_EVACT_enum
     ADC_EVACT_NONE_gc = (0x00<<0),  /* No event action */
     ADC_EVACT_CH0_gc = (0x01<<0),  /* First event triggers channel 0 */
     ADC_EVACT_CH01_gc = (0x02<<0),  /* First two events trigger channel 0,1 */
-    ADC_EVACT_CH012_gc = (0x03<<0),  /* First three events trigger channel 0,1,2 */
+    /* First three events trigger channel 0,1,2 */
+    ADC_EVACT_CH012_gc = (0x03<<0),  
     ADC_EVACT_CH0123_gc = (0x04<<0),  /* Events trigger channel 0,1,2,3 */
     ADC_EVACT_SWEEP_gc = (0x05<<0),  /* First event triggers sweep */
-    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  /* First event triggers synchronized sweep */
+    /* First event triggers synchronized sweep */
+    ADC_EVACT_SYNCHSWEEP_gc = (0x06<<0),  
 } ADC_EVACT_t;
 
 /* Interupt mode */
 typedef enum ADC_CH_INTMODE_enum
 {
-    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  /* Interrupt on conversion complete */
-    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  /* Interrupt on result below compare value */
-    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2),  /* Interrupt on result above compare value */
+    /* Interrupt on conversion complete */
+    ADC_CH_INTMODE_COMPLETE_gc = (0x00<<2),  
+    /* Interrupt on result below compare value */
+    ADC_CH_INTMODE_BELOW_gc = (0x01<<2),  
+    /* Interrupt on result above compare value */
+    ADC_CH_INTMODE_ABOVE_gc = (0x03<<2), 
 } ADC_CH_INTMODE_t;
 
 /* Interrupt level */
@@ -1420,8 +1519,10 @@ typedef struct DAC_struct
 /* Output channel selection */
 typedef enum DAC_CHSEL_enum
 {
-    DAC_CHSEL_SINGLE_gc = (0x00<<5),  /* Single channel operation (Channel A only) */
-    DAC_CHSEL_DUAL_gc = (0x02<<5),  /* Dual channel operation (S/H on both channels) */
+    /* Single channel operation (Channel A only) */
+    DAC_CHSEL_SINGLE_gc = (0x00<<5),  
+    /* Dual channel operation (S/H on both channels) */
+    DAC_CHSEL_DUAL_gc = (0x02<<5),  
 } DAC_CHSEL_t;
 
 /* Reference voltage selection */
@@ -1429,8 +1530,10 @@ typedef enum DAC_REFSEL_enum
 {
     DAC_REFSEL_INT1V_gc = (0x00<<3),  /* Internal 1V  */
     DAC_REFSEL_AVCC_gc = (0x01<<3),  /* Analog supply voltage */
-    DAC_REFSEL_AREFA_gc = (0x02<<3),  /* External reference on AREF on PORTA */
-    DAC_REFSEL_AREFB_gc = (0x03<<3),  /* External reference on AREF on PORTB */
+    /* External reference on AREF on PORTA */
+    DAC_REFSEL_AREFA_gc = (0x02<<3),  
+    /* External reference on AREF on PORTB */
+    DAC_REFSEL_AREFB_gc = (0x03<<3),  
 } DAC_REFSEL_t;
 
 /* Event channel selection */
@@ -1810,7 +1913,8 @@ typedef enum TWI_MASTER_TIMEOUT_enum
 typedef enum TWI_MASTER_CMD_enum
 {
     TWI_MASTER_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  /* Issue Repeated Start Condition */
+    /* Issue Repeated Start Condition */
+    TWI_MASTER_CMD_REPSTART_gc = (0x01<<0),  
     TWI_MASTER_CMD_RECVTRANS_gc = (0x02<<0),  /* Receive or Transmit Data */
     TWI_MASTER_CMD_STOP_gc = (0x03<<0),  /* Issue Stop Condition */
 } TWI_MASTER_CMD_t;
@@ -1820,7 +1924,8 @@ typedef enum TWI_MASTER_BUSSTATE_enum
 {
     TWI_MASTER_BUSSTATE_UNKNOWN_gc = (0x00<<0),  /* Unknown Bus State */
     TWI_MASTER_BUSSTATE_IDLE_gc = (0x01<<0),  /* Bus is Idle */
-    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  /* This Module Controls The Bus */
+    /* This Module Controls The Bus */
+    TWI_MASTER_BUSSTATE_OWNER_gc = (0x02<<0),  
     TWI_MASTER_BUSSTATE_BUSY_gc = (0x03<<0),  /* The Bus is Busy */
 } TWI_MASTER_BUSSTATE_t;
 
@@ -1837,8 +1942,10 @@ typedef enum TWI_SLAVE_INTLVL_enum
 typedef enum TWI_SLAVE_CMD_enum
 {
     TWI_SLAVE_CMD_NOACT_gc = (0x00<<0),  /* No Action */
-    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  /* Used To Complete a Transaction */
-    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0),  /* Used in Response to Address/Data Interrupt */
+    /* Used To Complete a Transaction */
+    TWI_SLAVE_CMD_COMPTRANS_gc = (0x02<<0),  
+    /* Used in Response to Address/Data Interrupt */
+    TWI_SLAVE_CMD_RESPONSE_gc = (0x03<<0), 
 } TWI_SLAVE_CMD_t;
 
 
@@ -2005,9 +2112,12 @@ typedef enum PORTCFG_CLKOUT_enum
 typedef enum PORTCFG_EVOUT_enum
 {
     PORTCFG_EVOUT_OFF_gc = (0x00<<4),  /* Event Output Disabled */
-    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  /* Event Channel 7 Output on Port C pin 7 */
-    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  /* Event Channel 7 Output on Port D pin 7 */
-    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  /* Event Channel 7 Output on Port E pin 7 */
+    /* Event Channel 7 Output on Port C pin 7 */
+    PORTCFG_EVOUT_PC7_gc = (0x01<<4),  
+    /* Event Channel 7 Output on Port D pin 7 */
+    PORTCFG_EVOUT_PD7_gc = (0x02<<4),  
+    /* Event Channel 7 Output on Port E pin 7 */
+    PORTCFG_EVOUT_PE7_gc = (0x03<<4),  
 } PORTCFG_EVOUT_t;
 
 /* Port Interrupt 0 Level */
@@ -2032,7 +2142,8 @@ typedef enum PORT_INT1LVL_enum
 typedef enum PORT_OPC_enum
 {
     PORT_OPC_TOTEM_gc = (0x00<<3),  /* Totempole */
-    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  /* Totempole w/ Bus keeper on Input and Output */
+    /* Totempole w/ Bus keeper on Input and Output */
+    PORT_OPC_BUSKEEPER_gc = (0x01<<3),  
     PORT_OPC_PULLDOWN_gc = (0x02<<3),  /* Totempole w/ Pull-down on Input */
     PORT_OPC_PULLUP_gc = (0x03<<3),  /* Totempole w/ Pull-up on Input */
     PORT_OPC_WIREDOR_gc = (0x04<<3),  /* Wired OR */
@@ -2244,7 +2355,8 @@ typedef enum TC_WGMODE_enum
     TC_WGMODE_FRQ_gc = (0x01<<0),  /* Frequency Generation Mode */
     TC_WGMODE_SS_gc = (0x03<<0),  /* Single Slope */
     TC_WGMODE_DS_T_gc = (0x05<<0),  /* Dual Slope, Update on TOP */
-    TC_WGMODE_DS_TB_gc = (0x06<<0),  /* Dual Slope, Update on TOP and BOTTOM */
+    /* Dual Slope, Update on TOP and BOTTOM */
+    TC_WGMODE_DS_TB_gc = (0x06<<0),  
     TC_WGMODE_DS_B_gc = (0x07<<0),  /* Dual Slope, Update on BOTTOM */
 } TC_WGMODE_t;
 
@@ -2349,9 +2461,12 @@ typedef enum AWEX_FDACT_enum
 typedef enum HIRES_HREN_enum
 {
     HIRES_HREN_NONE_gc = (0x00<<0),  /* No Fault Protection */
-    HIRES_HREN_TC0_gc = (0x01<<0),  /* Enable High Resolution on Timer/Counter 0 */
-    HIRES_HREN_TC1_gc = (0x02<<0),  /* Enable High Resolution on Timer/Counter 1 */
-    HIRES_HREN_BOTH_gc = (0x03<<0),  /* Enable High Resolution both Timer/Counters */
+    /* Enable High Resolution on Timer/Counter 0 */
+    HIRES_HREN_TC0_gc = (0x01<<0),  
+    /* Enable High Resolution on Timer/Counter 1 */
+    HIRES_HREN_TC1_gc = (0x02<<0),  
+    /* Enable High Resolution both Timer/Counters */
+    HIRES_HREN_BOTH_gc = (0x03<<0),  
 } HIRES_HREN_t;
 
 
@@ -2482,7 +2597,8 @@ IRCOM - IR Communication Module
 typedef struct IRCOM_struct
 {
     register8_t CTRL;  /* Control Register */
-    register8_t TXPLCTRL;  /* IrDA Transmitter Pulse Length Control Register */
+    /* IrDA Transmitter Pulse Length Control Register */
+    register8_t TXPLCTRL;  
     register8_t RXPLCTRL;  /* IrDA Receiver Pulse Length Control Register */
 } IRCOM_t;
 
@@ -2525,15 +2641,13 @@ typedef enum AES_INTLVL_enum
     AES_INTLVL_MED_gc = (0x02<<0),  /* Medium Level */
     AES_INTLVL_HI_gc = (0x03<<0),  /* High Level */
 } AES_INTLVL_t;
+/** @} */
 
-
-
-/*
-==========================================================================
-IO Module Instances. Mapped to memory.
-==========================================================================
-*/
-
+/**
+ * @name IO Module Instances. Mapped to Memory
+ * 
+ */
+/**@{**/
 #define GPIO    (*(GPIO_t *) 0x0000)  /* General Purpose IO Registers */
 #define VPORT0    (*(VPORT_t *) 0x0010)  /* Virtual Port 0 */
 #define VPORT1    (*(VPORT_t *) 0x0014)  /* Virtual Port 1 */
@@ -2583,35 +2697,47 @@ IO Module Instances. Mapped to memory.
 #define TCC1    (*(TC1_t *) 0x0840)  /* Timer/Counter C1 */
 #define AWEXC    (*(AWEX_t *) 0x0880)  /* Advanced Waveform Extension C */
 #define HIRESC    (*(HIRES_t *) 0x0890)  /* High-Resolution Extension C */
-#define USARTC0    (*(USART_t *) 0x08A0)  /* Universal Asynchronous Receiver-Transmitter C0 */
-#define USARTC1    (*(USART_t *) 0x08B0)  /* Universal Asynchronous Receiver-Transmitter C1 */
+/* Universal Asynchronous Receiver-Transmitter C0 */
+#define USARTC0    (*(USART_t *) 0x08A0)  
+/* Universal Asynchronous Receiver-Transmitter C1 */
+#define USARTC1    (*(USART_t *) 0x08B0)  
 #define SPIC    (*(SPI_t *) 0x08C0)  /* Serial Peripheral Interface C */
 #define IRCOM    (*(IRCOM_t *) 0x08F8)  /* IR Communication Module */
 #define TCD0    (*(TC0_t *) 0x0900)  /* Timer/Counter D0 */
 #define TCD1    (*(TC1_t *) 0x0940)  /* Timer/Counter D1 */
 #define HIRESD    (*(HIRES_t *) 0x0990)  /* High-Resolution Extension D */
-#define USARTD0    (*(USART_t *) 0x09A0)  /* Universal Asynchronous Receiver-Transmitter D0 */
-#define USARTD1    (*(USART_t *) 0x09B0)  /* Universal Asynchronous Receiver-Transmitter D1 */
+/* Universal Asynchronous Receiver-Transmitter D0 */
+#define USARTD0    (*(USART_t *) 0x09A0)  
+/* Universal Asynchronous Receiver-Transmitter D1 */
+#define USARTD1    (*(USART_t *) 0x09B0)  
 #define SPID    (*(SPI_t *) 0x09C0)  /* Serial Peripheral Interface D */
 #define TCE0    (*(TC0_t *) 0x0A00)  /* Timer/Counter E0 */
 #define TCE1    (*(TC1_t *) 0x0A40)  /* Timer/Counter E1 */
 #define AWEXE    (*(AWEX_t *) 0x0A80)  /* Advanced Waveform Extension E */
 #define HIRESE    (*(HIRES_t *) 0x0A90)  /* High-Resolution Extension E */
-#define USARTE0    (*(USART_t *) 0x0AA0)  /* Universal Asynchronous Receiver-Transmitter E0 */
-#define USARTE1    (*(USART_t *) 0x0AB0)  /* Universal Asynchronous Receiver-Transmitter E1 */
+/* Universal Asynchronous Receiver-Transmitter E0 */
+#define USARTE0    (*(USART_t *) 0x0AA0)  
+/* Universal Asynchronous Receiver-Transmitter E1 */
+#define USARTE1    (*(USART_t *) 0x0AB0)  
 #define SPIE    (*(SPI_t *) 0x0AC0)  /* Serial Peripheral Interface E */
 #define TCF0    (*(TC0_t *) 0x0B00)  /* Timer/Counter F0 */
 #define TCF1    (*(TC1_t *) 0x0B40)  /* Timer/Counter F1 */
 #define HIRESF    (*(HIRES_t *) 0x0B90)  /* High-Resolution Extension F */
-#define USARTF0    (*(USART_t *) 0x0BA0)  /* Universal Asynchronous Receiver-Transmitter F0 */
-#define USARTF1    (*(USART_t *) 0x0BB0)  /* Universal Asynchronous Receiver-Transmitter F1 */
+/* Universal Asynchronous Receiver-Transmitter F0 */
+#define USARTF0    (*(USART_t *) 0x0BA0)  
+/* Universal Asynchronous Receiver-Transmitter F1 */
+#define USARTF1    (*(USART_t *) 0x0BB0)  
 #define SPIF    (*(SPI_t *) 0x0BC0)  /* Serial Peripheral Interface F */
 
 
 #endif /* !defined (__ASSEMBLER__) */
+/** @} */
 
-
-/* ========== Flattened fully qualified IO register names ========== */
+/**
+ * @name Flattened Fully Qualified IO Register Names
+ * 
+ */
+/**@{**/
 
 /* GPIO - General Purpose IO Registers */
 #define GPIO_GPIO0  _SFR_MEM8(0x0000)
@@ -3629,11 +3755,13 @@ IO Module Instances. Mapped to memory.
 #define SPIF_INTCTRL  _SFR_MEM8(0x0BC1)
 #define SPIF_STATUS  _SFR_MEM8(0x0BC2)
 #define SPIF_DATA  _SFR_MEM8(0x0BC3)
+/** @} */
 
-
-
-/*================== Bitfield Definitions ================== */
-
+/**
+ * @name Bitfield Definitions
+ * 
+ */
+/**@{**/
 /* XOCD - On-Chip Debug System */
 /* OCD.OCDR1  bit masks and bit positions */
 #define OCD_OCDRD_bm  0x01  /* OCDR Dirty bit mask. */
@@ -3714,12 +3842,18 @@ IO Module Instances. Mapped to memory.
 #define CLK_PSADIV4_bm  (1<<6)  /* Prescaler A Division Factor bit 4 mask. */
 #define CLK_PSADIV4_bp  6  /* Prescaler A Division Factor bit 4 position. */
 
-#define CLK_PSBCDIV_gm  0x03  /* Prescaler B and C Division factor group mask. */
-#define CLK_PSBCDIV_gp  0  /* Prescaler B and C Division factor group position. */
-#define CLK_PSBCDIV0_bm  (1<<0)  /* Prescaler B and C Division factor bit 0 mask. */
-#define CLK_PSBCDIV0_bp  0  /* Prescaler B and C Division factor bit 0 position. */
-#define CLK_PSBCDIV1_bm  (1<<1)  /* Prescaler B and C Division factor bit 1 mask. */
-#define CLK_PSBCDIV1_bp  1  /* Prescaler B and C Division factor bit 1 position. */
+/* Prescaler B and C Division factor group mask. */
+#define CLK_PSBCDIV_gm  0x03  
+/* Prescaler B and C Division factor group position. */
+#define CLK_PSBCDIV_gp  0  
+/* Prescaler B and C Division factor bit 0 mask. */
+#define CLK_PSBCDIV0_bm  (1<<0)  
+/* Prescaler B and C Division factor bit 0 position. */
+#define CLK_PSBCDIV0_bp  0  
+/* Prescaler B and C Division factor bit 1 mask. */
+#define CLK_PSBCDIV1_bm  (1<<1) 
+/* Prescaler B and C Division factor bit 1 position. */
+#define CLK_PSBCDIV1_bp  1  
 
 
 /* CLK.LOCK  bit masks and bit positions */
@@ -3895,14 +4029,20 @@ IO Module Instances. Mapped to memory.
 #define OSC_XOSCEN_bm  0x08  /* External Oscillator Enable bit mask. */
 #define OSC_XOSCEN_bp  3  /* External Oscillator Enable bit position. */
 
-#define OSC_RC32KEN_bm  0x04  /* Internal 32kHz RC Oscillator Enable bit mask. */
-#define OSC_RC32KEN_bp  2  /* Internal 32kHz RC Oscillator Enable bit position. */
+/* Internal 32kHz RC Oscillator Enable bit mask. */
+#define OSC_RC32KEN_bm  0x04 
+/* Internal 32kHz RC Oscillator Enable bit position. */
+#define OSC_RC32KEN_bp  2  
 
-#define OSC_RC32MEN_bm  0x02  /* Internal 32MHz RC Oscillator Enable bit mask. */
-#define OSC_RC32MEN_bp  1  /* Internal 32MHz RC Oscillator Enable bit position. */
+/* Internal 32MHz RC Oscillator Enable bit mask. */
+#define OSC_RC32MEN_bm  0x02  
+/* Internal 32MHz RC Oscillator Enable bit position. */
+#define OSC_RC32MEN_bp  1  
 
-#define OSC_RC2MEN_bm  0x01  /* Internal 2MHz RC Oscillator Enable bit mask. */
-#define OSC_RC2MEN_bp  0  /* Internal 2MHz RC Oscillator Enable bit position. */
+/* Internal 2MHz RC Oscillator Enable bit mask. */
+#define OSC_RC2MEN_bm  0x01  
+/* Internal 2MHz RC Oscillator Enable bit position. */
+#define OSC_RC2MEN_bp  0  
 
 
 /* OSC.STATUS  bit masks and bit positions */
@@ -3912,14 +4052,20 @@ IO Module Instances. Mapped to memory.
 #define OSC_XOSCRDY_bm  0x08  /* External Oscillator Ready bit mask. */
 #define OSC_XOSCRDY_bp  3  /* External Oscillator Ready bit position. */
 
-#define OSC_RC32KRDY_bm  0x04  /* Internal 32kHz RC Oscillator Ready bit mask. */
-#define OSC_RC32KRDY_bp  2  /* Internal 32kHz RC Oscillator Ready bit position. */
+/* Internal 32kHz RC Oscillator Ready bit mask. */
+#define OSC_RC32KRDY_bm  0x04 
+/* Internal 32kHz RC Oscillator Ready bit position. */
+#define OSC_RC32KRDY_bp  2  
 
-#define OSC_RC32MRDY_bm  0x02  /* Internal 32MHz RC Oscillator Ready bit mask. */
-#define OSC_RC32MRDY_bp  1  /* Internal 32MHz RC Oscillator Ready bit position. */
+/* Internal 32MHz RC Oscillator Ready bit mask. */
+#define OSC_RC32MRDY_bm  0x02 
+/* Internal 32MHz RC Oscillator Ready bit position. */
+#define OSC_RC32MRDY_bp  1  
 
-#define OSC_RC2MRDY_bm  0x01  /* Internal 2MHz RC Oscillator Ready bit mask. */
-#define OSC_RC2MRDY_bp  0  /* Internal 2MHz RC Oscillator Ready bit position. */
+/* Internal 2MHz RC Oscillator Ready bit mask. */
+#define OSC_RC2MRDY_bm  0x01  
+/* Internal 2MHz RC Oscillator Ready bit position. */
+#define OSC_RC2MRDY_bp  0  
 
 
 /* OSC.XOSCCTRL  bit masks and bit positions */
@@ -3933,21 +4079,33 @@ IO Module Instances. Mapped to memory.
 #define OSC_X32KLPM_bm  0x20  /* 32kHz XTAL OSC Low-power Mode bit mask. */
 #define OSC_X32KLPM_bp  5  /* 32kHz XTAL OSC Low-power Mode bit position. */
 
-#define OSC_XOSCSEL_gm  0x0F  /* External Oscillator Selection and Startup Time group mask. */
-#define OSC_XOSCSEL_gp  0  /* External Oscillator Selection and Startup Time group position. */
-#define OSC_XOSCSEL0_bm  (1<<0)  /* External Oscillator Selection and Startup Time bit 0 mask. */
-#define OSC_XOSCSEL0_bp  0  /* External Oscillator Selection and Startup Time bit 0 position. */
-#define OSC_XOSCSEL1_bm  (1<<1)  /* External Oscillator Selection and Startup Time bit 1 mask. */
-#define OSC_XOSCSEL1_bp  1  /* External Oscillator Selection and Startup Time bit 1 position. */
-#define OSC_XOSCSEL2_bm  (1<<2)  /* External Oscillator Selection and Startup Time bit 2 mask. */
-#define OSC_XOSCSEL2_bp  2  /* External Oscillator Selection and Startup Time bit 2 position. */
-#define OSC_XOSCSEL3_bm  (1<<3)  /* External Oscillator Selection and Startup Time bit 3 mask. */
-#define OSC_XOSCSEL3_bp  3  /* External Oscillator Selection and Startup Time bit 3 position. */
+/* External Oscillator Selection and Startup Time group mask. */
+#define OSC_XOSCSEL_gm  0x0F  
+/* External Oscillator Selection and Startup Time group position. */
+#define OSC_XOSCSEL_gp  0
+/* External Oscillator Selection and Startup Time bit 0 mask. */
+#define OSC_XOSCSEL0_bm  (1<<0) 
+/* External Oscillator Selection and Startup Time bit 0 position. */
+#define OSC_XOSCSEL0_bp  0  
+/* External Oscillator Selection and Startup Time bit 1 mask. */
+#define OSC_XOSCSEL1_bm  (1<<1)  
+/* External Oscillator Selection and Startup Time bit 1 position. */
+#define OSC_XOSCSEL1_bp  1 
+/* External Oscillator Selection and Startup Time bit 2 mask. */
+#define OSC_XOSCSEL2_bm  (1<<2)  
+/* External Oscillator Selection and Startup Time bit 2 position. */
+#define OSC_XOSCSEL2_bp  2  
+/* External Oscillator Selection and Startup Time bit 3 mask. */
+#define OSC_XOSCSEL3_bm  (1<<3)  
+/* External Oscillator Selection and Startup Time bit 3 position. */
+#define OSC_XOSCSEL3_bp  3  
 
 
 /* OSC.XOSCFAIL  bit masks and bit positions */
-#define OSC_XOSCFDIF_bm  0x02  /* Failure Detection Interrupt Flag bit mask. */
-#define OSC_XOSCFDIF_bp  1  /* Failure Detection Interrupt Flag bit position. */
+/* Failure Detection Interrupt Flag bit mask. */
+#define OSC_XOSCFDIF_bm  0x02  
+/* Failure Detection Interrupt Flag bit position. */
+#define OSC_XOSCFDIF_bp  1  
 
 #define OSC_XOSCFDEN_bm  0x01  /* Failure Detection Enable bit mask. */
 #define OSC_XOSCFDEN_bp  0  /* Failure Detection Enable bit position. */
@@ -4033,8 +4191,10 @@ IO Module Instances. Mapped to memory.
 #define RST_SRF_bm  0x20  /* Software Reset Flag bit mask. */
 #define RST_SRF_bp  5  /* Software Reset Flag bit position. */
 
-#define RST_PDIRF_bm  0x10  /* Programming and Debug Interface Interface Reset Flag bit mask. */
-#define RST_PDIRF_bp  4  /* Programming and Debug Interface Interface Reset Flag bit position. */
+/* Programming and Debug Interface Interface Reset Flag bit mask. */
+#define RST_PDIRF_bm  0x10  
+/* Programming and Debug Interface Interface Reset Flag bit position. */
+#define RST_PDIRF_bp  4  
 
 #define RST_WDRF_bm  0x08  /* Watchdog Reset Flag bit mask. */
 #define RST_WDRF_bp  3  /* Watchdog Reset Flag bit position. */
@@ -4128,8 +4288,10 @@ IO Module Instances. Mapped to memory.
 #define PMIC_HILVLEX_bm  0x04  /* High Level Interrupt Executing bit mask. */
 #define PMIC_HILVLEX_bp  2  /* High Level Interrupt Executing bit position. */
 
-#define PMIC_MEDLVLEX_bm  0x02  /* Medium Level Interrupt Executing bit mask. */
-#define PMIC_MEDLVLEX_bp  1  /* Medium Level Interrupt Executing bit position. */
+/* Medium Level Interrupt Executing bit mask. */
+#define PMIC_MEDLVLEX_bm  0x02  
+/* Medium Level Interrupt Executing bit position. */
+#define PMIC_MEDLVLEX_bp  1
 
 #define PMIC_LOLVLEX_bm  0x01  /* Low Level Interrupt Executing bit mask. */
 #define PMIC_LOLVLEX_bp  0  /* Low Level Interrupt Executing bit position. */
@@ -4166,8 +4328,10 @@ IO Module Instances. Mapped to memory.
 #define DMA_CH_TRFREQ_bm  0x10  /* Channel Transfer Request bit mask. */
 #define DMA_CH_TRFREQ_bp  4  /* Channel Transfer Request bit position. */
 
-#define DMA_CH_SINGLE_bm  0x04  /* Channel Single Shot Data Transfer bit mask. */
-#define DMA_CH_SINGLE_bp  2  /* Channel Single Shot Data Transfer bit position. */
+/* Channel Single Shot Data Transfer bit mask. */
+#define DMA_CH_SINGLE_bm  0x04  
+/* Channel Single Shot Data Transfer bit position. */
+#define DMA_CH_SINGLE_bp  2  
 
 #define DMA_CH_BURSTLEN_gm  0x03  /* Channel Transfer Mode group mask. */
 #define DMA_CH_BURSTLEN_gp  0  /* Channel Transfer Mode group position. */
@@ -4184,55 +4348,93 @@ IO Module Instances. Mapped to memory.
 #define DMA_CH_CHPEND_bm  0x40  /* Block Transfer Pending bit mask. */
 #define DMA_CH_CHPEND_bp  6  /* Block Transfer Pending bit position. */
 
-#define DMA_CH_ERRIF_bm  0x20  /* Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH_ERRIF_bp  5  /* Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH_TRNIF_bm  0x10  /* Transaction Complete Interrup Flag bit mask. */
-#define DMA_CH_TRNIF_bp  4  /* Transaction Complete Interrup Flag bit position. */
-
-#define DMA_CH_ERRINTLVL_gm  0x0C  /* Transfer Error Interrupt Level group mask. */
-#define DMA_CH_ERRINTLVL_gp  2  /* Transfer Error Interrupt Level group position. */
-#define DMA_CH_ERRINTLVL0_bm  (1<<2)  /* Transfer Error Interrupt Level bit 0 mask. */
-#define DMA_CH_ERRINTLVL0_bp  2  /* Transfer Error Interrupt Level bit 0 position. */
-#define DMA_CH_ERRINTLVL1_bm  (1<<3)  /* Transfer Error Interrupt Level bit 1 mask. */
-#define DMA_CH_ERRINTLVL1_bp  3  /* Transfer Error Interrupt Level bit 1 position. */
-
-#define DMA_CH_TRNINTLVL_gm  0x03  /* Transaction Complete Interrupt Level group mask. */
-#define DMA_CH_TRNINTLVL_gp  0  /* Transaction Complete Interrupt Level group position. */
-#define DMA_CH_TRNINTLVL0_bm  (1<<0)  /* Transaction Complete Interrupt Level bit 0 mask. */
-#define DMA_CH_TRNINTLVL0_bp  0  /* Transaction Complete Interrupt Level bit 0 position. */
-#define DMA_CH_TRNINTLVL1_bm  (1<<1)  /* Transaction Complete Interrupt Level bit 1 mask. */
-#define DMA_CH_TRNINTLVL1_bp  1  /* Transaction Complete Interrupt Level bit 1 position. */
+/* Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH_ERRIF_bm  0x20  
+/* Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH_ERRIF_bp  5  
+
+/* Transaction Complete Interrup Flag bit mask. */
+#define DMA_CH_TRNIF_bm  0x10  
+/* Transaction Complete Interrup Flag bit position. */
+#define DMA_CH_TRNIF_bp  4  
+
+/* Transfer Error Interrupt Level group mask. */
+#define DMA_CH_ERRINTLVL_gm  0x0C  
+/* Transfer Error Interrupt Level group position. */
+#define DMA_CH_ERRINTLVL_gp  2  
+/* Transfer Error Interrupt Level bit 0 mask. */
+#define DMA_CH_ERRINTLVL0_bm  (1<<2)  
+/* Transfer Error Interrupt Level bit 0 position. */
+#define DMA_CH_ERRINTLVL0_bp  2  
+/* Transfer Error Interrupt Level bit 1 mask. */
+#define DMA_CH_ERRINTLVL1_bm  (1<<3)  
+ /* Transfer Error Interrupt Level bit 1 position. */
+#define DMA_CH_ERRINTLVL1_bp  3 
+
+/* Transaction Complete Interrupt Level group mask. */
+#define DMA_CH_TRNINTLVL_gm  0x03  
+/* Transaction Complete Interrupt Level group position. */
+#define DMA_CH_TRNINTLVL_gp  0  
+/* Transaction Complete Interrupt Level bit 0 mask. */
+#define DMA_CH_TRNINTLVL0_bm  (1<<0)  
+/* Transaction Complete Interrupt Level bit 0 position. */
+#define DMA_CH_TRNINTLVL0_bp  0  
+/* Transaction Complete Interrupt Level bit 1 mask. */
+#define DMA_CH_TRNINTLVL1_bm  (1<<1)  
+/* Transaction Complete Interrupt Level bit 1 position. */
+#define DMA_CH_TRNINTLVL1_bp  1  
 
 
 /* DMA_CH.ADDRCTRL  bit masks and bit positions */
-#define DMA_CH_SRCRELOAD_gm  0xC0  /* Channel Source Address Reload group mask. */
-#define DMA_CH_SRCRELOAD_gp  6  /* Channel Source Address Reload group position. */
-#define DMA_CH_SRCRELOAD0_bm  (1<<6)  /* Channel Source Address Reload bit 0 mask. */
-#define DMA_CH_SRCRELOAD0_bp  6  /* Channel Source Address Reload bit 0 position. */
-#define DMA_CH_SRCRELOAD1_bm  (1<<7)  /* Channel Source Address Reload bit 1 mask. */
-#define DMA_CH_SRCRELOAD1_bp  7  /* Channel Source Address Reload bit 1 position. */
+/* Channel Source Address Reload group mask. */
+#define DMA_CH_SRCRELOAD_gm  0xC0  
+/* Channel Source Address Reload group position. */
+#define DMA_CH_SRCRELOAD_gp  6  
+/* Channel Source Address Reload bit 0 mask. */
+#define DMA_CH_SRCRELOAD0_bm  (1<<6)  
+/* Channel Source Address Reload bit 0 position. */
+#define DMA_CH_SRCRELOAD0_bp  6  
+/* Channel Source Address Reload bit 1 mask. */
+#define DMA_CH_SRCRELOAD1_bm  (1<<7)  
+/* Channel Source Address Reload bit 1 position. */
+#define DMA_CH_SRCRELOAD1_bp  7  
 
 #define DMA_CH_SRCDIR_gm  0x30  /* Channel Source Address Mode group mask. */
 #define DMA_CH_SRCDIR_gp  4  /* Channel Source Address Mode group position. */
-#define DMA_CH_SRCDIR0_bm  (1<<4)  /* Channel Source Address Mode bit 0 mask. */
-#define DMA_CH_SRCDIR0_bp  4  /* Channel Source Address Mode bit 0 position. */
-#define DMA_CH_SRCDIR1_bm  (1<<5)  /* Channel Source Address Mode bit 1 mask. */
-#define DMA_CH_SRCDIR1_bp  5  /* Channel Source Address Mode bit 1 position. */
-
-#define DMA_CH_DESTRELOAD_gm  0x0C  /* Channel Destination Address Reload group mask. */
-#define DMA_CH_DESTRELOAD_gp  2  /* Channel Destination Address Reload group position. */
-#define DMA_CH_DESTRELOAD0_bm  (1<<2)  /* Channel Destination Address Reload bit 0 mask. */
-#define DMA_CH_DESTRELOAD0_bp  2  /* Channel Destination Address Reload bit 0 position. */
-#define DMA_CH_DESTRELOAD1_bm  (1<<3)  /* Channel Destination Address Reload bit 1 mask. */
-#define DMA_CH_DESTRELOAD1_bp  3  /* Channel Destination Address Reload bit 1 position. */
-
-#define DMA_CH_DESTDIR_gm  0x03  /* Channel Destination Address Mode group mask. */
-#define DMA_CH_DESTDIR_gp  0  /* Channel Destination Address Mode group position. */
-#define DMA_CH_DESTDIR0_bm  (1<<0)  /* Channel Destination Address Mode bit 0 mask. */
-#define DMA_CH_DESTDIR0_bp  0  /* Channel Destination Address Mode bit 0 position. */
-#define DMA_CH_DESTDIR1_bm  (1<<1)  /* Channel Destination Address Mode bit 1 mask. */
-#define DMA_CH_DESTDIR1_bp  1  /* Channel Destination Address Mode bit 1 position. */
+/* Channel Source Address Mode bit 0 mask. */
+#define DMA_CH_SRCDIR0_bm  (1<<4)  
+/* Channel Source Address Mode bit 0 position. */
+#define DMA_CH_SRCDIR0_bp  4  
+/* Channel Source Address Mode bit 1 mask. */
+#define DMA_CH_SRCDIR1_bm  (1<<5)  
+/* Channel Source Address Mode bit 1 position. */
+#define DMA_CH_SRCDIR1_bp  5  
+
+/* Channel Destination Address Reload group mask. */
+#define DMA_CH_DESTRELOAD_gm  0x0C  
+/* Channel Destination Address Reload group position. */
+#define DMA_CH_DESTRELOAD_gp  2  
+/* Channel Destination Address Reload bit 0 mask. */
+#define DMA_CH_DESTRELOAD0_bm  (1<<2)  
+/* Channel Destination Address Reload bit 0 position. */
+#define DMA_CH_DESTRELOAD0_bp  2  
+/* Channel Destination Address Reload bit 1 mask. */
+#define DMA_CH_DESTRELOAD1_bm  (1<<3)  
+/* Channel Destination Address Reload bit 1 position. */
+#define DMA_CH_DESTRELOAD1_bp  3  
+
+/* Channel Destination Address Mode group mask. */
+#define DMA_CH_DESTDIR_gm  0x03  
+/* Channel Destination Address Mode group position. */
+#define DMA_CH_DESTDIR_gp  0  
+/* Channel Destination Address Mode bit 0 mask. */
+#define DMA_CH_DESTDIR0_bm  (1<<0)  
+/* Channel Destination Address Mode bit 0 position. */
+#define DMA_CH_DESTDIR0_bp  0  
+/* Channel Destination Address Mode bit 1 mask. */
+#define DMA_CH_DESTDIR1_bm  (1<<1)  
+/* Channel Destination Address Mode bit 1 position. */
+#define DMA_CH_DESTDIR1_bp  1  
 
 
 /* DMA_CH.TRIGSRC  bit masks and bit positions */
@@ -4279,29 +4481,45 @@ IO Module Instances. Mapped to memory.
 
 
 /* DMA.INTFLAGS  bit masks and bit positions */
-#define DMA_CH3ERRIF_bm  0x80  /* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH3ERRIF_bp  7  /* Channel 3 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH2ERRIF_bm  0x40  /* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH2ERRIF_bp  6  /* Channel 2 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH1ERRIF_bm  0x20  /* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH1ERRIF_bp  5  /* Channel 1 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH0ERRIF_bm  0x10  /* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
-#define DMA_CH0ERRIF_bp  4  /* Channel 0 Block Transfer Error Interrupt Flag bit position. */
-
-#define DMA_CH3TRNIF_bm  0x08  /* Channel 3 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH3TRNIF_bp  3  /* Channel 3 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH2TRNIF_bm  0x04  /* Channel 2 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH2TRNIF_bp  2  /* Channel 2 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH1TRNIF_bm  0x02  /* Channel 1 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH1TRNIF_bp  1  /* Channel 1 Transaction Complete Interrupt Flag bit position. */
-
-#define DMA_CH0TRNIF_bm  0x01  /* Channel 0 Transaction Complete Interrupt Flag bit mask. */
-#define DMA_CH0TRNIF_bp  0  /* Channel 0 Transaction Complete Interrupt Flag bit position. */
+/* Channel 3 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH3ERRIF_bm  0x80  
+/* Channel 3 Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH3ERRIF_bp  7  
+
+/* Channel 2 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH2ERRIF_bm  0x40  
+/* Channel 2 Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH2ERRIF_bp  6  
+
+/* Channel 1 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH1ERRIF_bm  0x20  
+/* Channel 1 Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH1ERRIF_bp  5  
+
+/* Channel 0 Block Transfer Error Interrupt Flag bit mask. */
+#define DMA_CH0ERRIF_bm  0x10  
+/* Channel 0 Block Transfer Error Interrupt Flag bit position. */
+#define DMA_CH0ERRIF_bp  4  
+
+/* Channel 3 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH3TRNIF_bm  0x08  
+/* Channel 3 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH3TRNIF_bp  3  
+
+/* Channel 2 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH2TRNIF_bm  0x04  
+/* Channel 2 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH2TRNIF_bp  2  
+
+/* Channel 1 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH1TRNIF_bm  0x02  
+/* Channel 1 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH1TRNIF_bp  1 
+
+/* Channel 0 Transaction Complete Interrupt Flag bit mask. */
+#define DMA_CH0TRNIF_bm  0x01  
+/* Channel 0 Transaction Complete Interrupt Flag bit position. */
+#define DMA_CH0TRNIF_bp  0  
 
 
 /* DMA.STATUS  bit masks and bit positions */
@@ -4318,16 +4536,20 @@ IO Module Instances. Mapped to memory.
 #define DMA_CH0BUSY_bp  4  /* Channel 0 Block Transfer Busy bit position. */
 
 #define DMA_CH3PEND_bm  0x08  /* Channel 3 Block Transfer Pending bit mask. */
-#define DMA_CH3PEND_bp  3  /* Channel 3 Block Transfer Pending bit position. */
+/* Channel 3 Block Transfer Pending bit position. */
+#define DMA_CH3PEND_bp  3  
 
 #define DMA_CH2PEND_bm  0x04  /* Channel 2 Block Transfer Pending bit mask. */
-#define DMA_CH2PEND_bp  2  /* Channel 2 Block Transfer Pending bit position. */
+/* Channel 2 Block Transfer Pending bit position. */
+#define DMA_CH2PEND_bp  2  
 
 #define DMA_CH1PEND_bm  0x02  /* Channel 1 Block Transfer Pending bit mask. */
-#define DMA_CH1PEND_bp  1  /* Channel 1 Block Transfer Pending bit position. */
+/* Channel 1 Block Transfer Pending bit position. */
+#define DMA_CH1PEND_bp  1  
 
 #define DMA_CH0PEND_bm  0x01  /* Channel 0 Block Transfer Pending bit mask. */
-#define DMA_CH0PEND_bp  0  /* Channel 0 Block Transfer Pending bit position. */
+/* Channel 0 Block Transfer Pending bit position. */
+#define DMA_CH0PEND_bp  0  
 
 
 /* EVSYS - Event System */
@@ -4500,12 +4722,18 @@ IO Module Instances. Mapped to memory.
 
 
 /* EVSYS.CH0CTRL  bit masks and bit positions */
-#define EVSYS_QDIRM_gm  0x60  /* Quadrature Decoder Index Recognition Mode group mask. */
-#define EVSYS_QDIRM_gp  5  /* Quadrature Decoder Index Recognition Mode group position. */
-#define EVSYS_QDIRM0_bm  (1<<5)  /* Quadrature Decoder Index Recognition Mode bit 0 mask. */
-#define EVSYS_QDIRM0_bp  5  /* Quadrature Decoder Index Recognition Mode bit 0 position. */
-#define EVSYS_QDIRM1_bm  (1<<6)  /* Quadrature Decoder Index Recognition Mode bit 1 mask. */
-#define EVSYS_QDIRM1_bp  6  /* Quadrature Decoder Index Recognition Mode bit 1 position. */
+/* Quadrature Decoder Index Recognition Mode group mask. */
+#define EVSYS_QDIRM_gm  0x60  
+/* Quadrature Decoder Index Recognition Mode group position. */
+#define EVSYS_QDIRM_gp  5  
+/* Quadrature Decoder Index Recognition Mode bit 0 mask. */
+#define EVSYS_QDIRM0_bm  (1<<5)  
+/* Quadrature Decoder Index Recognition Mode bit 0 position. */
+#define EVSYS_QDIRM0_bp  5  
+/* Quadrature Decoder Index Recognition Mode bit 1 mask. */
+#define EVSYS_QDIRM1_bm  (1<<6)  
+/* Quadrature Decoder Index Recognition Mode bit 1 position. */
+#define EVSYS_QDIRM1_bp  6  
 
 #define EVSYS_QDIEN_bm  0x10  /* Quadrature Decoder Index Enable bit mask. */
 #define EVSYS_QDIEN_bp  4  /* Quadrature Decoder Index Enable bit position. */
@@ -4691,7 +4919,8 @@ IO Module Instances. Mapped to memory.
 #define NVM_FBUSY_bp  6  /* Flash Memory Busy bit position. */
 
 #define NVM_EELOAD_bm  0x02  /* EEPROM Page Buffer Active Loading bit mask. */
-#define NVM_EELOAD_bp  1  /* EEPROM Page Buffer Active Loading bit position. */
+/* EEPROM Page Buffer Active Loading bit position. */
+#define NVM_EELOAD_bp  1  
 
 #define NVM_FLOAD_bm  0x01  /* Flash Page Buffer Active Loading bit mask. */
 #define NVM_FLOAD_bp  0  /* Flash Page Buffer Active Loading bit position. */
@@ -4705,19 +4934,31 @@ IO Module Instances. Mapped to memory.
 #define NVM_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
 #define NVM_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
 
-#define NVM_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
+/* Boot Lock Bits - Application Section group mask. */
+#define NVM_BLBA_gm  0x30  
+/* Boot Lock Bits - Application Section group position. */
+#define NVM_BLBA_gp  4  
+ /* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_BLBA0_bm  (1<<4) 
+/* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_BLBA0_bp  4  
+/* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_BLBA1_bm  (1<<5)  
+/* Boot Lock Bits - Application Section bit 1 position. */
+#define NVM_BLBA1_bp  5  
+
+/* Boot Lock Bits - Application Table group mask. */
+#define NVM_BLBAT_gm  0x0C  
+/* Boot Lock Bits - Application Table group position. */
+#define NVM_BLBAT_gp  2  
+/* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_BLBAT0_bm  (1<<2)  
+/* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_BLBAT0_bp  2  
+/* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_BLBAT1_bm  (1<<3)  
+/* Boot Lock Bits - Application Table bit 1 position. */
+#define NVM_BLBAT1_bp  3  
 
 #define NVM_LB_gm  0x03  /* Lock Bits group mask. */
 #define NVM_LB_gp  0  /* Lock Bits group position. */
@@ -4728,26 +4969,44 @@ IO Module Instances. Mapped to memory.
 
 
 /* NVM_LOCKBITS.LOCKBITS  bit masks and bit positions */
-#define NVM_LOCKBITS_BLBB_gm  0xC0  /* Boot Lock Bits - Boot Section group mask. */
-#define NVM_LOCKBITS_BLBB_gp  6  /* Boot Lock Bits - Boot Section group position. */
-#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  /* Boot Lock Bits - Boot Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBB0_bp  6  /* Boot Lock Bits - Boot Section bit 0 position. */
-#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  /* Boot Lock Bits - Boot Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBB1_bp  7  /* Boot Lock Bits - Boot Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBA_gm  0x30  /* Boot Lock Bits - Application Section group mask. */
-#define NVM_LOCKBITS_BLBA_gp  4  /* Boot Lock Bits - Application Section group position. */
-#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  /* Boot Lock Bits - Application Section bit 0 mask. */
-#define NVM_LOCKBITS_BLBA0_bp  4  /* Boot Lock Bits - Application Section bit 0 position. */
-#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  /* Boot Lock Bits - Application Section bit 1 mask. */
-#define NVM_LOCKBITS_BLBA1_bp  5  /* Boot Lock Bits - Application Section bit 1 position. */
-
-#define NVM_LOCKBITS_BLBAT_gm  0x0C  /* Boot Lock Bits - Application Table group mask. */
-#define NVM_LOCKBITS_BLBAT_gp  2  /* Boot Lock Bits - Application Table group position. */
-#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  /* Boot Lock Bits - Application Table bit 0 mask. */
-#define NVM_LOCKBITS_BLBAT0_bp  2  /* Boot Lock Bits - Application Table bit 0 position. */
-#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  /* Boot Lock Bits - Application Table bit 1 mask. */
-#define NVM_LOCKBITS_BLBAT1_bp  3  /* Boot Lock Bits - Application Table bit 1 position. */
+/* Boot Lock Bits - Boot Section group mask. */
+#define NVM_LOCKBITS_BLBB_gm  0xC0  
+/* Boot Lock Bits - Boot Section group position. */
+#define NVM_LOCKBITS_BLBB_gp  6  
+/* Boot Lock Bits - Boot Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBB0_bm  (1<<6)  
+ /* Boot Lock Bits - Boot Section bit 0 position. */
+#define NVM_LOCKBITS_BLBB0_bp  6 
+/* Boot Lock Bits - Boot Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBB1_bm  (1<<7)  
+/* Boot Lock Bits - Boot Section bit 1 position. */
+#define NVM_LOCKBITS_BLBB1_bp  7  
+
+/* Boot Lock Bits - Application Section group mask. */
+#define NVM_LOCKBITS_BLBA_gm  0x30  
+/* Boot Lock Bits - Application Section group position. */
+#define NVM_LOCKBITS_BLBA_gp  4  
+/* Boot Lock Bits - Application Section bit 0 mask. */
+#define NVM_LOCKBITS_BLBA0_bm  (1<<4)  
+/* Boot Lock Bits - Application Section bit 0 position. */
+#define NVM_LOCKBITS_BLBA0_bp  4  
+/* Boot Lock Bits - Application Section bit 1 mask. */
+#define NVM_LOCKBITS_BLBA1_bm  (1<<5)  
+/* Boot Lock Bits - Application Section bit 1 position. */
+#define NVM_LOCKBITS_BLBA1_bp  5  
+
+/* Boot Lock Bits - Application Table group mask. */
+#define NVM_LOCKBITS_BLBAT_gm  0x0C  
+/* Boot Lock Bits - Application Table group position. */
+#define NVM_LOCKBITS_BLBAT_gp  2  
+/* Boot Lock Bits - Application Table bit 0 mask. */
+#define NVM_LOCKBITS_BLBAT0_bm  (1<<2)  
+/* Boot Lock Bits - Application Table bit 0 position. */
+#define NVM_LOCKBITS_BLBAT0_bp  2  
+/* Boot Lock Bits - Application Table bit 1 mask. */
+#define NVM_LOCKBITS_BLBAT1_bm  (1<<3)  
+/* Boot Lock Bits - Application Table bit 1 position. */
+#define NVM_LOCKBITS_BLBAT1_bp  3  
 
 #define NVM_LOCKBITS_LB_gm  0x03  /* Lock Bits group mask. */
 #define NVM_LOCKBITS_LB_gp  0  /* Lock Bits group position. */
@@ -4779,16 +5038,26 @@ IO Module Instances. Mapped to memory.
 
 
 /* NVM_FUSES.FUSEBYTE1  bit masks and bit positions */
-#define NVM_FUSES_WDWP_gm  0xF0  /* Watchdog Window Timeout Period group mask. */
-#define NVM_FUSES_WDWP_gp  4  /* Watchdog Window Timeout Period group position. */
-#define NVM_FUSES_WDWP0_bm  (1<<4)  /* Watchdog Window Timeout Period bit 0 mask. */
-#define NVM_FUSES_WDWP0_bp  4  /* Watchdog Window Timeout Period bit 0 position. */
-#define NVM_FUSES_WDWP1_bm  (1<<5)  /* Watchdog Window Timeout Period bit 1 mask. */
-#define NVM_FUSES_WDWP1_bp  5  /* Watchdog Window Timeout Period bit 1 position. */
-#define NVM_FUSES_WDWP2_bm  (1<<6)  /* Watchdog Window Timeout Period bit 2 mask. */
-#define NVM_FUSES_WDWP2_bp  6  /* Watchdog Window Timeout Period bit 2 position. */
-#define NVM_FUSES_WDWP3_bm  (1<<7)  /* Watchdog Window Timeout Period bit 3 mask. */
-#define NVM_FUSES_WDWP3_bp  7  /* Watchdog Window Timeout Period bit 3 position. */
+/* Watchdog Window Timeout Period group mask. */
+#define NVM_FUSES_WDWP_gm  0xF0  
+/* Watchdog Window Timeout Period group position. */
+#define NVM_FUSES_WDWP_gp  4  
+/* Watchdog Window Timeout Period bit 0 mask. */
+#define NVM_FUSES_WDWP0_bm  (1<<4)  
+/* Watchdog Window Timeout Period bit 0 position. */
+#define NVM_FUSES_WDWP0_bp  4  
+/* Watchdog Window Timeout Period bit 1 mask. */
+#define NVM_FUSES_WDWP1_bm  (1<<5)  
+/* Watchdog Window Timeout Period bit 1 position. */
+#define NVM_FUSES_WDWP1_bp  5  
+/* Watchdog Window Timeout Period bit 2 mask. */
+#define NVM_FUSES_WDWP2_bm  (1<<6)  
+/* Watchdog Window Timeout Period bit 2 position. */
+#define NVM_FUSES_WDWP2_bp  6  
+/* Watchdog Window Timeout Period bit 3 mask. */
+#define NVM_FUSES_WDWP3_bm  (1<<7)  
+/* Watchdog Window Timeout Period bit 3 position. */
+#define NVM_FUSES_WDWP3_bp  7  
 
 #define NVM_FUSES_WDP_gm  0x0F  /* Watchdog Timeout Period group mask. */
 #define NVM_FUSES_WDP_gp  0  /* Watchdog Timeout Period group position. */
@@ -4806,22 +5075,36 @@ IO Module Instances. Mapped to memory.
 #define NVM_FUSES_DVSDON_bm  0x80  /* Spike Detector Enable bit mask. */
 #define NVM_FUSES_DVSDON_bp  7  /* Spike Detector Enable bit position. */
 
-#define NVM_FUSES_BOOTRST_bm  0x40  /* Boot Loader Section Reset Vector bit mask. */
-#define NVM_FUSES_BOOTRST_bp  6  /* Boot Loader Section Reset Vector bit position. */
-
-#define NVM_FUSES_BODACT_gm  0x0C  /* BOD Operation in Active Mode group mask. */
-#define NVM_FUSES_BODACT_gp  2  /* BOD Operation in Active Mode group position. */
-#define NVM_FUSES_BODACT0_bm  (1<<2)  /* BOD Operation in Active Mode bit 0 mask. */
-#define NVM_FUSES_BODACT0_bp  2  /* BOD Operation in Active Mode bit 0 position. */
-#define NVM_FUSES_BODACT1_bm  (1<<3)  /* BOD Operation in Active Mode bit 1 mask. */
-#define NVM_FUSES_BODACT1_bp  3  /* BOD Operation in Active Mode bit 1 position. */
-
-#define NVM_FUSES_BODPD_gm  0x03  /* BOD Operation in Power-Down Mode group mask. */
-#define NVM_FUSES_BODPD_gp  0  /* BOD Operation in Power-Down Mode group position. */
-#define NVM_FUSES_BODPD0_bm  (1<<0)  /* BOD Operation in Power-Down Mode bit 0 mask. */
-#define NVM_FUSES_BODPD0_bp  0  /* BOD Operation in Power-Down Mode bit 0 position. */
-#define NVM_FUSES_BODPD1_bm  (1<<1)  /* BOD Operation in Power-Down Mode bit 1 mask. */
-#define NVM_FUSES_BODPD1_bp  1  /* BOD Operation in Power-Down Mode bit 1 position. */
+/* Boot Loader Section Reset Vector bit mask. */
+#define NVM_FUSES_BOOTRST_bm  0x40  
+/* Boot Loader Section Reset Vector bit position. */
+#define NVM_FUSES_BOOTRST_bp  6  
+
+/* BOD Operation in Active Mode group mask. */
+#define NVM_FUSES_BODACT_gm  0x0C  
+/* BOD Operation in Active Mode group position. */
+#define NVM_FUSES_BODACT_gp  2 
+/* BOD Operation in Active Mode bit 0 mask. */
+#define NVM_FUSES_BODACT0_bm  (1<<2)  
+/* BOD Operation in Active Mode bit 0 position. */
+#define NVM_FUSES_BODACT0_bp  2  
+/* BOD Operation in Active Mode bit 1 mask. */
+#define NVM_FUSES_BODACT1_bm  (1<<3)  
+/* BOD Operation in Active Mode bit 1 position. */
+#define NVM_FUSES_BODACT1_bp  3  
+
+/* BOD Operation in Power-Down Mode group mask. */
+#define NVM_FUSES_BODPD_gm  0x03  
+/* BOD Operation in Power-Down Mode group position. */
+#define NVM_FUSES_BODPD_gp  0  
+/* BOD Operation in Power-Down Mode bit 0 mask. */
+#define NVM_FUSES_BODPD0_bm  (1<<0)  
+/* BOD Operation in Power-Down Mode bit 0 position. */
+#define NVM_FUSES_BODPD0_bp  0  
+/* BOD Operation in Power-Down Mode bit 1 mask. */
+#define NVM_FUSES_BODPD1_bm  (1<<1)  
+/* BOD Operation in Power-Down Mode bit 1 position. */
+#define NVM_FUSES_BODPD1_bp  1  
 
 
 /* NVM_FUSES.FUSEBYTE4  bit masks and bit positions */
@@ -4840,17 +5123,27 @@ IO Module Instances. Mapped to memory.
 
 
 /* NVM_FUSES.FUSEBYTE5  bit masks and bit positions */
-#define NVM_FUSES_EESAVE_bm  0x08  /* Preserve EEPROM Through Chip Erase bit mask. */
-#define NVM_FUSES_EESAVE_bp  3  /* Preserve EEPROM Through Chip Erase bit position. */
-
-#define NVM_FUSES_BODLVL_gm  0x07  /* Brown Out Detection Voltage Level group mask. */
-#define NVM_FUSES_BODLVL_gp  0  /* Brown Out Detection Voltage Level group position. */
-#define NVM_FUSES_BODLVL0_bm  (1<<0)  /* Brown Out Detection Voltage Level bit 0 mask. */
-#define NVM_FUSES_BODLVL0_bp  0  /* Brown Out Detection Voltage Level bit 0 position. */
-#define NVM_FUSES_BODLVL1_bm  (1<<1)  /* Brown Out Detection Voltage Level bit 1 mask. */
-#define NVM_FUSES_BODLVL1_bp  1  /* Brown Out Detection Voltage Level bit 1 position. */
-#define NVM_FUSES_BODLVL2_bm  (1<<2)  /* Brown Out Detection Voltage Level bit 2 mask. */
-#define NVM_FUSES_BODLVL2_bp  2  /* Brown Out Detection Voltage Level bit 2 position. */
+/* Preserve EEPROM Through Chip Erase bit mask. */
+#define NVM_FUSES_EESAVE_bm  0x08  
+/* Preserve EEPROM Through Chip Erase bit position. */
+#define NVM_FUSES_EESAVE_bp  3  
+
+/* Brown Out Detection Voltage Level group mask. */
+#define NVM_FUSES_BODLVL_gm  0x07  
+/* Brown Out Detection Voltage Level group position. */
+#define NVM_FUSES_BODLVL_gp  0  
+/* Brown Out Detection Voltage Level bit 0 mask. */
+#define NVM_FUSES_BODLVL0_bm  (1<<0)  
+/* Brown Out Detection Voltage Level bit 0 position. */
+#define NVM_FUSES_BODLVL0_bp  0  
+/* Brown Out Detection Voltage Level bit 1 mask. */
+#define NVM_FUSES_BODLVL1_bm  (1<<1)  
+/* Brown Out Detection Voltage Level bit 1 position. */
+#define NVM_FUSES_BODLVL1_bp  1  
+/* Brown Out Detection Voltage Level bit 2 mask. */
+#define NVM_FUSES_BODLVL2_bm  (1<<2)  
+/* Brown Out Detection Voltage Level bit 2 position. */
+#define NVM_FUSES_BODLVL2_bp  2  
 
 
 /* AC - Analog Comparator */
@@ -5309,12 +5602,18 @@ IO Module Instances. Mapped to memory.
 
 
 /* RTC.INTCTRL  bit masks and bit positions */
-#define RTC_COMPINTLVL_gm  0x0C  /* Compare Match Interrupt Level group mask. */
-#define RTC_COMPINTLVL_gp  2  /* Compare Match Interrupt Level group position. */
-#define RTC_COMPINTLVL0_bm  (1<<2)  /* Compare Match Interrupt Level bit 0 mask. */
-#define RTC_COMPINTLVL0_bp  2  /* Compare Match Interrupt Level bit 0 position. */
-#define RTC_COMPINTLVL1_bm  (1<<3)  /* Compare Match Interrupt Level bit 1 mask. */
-#define RTC_COMPINTLVL1_bp  3  /* Compare Match Interrupt Level bit 1 position. */
+/* Compare Match Interrupt Level group mask. */
+#define RTC_COMPINTLVL_gm  0x0C  
+/* Compare Match Interrupt Level group position. */
+#define RTC_COMPINTLVL_gp  2  
+ /* Compare Match Interrupt Level bit 0 mask. */
+#define RTC_COMPINTLVL0_bm  (1<<2) 
+/* Compare Match Interrupt Level bit 0 position. */
+#define RTC_COMPINTLVL0_bp  2  
+/* Compare Match Interrupt Level bit 1 mask. */
+#define RTC_COMPINTLVL1_bm  (1<<3)  
+/* Compare Match Interrupt Level bit 1 position. */
+#define RTC_COMPINTLVL1_bp  3  
 
 #define RTC_OVFINTLVL_gm  0x03  /* Overflow Interrupt Level group mask. */
 #define RTC_OVFINTLVL_gp  0  /* Overflow Interrupt Level group position. */
@@ -5459,14 +5758,22 @@ IO Module Instances. Mapped to memory.
 #define EBI_WRDLY1_bm  (1<<7)  /* SDRAM Write Recovery Delay bit 1 mask. */
 #define EBI_WRDLY1_bp  7  /* SDRAM Write Recovery Delay bit 1 position. */
 
-#define EBI_ESRDLY_gm  0x38  /* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
-#define EBI_ESRDLY_gp  3  /* SDRAM Exit-Self-refresh-to-Active Delay group position. */
-#define EBI_ESRDLY0_bm  (1<<3)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
-#define EBI_ESRDLY0_bp  3  /* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
-#define EBI_ESRDLY1_bm  (1<<4)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
-#define EBI_ESRDLY1_bp  4  /* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
-#define EBI_ESRDLY2_bm  (1<<5)  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
-#define EBI_ESRDLY2_bp  5  /* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
+/* SDRAM Exit-Self-refresh-to-Active Delay group mask. */
+#define EBI_ESRDLY_gm  0x38  
+/* SDRAM Exit-Self-refresh-to-Active Delay group position. */
+#define EBI_ESRDLY_gp  3  
+/* SDRAM Exit-Self-refresh-to-Active Delay bit 0 mask. */
+#define EBI_ESRDLY0_bm  (1<<3)  
+/* SDRAM Exit-Self-refresh-to-Active Delay bit 0 position. */
+#define EBI_ESRDLY0_bp  3  
+/* SDRAM Exit-Self-refresh-to-Active Delay bit 1 mask. */
+#define EBI_ESRDLY1_bm  (1<<4)  
+/* SDRAM Exit-Self-refresh-to-Active Delay bit 1 position. */
+#define EBI_ESRDLY1_bp  4  
+/* SDRAM Exit-Self-refresh-to-Active Delay bit 2 mask. */
+#define EBI_ESRDLY2_bm  (1<<5)  
+/* SDRAM Exit-Self-refresh-to-Active Delay bit 2 position. */
+#define EBI_ESRDLY2_bp  5  
 
 #define EBI_ROWCOLDLY_gm  0x07  /* SDRAM Row-to-Column Delay group mask. */
 #define EBI_ROWCOLDLY_gp  0  /* SDRAM Row-to-Column Delay group position. */
@@ -5562,8 +5869,10 @@ IO Module Instances. Mapped to memory.
 #define TWI_SLAVE_DIEN_bm  0x20  /* Data Interrupt Enable bit mask. */
 #define TWI_SLAVE_DIEN_bp  5  /* Data Interrupt Enable bit position. */
 
-#define TWI_SLAVE_APIEN_bm  0x10  /* Address/Stop Interrupt Enable bit mask. */
-#define TWI_SLAVE_APIEN_bp  4  /* Address/Stop Interrupt Enable bit position. */
+/* Address/Stop Interrupt Enable bit mask. */
+#define TWI_SLAVE_APIEN_bm  0x10  
+/* Address/Stop Interrupt Enable bit position. */
+#define TWI_SLAVE_APIEN_bp  4  
 
 #define TWI_SLAVE_ENABLE_bm  0x08  /* Enable TWI Slave bit mask. */
 #define TWI_SLAVE_ENABLE_bp  3  /* Enable TWI Slave bit position. */
@@ -6052,33 +6361,57 @@ IO Module Instances. Mapped to memory.
 
 
 /* TC0.INTCTRLB  bit masks and bit positions */
-#define TC0_CCDINTLVL_gm  0xC0  /* Compare or Capture D Interrupt Level group mask. */
-#define TC0_CCDINTLVL_gp  6  /* Compare or Capture D Interrupt Level group position. */
-#define TC0_CCDINTLVL0_bm  (1<<6)  /* Compare or Capture D Interrupt Level bit 0 mask. */
-#define TC0_CCDINTLVL0_bp  6  /* Compare or Capture D Interrupt Level bit 0 position. */
-#define TC0_CCDINTLVL1_bm  (1<<7)  /* Compare or Capture D Interrupt Level bit 1 mask. */
-#define TC0_CCDINTLVL1_bp  7  /* Compare or Capture D Interrupt Level bit 1 position. */
-
-#define TC0_CCCINTLVL_gm  0x30  /* Compare or Capture C Interrupt Level group mask. */
-#define TC0_CCCINTLVL_gp  4  /* Compare or Capture C Interrupt Level group position. */
-#define TC0_CCCINTLVL0_bm  (1<<4)  /* Compare or Capture C Interrupt Level bit 0 mask. */
-#define TC0_CCCINTLVL0_bp  4  /* Compare or Capture C Interrupt Level bit 0 position. */
-#define TC0_CCCINTLVL1_bm  (1<<5)  /* Compare or Capture C Interrupt Level bit 1 mask. */
-#define TC0_CCCINTLVL1_bp  5  /* Compare or Capture C Interrupt Level bit 1 position. */
-
-#define TC0_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC0_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC0_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC0_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC0_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC0_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC0_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC0_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC0_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC0_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC0_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC0_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
+/* Compare or Capture D Interrupt Level group mask. */
+#define TC0_CCDINTLVL_gm  0xC0  
+/* Compare or Capture D Interrupt Level group position. */
+#define TC0_CCDINTLVL_gp  6  
+/* Compare or Capture D Interrupt Level bit 0 mask. */
+#define TC0_CCDINTLVL0_bm  (1<<6)  
+/* Compare or Capture D Interrupt Level bit 0 position. */
+#define TC0_CCDINTLVL0_bp  6  
+/* Compare or Capture D Interrupt Level bit 1 mask. */
+#define TC0_CCDINTLVL1_bm  (1<<7)  
+/* Compare or Capture D Interrupt Level bit 1 position. */
+#define TC0_CCDINTLVL1_bp  7  
+
+/* Compare or Capture C Interrupt Level group mask. */
+#define TC0_CCCINTLVL_gm  0x30  
+ /* Compare or Capture C Interrupt Level group position. */
+#define TC0_CCCINTLVL_gp  4 
+/* Compare or Capture C Interrupt Level bit 0 mask. */
+#define TC0_CCCINTLVL0_bm  (1<<4)  
+/* Compare or Capture C Interrupt Level bit 0 position. */
+#define TC0_CCCINTLVL0_bp  4  
+ /* Compare or Capture C Interrupt Level bit 1 mask. */
+#define TC0_CCCINTLVL1_bm  (1<<5) 
+/* Compare or Capture C Interrupt Level bit 1 position. */
+#define TC0_CCCINTLVL1_bp  5  
+
+/* Compare or Capture B Interrupt Level group mask. */
+#define TC0_CCBINTLVL_gm  0x0C  
+/* Compare or Capture B Interrupt Level group position. */
+#define TC0_CCBINTLVL_gp  2  
+/* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC0_CCBINTLVL0_bm  (1<<2)  
+ /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC0_CCBINTLVL0_bp  2 
+/* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC0_CCBINTLVL1_bm  (1<<3)  
+/* Compare or Capture B Interrupt Level bit 1 position. */
+#define TC0_CCBINTLVL1_bp  3  
+
+/* Compare or Capture A Interrupt Level group mask. */
+#define TC0_CCAINTLVL_gm  0x03  
+/* Compare or Capture A Interrupt Level group position. */
+#define TC0_CCAINTLVL_gp  0  
+/* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC0_CCAINTLVL0_bm  (1<<0)  
+/* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC0_CCAINTLVL0_bp  0  
+/* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC0_CCAINTLVL1_bm  (1<<1)  
+/* Compare or Capture A Interrupt Level bit 1 position. */
+#define TC0_CCAINTLVL1_bp  1  
 
 
 /* TC0.CTRLFCLR  bit masks and bit positions */
@@ -6146,17 +6479,25 @@ IO Module Instances. Mapped to memory.
 
 
 /* TC0.INTFLAGS  bit masks and bit positions */
-#define TC0_CCDIF_bm  0x80  /* Compare or Capture D Interrupt Flag bit mask. */
-#define TC0_CCDIF_bp  7  /* Compare or Capture D Interrupt Flag bit position. */
-
-#define TC0_CCCIF_bm  0x40  /* Compare or Capture C Interrupt Flag bit mask. */
-#define TC0_CCCIF_bp  6  /* Compare or Capture C Interrupt Flag bit position. */
-
-#define TC0_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC0_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
-
-#define TC0_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC0_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
+/* Compare or Capture D Interrupt Flag bit mask. */
+#define TC0_CCDIF_bm  0x80  
+/* Compare or Capture D Interrupt Flag bit position. */
+#define TC0_CCDIF_bp  7  
+
+/* Compare or Capture C Interrupt Flag bit mask. */
+#define TC0_CCCIF_bm  0x40  
+/* Compare or Capture C Interrupt Flag bit position. */
+#define TC0_CCCIF_bp  6  
+
+/* Compare or Capture B Interrupt Flag bit mask. */
+#define TC0_CCBIF_bm  0x20  
+/* Compare or Capture B Interrupt Flag bit position. */
+#define TC0_CCBIF_bp  5  
+
+/* Compare or Capture A Interrupt Flag bit mask. */
+#define TC0_CCAIF_bm  0x10  
+/* Compare or Capture A Interrupt Flag bit position. */
+#define TC0_CCAIF_bp  4  
 
 #define TC0_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
 #define TC0_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
@@ -6253,19 +6594,31 @@ IO Module Instances. Mapped to memory.
 
 
 /* TC1.INTCTRLB  bit masks and bit positions */
-#define TC1_CCBINTLVL_gm  0x0C  /* Compare or Capture B Interrupt Level group mask. */
-#define TC1_CCBINTLVL_gp  2  /* Compare or Capture B Interrupt Level group position. */
-#define TC1_CCBINTLVL0_bm  (1<<2)  /* Compare or Capture B Interrupt Level bit 0 mask. */
-#define TC1_CCBINTLVL0_bp  2  /* Compare or Capture B Interrupt Level bit 0 position. */
-#define TC1_CCBINTLVL1_bm  (1<<3)  /* Compare or Capture B Interrupt Level bit 1 mask. */
-#define TC1_CCBINTLVL1_bp  3  /* Compare or Capture B Interrupt Level bit 1 position. */
-
-#define TC1_CCAINTLVL_gm  0x03  /* Compare or Capture A Interrupt Level group mask. */
-#define TC1_CCAINTLVL_gp  0  /* Compare or Capture A Interrupt Level group position. */
-#define TC1_CCAINTLVL0_bm  (1<<0)  /* Compare or Capture A Interrupt Level bit 0 mask. */
-#define TC1_CCAINTLVL0_bp  0  /* Compare or Capture A Interrupt Level bit 0 position. */
-#define TC1_CCAINTLVL1_bm  (1<<1)  /* Compare or Capture A Interrupt Level bit 1 mask. */
-#define TC1_CCAINTLVL1_bp  1  /* Compare or Capture A Interrupt Level bit 1 position. */
+/* Compare or Capture B Interrupt Level group mask. */
+#define TC1_CCBINTLVL_gm  0x0C  
+/* Compare or Capture B Interrupt Level group position. */
+#define TC1_CCBINTLVL_gp  2  
+/* Compare or Capture B Interrupt Level bit 0 mask. */
+#define TC1_CCBINTLVL0_bm  (1<<2)  
+ /* Compare or Capture B Interrupt Level bit 0 position. */
+#define TC1_CCBINTLVL0_bp  2 
+/* Compare or Capture B Interrupt Level bit 1 mask. */
+#define TC1_CCBINTLVL1_bm  (1<<3)  
+/* Compare or Capture B Interrupt Level bit 1 position. */
+#define TC1_CCBINTLVL1_bp  3  
+
+/* Compare or Capture A Interrupt Level group mask. */
+#define TC1_CCAINTLVL_gm  0x03  
+/* Compare or Capture A Interrupt Level group position. */
+#define TC1_CCAINTLVL_gp  0  
+/* Compare or Capture A Interrupt Level bit 0 mask. */
+#define TC1_CCAINTLVL0_bm  (1<<0)  
+/* Compare or Capture A Interrupt Level bit 0 position. */
+#define TC1_CCAINTLVL0_bp  0  
+/* Compare or Capture A Interrupt Level bit 1 mask. */
+#define TC1_CCAINTLVL1_bm  (1<<1)  
+/* Compare or Capture A Interrupt Level bit 1 position. */
+#define TC1_CCAINTLVL1_bp  1  
 
 
 /* TC1.CTRLFCLR  bit masks and bit positions */
@@ -6321,11 +6674,16 @@ IO Module Instances. Mapped to memory.
 
 
 /* TC1.INTFLAGS  bit masks and bit positions */
-#define TC1_CCBIF_bm  0x20  /* Compare or Capture B Interrupt Flag bit mask. */
-#define TC1_CCBIF_bp  5  /* Compare or Capture B Interrupt Flag bit position. */
 
-#define TC1_CCAIF_bm  0x10  /* Compare or Capture A Interrupt Flag bit mask. */
-#define TC1_CCAIF_bp  4  /* Compare or Capture A Interrupt Flag bit position. */
+/* Compare or Capture B Interrupt Flag bit mask. */
+#define TC1_CCBIF_bm  0x20  
+/* Compare or Capture B Interrupt Flag bit position. */
+#define TC1_CCBIF_bp  5  
+
+/* Compare or Capture A Interrupt Flag bit mask. */
+#define TC1_CCAIF_bm  0x10  
+/* Compare or Capture A Interrupt Flag bit position. */
+#define TC1_CCAIF_bp  4  
 
 #define TC1_ERRIF_bm  0x02  /* Error Interrupt Flag bit mask. */
 #define TC1_ERRIF_bp  1  /* Error Interrupt Flag bit position. */
@@ -6341,22 +6699,32 @@ IO Module Instances. Mapped to memory.
 #define AWEX_CWCM_bm  0x10  /* Common Waveform Channel Mode bit mask. */
 #define AWEX_CWCM_bp  4  /* Common Waveform Channel Mode bit position. */
 
-#define AWEX_DTICCDEN_bm  0x08  /* Dead Time Insertion Compare Channel D Enable bit mask. */
-#define AWEX_DTICCDEN_bp  3  /* Dead Time Insertion Compare Channel D Enable bit position. */
+/* Dead Time Insertion Compare Channel D Enable bit mask. */
+#define AWEX_DTICCDEN_bm  0x08  
+/* Dead Time Insertion Compare Channel D Enable bit position. */
+#define AWEX_DTICCDEN_bp  3  
 
-#define AWEX_DTICCCEN_bm  0x04  /* Dead Time Insertion Compare Channel C Enable bit mask. */
-#define AWEX_DTICCCEN_bp  2  /* Dead Time Insertion Compare Channel C Enable bit position. */
+/* Dead Time Insertion Compare Channel C Enable bit mask. */
+#define AWEX_DTICCCEN_bm  0x04  
+/* Dead Time Insertion Compare Channel C Enable bit position. */
+#define AWEX_DTICCCEN_bp  2  
 
-#define AWEX_DTICCBEN_bm  0x02  /* Dead Time Insertion Compare Channel B Enable bit mask. */
-#define AWEX_DTICCBEN_bp  1  /* Dead Time Insertion Compare Channel B Enable bit position. */
+/* Dead Time Insertion Compare Channel B Enable bit mask. */
+#define AWEX_DTICCBEN_bm  0x02  
+/* Dead Time Insertion Compare Channel B Enable bit position. */
+#define AWEX_DTICCBEN_bp  1  
 
-#define AWEX_DTICCAEN_bm  0x01  /* Dead Time Insertion Compare Channel A Enable bit mask. */
-#define AWEX_DTICCAEN_bp  0  /* Dead Time Insertion Compare Channel A Enable bit position. */
+/* Dead Time Insertion Compare Channel A Enable bit mask. */
+#define AWEX_DTICCAEN_bm  0x01  
+/* Dead Time Insertion Compare Channel A Enable bit position. */
+#define AWEX_DTICCAEN_bp  0  
 
 
 /* AWEX.FDCTRL  bit masks and bit positions */
-#define AWEX_FDDBD_bm  0x10  /* Fault Detect on Disable Break Disable bit mask. */
-#define AWEX_FDDBD_bp  4  /* Fault Detect on Disable Break Disable bit position. */
+/* Fault Detect on Disable Break Disable bit mask. */
+#define AWEX_FDDBD_bm  0x10  
+/* Fault Detect on Disable Break Disable bit position. */
+#define AWEX_FDDBD_bp  4  
 
 #define AWEX_FDMODE_bm  0x04  /* Fault Detect Mode bit mask. */
 #define AWEX_FDMODE_bp  2  /* Fault Detect Mode bit position. */
@@ -6373,11 +6741,15 @@ IO Module Instances. Mapped to memory.
 #define AWEX_FDF_bm  0x04  /* Fault Detect Flag bit mask. */
 #define AWEX_FDF_bp  2  /* Fault Detect Flag bit position. */
 
-#define AWEX_DTHSBUFV_bm  0x02  /* Dead Time High Side Buffer Valid bit mask. */
-#define AWEX_DTHSBUFV_bp  1  /* Dead Time High Side Buffer Valid bit position. */
+/* Dead Time High Side Buffer Valid bit mask. */
+#define AWEX_DTHSBUFV_bm  0x02  
+/* Dead Time High Side Buffer Valid bit position. */
+#define AWEX_DTHSBUFV_bp  1  
 
-#define AWEX_DTLSBUFV_bm  0x01  /* Dead Time Low Side Buffer Valid bit mask. */
-#define AWEX_DTLSBUFV_bp  0  /* Dead Time Low Side Buffer Valid bit position. */
+/* Dead Time Low Side Buffer Valid bit mask. */
+#define AWEX_DTLSBUFV_bm  0x01  
+/* Dead Time Low Side Buffer Valid bit position. */
+#define AWEX_DTLSBUFV_bp  0  
 
 
 /* HIRES.CTRL  bit masks and bit positions */
@@ -6423,17 +6795,25 @@ IO Module Instances. Mapped to memory.
 
 #define USART_TXCINTLVL_gm  0x0C  /* Transmit Interrupt Level group mask. */
 #define USART_TXCINTLVL_gp  2  /* Transmit Interrupt Level group position. */
-#define USART_TXCINTLVL0_bm  (1<<2)  /* Transmit Interrupt Level bit 0 mask. */
+/* Transmit Interrupt Level bit 0 mask. */
+#define USART_TXCINTLVL0_bm  (1<<2)  
 #define USART_TXCINTLVL0_bp  2  /* Transmit Interrupt Level bit 0 position. */
-#define USART_TXCINTLVL1_bm  (1<<3)  /* Transmit Interrupt Level bit 1 mask. */
+/* Transmit Interrupt Level bit 1 mask. */
+#define USART_TXCINTLVL1_bm  (1<<3)  
 #define USART_TXCINTLVL1_bp  3  /* Transmit Interrupt Level bit 1 position. */
 
-#define USART_DREINTLVL_gm  0x03  /* Data Register Empty Interrupt Level group mask. */
-#define USART_DREINTLVL_gp  0  /* Data Register Empty Interrupt Level group position. */
-#define USART_DREINTLVL0_bm  (1<<0)  /* Data Register Empty Interrupt Level bit 0 mask. */
-#define USART_DREINTLVL0_bp  0  /* Data Register Empty Interrupt Level bit 0 position. */
-#define USART_DREINTLVL1_bm  (1<<1)  /* Data Register Empty Interrupt Level bit 1 mask. */
-#define USART_DREINTLVL1_bp  1  /* Data Register Empty Interrupt Level bit 1 position. */
+/* Data Register Empty Interrupt Level group mask. */
+#define USART_DREINTLVL_gm  0x03  
+/* Data Register Empty Interrupt Level group position. */
+#define USART_DREINTLVL_gp  0  
+/* Data Register Empty Interrupt Level bit 0 mask. */
+#define USART_DREINTLVL0_bm  (1<<0) 
+/* Data Register Empty Interrupt Level bit 0 position. */
+#define USART_DREINTLVL0_bp  0  
+/* Data Register Empty Interrupt Level bit 1 mask. */
+#define USART_DREINTLVL1_bm  (1<<1)  
+/* Data Register Empty Interrupt Level bit 1 position. */
+#define USART_DREINTLVL1_bp  1  
 
 
 /* USART.CTRLB  bit masks and bit positions */
@@ -6446,8 +6826,10 @@ IO Module Instances. Mapped to memory.
 #define USART_CLK2X_bm  0x04  /* Double transmission speed bit mask. */
 #define USART_CLK2X_bp  2  /* Double transmission speed bit position. */
 
-#define USART_MPCM_bm  0x02  /* Multi-processor Communication Mode bit mask. */
-#define USART_MPCM_bp  1  /* Multi-processor Communication Mode bit position. */
+/* Multi-processor Communication Mode bit mask. */
+#define USART_MPCM_bm  0x02  
+/* Multi-processor Communication Mode bit position. */
+#define USART_MPCM_bp  1  
 
 #define USART_TXB8_bm  0x01  /* Transmit bit 8 bit mask. */
 #define USART_TXB8_bp  0  /* Transmit bit 8 bit position. */
@@ -6484,22 +6866,38 @@ IO Module Instances. Mapped to memory.
 /* USART.BAUDCTRLA  bit masks and bit positions */
 #define USART_BSEL_gm  0xFF  /* Baud Rate Selection Bits [7:0] group mask. */
 #define USART_BSEL_gp  0  /* Baud Rate Selection Bits [7:0] group position. */
-#define USART_BSEL0_bm  (1<<0)  /* Baud Rate Selection Bits [7:0] bit 0 mask. */
-#define USART_BSEL0_bp  0  /* Baud Rate Selection Bits [7:0] bit 0 position. */
-#define USART_BSEL1_bm  (1<<1)  /* Baud Rate Selection Bits [7:0] bit 1 mask. */
-#define USART_BSEL1_bp  1  /* Baud Rate Selection Bits [7:0] bit 1 position. */
-#define USART_BSEL2_bm  (1<<2)  /* Baud Rate Selection Bits [7:0] bit 2 mask. */
-#define USART_BSEL2_bp  2  /* Baud Rate Selection Bits [7:0] bit 2 position. */
-#define USART_BSEL3_bm  (1<<3)  /* Baud Rate Selection Bits [7:0] bit 3 mask. */
-#define USART_BSEL3_bp  3  /* Baud Rate Selection Bits [7:0] bit 3 position. */
-#define USART_BSEL4_bm  (1<<4)  /* Baud Rate Selection Bits [7:0] bit 4 mask. */
-#define USART_BSEL4_bp  4  /* Baud Rate Selection Bits [7:0] bit 4 position. */
-#define USART_BSEL5_bm  (1<<5)  /* Baud Rate Selection Bits [7:0] bit 5 mask. */
-#define USART_BSEL5_bp  5  /* Baud Rate Selection Bits [7:0] bit 5 position. */
-#define USART_BSEL6_bm  (1<<6)  /* Baud Rate Selection Bits [7:0] bit 6 mask. */
-#define USART_BSEL6_bp  6  /* Baud Rate Selection Bits [7:0] bit 6 position. */
-#define USART_BSEL7_bm  (1<<7)  /* Baud Rate Selection Bits [7:0] bit 7 mask. */
-#define USART_BSEL7_bp  7  /* Baud Rate Selection Bits [7:0] bit 7 position. */
+/* Baud Rate Selection Bits [7:0] bit 0 mask. */
+#define USART_BSEL0_bm  (1<<0)  
+/* Baud Rate Selection Bits [7:0] bit 0 position. */
+#define USART_BSEL0_bp  0  
+/* Baud Rate Selection Bits [7:0] bit 1 mask. */
+#define USART_BSEL1_bm  (1<<1)  
+/* Baud Rate Selection Bits [7:0] bit 1 position. */
+#define USART_BSEL1_bp  1  
+/* Baud Rate Selection Bits [7:0] bit 2 mask. */
+#define USART_BSEL2_bm  (1<<2)  
+/* Baud Rate Selection Bits [7:0] bit 2 position. */
+#define USART_BSEL2_bp  2  
+/* Baud Rate Selection Bits [7:0] bit 3 mask. */
+#define USART_BSEL3_bm  (1<<3)  
+/* Baud Rate Selection Bits [7:0] bit 3 position. */
+#define USART_BSEL3_bp  3  
+/* Baud Rate Selection Bits [7:0] bit 4 mask. */
+#define USART_BSEL4_bm  (1<<4)  
+/* Baud Rate Selection Bits [7:0] bit 4 position. */
+#define USART_BSEL4_bp  4  
+/* Baud Rate Selection Bits [7:0] bit 5 mask. */
+#define USART_BSEL5_bm  (1<<5)  
+/* Baud Rate Selection Bits [7:0] bit 5 position. */
+#define USART_BSEL5_bp  5  
+/* Baud Rate Selection Bits [7:0] bit 6 mask. */
+#define USART_BSEL6_bm  (1<<6)  
+/* Baud Rate Selection Bits [7:0] bit 6 position. */
+#define USART_BSEL6_bp  6  
+/* Baud Rate Selection Bits [7:0] bit 7 mask. */
+#define USART_BSEL7_bm  (1<<7)  
+/* Baud Rate Selection Bits [7:0] bit 7 position. */
+#define USART_BSEL7_bp  7
 
 
 /* USART.BAUDCTRLB  bit masks and bit positions */
@@ -6640,14 +7038,19 @@ IO Module Instances. Mapped to memory.
 #define PIN6_bp 6
 #define PIN7_bm 0x80 
 #define PIN7_bp 7
+/** @} */
 
-
-/* ========== Interrupt Vector Definitions ========== */
+/**
+ * @name Interrupt Vector Definitions
+ * 
+ */
+/**@{**/
 /* Vector 0 is the reset vector */
 
 /* OSC interrupt vectors */
 #define OSC_XOSCF_vect_num  1
-#define OSC_XOSCF_vect      _VECTOR(1)  /* External Oscillator Failure Interrupt (NMI) */
+/* External Oscillator Failure Interrupt (NMI) */
+#define OSC_XOSCF_vect      _VECTOR(1)
 
 /* PORTC interrupt vectors */
 #define PORTC_INT0_vect_num  2
@@ -6717,7 +7120,8 @@ IO Module Instances. Mapped to memory.
 #define USARTC0_DRE_vect_num  26
 #define USARTC0_DRE_vect      _VECTOR(26)  /* Data Register Empty Interrupt */
 #define USARTC0_TXC_vect_num  27
-#define USARTC0_TXC_vect      _VECTOR(27)  /* Transmission Complete Interrupt */
+/* Transmission Complete Interrupt */
+#define USARTC0_TXC_vect      _VECTOR(27)
 
 /* USARTC1 interrupt vectors */
 #define USARTC1_RXC_vect_num  28
@@ -6725,7 +7129,8 @@ IO Module Instances. Mapped to memory.
 #define USARTC1_DRE_vect_num  29
 #define USARTC1_DRE_vect      _VECTOR(29)  /* Data Register Empty Interrupt */
 #define USARTC1_TXC_vect_num  30
-#define USARTC1_TXC_vect      _VECTOR(30)  /* Transmission Complete Interrupt */
+ /* Transmission Complete Interrupt */
+#define USARTC1_TXC_vect      _VECTOR(30)
 
 /* AES interrupt vectors */
 #define AES_INT_vect_num  31
@@ -6807,7 +7212,8 @@ IO Module Instances. Mapped to memory.
 #define USARTE0_DRE_vect_num  59
 #define USARTE0_DRE_vect      _VECTOR(59)  /* Data Register Empty Interrupt */
 #define USARTE0_TXC_vect_num  60
-#define USARTE0_TXC_vect      _VECTOR(60)  /* Transmission Complete Interrupt */
+/* Transmission Complete Interrupt */
+#define USARTE0_TXC_vect      _VECTOR(60)
 
 /* USARTE1 interrupt vectors */
 #define USARTE1_RXC_vect_num  61
@@ -6815,7 +7221,8 @@ IO Module Instances. Mapped to memory.
 #define USARTE1_DRE_vect_num  62
 #define USARTE1_DRE_vect      _VECTOR(62)  /* Data Register Empty Interrupt */
 #define USARTE1_TXC_vect_num  63
-#define USARTE1_TXC_vect      _VECTOR(63)  /* Transmission Complete Interrupt */
+/* Transmission Complete Interrupt */
+#define USARTE1_TXC_vect      _VECTOR(63)
 
 /* PORTD interrupt vectors */
 #define PORTD_INT0_vect_num  64
@@ -6887,7 +7294,8 @@ IO Module Instances. Mapped to memory.
 #define USARTD0_DRE_vect_num  89
 #define USARTD0_DRE_vect      _VECTOR(89)  /* Data Register Empty Interrupt */
 #define USARTD0_TXC_vect_num  90
-#define USARTD0_TXC_vect      _VECTOR(90)  /* Transmission Complete Interrupt */
+/* Transmission Complete Interrupt */
+#define USARTD0_TXC_vect      _VECTOR(90)
 
 /* USARTD1 interrupt vectors */
 #define USARTD1_RXC_vect_num  91
@@ -6895,7 +7303,8 @@ IO Module Instances. Mapped to memory.
 #define USARTD1_DRE_vect_num  92
 #define USARTD1_DRE_vect      _VECTOR(92)  /* Data Register Empty Interrupt */
 #define USARTD1_TXC_vect_num  93
-#define USARTD1_TXC_vect      _VECTOR(93)  /* Transmission Complete Interrupt */
+/* Transmission Complete Interrupt */
+#define USARTD1_TXC_vect      _VECTOR(93)
 
 /* PORTQ interrupt vectors */
 #define PORTQ_INT0_vect_num  94
@@ -6965,25 +7374,32 @@ IO Module Instances. Mapped to memory.
 #define USARTF0_RXC_vect_num  119
 #define USARTF0_RXC_vect      _VECTOR(119)  /* Reception Complete Interrupt */
 #define USARTF0_DRE_vect_num  120
-#define USARTF0_DRE_vect      _VECTOR(120)  /* Data Register Empty Interrupt */
+/* Data Register Empty Interrupt */
+#define USARTF0_DRE_vect      _VECTOR(120)  
 #define USARTF0_TXC_vect_num  121
-#define USARTF0_TXC_vect      _VECTOR(121)  /* Transmission Complete Interrupt */
+/* Transmission Complete Interrupt */
+#define USARTF0_TXC_vect      _VECTOR(121)
 
 /* USARTF1 interrupt vectors */
 #define USARTF1_RXC_vect_num  122
 #define USARTF1_RXC_vect      _VECTOR(122)  /* Reception Complete Interrupt */
 #define USARTF1_DRE_vect_num  123
-#define USARTF1_DRE_vect      _VECTOR(123)  /* Data Register Empty Interrupt */
+/* Data Register Empty Interrupt */
+#define USARTF1_DRE_vect      _VECTOR(123)
 #define USARTF1_TXC_vect_num  124
-#define USARTF1_TXC_vect      _VECTOR(124)  /* Transmission Complete Interrupt */
+/* Transmission Complete Interrupt */
+#define USARTF1_TXC_vect      _VECTOR(124) 
 
 
 #define _VECTOR_SIZE 4 /* Size of individual vector. */
 #define _VECTORS_SIZE (125 * _VECTOR_SIZE)
+/** @} */
 
-
-/* ========== Constants ========== */
-
+/**
+ * @name Constants
+ * 
+ */
+/**@{**/
 #define PROGMEM_START     (0x0000)
 #define PROGMEM_SIZE      (139264)
 #define PROGMEM_PAGE_SIZE (512)
@@ -6997,7 +7413,8 @@ IO Module Instances. Mapped to memory.
 #define APPTABLE_SECTION_START     (0x1E000)
 #define APPTABLE_SECTION_SIZE      (8192)
 #define APPTABLE_SECTION_PAGE_SIZE (512)
-#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + APPTABLE_SECTION_SIZE - 1)
+#define APPTABLE_SECTION_END       (APPTABLE_SECTION_START + \
+                                    APPTABLE_SECTION_SIZE - 1)
 
 #define BOOT_SECTION_START     (0x20000)
 #define BOOT_SECTION_SIZE      (8192)
@@ -7052,12 +7469,14 @@ IO Module Instances. Mapped to memory.
 #define USER_SIGNATURES_START     (0x0000)
 #define USER_SIGNATURES_SIZE      (512)
 #define USER_SIGNATURES_PAGE_SIZE (0)
-#define USER_SIGNATURES_END       (USER_SIGNATURES_START + USER_SIGNATURES_SIZE - 1)
+#define USER_SIGNATURES_END       (USER_SIGNATURES_START + \
+                                   USER_SIGNATURES_SIZE - 1)
 
 #define PROD_SIGNATURES_START     (0x0000)
 #define PROD_SIGNATURES_SIZE      (52)
 #define PROD_SIGNATURES_PAGE_SIZE (0)
-#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + PROD_SIGNATURES_SIZE - 1)
+#define PROD_SIGNATURES_END       (PROD_SIGNATURES_START + \
+                                   PROD_SIGNATURES_SIZE - 1)
 
 #define FLASHEND     PROGMEM_END
 #define SPM_PAGESIZE PROGMEM_PAGE_SIZE
@@ -7069,9 +7488,13 @@ IO Module Instances. Mapped to memory.
 #define XRAMEND      EXTERNAL_SRAM_END
 #define E2END        EEPROM_END
 #define E2PAGESIZE   EEPROM_PAGE_SIZE
+/** @} */
 
-
-/* ========== Fuses ========== */
+/**
+ * @name Fuses
+ * 
+ */
+/**@{**/
 #define FUSE_MEMORY_SIZE 6
 
 /* Fuse Byte 0 */
@@ -7090,18 +7513,27 @@ IO Module Instances. Mapped to memory.
 #define FUSE_WDP1  (unsigned char)~_BV(1)  /* Watchdog Timeout Period Bit 1 */
 #define FUSE_WDP2  (unsigned char)~_BV(2)  /* Watchdog Timeout Period Bit 2 */
 #define FUSE_WDP3  (unsigned char)~_BV(3)  /* Watchdog Timeout Period Bit 3 */
-#define FUSE_WDWP0  (unsigned char)~_BV(4)  /* Watchdog Window Timeout Period Bit 0 */
-#define FUSE_WDWP1  (unsigned char)~_BV(5)  /* Watchdog Window Timeout Period Bit 1 */
-#define FUSE_WDWP2  (unsigned char)~_BV(6)  /* Watchdog Window Timeout Period Bit 2 */
-#define FUSE_WDWP3  (unsigned char)~_BV(7)  /* Watchdog Window Timeout Period Bit 3 */
+/* Watchdog Window Timeout Period Bit 0 */
+#define FUSE_WDWP0  (unsigned char)~_BV(4)
+/* Watchdog Window Timeout Period Bit 1 */
+#define FUSE_WDWP1  (unsigned char)~_BV(5)
+/* Watchdog Window Timeout Period Bit 2 */
+#define FUSE_WDWP2  (unsigned char)~_BV(6)
+/* Watchdog Window Timeout Period Bit 3 */
+#define FUSE_WDWP3  (unsigned char)~_BV(7)
 #define FUSE1_DEFAULT  (0xFF)
 
 /* Fuse Byte 2 */
-#define FUSE_BODPD0  (unsigned char)~_BV(0)  /* BOD Operation in Power-Down Mode Bit 0 */
-#define FUSE_BODPD1  (unsigned char)~_BV(1)  /* BOD Operation in Power-Down Mode Bit 1 */
-#define FUSE_BODACT0  (unsigned char)~_BV(2)  /* BOD Operation in Active Mode Bit 0 */
-#define FUSE_BODACT1  (unsigned char)~_BV(3)  /* BOD Operation in Active Mode Bit 1 */
-#define FUSE_BOOTRST  (unsigned char)~_BV(6)  /* Boot Loader Section Reset Vector */
+/* BOD Operation in Power-Down Mode Bit 0 */
+#define FUSE_BODPD0  (unsigned char)~_BV(0)
+/* BOD Operation in Power-Down Mode Bit 1 */
+#define FUSE_BODPD1  (unsigned char)~_BV(1)
+/* BOD Operation in Active Mode Bit 0 */
+#define FUSE_BODACT0  (unsigned char)~_BV(2)
+/* BOD Operation in Active Mode Bit 1 */
+#define FUSE_BODACT1  (unsigned char)~_BV(3)
+/* Boot Loader Section Reset Vector */
+#define FUSE_BOOTRST  (unsigned char)~_BV(6)
 #define FUSE_DVSDON  (unsigned char)~_BV(7)  /* Spike Detector Enable */
 #define FUSE2_DEFAULT  (0xFF)
 
@@ -7115,25 +7547,37 @@ IO Module Instances. Mapped to memory.
 #define FUSE4_DEFAULT  (0xFF)
 
 /* Fuse Byte 5 */
-#define FUSE_BODLVL0  (unsigned char)~_BV(0)  /* Brown Out Detection Voltage Level Bit 0 */
-#define FUSE_BODLVL1  (unsigned char)~_BV(1)  /* Brown Out Detection Voltage Level Bit 1 */
-#define FUSE_BODLVL2  (unsigned char)~_BV(2)  /* Brown Out Detection Voltage Level Bit 2 */
-#define FUSE_EESAVE  (unsigned char)~_BV(3)  /* Preserve EEPROM Through Chip Erase */
+/* Brown Out Detection Voltage Level Bit 0 */
+#define FUSE_BODLVL0  (unsigned char)~_BV(0)
+/* Brown Out Detection Voltage Level Bit 1 */
+#define FUSE_BODLVL1  (unsigned char)~_BV(1)
+/* Brown Out Detection Voltage Level Bit 2 */
+#define FUSE_BODLVL2  (unsigned char)~_BV(2)
+/* Preserve EEPROM Through Chip Erase */
+#define FUSE_EESAVE  (unsigned char)~_BV(3)
 #define FUSE5_DEFAULT  (0xFF)
+/** @} */
 
-
-/* ========== Lock Bits ========== */
+/**
+ * @name Lock Bits
+ * 
+ */
+/**@{**/
 #define __LOCK_BITS_EXIST
 #define __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST
 #define __BOOT_LOCK_APPLICATION_BITS_EXIST
 #define __BOOT_LOCK_BOOT_BITS_EXIST
+/** @} */
 
-
-/* ========== Signature ========== */
+/**
+ * @name Signature
+ * 
+ */
+/**@{**/
 #define SIGNATURE_0 0x1E
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x4C
-
+/** @} */
 
 #endif /* _AVR_ATxmega128A1_H_ */
 
diff --git a/cpukit/score/cpu/avr/avr/iox128a3.h b/cpukit/score/cpu/avr/avr/iox128a3.h
index 9ec0cd8cc2..e5edf62944 100644
--- a/cpukit/score/cpu/avr/avr/iox128a3.h
+++ b/cpukit/score/cpu/avr/avr/iox128a3.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox128a3.h
+ *
+ * @brief Definitions for ATxmega128A3
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox128a3.h - definitions for ATxmega128A3 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iox128a3.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega128A3_H_
 #define _AVR_ATxmega128A3_H_ 1
 
+/**
+ *  @defgroup Avr_iox128a3 ATxmega128A3 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Ungrouped common registers */
 #define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -6437,21 +6448,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -6885,5 +6896,5 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_2 0x42
 
 
+/**@}*/
 #endif /* _AVR_ATxmega128A3_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox16a4.h b/cpukit/score/cpu/avr/avr/iox16a4.h
index 1fcaab401f..cff1d53360 100644
--- a/cpukit/score/cpu/avr/avr/iox16a4.h
+++ b/cpukit/score/cpu/avr/avr/iox16a4.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox16a4.h
+ *
+ * @brief Definitions for ATxmega16A4
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox16a4.h - definitions for ATxmega16A4 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,8 +46,14 @@
 #  define _AVR_IOXXX_H_ "iox16a4.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
+/**
+ *  @defgroup Avr_iox16a4 ATxmega16A4 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_ATxmega16A4_H_
 #define _AVR_ATxmega16A4_H_ 1
@@ -6251,21 +6262,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -6640,5 +6651,5 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_2 0x41
 
 
+/**@}*/
 #endif /* _AVR_ATxmega16A4_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox16d4.h b/cpukit/score/cpu/avr/avr/iox16d4.h
index dac0bbad29..0bb088759c 100644
--- a/cpukit/score/cpu/avr/avr/iox16d4.h
+++ b/cpukit/score/cpu/avr/avr/iox16d4.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox16d4.h
+ *
+ * @brief Definitions for ATxmega16D4
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox16d4.h - definitions for ATxmega16D4 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ *   Copyright (c) 2009 Atmel Corporation
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iox16d4.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega16D4_H_
 #define _AVR_ATxmega16D4_H_ 1
 
+/**
+ *  @defgroup Avr_iox16d4 ATxmega16D4 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Ungrouped common registers */
 #define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -5218,21 +5229,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -5537,5 +5548,5 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_2 0x42
 
 
+/**@}*/
 #endif /* _AVR_ATxmega16D4_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox192a3.h b/cpukit/score/cpu/avr/avr/iox192a3.h
index 9da95a119c..e0f7c26ab2 100644
--- a/cpukit/score/cpu/avr/avr/iox192a3.h
+++ b/cpukit/score/cpu/avr/avr/iox192a3.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox192a3.h
+ *
+ * @brief Definitions for ATxmega192A3
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox192a3.h - definitions for ATxmega192A3 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ *   Copyright (c) 2009 Atmel Corporation
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iox192a3.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega192A3_H_
 #define _AVR_ATxmega192A3_H_ 1
 
+/**
+ *  @defgroup Avr_iox192a3 ATxmega192A3 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Ungrouped common registers */
 #define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -6437,21 +6448,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -6885,5 +6896,5 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_2 0x44
 
 
+/**@}*/
 #endif /* _AVR_ATxmega192A3_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox192d3.h b/cpukit/score/cpu/avr/avr/iox192d3.h
index f36fc58f9f..e29356e3cf 100644
--- a/cpukit/score/cpu/avr/avr/iox192d3.h
+++ b/cpukit/score/cpu/avr/avr/iox192d3.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox192d3.h
+ *
+ * @brief Definitions for ATxmega192D3
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox192d3.h - definitions for ATxmega192D3 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ *  Copyright (c) 2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iox192d3.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega192D3_H_
 #define _AVR_ATxmega192D3_H_ 1
 
+/**
+ *  @defgroup Avr_iox192d3 ATxmega192D3 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Ungrouped common registers */
 #define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -5294,21 +5305,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -5640,6 +5651,5 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_1 0x97
 #define SIGNATURE_2 0x49
 
-
+/**@}*/
 #endif /* _AVR_ATxmega192D3_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox256a3b.h b/cpukit/score/cpu/avr/avr/iox256a3b.h
index 69e29f6bee..deee492cca 100644
--- a/cpukit/score/cpu/avr/avr/iox256a3b.h
+++ b/cpukit/score/cpu/avr/avr/iox256a3b.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox256a3b.h
+ *
+ * @brief Definitions for ATxmega256A3B
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox256a3b.h - definitions for ATxmega256A3B */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iox256a3b.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega256A3B_H_
 #define _AVR_ATxmega256A3B_H_ 1
 
+/**
+ *  @defgroup Avr_iox256a3b ATxmega256A3B Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Ungrouped common registers */
 #define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -6451,21 +6462,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -6887,5 +6898,5 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_2 0x43
 
 
+/**@}*/
 #endif /* _AVR_ATxmega256A3B_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox256d3.h b/cpukit/score/cpu/avr/avr/iox256d3.h
index 83d242f865..a49879811d 100644
--- a/cpukit/score/cpu/avr/avr/iox256d3.h
+++ b/cpukit/score/cpu/avr/avr/iox256d3.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox256d3.h
+ *
+ * @brief Definitions for ATxmega256D3
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox256d3.h - definitions for ATxmega256D3 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *
+ *   * Neither the name of the copyright holders nor the names of
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,19 @@
 #  define _AVR_IOXXX_H_ "iox256d3.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega256D3_H_
 #define _AVR_ATxmega256D3_H_ 1
 
+/**
+ * @defgroup AvrDef_iox256d3 ATxmega256D3 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
 
 /* Ungrouped common registers */
 #define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -5103,21 +5115,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -5451,5 +5463,6 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_2 0x44
 
 
+/** @} */
 #endif /* _AVR_ATxmega256D3_H_ */
 
diff --git a/cpukit/score/cpu/avr/avr/iox32a4.h b/cpukit/score/cpu/avr/avr/iox32a4.h
index 7cbf7de2e7..f0eba4ecc0 100644
--- a/cpukit/score/cpu/avr/avr/iox32a4.h
+++ b/cpukit/score/cpu/avr/avr/iox32a4.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox32a4.h
+ *
+ * @brief Definitions for ATxmega32A4
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox32a4.h - definitions for ATxmega32A4 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ *   Copyright (c) 2009 Atmel Corporation
+ *   All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iox32a4.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega32A4_H_
 #define _AVR_ATxmega32A4_H_ 1
 
+/**
+ *  @defgroup Avr_iox32a4 ATxmega32A4 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Ungrouped common registers */
 #define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -6251,21 +6262,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -6640,5 +6651,5 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_2 0x41
 
 
+/**@}*/
 #endif /* _AVR_ATxmega32A4_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox32d4.h b/cpukit/score/cpu/avr/avr/iox32d4.h
index 7f7d710704..248e32cadf 100644
--- a/cpukit/score/cpu/avr/avr/iox32d4.h
+++ b/cpukit/score/cpu/avr/avr/iox32d4.h
@@ -1,6 +1,13 @@
+/**
+ * @file
+ *
+ * @brief Definitions for ATxmega32D4
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
+
 /* Copyright (c) 2009 Atmel Corporation
    All rights reserved.
-
    Redistribution and use in source and binary forms, with or without
    modification, are permitted provided that the following conditions are met:
 
@@ -47,6 +54,14 @@
 #ifndef _AVR_ATxmega32D4_H_
 #define _AVR_ATxmega32D4_H_ 1
 
+/**
+ * @defgroup AvrDef_iox32d4 ATxmega32D4 Definitions
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 
 /* Ungrouped common registers */
 #define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -5539,6 +5554,7 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_1 0x95
 #define SIGNATURE_2 0x42
 
+/** @} */
 
 #endif /* _AVR_ATxmega32D4_H_ */
 
diff --git a/cpukit/score/cpu/avr/avr/iox64a1.h b/cpukit/score/cpu/avr/avr/iox64a1.h
index ba9d4c1a8d..73acf1afdc 100644
--- a/cpukit/score/cpu/avr/avr/iox64a1.h
+++ b/cpukit/score/cpu/avr/avr/iox64a1.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox64a1.h
+ *
+ * @brief Definitions for ATxmega64A1
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox64a1.h - definitions for ATxmega64A1 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ * Copyright (c) 2009 Atmel Corporation
+ * All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ *
+ *  * Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ *
+ *  * Neither the name of the copyright holders nor the names of
+ *    contributors may be used to endorse or promote products derived
+ *    from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iox64a1.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega64A1_H_
 #define _AVR_ATxmega64A1_H_ 1
 
+/**
+ *  @defgroup Avr_iox64a1 ATxmega64A1 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Ungrouped common registers */
 #define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -6624,21 +6635,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -7135,5 +7146,5 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_2 0x4E
 
 
+/**@}*/
 #endif /* _AVR_ATxmega64A1_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox64a3.h b/cpukit/score/cpu/avr/avr/iox64a3.h
index 7abb12a732..a3a73a44e9 100644
--- a/cpukit/score/cpu/avr/avr/iox64a3.h
+++ b/cpukit/score/cpu/avr/avr/iox64a3.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox64a3.h
+ *
+ * @brief Definitions for ATxmega64A3
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox64a3.h - definitions for ATxmega64A3 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ *  Copyright (c) 2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iox64a3.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega64A3_H_
 #define _AVR_ATxmega64A3_H_ 1
 
+/**
+ *  @defgroup Avr_iox64a3 ATxmega64A3 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Ungrouped common registers */
 #define GPIO0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -6437,21 +6448,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -6884,6 +6895,5 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x42
 
-
+/**@}*/
 #endif /* _AVR_ATxmega64A3_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/iox64d3.h b/cpukit/score/cpu/avr/avr/iox64d3.h
index b4954f49dc..5a0bdb5584 100644
--- a/cpukit/score/cpu/avr/avr/iox64d3.h
+++ b/cpukit/score/cpu/avr/avr/iox64d3.h
@@ -1,37 +1,42 @@
-/* Copyright (c) 2009 Atmel Corporation
-   All rights reserved.
+/**
+ * @file avr/iox64d3.h
+ *
+ * @brief Definitions for ATxmega64D3
+ *
+ * This file should only be included from <avr/io.h>, never directly.
+ */
 
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/iox64d3.h - definitions for ATxmega64D3 */
-
-/* This file should only be included from <avr/io.h>, never directly. */
+/*
+ *  Copyright (c) 2009 Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_IO_H_
 #  error "Include <avr/io.h> instead of this file."
@@ -41,12 +46,18 @@
 #  define _AVR_IOXXX_H_ "iox64d3.h"
 #else
 #  error "Attempt to include more than one <avr/ioXXX.h> file."
-#endif 
+#endif
 
 
 #ifndef _AVR_ATxmega64D3_H_
 #define _AVR_ATxmega64D3_H_ 1
 
+/**
+ *  @defgroup Avr_iox64d3 ATxmega64D3 Definitions
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 /* Ungrouped common registers */
 #define GPIOR0  _SFR_MEM8(0x0000)  /* General Purpose IO Register 0 */
@@ -5308,21 +5319,21 @@ IO Module Instances. Mapped to memory.
 
 // Generic Port Pins
 
-#define PIN0_bm 0x01 
+#define PIN0_bm 0x01
 #define PIN0_bp 0
 #define PIN1_bm 0x02
 #define PIN1_bp 1
-#define PIN2_bm 0x04 
+#define PIN2_bm 0x04
 #define PIN2_bp 2
-#define PIN3_bm 0x08 
+#define PIN3_bm 0x08
 #define PIN3_bp 3
-#define PIN4_bm 0x10 
+#define PIN4_bm 0x10
 #define PIN4_bp 4
-#define PIN5_bm 0x20 
+#define PIN5_bm 0x20
 #define PIN5_bp 5
-#define PIN6_bm 0x40 
+#define PIN6_bm 0x40
 #define PIN6_bp 6
-#define PIN7_bm 0x80 
+#define PIN7_bm 0x80
 #define PIN7_bp 7
 
 
@@ -5654,6 +5665,5 @@ IO Module Instances. Mapped to memory.
 #define SIGNATURE_1 0x96
 #define SIGNATURE_2 0x4A
 
-
+/**@}*/
 #endif /* _AVR_ATxmega64D3_H_ */
-
diff --git a/cpukit/score/cpu/avr/avr/lock.h b/cpukit/score/cpu/avr/avr/lock.h
index 5ffb769513..182f0f4cd8 100644
--- a/cpukit/score/cpu/avr/avr/lock.h
+++ b/cpukit/score/cpu/avr/avr/lock.h
@@ -1,187 +1,191 @@
-/* Copyright (c) 2007, Atmel Corporation
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/* avr/lock.h - Lock Bits API */
+/**
+ * @file avr/lock.h
+ *
+ * @brief Lock Bits API
+ *  \par Introduction
+ *
+ *  The Lockbit API allows a user to specify the lockbit settings for the
+ *  specific AVR device they are compiling for. These lockbit settings will be
+ *  placed in a special section in the ELF output file, after linking.
+ *
+ *  Programming tools can take advantage of the lockbit information embedded in
+ *  the ELF file, by extracting this information and determining if the lockbits
+ *  need to be programmed after programming the Flash and EEPROM memories.
+ *  This also allows a single ELF file to contain all the
+ *  information needed to program an AVR.
+ *
+ *  To use the Lockbit API, include the <avr/io.h> header file, which in turn
+ *  automatically includes the individual I/O header file and the <avr/lock.h>
+ *  file. These other two files provides everything necessary to set the AVR
+ *  lockbits.
+ *
+ *  \par Lockbit API
+ *
+ *  Each I/O header file may define up to 3 macros that controls what kinds
+ *  of lockbits are available to the user.
+ *
+ *  If __LOCK_BITS_EXIST is defined, then two lock bits are available to the
+ *  user and 3 mode settings are defined for these two bits.
+ *
+ *  If __BOOT_LOCK_BITS_0_EXIST is defined, then the two BLB0 lock bits are
+ *  available to the user and 4 mode settings are defined for these two bits.
+ *
+ *  If __BOOT_LOCK_BITS_1_EXIST is defined, then the two BLB1 lock bits are
+ *  available to the user and 4 mode settings are defined for these two bits.
+ *
+ *  If __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST is defined then two lock bits
+ *  are available to set the locking mode for the Application Table Section
+ *  (which is used in the XMEGA family).
+ *
+ *  If __BOOT_LOCK_APPLICATION_BITS_EXIST is defined then two lock bits are
+ *  available to set the locking mode for the Application Section (which is used
+ *  in the XMEGA family).
+ *
+ *  If __BOOT_LOCK_BOOT_BITS_EXIST is defined then two lock bits are available
+ *  to set the locking mode for the Boot Loader Section (which is used in the
+ *  XMEGA family).
+ *
+ *  The AVR lockbit modes have inverted values, logical 1 for an unprogrammed
+ *  (disabled) bit and logical 0 for a programmed (enabled) bit. The defined
+ *  macros for each individual lock bit represent this in their definition by a
+ *  bit-wise inversion of a mask. For example, the LB_MODE_3 macro is defined
+ *  as:
+ *  \code
+ *  #define LB_MODE_3  (0xFC)
+ *  \endcode
+ *
+ *  To combine the lockbit mode macros together to represent a whole byte,
+ *  use the bitwise AND operator, like so:
+ *  \code
+ *  (LB_MODE_3 & BLB0_MODE_2)
+ *  \endcode
+ *
+ *  <avr/lock.h> also defines a macro that provides a default lockbit value:
+ *  LOCKBITS_DEFAULT which is defined to be 0xFF.
+ *
+ *  See the AVR device specific datasheet for more details about these
+ *  lock bits and the available mode settings.
+ *
+ *  A convenience macro, LOCKMEM, is defined as a GCC attribute for a
+ *  custom-named section of ".lock".
+ *
+ *  A convenience macro, LOCKBITS, is defined that declares a variable, __lock,
+ *  of type unsigned char with the attribute defined by LOCKMEM. This variable
+ *  allows the end user to easily set the lockbit data.
+ *
+ *  \note If a device-specific I/O header file has previously defined LOCKMEM,
+ *  then LOCKMEM is not redefined. If a device-specific I/O header file has
+ *  previously defined LOCKBITS, then LOCKBITS is not redefined. LOCKBITS is
+ *  currently known to be defined in the I/O header files for the XMEGA devices.
+ *
+ *  \par API Usage Example
+ *
+ *  Putting all of this together is easy:
+ *
+ *  \code
+ *  #include <avr/io.h>
+ *
+ *  LOCKBITS = (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4);
+ *
+ *  int main(void)
+ *  {
+ *      return 0;
+ *  }
+ *  \endcode
+ *
+ *  Or:
+ *
+ *  \code
+ *  #include <avr/io.h>
+ *
+ *  unsigned char __lock __attribute__((section (".lock"))) =
+ *      (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4);
+ *
+ *  int main(void)
+ *  {
+ *      return 0;
+ *  }
+ *  \endcode
+ *
+ *
+ *
+ *  However there are a number of caveats that you need to be aware of to
+ *  use this API properly.
+ *
+ *  Be sure to include <avr/io.h> to get all of the definitions for the API.
+ *  The LOCKBITS macro defines a global variable to store the lockbit data. This
+ *  variable is assigned to its own linker section. Assign the desired lockbit
+ *  values immediately in the variable initialization.
+ *
+ *  The .lock section in the ELF file will get its values from the initial
+ *  variable assignment ONLY. This means that you can NOT assign values to
+ *  this variable in functions and the new values will not be put into the
+ *  ELF .lock section.
+ *
+ *  The global variable is declared in the LOCKBITS macro has two leading
+ *  underscores, which means that it is reserved for the "implementation",
+ *  meaning the library, so it will not conflict with a user-named variable.
+ *
+ *  You must initialize the lockbit variable to some meaningful value, even
+ *  if it is the default value. This is because the lockbits default to a
+ *  logical 1, meaning unprogrammed. Normal uninitialized data defaults to all
+ *  locgial zeros. So it is vital that all lockbits are initialized, even with
+ *  default data. If they are not, then the lockbits may not programmed to the
+ *  desired settings and can possibly put your device into an unrecoverable
+ *  state.
+ *
+ *  Be sure to have the -mmcu=<em>device</em> flag in your compile command line and
+ *  your linker command line to have the correct device selected and to have
+ *  the correct I/O header file included when you include <avr/io.h>.
+ *
+ *  You can print out the contents of the .lock section in the ELF file by
+ *  using this command line:
+ *  \code
+ *  avr-objdump -s -j .lock <ELF file>
+ *  \endcode
+ */
+
+/*
+ *  Copyright (c) 2007, Atmel Corporation
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _AVR_LOCK_H_
 #define _AVR_LOCK_H_  1
 
-
-/** \file */
-/** \defgroup avr_lock <avr/lock.h>: Lockbit Support
-
-    \par Introduction
-
-    The Lockbit API allows a user to specify the lockbit settings for the 
-    specific AVR device they are compiling for. These lockbit settings will be 
-    placed in a special section in the ELF output file, after linking.
-
-    Programming tools can take advantage of the lockbit information embedded in
-    the ELF file, by extracting this information and determining if the lockbits
-    need to be programmed after programming the Flash and EEPROM memories.
-    This also allows a single ELF file to contain all the
-    information needed to program an AVR. 
-
-    To use the Lockbit API, include the <avr/io.h> header file, which in turn
-    automatically includes the individual I/O header file and the <avr/lock.h>
-    file. These other two files provides everything necessary to set the AVR
-    lockbits.
-    
-    \par Lockbit API
-    
-    Each I/O header file may define up to 3 macros that controls what kinds
-    of lockbits are available to the user.
-    
-    If __LOCK_BITS_EXIST is defined, then two lock bits are available to the
-    user and 3 mode settings are defined for these two bits.
-    
-    If __BOOT_LOCK_BITS_0_EXIST is defined, then the two BLB0 lock bits are
-    available to the user and 4 mode settings are defined for these two bits.
-    
-    If __BOOT_LOCK_BITS_1_EXIST is defined, then the two BLB1 lock bits are
-    available to the user and 4 mode settings are defined for these two bits.
-
-    If __BOOT_LOCK_APPLICATION_TABLE_BITS_EXIST is defined then two lock bits
-    are available to set the locking mode for the Application Table Section 
-    (which is used in the XMEGA family).
-    
-    If __BOOT_LOCK_APPLICATION_BITS_EXIST is defined then two lock bits are
-    available to set the locking mode for the Application Section (which is used
-    in the XMEGA family).
-    
-    If __BOOT_LOCK_BOOT_BITS_EXIST is defined then two lock bits are available
-    to set the locking mode for the Boot Loader Section (which is used in the
-    XMEGA family).
-
-    The AVR lockbit modes have inverted values, logical 1 for an unprogrammed 
-    (disabled) bit and logical 0 for a programmed (enabled) bit. The defined 
-    macros for each individual lock bit represent this in their definition by a 
-    bit-wise inversion of a mask. For example, the LB_MODE_3 macro is defined 
-    as:
-    \code
-    #define LB_MODE_3  (0xFC)
-`   \endcode
-    
-    To combine the lockbit mode macros together to represent a whole byte,
-    use the bitwise AND operator, like so:
-    \code
-    (LB_MODE_3 & BLB0_MODE_2)
-    \endcode
-    
-    <avr/lock.h> also defines a macro that provides a default lockbit value:
-    LOCKBITS_DEFAULT which is defined to be 0xFF.
-
-    See the AVR device specific datasheet for more details about these
-    lock bits and the available mode settings.
-    
-    A convenience macro, LOCKMEM, is defined as a GCC attribute for a 
-    custom-named section of ".lock".
-    
-    A convenience macro, LOCKBITS, is defined that declares a variable, __lock, 
-    of type unsigned char with the attribute defined by LOCKMEM. This variable
-    allows the end user to easily set the lockbit data.
-
-    \note If a device-specific I/O header file has previously defined LOCKMEM,
-    then LOCKMEM is not redefined. If a device-specific I/O header file has
-    previously defined LOCKBITS, then LOCKBITS is not redefined. LOCKBITS is
-    currently known to be defined in the I/O header files for the XMEGA devices.
-
-    \par API Usage Example
-    
-    Putting all of this together is easy:
-    
-    \code
-    #include <avr/io.h>
-
-    LOCKBITS = (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4);
-
-    int main(void)
-    {
-        return 0;
-    }
-    \endcode
-    
-    Or:
-    
-    \code
-    #include <avr/io.h>
-
-    unsigned char __lock __attribute__((section (".lock"))) = 
-        (LB_MODE_1 & BLB0_MODE_3 & BLB1_MODE_4);
-
-    int main(void)
-    {
-        return 0;
-    }
-    \endcode
-    
-    
-    
-    However there are a number of caveats that you need to be aware of to
-    use this API properly.
-    
-    Be sure to include <avr/io.h> to get all of the definitions for the API.
-    The LOCKBITS macro defines a global variable to store the lockbit data. This 
-    variable is assigned to its own linker section. Assign the desired lockbit 
-    values immediately in the variable initialization.
-    
-    The .lock section in the ELF file will get its values from the initial 
-    variable assignment ONLY. This means that you can NOT assign values to 
-    this variable in functions and the new values will not be put into the
-    ELF .lock section.
-    
-    The global variable is declared in the LOCKBITS macro has two leading 
-    underscores, which means that it is reserved for the "implementation",
-    meaning the library, so it will not conflict with a user-named variable.
-    
-    You must initialize the lockbit variable to some meaningful value, even
-    if it is the default value. This is because the lockbits default to a 
-    logical 1, meaning unprogrammed. Normal uninitialized data defaults to all 
-    locgial zeros. So it is vital that all lockbits are initialized, even with 
-    default data. If they are not, then the lockbits may not programmed to the 
-    desired settings and can possibly put your device into an unrecoverable 
-    state.
-    
-    Be sure to have the -mmcu=<em>device</em> flag in your compile command line and
-    your linker command line to have the correct device selected and to have 
-    the correct I/O header file included when you include <avr/io.h>.
-
-    You can print out the contents of the .lock section in the ELF file by
-    using this command line:
-    \code
-    avr-objdump -s -j .lock <ELF file>
-    \endcode
-
-*/
-
+/**
+ *  @defgroup avr_lock Lockbit Support
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef __ASSEMBLER__
 
@@ -235,4 +239,5 @@
 
 #define LOCKBITS_DEFAULT (0xFF)
 
+/**@}*/
 #endif /* _AVR_LOCK_H_ */
diff --git a/cpukit/score/cpu/avr/avr/parity.h b/cpukit/score/cpu/avr/avr/parity.h
index 06fd41db96..e01148e7dd 100644
--- a/cpukit/score/cpu/avr/avr/parity.h
+++ b/cpukit/score/cpu/avr/avr/parity.h
@@ -1,38 +1,55 @@
-/* Copyright (c) 2005 Joerg Wunsch
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
+/**
+ * @file
+ *
+ * @brief Koved to <util/parity.h>
+ */
+
+/*
+ * Copyright (c) 2005 Joerg Wunsch
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 
 #ifndef _AVR_PARITY_H_
 #define _AVR_PARITY_H_
 
+/**
+ * @defgroup AvrParity Parity
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 #warning "This file has been moved to <util/parity.h>."
 #include <util/parity.h>
 
+/** @} */
 #endif /* _AVR_PARITY_H_ */
diff --git a/cpukit/score/cpu/avr/avr/pgmspace.h b/cpukit/score/cpu/avr/avr/pgmspace.h
index 4036f68275..42010168b1 100644
--- a/cpukit/score/cpu/avr/avr/pgmspace.h
+++ b/cpukit/score/cpu/avr/avr/pgmspace.h
@@ -1,80 +1,85 @@
-/* Copyright (c) 2002 - 2007  Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
+/**
+ * @file pgmspace.h
+ *
+ * @brief Definitions for ATmega640
+ *
+ *  The functions in this module provide interfaces for a program to access
+ *  data stored in program space (flash memory) of the device.  In order to
+ *  use these functions, the target device must support either the \c LPM or
+ *  \c ELPM instructions.
+ *
+ *  @note These functions are an attempt to provide some compatibility with
+ *  header files that come with IAR C, to make porting applications between
+ *  different compilers easier.  This is not 100% compatibility though (GCC
+ *  does not have full support for multiple address spaces yet).
+ *
+ *  @note If you are working with strings which are completely based in ram,
+ *   use the standard string functions described in \ref avr_string.
+ *
+ *  \note If possible, put your constant tables in the lower 64 KB and use
+ *  pgm_read_byte_near() or pgm_read_word_near() instead of
+ *  pgm_read_byte_far() or pgm_read_word_far() since it is more efficient that
+ *  way, and you can still use the upper 64K for executable code.
+ *  All functions that are suffixed with a \c _P \e require their
+ *  arguments to be in the lower 64 KB of the flash ROM, as they do
+ *  not use ELPM instructions.  This is normally not a big concern as
+ *  the linker setup arranges any program space constants declared
+ *  using the macros from this header file so they are placed right after
+ *  the interrupt vectors, and in front of any executable code.  However,
+ *  it can become a problem if there are too many of these constants, or
+ *  for bootloaders on devices with more than 64 KB of ROM.
+ *  <em>All these functions will not work in that situation.</em>
+ *
+ * Contributors:
+ *   Created by Marek Michalkiewicz <marekm@linux.org.pl>
+ *   Eric B. Weddington <eric@ecentral.com>
+ *   Wolfgang Haidinger <wh@vmars.tuwien.ac.at> (pgm_read_dword())
+ *   Ivanov Anton <anton@arc.com.ru> (pgm_read_float())
+ */
 
 /*
-   pgmspace.h
-
-   Contributors:
-     Created by Marek Michalkiewicz <marekm@linux.org.pl>
-     Eric B. Weddington <eric@ecentral.com>
-     Wolfgang Haidinger <wh@vmars.tuwien.ac.at> (pgm_read_dword())
-     Ivanov Anton <anton@arc.com.ru> (pgm_read_float())
+ * Copyright (c) 2002 - 2007  Marek Michalkiewicz
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *  * Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *   * Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in
+ *     the documentation and/or other materials provided with the
+ *     distribution.
+ *
+ *   * Neither the name of the copyright holders nor the names of
+ *     contributors may be used to endorse or promote products derived
+ *     from this software without specific prior written permission.
+ *
+ *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *  POSSIBILITY OF SUCH DAMAGE.
  */
 
-/** \file */
-/** \defgroup avr_pgmspace <avr/pgmspace.h>: Program Space Utilities
-    \code
-    #include <avr/io.h>
-    #include <avr/pgmspace.h>
-    \endcode
-
-    The functions in this module provide interfaces for a program to access
-    data stored in program space (flash memory) of the device.  In order to
-    use these functions, the target device must support either the \c LPM or
-    \c ELPM instructions.
-
-    \note These functions are an attempt to provide some compatibility with
-    header files that come with IAR C, to make porting applications between
-    different compilers easier.  This is not 100% compatibility though (GCC
-    does not have full support for multiple address spaces yet).
-
-    \note If you are working with strings which are completely based in ram,
-    use the standard string functions described in \ref avr_string.
-
-    \note If possible, put your constant tables in the lower 64 KB and use
-    pgm_read_byte_near() or pgm_read_word_near() instead of
-    pgm_read_byte_far() or pgm_read_word_far() since it is more efficient that
-    way, and you can still use the upper 64K for executable code.
-    All functions that are suffixed with a \c _P \e require their
-    arguments to be in the lower 64 KB of the flash ROM, as they do
-    not use ELPM instructions.  This is normally not a big concern as
-    the linker setup arranges any program space constants declared
-    using the macros from this header file so they are placed right after
-    the interrupt vectors, and in front of any executable code.  However,
-    it can become a problem if there are too many of these constants, or
-    for bootloaders on devices with more than 64 KB of ROM.
-    <em>All these functions will not work in that situation.</em>
-*/
-
 #ifndef __PGMSPACE_H_
 #define __PGMSPACE_H_ 1
 
+/**
+ * @defgroup avr_pgmspace Program Space Utilities
+ *
+ * @ingroup avr
+ *
+ */
+/**@{**/
+
 #define __need_size_t
 #include <inttypes.h>
 #include <stddef.h>
@@ -402,7 +407,7 @@ typedef uint64_t  prog_uint64_t PROGMEM;
 
 /** \ingroup avr_pgmspace
     \def pgm_read_byte_near(address_short)
-    Read a byte from the program space with a 16-bit (near) address. 
+    Read a byte from the program space with a 16-bit (near) address.
     \note The address is a byte address.
     The address is in the program space. */
 
@@ -410,16 +415,16 @@ typedef uint64_t  prog_uint64_t PROGMEM;
 
 /** \ingroup avr_pgmspace
     \def pgm_read_word_near(address_short)
-    Read a word from the program space with a 16-bit (near) address. 
-    \note The address is a byte address. 
+    Read a word from the program space with a 16-bit (near) address.
+    \note The address is a byte address.
     The address is in the program space. */
 
 #define pgm_read_word_near(address_short) __LPM_word((uint16_t)(address_short))
 
 /** \ingroup avr_pgmspace
     \def pgm_read_dword_near(address_short)
-    Read a double word from the program space with a 16-bit (near) address. 
-    \note The address is a byte address. 
+    Read a double word from the program space with a 16-bit (near) address.
+    \note The address is a byte address.
     The address is in the program space. */
 
 #define pgm_read_dword_near(address_short) \
@@ -427,8 +432,8 @@ typedef uint64_t  prog_uint64_t PROGMEM;
 
 /** \ingroup avr_pgmspace
     \def pgm_read_float_near(address_short)
-    Read a float from the program space with a 16-bit (near) address. 
-    \note The address is a byte address. 
+    Read a float from the program space with a 16-bit (near) address.
+    \note The address is a byte address.
     The address is in the program space. */
 
 #define pgm_read_float_near(address_short) \
@@ -718,10 +723,10 @@ typedef uint64_t  prog_uint64_t PROGMEM;
     __result;                             \
 }))
 
-/* 
-Check for architectures that implement RAMPD (avrxmega3, avrxmega5, 
+/*
+Check for architectures that implement RAMPD (avrxmega3, avrxmega5,
 avrxmega7) as they need to save/restore RAMPZ for ELPM macros so it does
-not interfere with data accesses. 
+not interfere with data accesses.
 */
 #if defined (__AVR_HAVE_RAMPD__)
 
@@ -753,16 +758,16 @@ not interfere with data accesses.
 
 /** \ingroup avr_pgmspace
     \def pgm_read_byte_far(address_long)
-    Read a byte from the program space with a 32-bit (far) address. 
+    Read a byte from the program space with a 32-bit (far) address.
 
-    \note The address is a byte address. 
+    \note The address is a byte address.
     The address is in the program space. */
 
 #define pgm_read_byte_far(address_long)  __ELPM((uint32_t)(address_long))
 
 /** \ingroup avr_pgmspace
     \def pgm_read_word_far(address_long)
-    Read a word from the program space with a 32-bit (far) address. 
+    Read a word from the program space with a 32-bit (far) address.
 
     \note The address is a byte address.
     The address is in the program space. */
@@ -771,7 +776,7 @@ not interfere with data accesses.
 
 /** \ingroup avr_pgmspace
     \def pgm_read_dword_far(address_long)
-    Read a double word from the program space with a 32-bit (far) address. 
+    Read a double word from the program space with a 32-bit (far) address.
 
     \note The address is a byte address.
     The address is in the program space. */
@@ -780,7 +785,7 @@ not interfere with data accesses.
 
 /** \ingroup avr_pgmspace
     \def pgm_read_float_far(address_long)
-    Read a float from the program space with a 32-bit (far) address. 
+    Read a float from the program space with a 32-bit (far) address.
 
     \note The address is a byte address.
     The address is in the program space. */
@@ -791,36 +796,36 @@ not interfere with data accesses.
 
 /** \ingroup avr_pgmspace
     \def pgm_read_byte(address_short)
-    Read a byte from the program space with a 16-bit (near) address. 
+    Read a byte from the program space with a 16-bit (near) address.
 
-    \note The address is a byte address. 
+    \note The address is a byte address.
     The address is in the program space. */
 
 #define pgm_read_byte(address_short)    pgm_read_byte_near(address_short)
 
 /** \ingroup avr_pgmspace
     \def pgm_read_word(address_short)
-    Read a word from the program space with a 16-bit (near) address. 
+    Read a word from the program space with a 16-bit (near) address.
 
-    \note The address is a byte address. 
+    \note The address is a byte address.
     The address is in the program space. */
 
 #define pgm_read_word(address_short)    pgm_read_word_near(address_short)
 
 /** \ingroup avr_pgmspace
     \def pgm_read_dword(address_short)
-    Read a double word from the program space with a 16-bit (near) address. 
+    Read a double word from the program space with a 16-bit (near) address.
 
-    \note The address is a byte address. 
+    \note The address is a byte address.
     The address is in the program space. */
 
 #define pgm_read_dword(address_short)   pgm_read_dword_near(address_short)
 
 /** \ingroup avr_pgmspace
     \def pgm_read_float(address_short)
-    Read a float from the program space with a 16-bit (near) address. 
+    Read a float from the program space with a 16-bit (near) address.
 
-    \note The address is a byte address. 
+    \note The address is a byte address.
     The address is in the program space. */
 
 #define pgm_read_float(address_short)   pgm_read_float_near(address_short)
@@ -878,4 +883,5 @@ extern char *strtok_rP(char *__s, PGM_P __delim, char **__last);
 }
 #endif
 
+/** @} */
 #endif /* __PGMSPACE_H_ */
diff --git a/cpukit/score/cpu/avr/avr/portpins.h b/cpukit/score/cpu/avr/avr/portpins.h
index 04e9b094f1..5c84e9db89 100644
--- a/cpukit/score/cpu/avr/avr/portpins.h
+++ b/cpukit/score/cpu/avr/avr/portpins.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Define Generic PORTn, DDn, and PINn Values
+ */
+
 /* Copyright (c) 2003  Theodore A. Roth
    All rights reserved.
 
@@ -38,8 +44,6 @@
 #  error "Include <avr/io.h> instead of this file."
 #endif
 
-/* Define Generic PORTn, DDn, and PINn values. */
-
 /* Port Data Register (generic) */
 #define    PORT7        7
 #define    PORT6        6
@@ -70,7 +74,9 @@
 #define    PIN1         1
 #define    PIN0         0
 
-/* Define PORTxn an Pxn values for all possible port pins if not defined already by io.h. */
+/* Define PORTxn an Pxn values for all possible port pins 
+ * if not defined already by io.h. 
+ */
 
 /* PORT A */
 
diff --git a/cpukit/score/cpu/avr/avr/power.h b/cpukit/score/cpu/avr/avr/power.h
index cf44b10866..b101f3bcbd 100644
--- a/cpukit/score/cpu/avr/avr/power.h
+++ b/cpukit/score/cpu/avr/avr/power.h
@@ -1,30 +1,56 @@
-/* Copyright (c) 2006, 2007, 2008  Eric B. Weddington
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
+/**
+ * @file avr/iom644PA.h
+ *
+ * @brief Power Reduction Management
+ *
+ * Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that
+ * allow you to reduce power consumption by disabling or enabling various on-board
+ * peripherals as needed.
+ *
+ * There are many macros in this header file that provide an easy interface
+ * to enable or disable on-board peripherals to reduce power. See the table below.
+ *
+ * @note Not all AVR devices have a Power Reduction Register (for example
+ * the ATmega128). On those devices without a Power Reduction Register, these
+ * macros are not available.
+ *
+ * @note Not all AVR devices contain the same peripherals (for example, the LCD
+ * interface), or they will be named differently (for example, USART and
+ * USART0). Please consult your device's datasheet, or the header file, to
+ * find out which macros are applicable to your device.
+ */
+
+/*
+ *  Copyright (c) 2006, 2007, 2008  Eric B. Weddington
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 
 #ifndef _AVR_POWER_H_
@@ -33,311 +59,14 @@
 #include <avr/io.h>
 #include <stdint.h>
 
-
-/** \file */
-/** \defgroup avr_power <avr/power.h>: Power Reduction Management
-
-\code #include <avr/power.h>\endcode
-
-Many AVRs contain a Power Reduction Register (PRR) or Registers (PRRx) that 
-allow you to reduce power consumption by disabling or enabling various on-board 
-peripherals as needed.
-
-There are many macros in this header file that provide an easy interface
-to enable or disable on-board peripherals to reduce power. See the table below.
-
-\note Not all AVR devices have a Power Reduction Register (for example
-the ATmega128). On those devices without a Power Reduction Register, these 
-macros are not available.
-
-\note Not all AVR devices contain the same peripherals (for example, the LCD
-interface), or they will be named differently (for example, USART and 
-USART0). Please consult your device's datasheet, or the header file, to 
-find out which macros are applicable to your device.
-
-*/
-
-
-/** \addtogroup avr_power
-
-\anchor avr_powermacros
-<small>
-<center>
-<table border="3">
-  <tr>
-    <td width="10%"><strong>Power Macro</strong></td>
-    <td width="15%"><strong>Description</strong></td>
-    <td width="75%"><strong>Applicable for device</strong></td>
-  </tr>
-
-  <tr>
-    <td>power_adc_enable()</td>
-    <td>Enable the Analog to Digital Converter module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
-  </tr>
-
-  <tr>
-    <td>power_adc_disable()</td>
-    <td>Disable the Analog to Digital Converter module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
-  </tr>
-
-  <tr>
-    <td>power_lcd_enable()</td>
-    <td>Enable the LCD module.</td>
-    <td>ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490</td>
-  </tr>
-
-  <tr>
-    <td>power_lcd_disable().</td>
-    <td>Disable the LCD module.</td>
-    <td>ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490</td>
-  </tr>
-
-  <tr>
-    <td>power_psc0_enable()</td>
-    <td>Enable the Power Stage Controller 0 module.</td>
-    <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
-  </tr>
-
-  <tr>
-    <td>power_psc0_disable()</td>
-    <td>Disable the Power Stage Controller 0 module.</td>
-    <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
-  </tr>
-
-  <tr>
-    <td>power_psc1_enable()</td>
-    <td>Enable the Power Stage Controller 1 module.</td>
-    <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
-  </tr>
-
-  <tr>
-    <td>power_psc1_disable()</td>
-    <td>Disable the Power Stage Controller 1 module.</td>
-    <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
-  </tr>
-
-  <tr>
-    <td>power_psc2_enable()</td>
-    <td>Enable the Power Stage Controller 2 module.</td>
-    <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
-  </tr>
-
-  <tr>
-    <td>power_psc2_disable()</td>
-    <td>Disable the Power Stage Controller 2 module.</td>
-    <td>AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
-  </tr>
-
-  <tr>
-    <td>power_spi_enable()</td>
-    <td>Enable the Serial Peripheral Interface module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168</td>
-  </tr>
-
-  <tr>
-    <td>power_spi_disable()</td>
-    <td>Disable the Serial Peripheral Interface module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168</td>
-  </tr>
-
-  <tr>
-    <td>power_timer0_enable()</td>
-    <td>Enable the Timer 0 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM216, AT90PWM316, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
-  </tr>
-
-  <tr>
-    <td>power_timer0_disable()</td>
-    <td>Disable the Timer 0 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
-  </tr>
-
-  <tr>
-    <td>power_timer1_enable()</td>
-    <td>Enable the Timer 1 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
-  </tr>
-
-  <tr>
-    <td>power_timer1_disable()</td>
-    <td>Disable the Timer 1 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
-  </tr>
-
-  <tr>
-    <td>power_timer2_enable()</td>
-    <td>Enable the Timer 2 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168</td>
-  </tr>
-
-  <tr>
-    <td>power_timer2_disable()</td>
-    <td>Disable the Timer 2 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168</td>
-  </tr>
-
-  <tr>
-    <td>power_timer3_enable()</td>
-    <td>Enable the Timer 3 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287</td>
-  </tr>
-
-  <tr>
-    <td>power_timer3_disable()</td>
-    <td>Disable the Timer 3 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287</td>
-  </tr>
-
-  <tr>
-    <td>power_timer4_enable()</td>
-    <td>Enable the Timer 4 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561</td>
-  </tr>
-
-  <tr>
-    <td>power_timer4_disable()</td>
-    <td>Disable the Timer 4 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561</td>
-  </tr>
-
-  <tr>
-    <td>power_timer5_enable()</td>
-    <td>Enable the Timer 5 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561</td>
-  </tr>
-
-  <tr>
-    <td>power_timer5_disable()</td>
-    <td>Disable the Timer 5 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561</td>
-  </tr>
-
-  <tr>
-    <td>power_twi_enable()</td>
-    <td>Enable the Two Wire Interface module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168</td>
-  </tr>
-
-  <tr>
-    <td>power_twi_disable()</td>
-    <td>Disable the Two Wire Interface module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168</td>
-  </tr>
-
-  <tr>
-    <td>power_usart_enable()</td>
-    <td>Enable the USART module.</td>
-    <td>AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
-  </tr>
-
-  <tr>
-    <td>power_usart_disable()</td>
-    <td>Disable the USART module.</td>
-    <td>AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B</td>
-  </tr>
-
-  <tr>
-    <td>power_usart0_enable()</td>
-    <td>Enable the USART 0 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168</td>
-  </tr>
-
-  <tr>
-    <td>power_usart0_disable()</td>
-    <td>Disable the USART 0 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega48, ATmega88, ATmega168</td>
-  </tr>
-
-  <tr>
-    <td>power_usart1_enable()</td>
-    <td>Enable the USART 1 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P</td>
-  </tr>
-
-  <tr>
-    <td>power_usart1_disable()</td>
-    <td>Disable the USART 1 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, ATmega164P, ATmega324P</td>
-  </tr>
-
-  <tr>
-    <td>power_usart2_enable()</td>
-    <td>Enable the USART 2 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
-  </tr>
-
-  <tr>
-    <td>power_usart2_disable()</td>
-    <td>Disable the USART 2 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
-  </tr>
-
-  <tr>
-    <td>power_usart3_enable()</td>
-    <td>Enable the USART 3 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
-  </tr>
-
-  <tr>
-    <td>power_usart3_disable()</td>
-    <td>Disable the USART 3 module.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561</td>
-  </tr>
-
-  <tr>
-    <td>power_usb_enable()</td>
-    <td>Enable the USB module.</td>
-    <td>AT90USB646, AT90USB647, AT90USB1286, AT90USB1287</td>
-  </tr>
-
-  <tr>
-    <td>power_usb_disable()</td>
-    <td>Disable the USB module.</td>
-    <td>AT90USB646, AT90USB647, AT90USB1286, AT90USB1287</td>
-  </tr>
-
-  <tr>
-    <td>power_usi_enable()</td>
-    <td>Enable the Universal Serial Interface module.</td>
-    <td>ATtiny24, ATtiny44, ATtiny84, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
-  </tr>
-
-  <tr>
-    <td>power_usi_disable()</td>
-    <td>Disable the Universal Serial Interface module.</td>
-    <td>ATtiny24, ATtiny44, ATtiny84, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
-  </tr>
-
-  <tr>
-    <td>power_vadc_enable()</td>
-    <td>Enable the Voltage ADC module.</td>
-    <td>ATmega406</td>
-  </tr>
-
-  <tr>
-    <td>power_vadc_disable()</td>
-    <td>Disable the Voltage ADC module.</td>
-    <td>ATmega406</td>
-  </tr>
-
-  <tr>
-    <td>power_all_enable()</td>
-    <td>Enable all modules.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
-  </tr>
-
-  <tr>
-    <td>power_all_disable()</td>
-    <td>Disable all modules.</td>
-    <td>ATmega640, ATmega1280, ATmega1281, ATmega128RFA1, ATmega2560, ATmega2561, AT90USB646, AT90USB647, AT90USB1286, AT90USB1287, AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316, ATmega165, ATmega165P, ATmega325, ATmega3250, ATmega645, ATmega6450, ATmega169, ATmega169P, ATmega329, ATmega3290, ATmega649, ATmega6490, ATmega164P, ATmega324P, ATmega644, ATmega406, ATmega48, ATmega88, ATmega168, ATtiny24, ATtiny44, ATtiny84, ATtiny25, ATtiny45, ATtiny85, ATtiny261, ATtiny461, ATtiny861</td>
-  </tr>
-</table>
-</center>
-</small>
-
-@} */
+/**
+ *  @defgroup avr_power Power Reduction Management
+ *
+ *  @ingroup avr
+ *
+ *  @addtogroup avr_power
+ */
+/**@{*/
 
 
 #if defined(__AVR_ATxmega16A4__) \
@@ -481,7 +210,7 @@ do { \
 || defined(__AVR_ATmega1280__) \
 || defined(__AVR_ATmega1281__) \
 || defined(__AVR_ATmega2560__) \
-|| defined(__AVR_ATmega2561__) 
+|| defined(__AVR_ATmega2561__)
 
 #define power_adc_enable()      (PRR0 &= (uint8_t)~(1 << PRADC))
 #define power_adc_disable()     (PRR0 |= (uint8_t)(1 << PRADC))
@@ -1341,7 +1070,7 @@ without a Clock Prescale Register, these macros are not available.
 
 
 /** \addtogroup avr_power
-\code 
+\code
 typedef enum
 {
     clock_div_1 = 0,
@@ -1468,7 +1197,5 @@ void clock_prescale_set(clock_div_t __x)
 
 #endif
 
-
-
-
+/**@}*/
 #endif /* _AVR_POWER_H_ */
diff --git a/cpukit/score/cpu/avr/avr/sfr_defs.h b/cpukit/score/cpu/avr/avr/sfr_defs.h
index b687f56167..2b8392689a 100644
--- a/cpukit/score/cpu/avr/avr/sfr_defs.h
+++ b/cpukit/score/cpu/avr/avr/sfr_defs.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Macros for Accessing AVR Special Function Registers
+ */
+
 /* Copyright (c) 2002, Marek Michalkiewicz <marekm@amelek.gda.pl>
    All rights reserved.
 
@@ -34,85 +40,89 @@
 #ifndef _AVR_SFR_DEFS_H_
 #define _AVR_SFR_DEFS_H_ 1
 
-/** \defgroup avr_sfr_notes Additional notes from <avr/sfr_defs.h>
-    \ingroup avr_sfr
-
-   The \c <avr/sfr_defs.h> file is included by all of the \c <avr/ioXXXX.h>
-   files, which use macros defined here to make the special function register
-   definitions look like C variables or simple constants, depending on the
-   <tt>_SFR_ASM_COMPAT</tt> define.  Some examples from \c <avr/iocanxx.h> to
-   show how to define such macros:
-
-\code
-#define PORTA   _SFR_IO8(0x02)
-#define EEAR    _SFR_IO16(0x21)
-#define UDR0    _SFR_MEM8(0xC6)
-#define TCNT3   _SFR_MEM16(0x94)
-#define CANIDT  _SFR_MEM32(0xF0)
-\endcode
-
-   If \c _SFR_ASM_COMPAT is not defined, C programs can use names like
-   <tt>PORTA</tt> directly in C expressions (also on the left side of
-   assignment operators) and GCC will do the right thing (use short I/O
-   instructions if possible).  The \c __SFR_OFFSET definition is not used in
-   any way in this case.
-
-   Define \c _SFR_ASM_COMPAT as 1 to make these names work as simple constants
-   (addresses of the I/O registers).  This is necessary when included in
-   preprocessed assembler (*.S) source files, so it is done automatically if
-   \c __ASSEMBLER__ is defined.  By default, all addresses are defined as if
-   they were memory addresses (used in \c lds/sts instructions).  To use these
-   addresses in \c in/out instructions, you must subtract 0x20 from them.
-
-   For more backwards compatibility, insert the following at the start of your
-   old assembler source file:
-
-\code
-#define __SFR_OFFSET 0
-\endcode
-
-   This automatically subtracts 0x20 from I/O space addresses, but it's a
-   hack, so it is recommended to change your source: wrap such addresses in
-   macros defined here, as shown below.  After this is done, the
-   <tt>__SFR_OFFSET</tt> definition is no longer necessary and can be removed.
-
-   Real example - this code could be used in a boot loader that is portable
-   between devices with \c SPMCR at different addresses.
-
-\verbatim
-<avr/iom163.h>: #define SPMCR _SFR_IO8(0x37)
-<avr/iom128.h>: #define SPMCR _SFR_MEM8(0x68)
-\endverbatim
-
-\code
-#if _SFR_IO_REG_P(SPMCR)
-	out	_SFR_IO_ADDR(SPMCR), r24
-#else
-	sts	_SFR_MEM_ADDR(SPMCR), r24
-#endif
-\endcode
-
-   You can use the \c in/out/cbi/sbi/sbic/sbis instructions, without the
-   <tt>_SFR_IO_REG_P</tt> test, if you know that the register is in the I/O
-   space (as with \c SREG, for example).  If it isn't, the assembler will
-   complain (I/O address out of range 0...0x3f), so this should be fairly
-   safe.
-
-   If you do not define \c __SFR_OFFSET (so it will be 0x20 by default), all
-   special register addresses are defined as memory addresses (so \c SREG is
-   0x5f), and (if code size and speed are not important, and you don't like
-   the ugly \#if above) you can always use lds/sts to access them.  But, this
-   will not work if <tt>__SFR_OFFSET</tt> != 0x20, so use a different macro
-   (defined only if <tt>__SFR_OFFSET</tt> == 0x20) for safety:
-
-\code
-	sts	_SFR_ADDR(SPMCR), r24
-\endcode
-
-   In C programs, all 3 combinations of \c _SFR_ASM_COMPAT and
-   <tt>__SFR_OFFSET</tt> are supported - the \c _SFR_ADDR(SPMCR) macro can be
-   used to get the address of the \c SPMCR register (0x57 or 0x68 depending on
-   device). */
+/**
+ * @defgroup avr_sfr_notes Additional notes from <avr/sfr_defs.h>
+ *
+ * @ingroup avr_sfr
+ *
+ * The @c <avr/sfr_defs.h> file is included by all of the @c <avr/ioXXXX.h>
+ * files, which use macros defined here to make the special function register
+ * definitions look like C variables or simple constants, depending on the
+ * <tt>_SFR_ASM_COMPAT</tt> define.  Some examples from @c <avr/iocanxx.h> to
+ * show how to define such macros:
+ *
+ * @code
+ * #define PORTA   _SFR_IO8(0x02)
+ * #define EEAR    _SFR_IO16(0x21)
+ * #define UDR0    _SFR_MEM8(0xC6)
+ * #define TCNT3   _SFR_MEM16(0x94)
+ * #define CANIDT  _SFR_MEM32(0xF0)
+ * @endcode
+ *
+ * If @c _SFR_ASM_COMPAT is not defined, C programs can use names like
+ * <tt>PORTA</tt> directly in C expressions (also on the left side of
+ * assignment operators) and GCC will do the right thing (use short I/O
+ * instructions if possible).  The @c __SFR_OFFSET definition is not used in
+ * any way in this case.
+ *
+ * Define @c _SFR_ASM_COMPAT as 1 to make these names work as simple constants
+ * (addresses of the I/O registers).  This is necessary when included in
+ * preprocessed assembler (*.S) source files, so it is done automatically if
+ * @c __ASSEMBLER__ is defined.  By default, all addresses are defined as if
+ * they were memory addresses (used in @c lds/sts instructions).  To use these
+ * addresses in @c in/out instructions, you must subtract 0x20 from them.
+ *
+ * For more backwards compatibility, insert the following at the start of your
+ * old assembler source file:
+ *
+ * @code
+ * #define __SFR_OFFSET 0
+ * @endcode
+ *
+ * This automatically subtracts 0x20 from I/O space addresses, but it's a
+ * hack, so it is recommended to change your source: wrap such addresses in
+ * macros defined here, as shown below.  After this is done, the
+ * <tt>__SFR_OFFSET</tt> definition is no longer necessary and can be removed.
+
+ * Real example - this code could be used in a boot loader that is portable
+ * between devices with @c SPMCR at different addresses.
+ *
+ * @verbatim
+ * <avr/iom163.h>: #define SPMCR _SFR_IO8(0x37)
+ * <avr/iom128.h>: #define SPMCR _SFR_MEM8(0x68)
+ * @endverbatim
+ *
+ * @code
+ * #if _SFR_IO_REG_P(SPMCR)
+ * 	out	_SFR_IO_ADDR(SPMCR), r24
+ * #else
+ *	sts	_SFR_MEM_ADDR(SPMCR), r24
+ * #endif
+ * @endcode
+ *
+ * You can use the @c in/out/cbi/sbi/sbic/sbis instructions, without the
+ * <tt>_SFR_IO_REG_P</tt> test, if you know that the register is in the I/O
+ * space (as with @c SREG, for example).  If it isn't, the assembler will
+ * complain (I/O address out of range 0...0x3f), so this should be fairly
+ * safe.
+ *
+ * If you do not define @c __SFR_OFFSET (so it will be 0x20 by default), all
+ * special register addresses are defined as memory addresses (so @c SREG is
+ * 0x5f), and (if code size and speed are not important, and you don't like
+ * the ugly \#if above) you can always use lds/sts to access them.  But, this
+ * will not work if <tt>__SFR_OFFSET</tt> != 0x20, so use a different macro
+ * (defined only if <tt>__SFR_OFFSET</tt> == 0x20) for safety:
+ *
+ * @code
+ *	sts	_SFR_ADDR(SPMCR), r24
+ * @endcode
+ *
+ * In C programs, all 3 combinations of @c _SFR_ASM_COMPAT and
+ * <tt>__SFR_OFFSET</tt> are supported - the @c _SFR_ADDR(SPMCR) macro can be
+ * used to get the address of the @c SPMCR register (0x57 or 0x68 depending on
+ * device).
+ */
+/**@{**/
 
 #ifdef __ASSEMBLER__
 #define _SFR_ASM_COMPAT 1
@@ -190,23 +200,23 @@
 #define _SFR_WORD(sfr) _MMIO_WORD(_SFR_ADDR(sfr))
 #define _SFR_DWORD(sfr) _MMIO_DWORD(_SFR_ADDR(sfr))
 
-/** \name Bit manipulation */
-
-/*@{*/
-/** \def _BV
-    \ingroup avr_sfr
-
-    \code #include <avr/io.h>\endcode
-
-    Converts a bit number into a byte value.
-
-    \note The bit shift is performed by the compiler which then inserts the
-    result into the code. Thus, there is no run-time overhead when using
-    _BV(). */
-    
+/**
+ * @name Bit Manipulation
+ */
+/**@{**/
+
+/**
+ * @code #include <avr/io.h> @endcode
+ *
+ * Converts a bit number into a byte value.
+ *
+ * @note The bit shift is performed by the compiler which then inserts the
+ *       result into the code. Thus, there is no run-time overhead when using
+ *       _BV().
+ */   
 #define _BV(bit) (1 << (bit))
 
-/*@}*/
+/** @} */
 
 #ifndef _VECTOR
 #define _VECTOR(N) __vector_ ## N
@@ -215,53 +225,47 @@
 #ifndef __ASSEMBLER__
 
 
-/** \name IO register bit manipulation */
-
-/*@{*/
-
-
-
-/** \def bit_is_set
-    \ingroup avr_sfr
-
-    \code #include <avr/io.h>\endcode
-
-    Test whether bit \c bit in IO register \c sfr is set. 
-    This will return a 0 if the bit is clear, and non-zero
-    if the bit is set. */
+/**
+ * @name IO Register Bit Manipulation
+ */
+/**@{**/
 
+/**
+ * @code #include <avr/io.h> @endcode
+ *
+ * Test whether bit @c bit in IO register @c sfr is set.
+ * This will return a 0 if the bit is clear, and non-zero
+ * if the bit is set.
+ */
 #define bit_is_set(sfr, bit) (_SFR_BYTE(sfr) & _BV(bit))
 
-/** \def bit_is_clear
-    \ingroup avr_sfr
-
-    \code #include <avr/io.h>\endcode
-
-    Test whether bit \c bit in IO register \c sfr is clear. 
-    This will return non-zero if the bit is clear, and a 0
-    if the bit is set. */
+/**
+ * @code #include <avr/io.h> @endcode
+ *
+ * Test whether bit @c bit in IO register @c sfr is clear.
+ * This will return non-zero if the bit is clear, and a 0
+ * if the bit is set.
+ */
 
 #define bit_is_clear(sfr, bit) (!(_SFR_BYTE(sfr) & _BV(bit)))
 
-/** \def loop_until_bit_is_set
-    \ingroup avr_sfr
-
-    \code #include <avr/io.h>\endcode
-
-    Wait until bit \c bit in IO register \c sfr is set. */
-
+/**
+ * @code #include <avr/io.h> @endcode
+ *
+ * Wait until bit @c bit in IO register @c sfr is set.
+ */
 #define loop_until_bit_is_set(sfr, bit) do { } while (bit_is_clear(sfr, bit))
 
-/** \def loop_until_bit_is_clear
-    \ingroup avr_sfr
-
-    \code #include <avr/io.h>\endcode
-
-    Wait until bit \c bit in IO register \c sfr is clear. */
-
+/**
+ * @code #include <avr/io.h> @endcode
+ *
+ * Wait until bit @c bit in IO register @c sfr is clear.
+ */
 #define loop_until_bit_is_clear(sfr, bit) do { } while (bit_is_set(sfr, bit))
 
-/*@}*/
+/** @} */
+
+/** @} */
 
 #endif /* !__ASSEMBLER__ */
 
diff --git a/cpukit/score/cpu/avr/avr/signal.h b/cpukit/score/cpu/avr/avr/signal.h
index e9a802408b..898df4acb8 100644
--- a/cpukit/score/cpu/avr/avr/signal.h
+++ b/cpukit/score/cpu/avr/avr/signal.h
@@ -1,38 +1,54 @@
-/* Copyright (c) 2002,2005,2006 Marek Michalkiewicz
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
+/**
+ * @file
+ *
+ * @brief Use <avr/interrupt.h>
+ */
+
+/*
+ *  Copyright (c) 2002, 2005, 2006 Marek Michalkiewicz
+ *  All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
 
 #ifndef _AVR_SIGNAL_H_
 #define _AVR_SIGNAL_H_
 
+/**
+ *  @defgroup Avr_signal Signal
+ *
+ *  @ingroup avr
+ */
+/**@{*/
+
 #warning "This header file is obsolete.  Use <avr/interrupt.h>."
 #include <avr/interrupt.h>
 
+/**@}*/
 #endif /* _AVR_SIGNAL_H_ */
diff --git a/cpukit/score/cpu/avr/avr/signature.h b/cpukit/score/cpu/avr/avr/signature.h
index 13d3138965..06aedce580 100644
--- a/cpukit/score/cpu/avr/avr/signature.h
+++ b/cpukit/score/cpu/avr/avr/signature.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Signature Support
+ */
+
 /* Copyright (c) 2009, Atmel Corporation
    All rights reserved.
 
@@ -34,38 +40,38 @@
 #ifndef _AVR_SIGNATURE_H_
 #define _AVR_SIGNATURE_H_ 1
 
-/** \file */
-/** \defgroup avr_signature <avr/signature.h>: Signature Support
-
-    \par Introduction
-
-    The <avr/signature.h> header file allows the user to automatically
-    and easily include the device's signature data in a special section of
-    the final linked ELF file.
-    
-    This value can then be used by programming software to compare the on-device
-    signature with the signature recorded in the ELF file to look for a match
-    before programming the device.
-    
-    \par API Usage Example
-
-    Usage is very simple; just include the header file:
-    
-    \code
-    #include <avr/signature.h>
-    \endcode
-    
-    This will declare a constant unsigned char array and it is initialized with
-    the three signature bytes, MSB first, that are defined in the device I/O
-    header file. This array is then placed in the .signature section in the
-    resulting linked ELF file.
-    
-    The three signature bytes that are used to initialize the array are 
-    these defined macros in the device I/O header file, from MSB to LSB:
-    SIGNATURE_2, SIGNATURE_1, SIGNATURE_0.
-    
-    This header file should only be included once in an application.
-*/
+/**
+ * @defgroup avr_signature Signature Support
+ *
+ * @par Introduction
+ *
+ * The <avr/signature.h> header file allows the user to automatically
+ * and easily include the device's signature data in a special section of
+ * the final linked ELF file.
+ *
+ * This value can then be used by programming software to compare the 
+ * on-device signature with the signature recorded in the ELF file
+ * to look for a match before programming the device.
+ * 
+ * @par API Usage Example
+ *
+ * Usage is very simple; just include the header file:
+ *
+ * @code{.c}
+ * #include <avr/signature.h>
+ * @endcode
+ *
+ * This will declare a constant unsigned char array and it is initialized with
+ * the three signature bytes, MSB first, that are defined in the device I/O
+ * header file. This array is then placed in the .signature section in the
+ * resulting linked ELF file.
+ * 
+ * The three signature bytes that are used to initialize the array are 
+ * these defined macros in the device I/O header file, from MSB to LSB:
+ * SIGNATURE_2, SIGNATURE_1, SIGNATURE_0.
+ * 
+ * This header file should only be included once in an application.
+ */
 
 #ifndef __ASSEMBLER__
 
@@ -75,8 +81,9 @@
 
 const unsigned char __signature[3] __attribute__((section (".signature"))) =
         { SIGNATURE_2, SIGNATURE_1, SIGNATURE_0 };
-
-#endif  /* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */
+        
+/* defined(SIGNATURE_0) && defined(SIGNATURE_1) && defined(SIGNATURE_2) */
+#endif
 
 #endif  /* __ASSEMBLER__ */
 
diff --git a/cpukit/score/cpu/avr/avr/sleep.h b/cpukit/score/cpu/avr/avr/sleep.h
index 48b789f797..9a2556c85c 100644
--- a/cpukit/score/cpu/avr/avr/sleep.h
+++ b/cpukit/score/cpu/avr/avr/sleep.h
@@ -1,3 +1,10 @@
+/**
+ * @file
+ *
+ * @brief Power Management and Sleep Modes
+ * 
+ */
+
 /* Copyright (c) 2002, 2004 Theodore A. Roth
    Copyright (c) 2004, 2007, 2008 Eric B. Weddington
    Copyright (c) 2005, 2006, 2007 Joerg Wunsch
@@ -37,103 +44,104 @@
 #include <avr/io.h>
 #include <stdint.h>
 
-
-/** \file */
-
-/** \defgroup avr_sleep <avr/sleep.h>: Power Management and Sleep Modes
-
-    \code #include <avr/sleep.h>\endcode
-
-    Use of the \c SLEEP instruction can allow an application to reduce its
-    power comsumption considerably. AVR devices can be put into different
-    sleep modes. Refer to the datasheet for the details relating to the device
-    you are using.
-
-    There are several macros provided in this header file to actually
-    put the device into sleep mode.  The simplest way is to optionally
-    set the desired sleep mode using \c set_sleep_mode() (it usually
-    defaults to idle mode where the CPU is put on sleep but all
-    peripheral clocks are still running), and then call
-    \c sleep_mode(). This macro automatically sets the sleep enable bit, goes 
-    to sleep, and clears the sleep enable bit.
-    
-    Example:
-    \code
-    #include <avr/sleep.h>
-
-    ...
-      set_sleep_mode(<mode>);
-      sleep_mode();
-    \endcode
-    
-    Note that unless your purpose is to completely lock the CPU (until a 
-    hardware reset), interrupts need to be enabled before going to sleep.
-
-    As the \c sleep_mode() macro might cause race conditions in some
-    situations, the individual steps of manipulating the sleep enable
-    (SE) bit, and actually issuing the \c SLEEP instruction, are provided
-    in the macros \c sleep_enable(), \c sleep_disable(), and
-    \c sleep_cpu().  This also allows for test-and-sleep scenarios that
-    take care of not missing the interrupt that will awake the device
-    from sleep.
-
-    Example:
-    \code
-    #include <avr/interrupt.h>
-    #include <avr/sleep.h>
-
-    ...
-      set_sleep_mode(<mode>);
-      cli();
-      if (some_condition)
-      {
-        sleep_enable();
-        sei();
-        sleep_cpu();
-        sleep_disable();
-      }
-      sei();
-    \endcode
-
-    This sequence ensures an atomic test of \c some_condition with
-    interrupts being disabled.  If the condition is met, sleep mode
-    will be prepared, and the \c SLEEP instruction will be scheduled
-    immediately after an \c SEI instruction.  As the intruction right
-    after the \c SEI is guaranteed to be executed before an interrupt
-    could trigger, it is sure the device will really be put to sleep.
-
-    Some devices have the ability to disable the Brown Out Detector (BOD) before 
-    going to sleep. This will also reduce power while sleeping. If the
-    specific AVR device has this ability then an additional macro is defined:
-    \c sleep_bod_disable(). This macro generates inlined assembly code
-    that will correctly implement the timed sequence for disabling the BOD
-    before sleeping. However, there is a limited number of cycles after the
-    BOD has been disabled that the device can be put into sleep mode, otherwise
-    the BOD will not truly be disabled. Recommended practice is to disable
-    the BOD (\c sleep_bod_disable()), set the interrupts (\c sei()), and then
-    put the device to sleep (\c sleep_cpu()), like so:
-
-    \code
-    #include <avr/interrupt.h>
-    #include <avr/sleep.h>
-
-    ...
-      set_sleep_mode(<mode>);
-      cli();
-      if (some_condition)
-      {
-        sleep_enable();
-        sleep_bod_disable();
-        sei();
-        sleep_cpu();
-        sleep_disable();
-      }
-      sei();
-    \endcode
-*/
-
-
-/* Define an internal sleep control register and an internal sleep enable bit mask. */
+/**
+ * @defgroup avr_sleep Power Management and Sleep Modes
+ * 
+ * Use of the @c SLEEP instruction can allow an application to reduce its
+ * power comsumption considerably. AVR devices can be put into different
+ * sleep modes. Refer to the datasheet for the details relating to the device
+ * you are using.
+ * 
+ * There are several macros provided in this header file to actually
+ * put the device into sleep mode.  The simplest way is to optionally
+ * set the desired sleep mode using @c set_sleep_mode() (it usually
+ * defaults to idle mode where the CPU is put on sleep but all
+ * peripheral clocks are still running), and then call
+ * @c sleep_mode(). This macro automatically sets the sleep enable bit, goes 
+ * to sleep, and clears the sleep enable bit.
+ *   
+ * Example:
+ * @code{.c}
+ * #include <avr/sleep.h>
+ * 
+ * ...
+ *   set_sleep_mode(<mode>);
+ *   sleep_mode();
+ * @endcode
+ *   
+ * Note that unless your purpose is to completely lock the CPU (until a 
+ * hardware reset), interrupts need to be enabled before going to sleep.
+ *
+ * As the @c sleep_mode() macro might cause race conditions in some
+ * situations, the individual steps of manipulating the sleep enable
+ * (SE) bit, and actually issuing the @c SLEEP instruction, are provided
+ * in the macros @c sleep_enable(), @c sleep_disable(), and
+ * @c sleep_cpu().  This also allows for test-and-sleep scenarios that
+ * take care of not missing the interrupt that will awake the device
+ * from sleep.
+ *
+ * Example:
+ * @code{.c}
+ * #include <avr/interrupt.h>
+ * #include <avr/sleep.h>*
+ *
+ * ...
+ *   set_sleep_mode(<mode>);
+ *   cli();
+ *   if (some_condition)
+ *   {
+ *     sleep_enable();
+ *     sei();
+ *     sleep_cpu();
+ *     sleep_disable();
+ *   }
+ *   sei();
+ * @endcode
+ * 
+ * This sequence ensures an atomic test of @c some_condition with
+ * interrupts being disabled.  If the condition is met, sleep mode
+ * will be prepared, and the @c SLEEP instruction will be scheduled
+ * immediately after an @c SEI instruction.  As the intruction right
+ * after the @c SEI is guaranteed to be executed before an interrupt
+ * could trigger, it is sure the device will really be put to sleep.
+ * 
+ * Some devices have the ability to disable the Brown Out Detector (BOD) 
+ * before going to sleep. This will also reduce power while sleeping. If the
+ * specific AVR device has this ability then an additional macro is defined:
+ * @c sleep_bod_disable(). This macro generates inlined assembly code
+ * that will correctly implement the timed sequence for disabling the BOD
+ * before sleeping. However, there is a limited number of cycles after the
+ * BOD has been disabled that the device can be put into sleep mode, otherwise
+ * the BOD will not truly be disabled. Recommended practice is to disable
+ * the BOD (@c sleep_bod_disable()), set the interrupts (@c sei()), and then
+ * put the device to sleep (@c sleep_cpu()), like so:
+ * 
+ * @code{.c}
+ * #include <avr/interrupt.h>
+ * #include <avr/sleep.h>*
+ *
+ * ...
+ *   set_sleep_mode(<mode>);
+ *   cli();
+ *   if (some_condition)
+ *   {
+ *     sleep_enable();
+ *     sleep_bod_disable();
+ *     sei();
+ *     sleep_cpu();
+ *     sleep_disable();
+ *  }
+ *   sei();
+ * @endcode
+ * 
+ */
+/**@{**/
+
+
+/* 
+ * Define an internal sleep control register and 
+ * an internal sleep enable bit mask. 
+ */
 #if defined(SLEEP_CTRL)
 
     /* XMEGA devices */
@@ -167,8 +175,11 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_PWR_DOWN || (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
-        EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
+        MCUCR = ((MCUCR & ~_BV(SM1)) | \
+        ((mode) == SLEEP_MODE_PWR_DOWN || \
+        (mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM1) : 0)); \
+        EMCUCR = ((EMCUCR & ~_BV(SM0)) | \
+        ((mode) == SLEEP_MODE_PWR_SAVE ? _BV(SM0) : 0)); \
     } while(0)
 
 
@@ -184,9 +195,12 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        MCUCR = ((MCUCR & ~_BV(SM1)) | ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
-        MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY  || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
-        EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
+        MCUCR = ((MCUCR & ~_BV(SM1)) | \
+        ((mode) == SLEEP_MODE_IDLE ? 0 : _BV(SM1))); \
+        MCUCSR = ((MCUCSR & ~_BV(SM2)) | ((mode) == SLEEP_MODE_STANDBY  || \
+        (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM2) : 0)); \
+        EMCUCR = ((EMCUCR & ~_BV(SM0)) | ((mode) == SLEEP_MODE_PWR_SAVE || \
+        (mode) == SLEEP_MODE_EXT_STANDBY ? _BV(SM0) : 0)); \
     } while(0)
 
 #elif defined(__AVR_AT90S2313__) \
@@ -217,7 +231,8 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
+        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG &  \
+        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
     } while(0)
 
 #elif defined(__AVR_AT90S4434__) \
@@ -253,7 +268,8 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
+        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
+        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
     } while(0)
 
 #elif defined(__AVR_ATtiny2313__) \
@@ -266,7 +282,8 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
+        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
+        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
     } while(0)
 
 #elif defined(__AVR_AT94K__)
@@ -277,7 +294,8 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
+        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
+        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
     } while(0)
 
 #elif defined(__AVR_ATtiny26__) \
@@ -290,7 +308,8 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1))) | (mode)); \
+        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
+        ~(_BV(SM0) | _BV(SM1))) | (mode)); \
     } while(0)
 
 #elif defined(__AVR_AT90PWM216__) \
@@ -304,7 +323,8 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
+        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
+        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
     } while(0)
 
 #elif defined(__AVR_AT90CAN128__) \
@@ -415,7 +435,8 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
+        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
+        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
     } while(0)
 
 #elif defined(__AVR_ATxmega16A4__) \
@@ -438,11 +459,13 @@
     #define SLEEP_MODE_PWR_DOWN     (SLEEP_SMODE1_bm)
     #define SLEEP_MODE_PWR_SAVE     (SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
     #define SLEEP_MODE_STANDBY      (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm)
-    #define SLEEP_MODE_EXT_STANDBY  (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)
+    #define SLEEP_MODE_EXT_STANDBY  (SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | \
+                                     SLEEP_SMODE0_bm)
 
     #define set_sleep_mode(mode) \
     do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
+        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
+        ~(SLEEP_SMODE2_bm | SLEEP_SMODE1_bm | SLEEP_SMODE0_bm)) | (mode)); \
     } while(0)
 
 #elif defined(__AVR_AT90SCR100__)
@@ -455,7 +478,8 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
+        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
+        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
     } while(0)
 
 #elif defined(__AVR_ATA6289__)
@@ -466,7 +490,8 @@
 
     #define set_sleep_mode(mode) \
     do { \
-        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
+        _SLEEP_CONTROL_REG = ((_SLEEP_CONTROL_REG & \
+        ~(_BV(SM0) | _BV(SM1) | _BV(SM2))) | (mode)); \
     } while(0)
 
 #else
@@ -477,18 +502,17 @@
 
 
 
-/** \ingroup avr_sleep
-
-    Put the device in sleep mode. How the device is brought out of sleep mode
-    depends on the specific mode selected with the set_sleep_mode() function.
-    See the data sheet for your device for more details. */
+/**
+ * Put the device in sleep mode. How the device is brought out of sleep mode
+ * depends on the specific mode selected with the set_sleep_mode() function.
+ * See the data sheet for your device for more details. 
+ */
 
 
 #if defined(__DOXYGEN__)
 
-/** \ingroup avr_sleep
-
-    Set the SE (sleep enable) bit.
+/**
+ * Set the SE (sleep enable) bit.
 */
 extern void sleep_enable (void);
 
@@ -504,10 +528,9 @@ do {                               \
 
 #if defined(__DOXYGEN__)
 
-/** \ingroup avr_sleep
-
-    Clear the SE (sleep enable) bit.
-*/
+/**
+ * Clear the SE (sleep enable) bit.
+ */
 extern void sleep_disable (void);
 
 #else
@@ -520,11 +543,10 @@ do {                               \
 #endif
 
 
-/** \ingroup avr_sleep
-
-    Put the device into sleep mode.  The SE bit must be set
-    beforehand, and it is recommended to clear it afterwards.
-*/
+/**
+ * Put the device into sleep mode.  The SE bit must be set
+ * beforehand, and it is recommended to clear it afterwards.
+ */
 #if defined(__DOXYGEN__)
 
 extern void sleep_cpu (void);
@@ -582,6 +604,6 @@ do { \
 #endif
 
 
-/*@}*/
+/** @} */
 
 #endif /* _AVR_SLEEP_H_ */
diff --git a/cpukit/score/cpu/avr/avr/version.h b/cpukit/score/cpu/avr/avr/version.h
index 7e0c3a3649..7af5025921 100644
--- a/cpukit/score/cpu/avr/avr/version.h
+++ b/cpukit/score/cpu/avr/avr/version.h
@@ -1,53 +1,63 @@
-/* Copyright (c) 2005, Joerg Wunsch                               -*- c -*-
-   All rights reserved.
-
-   Redistribution and use in source and binary forms, with or without
-   modification, are permitted provided that the following conditions are met:
-
-   * Redistributions of source code must retain the above copyright
-     notice, this list of conditions and the following disclaimer.
-
-   * Redistributions in binary form must reproduce the above copyright
-     notice, this list of conditions and the following disclaimer in
-     the documentation and/or other materials provided with the
-     distribution.
-
-   * Neither the name of the copyright holders nor the names of
-     contributors may be used to endorse or promote products derived
-     from this software without specific prior written permission.
-
-  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
-  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-  POSSIBILITY OF SUCH DAMAGE. */
-
-
-/** \defgroup avr_version <avr/version.h>: avr-libc version macros
-    \code #include <avr/version.h> \endcode
-
-    This header file defines macros that contain version numbers and
-    strings describing the current version of avr-libc.
+/**
+ * @file avr/iom644PA.h
+ *
+ * @brief Current Version of avr-libc
+ *
+ * This header file defines macros that contain version numbers and
+ * strings describing the current version of avr-libc.
+ *
+ * The version number itself basically consists of three pieces that
+ * are separated by a dot: the major number, the minor number, and
+ * the revision number.  For development versions (which use an odd
+ * minor number), the string representation additionally gets the
+ * date code (YYYYMMDD) appended.
+ *
+ * This file will also be included by \c <avr/io.h>.  That way,
+ * portable tests can be implemented using \c <avr/io.h> that can be
+ * used in code that wants to remain backwards-compatible to library
+ * versions prior to the date when the library version API had been
+ * added, as referenced but undefined C preprocessor macros
+ * automatically evaluate to 0.
+ */
 
-    The version number itself basically consists of three pieces that
-    are separated by a dot: the major number, the minor number, and
-    the revision number.  For development versions (which use an odd
-    minor number), the string representation additionally gets the
-    date code (YYYYMMDD) appended.
+/*
+ *  Copyright (c) 2005, Joerg Wunsch
+ *  All rights reserved.
+ *
+ *  Redistribution and use in source and binary forms, with or without
+ *  modification, are permitted provided that the following conditions are met:
+ *
+ * * Redistributions of source code must retain the above copyright
+ *   notice, this list of conditions and the following disclaimer.
+ *
+ * * Redistributions in binary form must reproduce the above copyright
+ *   notice, this list of conditions and the following disclaimer in
+ *   the documentation and/or other materials provided with the
+ *   distribution.
+ *
+ * * Neither the name of the copyright holders nor the names of
+ *   contributors may be used to endorse or promote products derived
+ *   from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
+ * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ */
 
-    This file will also be included by \c <avr/io.h>.  That way,
-    portable tests can be implemented using \c <avr/io.h> that can be
-    used in code that wants to remain backwards-compatible to library
-    versions prior to the date when the library version API had been
-    added, as referenced but undefined C preprocessor macros
-    automatically evaluate to 0.
-*/
+/**
+ *  @defgroup avr_version avr-libc Version Macros
+ *
+ *  @ingroup avr
+ */
+/**@{*/
 
 #ifndef _AVR_VERSION_H_
 #define _AVR_VERSION_H_
@@ -86,4 +96,5 @@
     Library revision number. */
 #define __AVR_LIBC_REVISION__       8
 
+/**@}*/
 #endif /* _AVR_VERSION_H_ */
diff --git a/cpukit/score/cpu/avr/avr/wdt.h b/cpukit/score/cpu/avr/avr/wdt.h
index 0b424c9a83..7337e273b3 100644
--- a/cpukit/score/cpu/avr/avr/wdt.h
+++ b/cpukit/score/cpu/avr/avr/wdt.h
@@ -1,3 +1,8 @@
+/**
+ * @file
+ * 
+ * @brief Watchdog Timer Handling
+ */
 /* Copyright (c) 2002, 2004 Marek Michalkiewicz
    Copyright (c) 2005, 2006, 2007 Eric B. Weddington
    All rights reserved.
@@ -40,59 +45,60 @@
 #include <avr/io.h>
 #include <stdint.h>
 
-/** \file */
-/** \defgroup avr_watchdog <avr/wdt.h>: Watchdog timer handling
-    \code #include <avr/wdt.h> \endcode
-
-    This header file declares the interface to some inline macros
-    handling the watchdog timer present in many AVR devices.  In order
-    to prevent the watchdog timer configuration from being
-    accidentally altered by a crashing application, a special timed
-    sequence is required in order to change it.  The macros within
-    this header file handle the required sequence automatically
-    before changing any value.  Interrupts will be disabled during
-    the manipulation.
-
-    \note Depending on the fuse configuration of the particular
-    device, further restrictions might apply, in particular it might
-    be disallowed to turn off the watchdog timer.
-
-    Note that for newer devices (ATmega88 and newer, effectively any
-    AVR that has the option to also generate interrupts), the watchdog
-    timer remains active even after a system reset (except a power-on
-    condition), using the fastest prescaler value (approximately 15
-    ms).  It is therefore required to turn off the watchdog early
-    during program startup, the datasheet recommends a sequence like
-    the following:
-
-    \code
-    #include <stdint.h>
-    #include <avr/wdt.h>
-
-    uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
-
-    void get_mcusr(void) \
-      __attribute__((naked)) \
-      __attribute__((section(".init3")));
-    void get_mcusr(void)
-    {
-      mcusr_mirror = MCUSR;
-      MCUSR = 0;
-      wdt_disable();
-    }
-    \endcode
-
-    Saving the value of MCUSR in \c mcusr_mirror is only needed if the
-    application later wants to examine the reset source, but in particular, 
-    clearing the watchdog reset flag before disabling the
-    watchdog is required, according to the datasheet.
+/** 
+ * @defgroup avr_watchdog Watchdog Timer Handling
+ *
+ * This header file declares the interface to some inline macros
+ * handling the watchdog timer present in many AVR devices.  In order
+ * to prevent the watchdog timer configuration from being
+ * accidentally altered by a crashing application, a special timed
+ * equence is required in order to change it.  The macros within
+ * this header file handle the required sequence automatically
+ * before changing any value.  Interrupts will be disabled during
+ * the manipulation.
+ * 
+ * Note: Depending on the fuse configuration of the particular
+ * device, further restrictions might apply, in particular it might
+ * be disallowed to turn off the watchdog timer.
+ * 
+ * Note that for newer devices (ATmega88 and newer, effectively any
+ * AVR that has the option to also generate interrupts), the watchdog
+ * timer remains active even after a system reset (except a power-on
+ * condition), using the fastest prescaler value (approximately 15
+ * ms).  It is therefore required to turn off the watchdog early
+ * during program startup, the datasheet recommends a sequence like
+ * the following:
+ * 
+ * @code{.c}
+ * #include <stdint.h>
+ * #include <avr/wdt.h>
+ *
+ * uint8_t mcusr_mirror __attribute__ ((section (".noinit")));
+ *
+ * void get_mcusr(void) \
+ *   __attribute__((naked)) \
+ *   __attribute__((section(".init3")));
+ * void get_mcusr(void)
+ * {
+ *   mcusr_mirror = MCUSR;
+ *   MCUSR = 0;
+ *   wdt_disable();
+ * }
+ * @endcode
+ *
+ * Saving the value of MCUSR in @c mcusr_mirror is only needed if the
+ * application later wants to examine the reset source, but in particular, 
+ * clearing the watchdog reset flag before disabling the
+ * watchdog is required, according to the datasheet.
+ * @{
 */
 
 /**
-   \ingroup avr_watchdog
-   Reset the watchdog timer.  When the watchdog timer is enabled,
-   a call to this instruction is required before the timer expires,
-   otherwise a watchdog-initiated device reset will occur. 
+ * @brief Watchdog Timer Reset
+ * 
+ * Reset the watchdog timer.  When the watchdog timer is enabled,
+ * a call to this instruction is required before the timer expires,
+ * otherwise a watchdog-initiated device reset will occur. 
 */
 
 #define wdt_reset() __asm__ __volatile__ ("wdr")
@@ -118,14 +124,13 @@
 
 
 /**
-   \ingroup avr_watchdog
-   Enable the watchdog timer, configuring it for expiry after
-   \c timeout (which is a combination of the \c WDP0 through
-   \c WDP2 bits to write into the \c WDTCR register; For those devices 
-   that have a \c WDTCSR register, it uses the combination of the \c WDP0 
-   through \c WDP3 bits).
-
-   See also the symbolic constants \c WDTO_15MS et al.
+ * Enable the watchdog timer, configuring it for expiry after
+ * @c timeout (which is a combination of the @c WDP0 through
+ * @c WDP2 bits to write into the @c WDTCR register; For those devices 
+ * that have a @c WDTCSR register, it uses the combination of the @c WDP0 
+ * through @c WDP3 bits).
+ *
+ * See also the symbolic constants @c WDTO_15MS et al.
 */
 
 
@@ -317,10 +322,9 @@ __asm__ __volatile__ (  \
     )
 
 /**
-   \ingroup avr_watchdog
-   Disable the watchdog timer, if possible.  This attempts to turn off the 
-   Enable bit in the watchdog control register. See the datasheet for 
-   details.
+ *  Disable the watchdog timer, if possible.  This attempts to turn off the 
+ *  Enable bit in the watchdog control register. See the datasheet for 
+ *  details.
 */
 #define wdt_disable() \
 __asm__ __volatile__ (  \
@@ -340,101 +344,77 @@ __asm__ __volatile__ (  \
 
 
 /**
-   \ingroup avr_watchdog
-   Symbolic constants for the watchdog timeout.  Since the watchdog
-   timer is based on a free-running RC oscillator, the times are
-   approximate only and apply to a supply voltage of 5 V.  At lower
-   supply voltages, the times will increase.  For older devices, the
-   times will be as large as three times when operating at Vcc = 3 V,
-   while the newer devices (e. g. ATmega128, ATmega8) only experience
-   a negligible change.
-
-   Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
-   500 ms, 1 s, 2 s.  (Some devices also allow for 4 s and 8 s.)
-   Symbolic constants are formed by the prefix
-   \c WDTO_, followed by the time.
-
-   Example that would select a watchdog timer expiry of approximately
-   500 ms:
-   \code
-   wdt_enable(WDTO_500MS);
-   \endcode
+ *  Symbolic constants for the watchdog timeout.  Since the watchdog
+ *  timer is based on a free-running RC oscillator, the times are
+ *  approximate only and apply to a supply voltage of 5 V.  At lower
+ *  supply voltages, the times will increase.  For older devices, the
+ *  times will be as large as three times when operating at Vcc = 3 V,
+ *  while the newer devices (e. g. ATmega128, ATmega8) only experience
+ *  a negligible change.
+ * 
+ *  Possible timeout values are: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms,
+ *  500 ms, 1 s, 2 s.  (Some devices also allow for 4 s and 8 s.)
+ *  Symbolic constants are formed by the prefix
+ *  @c WDTO_, followed by the time.
+ * 
+ *  Example that would select a watchdog timer expiry of approximately
+ *  500 ms:
+ * 
+ *  @code{.c}
+ *  wdt_enable(WDTO_500MS);
+ *  @endcode
 */
 #define WDTO_15MS   0
 
-/** \ingroup avr_watchdog
-    See \c WDT0_15MS */
+/** @see WDT0_15MS */
 #define WDTO_30MS   1
 
-/** \ingroup avr_watchdog See
-    \c WDT0_15MS */
+/** @see WDT0_15MS */
 #define WDTO_60MS   2
 
-/** \ingroup avr_watchdog
-    See \c WDT0_15MS */
+/** @see WDT0_15MS */
 #define WDTO_120MS  3
 
-/** \ingroup avr_watchdog
-    See \c WDT0_15MS */
+/** @see WDT0_15MS */
 #define WDTO_250MS  4
 
-/** \ingroup avr_watchdog
-    See \c WDT0_15MS */
+/** @see WDT0_15MS */
 #define WDTO_500MS  5
 
-/** \ingroup avr_watchdog
-    See \c WDT0_15MS */
+/** @see WDT0_15MS */
 #define WDTO_1S     6
 
-/** \ingroup avr_watchdog
-    See \c WDT0_15MS */
+/** @see WDT0_15MS */
 #define WDTO_2S     7
 
 #if defined(__DOXYGEN__) || defined(WDP3)
 
-/** \ingroup avr_watchdog
-    See \c WDT0_15MS
-    Note: This is only available on the 
-    ATtiny2313, 
-    ATtiny24, ATtiny44, ATtiny84, 
-    ATtiny25, ATtiny45, ATtiny85, 
-    ATtiny261, ATtiny461, ATtiny861, 
-    ATmega48, ATmega88, ATmega168,
-    ATmega48P, ATmega88P, ATmega168P, ATmega328P,
-    ATmega164P, ATmega324P, ATmega644P, ATmega644,
-    ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
-    ATmega8HVA, ATmega16HVA, ATmega32HVB,
-    ATmega406, ATmega1284P,
-    AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
-    AT90PWM81,
-    AT90USB82, AT90USB162,
-    AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
-    ATtiny48, ATtiny88.
-    */
+/**
+ * @see WDT0_15MS
+ * 
+ * Note: This is only available on:
+ * ATtiny2313, 
+ * ATtiny24, ATtiny44, ATtiny84, 
+ * ATtiny25, ATtiny45, ATtiny85, 
+ * ATtiny261, ATtiny461, ATtiny861, 
+ * ATmega48, ATmega88, ATmega168,
+ * ATmega48P, ATmega88P, ATmega168P, ATmega328P,
+ * ATmega164P, ATmega324P, ATmega644P, ATmega644,
+ * ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
+ * ATmega8HVA, ATmega16HVA, ATmega32HVB,
+ * ATmega406, ATmega1284P,
+ * AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
+ * AT90PWM81,
+ * AT90USB82, AT90USB162,
+ * AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
+ * ATtiny48, ATtiny88.
+ */
 #define WDTO_4S     8
 
-/** \ingroup avr_watchdog
-    See \c WDT0_15MS
-    Note: This is only available on the 
-    ATtiny2313, 
-    ATtiny24, ATtiny44, ATtiny84, 
-    ATtiny25, ATtiny45, ATtiny85, 
-    ATtiny261, ATtiny461, ATtiny861, 
-    ATmega48, ATmega88, ATmega168,
-    ATmega48P, ATmega88P, ATmega168P, ATmega328P,
-    ATmega164P, ATmega324P, ATmega644P, ATmega644,
-    ATmega640, ATmega1280, ATmega1281, ATmega2560, ATmega2561,
-    ATmega8HVA, ATmega16HVA, ATmega32HVB,
-    ATmega406, ATmega1284P,
-    AT90PWM1, AT90PWM2, AT90PWM2B, AT90PWM3, AT90PWM3B, AT90PWM216, AT90PWM316,
-    AT90PWM81,
-    AT90USB82, AT90USB162,
-    AT90USB646, AT90USB647, AT90USB1286, AT90USB1287,
-    ATtiny48, ATtiny88.
-    */
+/** @see WDTO_4S */
 #define WDTO_8S     9
 
 #endif  /* defined(__DOXYGEN__) || defined(WDP3) */
-   
+/** @} */   
 
 #endif /* _AVR_WDT_H_ */
diff --git a/cpukit/score/cpu/avr/rtems/asm.h b/cpukit/score/cpu/avr/rtems/asm.h
index 89f1385b36..e93841d06e 100644
--- a/cpukit/score/cpu/avr/rtems/asm.h
+++ b/cpukit/score/cpu/avr/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * @note The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
@@ -324,7 +327,7 @@
 	lpm / mov Rd,r0
 	lpm / adiw ZL,1
 	lpm / mov Rd,r0 / adiw ZL,1
-	
+
    For enhanced chips it is one instruction always.
 
    ATTENTION:  unlike enhanced chips SREG (S,V,N,Z,C) flags are
diff --git a/cpukit/score/cpu/avr/rtems/score/avr.h b/cpukit/score/cpu/avr/rtems/score/avr.h
index 23ecbb3e76..cee1a24102 100644
--- a/cpukit/score/cpu/avr/rtems/score/avr.h
+++ b/cpukit/score/cpu/avr/rtems/score/avr.h
@@ -1,13 +1,16 @@
 /**
- * @file rtems/score/avr.h
+ * @file
+ *
+ * @brief Intel AVR Set up Basic CPU Dependency Settings Based on
+ * Compiler Settings
+ *
+ * This file sets up basic CPU dependency settings based on
+ * compiler settings.  For example, it can determine if
+ * floating point is available.  This particular implementation
+ * is specified to the avr port.
  */
 
 /*
- *  This file sets up basic CPU dependency settings based on
- *  compiler settings.  For example, it can determine if
- *  floating point is available.  This particular implementation
- *  is specified to the avr port.
- *
  *  COPYRIGHT 2004, Ralf Corsepius, Ulm, Germany.
  *
  *  The license and distribution terms for this file may be
diff --git a/cpukit/score/cpu/avr/rtems/score/cpu.h b/cpukit/score/cpu/avr/rtems/score/cpu.h
index 2bfcbceaf9..5f1577af20 100644
--- a/cpukit/score/cpu/avr/rtems/score/cpu.h
+++ b/cpukit/score/cpu/avr/rtems/score/cpu.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/cpu.h
+ * @file
+ *
+ * @brief Intel AVR CPU Department Source
+ *
+ * This include file contains information pertaining to the AVR
+ * processor.
  */
 
 /*
- *  This include file contains information pertaining to the AVR
- *  processor.
- *
  *  COPYRIGHT (c) 1989-2006.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/avr/rtems/score/cpu_asm.h b/cpukit/score/cpu/avr/rtems/score/cpu_asm.h
index e3797a93f9..e11caec486 100644
--- a/cpukit/score/cpu/avr/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/avr/rtems/score/cpu_asm.h
@@ -1,12 +1,14 @@
 /**
- * @file rtems/score/cpu_asm.h
+ * @file
+ *
+ * @brief Intel AVR Assembly File
+ *
+ * Very loose template for an include file for the cpu_asm.? file
+ * if it is implemented as a ".S" file (preprocessed by cpp) instead
+ * of a ".s" file (preprocessed by gm4 or gasp).
  */
 
 /*
- *  Very loose template for an include file for the cpu_asm.? file
- *  if it is implemented as a ".S" file (preprocessed by cpp) instead
- *  of a ".s" file (preprocessed by gm4 or gasp).
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/avr/rtems/score/types.h b/cpukit/score/cpu/avr/rtems/score/types.h
index 77eb0dbc30..a4710d3331 100644
--- a/cpukit/score/cpu/avr/rtems/score/types.h
+++ b/cpukit/score/cpu/avr/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief Intel AVR CPU Type Definitions
+ *
+ * This include file contains type definitions pertaining to the Intel
+ * avr processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the Intel
- *  avr processor family.
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/bfin/rtems/asm.h b/cpukit/score/cpu/bfin/rtems/asm.h
index dbe0d7f407..5d133ddbdd 100644
--- a/cpukit/score/cpu/bfin/rtems/asm.h
+++ b/cpukit/score/cpu/bfin/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * @note The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
@@ -38,24 +41,24 @@
 
 #ifndef __USER_LABEL_PREFIX__
 /**
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents.  If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
  *
- *  This symbol is prefixed to all C program symbols.
+ * This symbol is prefixed to all C program symbols.
  */
 #define __USER_LABEL_PREFIX__ _
 #endif
 
 #ifndef __REGISTER_PREFIX__
 /**
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents.  If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
  *
- *  This symbol is prefixed to all register names.
+ * This symbol is prefixed to all register names.
  */
 #define __REGISTER_PREFIX__
 #endif
@@ -95,8 +98,9 @@
 #define BEGIN_DATA
 /** This macro is used to denote the end of a data section. */
 #define END_DATA
-/** This macro is used to denote the beginning of the
- *  unitialized data section.
+/**
+ * This macro is used to denote the beginning of the
+ * unitialized data section.
  */
 #define BEGIN_BSS
 /** This macro is used to denote the end of the unitialized data section.  */
@@ -105,18 +109,18 @@
 #define END
 
 /**
- *  This macro is used to declare a public global symbol.
+ * This macro is used to declare a public global symbol.
  *
- *  @note This must be tailored for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
  */
 #define PUBLIC(sym) .globl SYM (sym)
 
 /**
- *  This macro is used to prototype a public global symbol.
+ * This macro is used to prototype a public global symbol.
  *
- *  @note This must be tailored for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
  */
 #define EXTERN(sym) .globl SYM (sym)
 
diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h b/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h
index 3c5bf7b3ef..7b4a41ac05 100644
--- a/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h
+++ b/cpukit/score/cpu/bfin/rtems/bfin/bf52x.h
@@ -1,13 +1,17 @@
 /**
- *@file bf52x.h
+ * @file
  *
- *  This file defines basic MMR for the Blackfin 52x CPU.
- *  The MMR have been taken from the ADSP-BF52x Blackfin Processor
- *  Hardware Reference from Analog Devices. Mentioned Chapters
- *  refer to this Documentation.
+ * @brief Basic MMR for the Blackfin 52x CPU
  *
- *	Based on bf533.h
+ * This file defines basic MMR for the Blackfin 52x CPU.
+ * The MMR have been taken from the ADSP-BF52x Blackfin Processor
+ * Hardware Reference from Analog Devices. Mentioned Chapters
+ * refer to this Documentation.
  *
+ * Based on bf533.h
+ */
+
+/*
  *  COPYRIGHT (c) 2006.
  *  Atos Automacao Industrial LTDA.
  *             modified by Alain Schaefer <alain.schaefer@easc.ch>
@@ -18,11 +22,8 @@
  *  http://www.rtems.com/license/LICENSE.
  *
  *
- * @author    Rohan Kangralkar, ECE Department Northeastern University
- * @date	  02/15/2011
- *
- * HISTORY:
- *
+ * Author:    Rohan Kangralkar, ECE Department Northeastern University
+ * Date:	  02/15/2011
  */
 
 #ifndef _RTEMS_BFIN_52x_H
diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bf533.h b/cpukit/score/cpu/bfin/rtems/bfin/bf533.h
index 005a6fbb81..3ebff2cd90 100644
--- a/cpukit/score/cpu/bfin/rtems/bfin/bf533.h
+++ b/cpukit/score/cpu/bfin/rtems/bfin/bf533.h
@@ -1,14 +1,18 @@
-/*  bfin.h
+/**
+ * @file
  *
- *  This file defines basic MMR for the Blackfin 531/532/533 CPU.
- *  The MMR have been taken from the ADSP-BF533 Blackfin Processor
- *  Hardware Reference from Analog Devices. Mentioned Chapters
- *  refer to this Documentation.
+ * @brief Basic MMR for the Blackfin 531/532/533 CPU
  *
- *  The Blackfins MMRs are divided into core MMRs (0xFFE0 0000–0xFFFF FFFF)
- *  and System MMRs (0xFFC0 0000–0xFFE0 0000). The core MMRs are defined
- *  in bfin.h which is included.
+ * This file defines basic MMR for the Blackfin 531/532/533 CPU.
+ * The MMR have been taken from the ADSP-BF533 Blackfin Processor
+ * Hardware Reference from Analog Devices. Mentioned Chapters
+ * refer to this Documentation.
  *
+ * The Blackfins MMRs are divided into core MMRs (0xFFE0 0000–0xFFFF FFFF)
+ * and System MMRs (0xFFC0 0000–0xFFE0 0000). The core MMRs are defined
+ * in bfin.h which is included.
+ */
+/*
  *  COPYRIGHT (c) 2006.
  *  Atos Automacao Industrial LTDA.
  *             modified by Alain Schaefer <alain.schaefer@easc.ch>
diff --git a/cpukit/score/cpu/bfin/rtems/bfin/bfin.h b/cpukit/score/cpu/bfin/rtems/bfin/bfin.h
index f3d6341d5c..ad7631d054 100644
--- a/cpukit/score/cpu/bfin/rtems/bfin/bfin.h
+++ b/cpukit/score/cpu/bfin/rtems/bfin/bfin.h
@@ -1,8 +1,12 @@
-/*  bfin.h
+/**
+ * @file
  *
- *  This file defines Macros for MMR register common to all Blackfin
- *  Processors.
+ * @brief Macros for MMR register common to all Blackfin Processors
  *
+ * This file defines Macros for MMR register common to all Blackfin
+ * Processors.
+ */
+/*
  *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
  *             modified by Alain Schaefer <alain.schaefer@easc.ch>
  *                     and Antonio Giovanini <antonio@atos.com.br>
diff --git a/cpukit/score/cpu/bfin/rtems/score/bfin.h b/cpukit/score/cpu/bfin/rtems/score/bfin.h
index 9eda79fd2d..2907840680 100644
--- a/cpukit/score/cpu/bfin/rtems/score/bfin.h
+++ b/cpukit/score/cpu/bfin/rtems/score/bfin.h
@@ -1,10 +1,16 @@
-/*  bfin.h
+/**
+ * @file
  *
- *  This file sets up basic CPU dependency settings based on
- *  compiler settings.  For example, it can determine if
- *  floating point is available.  This particular implementation
- *  is specified to the Blackfin port.
+ * @brief Blackfin Set up Basic CPU Dependency Settings Based on
+ * Compiler Settings
  *
+ * This file sets up basic CPU dependency settings based on
+ * compiler settings.  For example, it can determine if
+ * floating point is available.  This particular implementation
+ * is specified to the Blackfin port.
+ */
+
+/*
  *
  *  COPYRIGHT (c) 1989-2006.
  *  On-Line Applications Research Corporation (OAR).
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu.h b/cpukit/score/cpu/bfin/rtems/score/cpu.h
index f6fab7543b..1b265276ba 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/cpu.h
+ * @file
+ *
+ * @brief Blackfin CPU Department Source
+ *
+ * This include file contains information pertaining to the Blackfin
+ * processor.
  */
 
 /*
- *  This include file contains information pertaining to the Blackfin
- *  processor.
- *
  *  COPYRIGHT (c) 1989-2006.
  *  On-Line Applications Research Corporation (OAR).
  *  adapted to Blackfin by Alain Schaefer <alain.schaefer@easc.ch>
@@ -29,77 +31,77 @@ extern "C" {
 /* conditional compilation parameters */
 
 /**
- *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ * Should the calls to @ref _Thread_Enable_dispatch be inlined?
  *
- *  If TRUE, then they are inlined.
- *  If FALSE, then a subroutine call is made.
+ * If TRUE, then they are inlined.
+ * If FALSE, then a subroutine call is made.
  *
- *  This conditional is an example of the classic trade-off of size
- *  versus speed.  Inlining the call (TRUE) typically increases the
- *  size of RTEMS while speeding up the enabling of dispatching.
+ * This conditional is an example of the classic trade-off of size
+ * versus speed.  Inlining the call (TRUE) typically increases the
+ * size of RTEMS while speeding up the enabling of dispatching.
  *
- *  @note In general, the @ref _Thread_Dispatch_disable_level will
- *  only be 0 or 1 unless you are in an interrupt handler and that
- *  interrupt handler invokes the executive.]  When not inlined
- *  something calls @ref _Thread_Enable_dispatch which in turns calls
- *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
- *  one subroutine call is avoided entirely.
+ * @note In general, the @ref _Thread_Dispatch_disable_level will
+ * only be 0 or 1 unless you are in an interrupt handler and that
+ * interrupt handler invokes the executive.]  When not inlined
+ * something calls @ref _Thread_Enable_dispatch which in turns calls
+ * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
+ * one subroutine call is avoided entirely.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INLINE_ENABLE_DISPATCH       FALSE
 
 /**
- *  Should the body of the search loops in _Thread_queue_Enqueue_priority
- *  be unrolled one time?  In unrolled each iteration of the loop examines
- *  two "nodes" on the chain being searched.  Otherwise, only one node
- *  is examined per iteration.
+ * Should the body of the search loops in _Thread_queue_Enqueue_priority
+ * be unrolled one time?  In unrolled each iteration of the loop examines
+ * two "nodes" on the chain being searched.  Otherwise, only one node
+ * is examined per iteration.
  *
- *  If TRUE, then the loops are unrolled.
- *  If FALSE, then the loops are not unrolled.
+ * If TRUE, then the loops are unrolled.
+ * If FALSE, then the loops are not unrolled.
  *
- *  The primary factor in making this decision is the cost of disabling
- *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- *  body of the loop.  On some CPUs, the flash is more expensive than
- *  one iteration of the loop body.  In this case, it might be desirable
- *  to unroll the loop.  It is important to note that on some CPUs, this
- *  code is the longest interrupt disable period in RTEMS.  So it is
- *  necessary to strike a balance when setting this parameter.
+ * The primary factor in making this decision is the cost of disabling
+ * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ * body of the loop.  On some CPUs, the flash is more expensive than
+ * one iteration of the loop body.  In this case, it might be desirable
+ * to unroll the loop.  It is important to note that on some CPUs, this
+ * code is the longest interrupt disable period in RTEMS.  So it is
+ * necessary to strike a balance when setting this parameter.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
 
 /**
- *  Does RTEMS manage a dedicated interrupt stack in software?
+ * Does RTEMS manage a dedicated interrupt stack in software?
  *
- *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
- *  If FALSE, nothing is done.
+ * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ * If FALSE, nothing is done.
  *
- *  If the CPU supports a dedicated interrupt stack in hardware,
- *  then it is generally the responsibility of the BSP to allocate it
- *  and set it up.
+ * If the CPU supports a dedicated interrupt stack in hardware,
+ * then it is generally the responsibility of the BSP to allocate it
+ * and set it up.
  *
- *  If the CPU does not support a dedicated interrupt stack, then
- *  the porter has two options: (1) execute interrupts on the
- *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
- *  interrupt stack.
+ * If the CPU does not support a dedicated interrupt stack, then
+ * the porter has two options: (1) execute interrupts on the
+ * stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ * interrupt stack.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
 
@@ -130,84 +132,84 @@ extern "C" {
 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
 
 /**
- *  Does this CPU have hardware support for a dedicated interrupt stack?
+ * Does this CPU have hardware support for a dedicated interrupt stack?
  *
- *  If TRUE, then it must be installed during initialization.
- *  If FALSE, then no installation is performed.
+ * If TRUE, then it must be installed during initialization.
+ * If FALSE, then no installation is performed.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
 
 /**
- *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
  *
- *  If TRUE, then the memory is allocated during initialization.
- *  If FALSE, then the memory is allocated during initialization.
+ * If TRUE, then the memory is allocated during initialization.
+ * If FALSE, then the memory is allocated during initialization.
  *
- *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
 
 /**
- *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector
- *  number (0)?
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ISR_PASSES_FRAME_POINTER 1
 
 /**
- *  @def CPU_HARDWARE_FP
+ * @def CPU_HARDWARE_FP
  *
- *  Does the CPU have hardware floating point?
+ * Does the CPU have hardware floating point?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
  *
- *  If there is a FP coprocessor such as the i387 or mc68881, then
- *  the answer is TRUE.
+ * If there is a FP coprocessor such as the i387 or mc68881, then
+ * the answer is TRUE.
  *
- *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
- *  It indicates whether or not this CPU model has FP support.  For
- *  example, it would be possible to have an i386_nofp CPU model
- *  which set this to false to indicate that you have an i386 without
- *  an i387 and wish to leave floating point support out of RTEMS.
+ * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
+ * It indicates whether or not this CPU model has FP support.  For
+ * example, it would be possible to have an i386_nofp CPU model
+ * which set this to false to indicate that you have an i386 without
+ * an i387 and wish to leave floating point support out of RTEMS.
  */
 
 /**
- *  @def CPU_SOFTWARE_FP
+ * @def CPU_SOFTWARE_FP
  *
- *  Does the CPU have no hardware floating point and GCC provides a
- *  software floating point implementation which must be context
- *  switched?
+ * Does the CPU have no hardware floating point and GCC provides a
+ * software floating point implementation which must be context
+ * switched?
  *
- *  This feature conditional is used to indicate whether or not there
- *  is software implemented floating point that must be context
- *  switched.  The determination of whether or not this applies
- *  is very tool specific and the state saved/restored is also
- *  compiler specific.
+ * This feature conditional is used to indicate whether or not there
+ * is software implemented floating point that must be context
+ * switched.  The determination of whether or not this applies
+ * is very tool specific and the state saved/restored is also
+ * compiler specific.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if ( BLACKFIN_CPU_HAS_FPU == 1 )
 #define CPU_HARDWARE_FP     TRUE
@@ -217,192 +219,194 @@ extern "C" {
 #define CPU_SOFTWARE_FP     FALSE
 
 /**
- *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
  *
- *  So far, the only CPUs in which this option has been used are the
- *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
- *  gcc both implicitly used the floating point registers to perform
- *  integer multiplies.  Similarly, the PowerPC port of gcc has been
- *  seen to allocate floating point local variables and touch the FPU
- *  even when the flow through a subroutine (like vfprintf()) might
- *  not use floating point formats.
+ * So far, the only CPUs in which this option has been used are the
+ * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
+ * gcc both implicitly used the floating point registers to perform
+ * integer multiplies.  Similarly, the PowerPC port of gcc has been
+ * seen to allocate floating point local variables and touch the FPU
+ * even when the flow through a subroutine (like vfprintf()) might
+ * not use floating point formats.
  *
- *  If a function which you would not think utilize the FP unit DOES,
- *  then one can not easily predict which tasks will use the FP hardware.
- *  In this case, this option should be TRUE.
+ * If a function which you would not think utilize the FP unit DOES,
+ * then one can not easily predict which tasks will use the FP hardware.
+ * In this case, this option should be TRUE.
  *
- *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALL_TASKS_ARE_FP     FALSE
 
 /**
- *  Should the IDLE task have a floating point context?
+ * Should the IDLE task have a floating point context?
  *
- *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- *  and it has a floating point context which is switched in and out.
- *  If FALSE, then the IDLE task does not have a floating point context.
+ * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ * and it has a floating point context which is switched in and out.
+ * If FALSE, then the IDLE task does not have a floating point context.
  *
- *  Setting this to TRUE negatively impacts the time required to preempt
- *  the IDLE task from an interrupt because the floating point context
- *  must be saved as part of the preemption.
+ * Setting this to TRUE negatively impacts the time required to preempt
+ * the IDLE task from an interrupt because the floating point context
+ * must be saved as part of the preemption.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_IDLE_TASK_IS_FP      FALSE
 
 /**
- *  Should the saving of the floating point registers be deferred
- *  until a context switch is made to another different floating point
- *  task?
+ * Should the saving of the floating point registers be deferred
+ * until a context switch is made to another different floating point
+ * task?
  *
- *  If TRUE, then the floating point context will not be stored until
- *  necessary.  It will remain in the floating point registers and not
- *  disturned until another floating point task is switched to.
+ * If TRUE, then the floating point context will not be stored until
+ * necessary.  It will remain in the floating point registers and not
+ * disturned until another floating point task is switched to.
  *
- *  If FALSE, then the floating point context is saved when a floating
- *  point task is switched out and restored when the next floating point
- *  task is restored.  The state of the floating point registers between
- *  those two operations is not specified.
+ * If FALSE, then the floating point context is saved when a floating
+ * point task is switched out and restored when the next floating point
+ * task is restored.  The state of the floating point registers between
+ * those two operations is not specified.
  *
- *  If the floating point context does NOT have to be saved as part of
- *  interrupt dispatching, then it should be safe to set this to TRUE.
+ * If the floating point context does NOT have to be saved as part of
+ * interrupt dispatching, then it should be safe to set this to TRUE.
  *
- *  Setting this flag to TRUE results in using a different algorithm
- *  for deciding when to save and restore the floating point context.
- *  The deferred FP switch algorithm minimizes the number of times
- *  the FP context is saved and restored.  The FP context is not saved
- *  until a context switch is made to another, different FP task.
- *  Thus in a system with only one FP task, the FP context will never
- *  be saved or restored.
+ * Setting this flag to TRUE results in using a different algorithm
+ * for deciding when to save and restore the floating point context.
+ * The deferred FP switch algorithm minimizes the number of times
+ * the FP context is saved and restored.  The FP context is not saved
+ * until a context switch is made to another, different FP task.
+ * Thus in a system with only one FP task, the FP context will never
+ * be saved or restored.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_USE_DEFERRED_FP_SWITCH       TRUE
 
 /**
- *  Does this port provide a CPU dependent IDLE task implementation?
+ * Does this port provide a CPU dependent IDLE task implementation?
  *
- *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
- *  must be provided and is the default IDLE thread body instead of
- *  @ref _CPU_Thread_Idle_body.
+ * If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ * must be provided and is the default IDLE thread body instead of
+ * @ref _CPU_Thread_Idle_body.
  *
- *  If FALSE, then use the generic IDLE thread body if the BSP does
- *  not provide one.
+ * If FALSE, then use the generic IDLE thread body if the BSP does
+ * not provide one.
  *
- *  This is intended to allow for supporting processors which have
- *  a low power or idle mode.  When the IDLE thread is executed, then
- *  the CPU can be powered down.
+ * This is intended to allow for supporting processors which have
+ * a low power or idle mode.  When the IDLE thread is executed, then
+ * the CPU can be powered down.
  *
- *  The order of precedence for selecting the IDLE thread body is:
+ * The order of precedence for selecting the IDLE thread body is:
  *
- *    -#  BSP provided
- *    -#  CPU dependent (if provided)
- *    -#  generic (if no BSP and no CPU dependent)
+ *   -#  BSP provided
+ *   -#  CPU dependent (if provided)
+ *   -#  generic (if no BSP and no CPU dependent)
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
 
 /**
- *  Does the stack grow up (toward higher addresses) or down
- *  (toward lower addresses)?
+ * Does the stack grow up (toward higher addresses) or down
+ * (toward lower addresses)?
  *
- *  If TRUE, then the grows upward.
- *  If FALSE, then the grows toward smaller addresses.
+ * If TRUE, then the grows upward.
+ * If FALSE, then the grows toward smaller addresses.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_GROWS_UP               FALSE
 
 /**
- *  The following is the variable attribute used to force alignment
- *  of critical RTEMS structures.  On some processors it may make
- *  sense to have these aligned on tighter boundaries than
- *  the minimum requirements of the compiler in order to have as
- *  much of the critical data area as possible in a cache line.
+ * The following is the variable attribute used to force alignment
+ * of critical RTEMS structures.  On some processors it may make
+ * sense to have these aligned on tighter boundaries than
+ * the minimum requirements of the compiler in order to have as
+ * much of the critical data area as possible in a cache line.
  *
- *  The placement of this macro in the declaration of the variables
- *  is based on the syntactically requirements of the GNU C
- *  "__attribute__" extension.  For example with GNU C, use
- *  the following to force a structures to a 32 byte boundary.
+ * The placement of this macro in the declaration of the variables
+ * is based on the syntactically requirements of the GNU C
+ * "__attribute__" extension.  For example with GNU C, use
+ * the following to force a structures to a 32 byte boundary.
  *
- *      __attribute__ ((aligned (32)))
+ *     __attribute__ ((aligned (32)))
  *
- *  @note Currently only the Priority Bit Map table uses this feature.
- *        To benefit from using this, the data must be heavily
- *        used so it will stay in the cache and used frequently enough
- *        in the executive to justify turning this on.
+ * @note Currently only the Priority Bit Map table uses this feature.
+ *       To benefit from using this, the data must be heavily
+ *       used so it will stay in the cache and used frequently enough
+ *       in the executive to justify turning this on.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STRUCTURE_ALIGNMENT
 
 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
 
 /**
- *  @defgroup CPUEndian Processor Dependent Endianness Support
+ * @defgroup CPUEndian Processor Dependent Endianness Support
+ *
+ * This group assists in issues related to processor endianness.
  *
- *  This group assists in issues related to processor endianness.
  */
+/**@{**/
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_LITTLE_ENDIAN
+ * @see CPU_LITTLE_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_BIG_ENDIAN                           FALSE
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_BIG_ENDIAN
+ * @see CPU_BIG_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_LITTLE_ENDIAN                        TRUE
 
+/** @} */
+
 /**
- *  @ingroup CPUInterrupt
- *  The following defines the number of bits actually used in the
- *  interrupt field of the task mode.  How those bits map to the
- *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ * @ingroup CPUInterrupt
+ * The following defines the number of bits actually used in the
+ * interrupt field of the task mode.  How those bits map to the
+ * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_MODES_INTERRUPT_MASK   0x00000001
 
@@ -419,52 +423,52 @@ extern "C" {
 /**
  * @defgroup CPUContext Processor Dependent Context Management
  *
- *  From the highest level viewpoint, there are 2 types of context to save.
+ * From the highest level viewpoint, there are 2 types of context to save.
  *
- *     -# Interrupt registers to save
- *     -# Task level registers to save
+ *    -# Interrupt registers to save
+ *    -# Task level registers to save
  *
- *  Since RTEMS handles integer and floating point contexts separately, this
- *  means we have the following 3 context items:
+ * Since RTEMS handles integer and floating point contexts separately, this
+ * means we have the following 3 context items:
  *
- *     -# task level context stuff::  Context_Control
- *     -# floating point task stuff:: Context_Control_fp
- *     -# special interrupt level context :: CPU_Interrupt_frame
+ *    -# task level context stuff::  Context_Control
+ *    -# floating point task stuff:: Context_Control_fp
+ *    -# special interrupt level context :: CPU_Interrupt_frame
  *
- *  On some processors, it is cost-effective to save only the callee
- *  preserved registers during a task context switch.  This means
- *  that the ISR code needs to save those registers which do not
- *  persist across function calls.  It is not mandatory to make this
- *  distinctions between the caller/callee saves registers for the
- *  purpose of minimizing context saved during task switch and on interrupts.
- *  If the cost of saving extra registers is minimal, simplicity is the
- *  choice.  Save the same context on interrupt entry as for tasks in
- *  this case.
+ * On some processors, it is cost-effective to save only the callee
+ * preserved registers during a task context switch.  This means
+ * that the ISR code needs to save those registers which do not
+ * persist across function calls.  It is not mandatory to make this
+ * distinctions between the caller/callee saves registers for the
+ * purpose of minimizing context saved during task switch and on interrupts.
+ * If the cost of saving extra registers is minimal, simplicity is the
+ * choice.  Save the same context on interrupt entry as for tasks in
+ * this case.
  *
- *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- *  care should be used in designing the context area.
+ * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ * care should be used in designing the context area.
  *
- *  On some CPUs with hardware floating point support, the Context_Control_fp
- *  structure will not be used or it simply consist of an array of a
- *  fixed number of bytes.   This is done when the floating point context
- *  is dumped by a "FP save context" type instruction and the format
- *  is not really defined by the CPU.  In this case, there is no need
- *  to figure out the exact format -- only the size.  Of course, although
- *  this is enough information for RTEMS, it is probably not enough for
- *  a debugger such as gdb.  But that is another problem.
+ * On some CPUs with hardware floating point support, the Context_Control_fp
+ * structure will not be used or it simply consist of an array of a
+ * fixed number of bytes.   This is done when the floating point context
+ * is dumped by a "FP save context" type instruction and the format
+ * is not really defined by the CPU.  In this case, there is no need
+ * to figure out the exact format -- only the size.  Of course, although
+ * this is enough information for RTEMS, it is probably not enough for
+ * a debugger such as gdb.  But that is another problem.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
+/**@{**/
 
 #ifndef ASM
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the minimal set of integer and processor state registers
- *  that must be saved during a voluntary context switch from one thread
- *  to another.
+ * This defines the minimal set of integer and processor state registers
+ * that must be saved during a voluntary context switch from one thread
+ * to another.
  */
 
 /* make sure this stays in sync with the assembly function
@@ -490,9 +494,8 @@ typedef struct {
   (_context)->register_sp
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the complete set of floating point registers that must
- *  be saved during any context switch from one thread to another.
+ * This defines the complete set of floating point registers that must
+ * be saved during any context switch from one thread to another.
  */
 typedef struct {
     /* FPU registers are listed here */
@@ -500,49 +503,51 @@ typedef struct {
 } Context_Control_fp;
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the set of integer and processor state registers that must
- *  be saved during an interrupt.  This set does not include any which are
- *  in @ref Context_Control.
+ * This defines the set of integer and processor state registers that must
+ * be saved during an interrupt.  This set does not include any which are
+ * in @ref Context_Control.
  */
 typedef struct {
     /** This field is a hint that a port will have a number of integer
-     *  registers that need to be saved when an interrupt occurs or
-     *  when a context switch occurs at the end of an ISR.
+     * registers that need to be saved when an interrupt occurs or
+     * when a context switch occurs at the end of an ISR.
      */
     /*uint32_t   special_interrupt_register;*/
 } CPU_Interrupt_frame;
 
 /**
- *  This variable is optional.  It is used on CPUs on which it is difficult
- *  to generate an "uninitialized" FP context.  It is filled in by
- *  @ref _CPU_Initialize and copied into the task's FP context area during
- *  @ref _CPU_Context_Initialize.
+ * This variable is optional.  It is used on CPUs on which it is difficult
+ * to generate an "uninitialized" FP context.  It is filled in by
+ * @ref _CPU_Initialize and copied into the task's FP context area during
+ * @ref _CPU_Context_Initialize.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 
+/** @} */
+
 /**
- *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ * @defgroup CPUInterrupt Processor Dependent Interrupt Management
  *
- *  On some CPUs, RTEMS supports a software managed interrupt stack.
- *  This stack is allocated by the Interrupt Manager and the switch
- *  is performed in @ref _ISR_Handler.  These variables contain pointers
- *  to the lowest and highest addresses in the chunk of memory allocated
- *  for the interrupt stack.  Since it is unknown whether the stack
- *  grows up or down (in general), this give the CPU dependent
- *  code the option of picking the version it wants to use.
+ * On some CPUs, RTEMS supports a software managed interrupt stack.
+ * This stack is allocated by the Interrupt Manager and the switch
+ * is performed in @ref _ISR_Handler.  These variables contain pointers
+ * to the lowest and highest addresses in the chunk of memory allocated
+ * for the interrupt stack.  Since it is unknown whether the stack
+ * grows up or down (in general), this give the CPU dependent
+ * code the option of picking the version it wants to use.
  *
- *  @note These two variables are required if the macro
- *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ * @note These two variables are required if the macro
+ *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
+/**@{**/
 
 /*
  *  Nothing prevents the porter from declaring more CPU specific variables.
@@ -555,133 +560,135 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 /* XXX: if needed, put more variables here */
 
 /**
- *  @ingroup CPUContext
- *  The size of the floating point context area.  On some CPUs this
- *  will not be a "sizeof" because the format of the floating point
- *  area is not defined -- only the size is.  This is usually on
- *  CPUs with a "floating point save context" instruction.
+ * @ingroup CPUContext
+ * The size of the floating point context area.  On some CPUs this
+ * will not be a "sizeof" because the format of the floating point
+ * area is not defined -- only the size is.  This is usually on
+ * CPUs with a "floating point save context" instruction.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
 
 #endif /* ASM */
 
 /**
- *  Amount of extra stack (above minimum stack size) required by
- *  MPCI receive server thread.  Remember that in a multiprocessor
- *  system this thread must exist and be able to process all directives.
+ * Amount of extra stack (above minimum stack size) required by
+ * MPCI receive server thread.  Remember that in a multiprocessor
+ * system this thread must exist and be able to process all directives.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
 
 /**
- *  @ingroup CPUInterrupt
- *  This defines the number of entries in the @ref _ISR_Vector_table managed
- *  by RTEMS.
+ * @ingroup CPUInterrupt
+ * This defines the number of entries in the @ref _ISR_Vector_table managed
+ * by RTEMS.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      16
 
 /**
- *  @ingroup CPUInterrupt
- *  This defines the highest interrupt vector number for this port.
+ * @ingroup CPUInterrupt
+ * This defines the highest interrupt vector number for this port.
  */
 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
 /**
- *  @ingroup CPUInterrupt
- *  This is defined if the port has a special way to report the ISR nesting
- *  level.  Most ports maintain the variable @a _ISR_Nest_level.
+ * @ingroup CPUInterrupt
+ * This is defined if the port has a special way to report the ISR nesting
+ * level.  Most ports maintain the variable @a _ISR_Nest_level.
  */
 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
+/** @} */
+
 /**
- *  @ingroup CPUContext
- *  Should be large enough to run all RTEMS tests.  This ensures
- *  that a "reasonable" small application should not have any problems.
+ * @ingroup CPUContext
+ * Should be large enough to run all RTEMS tests.  This ensures
+ * that a "reasonable" small application should not have any problems.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_MINIMUM_SIZE          (1024*8)
 
 #define CPU_SIZEOF_POINTER 4
 
 /**
- *  CPU's worst alignment requirement for data types on a byte boundary.  This
- *  alignment does not take into account the requirements for the stack.
+ * CPU's worst alignment requirement for data types on a byte boundary.  This
+ * alignment does not take into account the requirements for the stack.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALIGNMENT              8
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  heap handler.  This alignment requirement may be stricter than that
- *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
- *  common for the heap to follow the same alignment requirement as
- *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
- *  the heap, then this should be set to @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for the
+ * heap handler.  This alignment requirement may be stricter than that
+ * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
+ * common for the heap to follow the same alignment requirement as
+ * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
+ * the heap, then this should be set to @ref CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2 although it should be
- *         a multiple of 2 greater than or equal to 2.  The requirement
- *         to be a multiple of 2 is because the heap uses the least
- *         significant field of the front and back flags to indicate
- *         that a block is in use or free.  So you do not want any odd
- *         length blocks really putting length data in that bit.
+ * @note  This does not have to be a power of 2 although it should be
+ *        a multiple of 2 greater than or equal to 2.  The requirement
+ *        to be a multiple of 2 is because the heap uses the least
+ *        significant field of the front and back flags to indicate
+ *        that a block is in use or free.  So you do not want any odd
+ *        length blocks really putting length data in that bit.
  *
- *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
- *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
- *         elements allocated from the heap meet all restrictions.
+ *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ *        elements allocated from the heap meet all restrictions.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for memory
- *  buffers allocated by the partition manager.  This alignment requirement
- *  may be stricter than that for the data types alignment specified by
- *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
- *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
- *  strict enough for the partition, then this should be set to
- *  @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for memory
+ * buffers allocated by the partition manager.  This alignment requirement
+ * may be stricter than that for the data types alignment specified by
+ * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
+ * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
+ * strict enough for the partition, then this should be set to
+ * @ref CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than @ref CPU_ALIGNMENT.
+ * @note  This does not have to be a power of 2.  It does have to
+ *        be greater or equal to than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  stack.  This alignment requirement may be stricter than that for the
- *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
- *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
- *  set to 0.
+ * This number corresponds to the byte alignment requirement for the
+ * stack.  This alignment requirement may be stricter than that for the
+ * data types alignment specified by @ref CPU_ALIGNMENT.  If the
+ * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
+ * set to 0.
  *
- *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
+ * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_ALIGNMENT        8
 
@@ -690,25 +697,28 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
  */
 
 /**
- *  @ingroup CPUInterrupt
- *  Support routine to initialize the RTEMS vector table after it is allocated.
+ * @addtogroup CPUInterrupt
+ */
+/**@{**/
+
+/**
+ * Support routine to initialize the RTEMS vector table after it is allocated.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Initialize_vectors()
 
 /**
- *  @ingroup CPUInterrupt
- *  Disable all interrupts for an RTEMS critical section.  The previous
- *  level is returned in @a _isr_cookie.
+ * Disable all interrupts for an RTEMS critical section.  The previous
+ * level is returned in @a _isr_cookie.
  *
- *  @param[out] _isr_cookie will contain the previous level cookie
+ * @param[out] _isr_cookie will contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Disable( _level ) \
   {                                     \
@@ -717,33 +727,31 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 
 
 /**
- *  @ingroup CPUInterrupt
- *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- *  This indicates the end of an RTEMS critical section.  The parameter
- *  @a _isr_cookie is not modified.
+ * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ * This indicates the end of an RTEMS critical section.  The parameter
+ * @a _isr_cookie is not modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Enable( _level ) { \
     __asm__ __volatile__ ("sti %0; csync \n" : : "d" (_level) );   \
   }
 
 /**
- *  @ingroup CPUInterrupt
- *  This temporarily restores the interrupt to @a _isr_cookie before immediately
- *  disabling them again.  This is used to divide long RTEMS critical
- *  sections into two or more parts.  The parameter @a _isr_cookie is not
- *  modified.
+ * This temporarily restores the interrupt to @a _isr_cookie before immediately
+ * disabling them again.  This is used to divide long RTEMS critical
+ * sections into two or more parts.  The parameter @a _isr_cookie is not
+ * modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Flash( _level ) { \
     __asm__ __volatile__ ("sti %0; csync; cli r0; csync" \
@@ -751,21 +759,19 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
   }
 
 /**
- *  @ingroup CPUInterrupt
+ * This routine and @ref _CPU_ISR_Get_level
+ * Map the interrupt level in task mode onto the hardware that the CPU
+ * actually provides.  Currently, interrupt levels which do not
+ * map onto the CPU in a generic fashion are undefined.  Someday,
+ * it would be nice if these were "mapped" by the application
+ * via a callout.  For example, m68k has 8 levels 0 - 7, levels
+ * 8 - 255 would be available for bsp/application specific meaning.
+ * This could be used to manage a programmable interrupt controller
+ * via the rtems_task_mode directive.
  *
- *  This routine and @ref _CPU_ISR_Get_level
- *  Map the interrupt level in task mode onto the hardware that the CPU
- *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a generic fashion are undefined.  Someday,
- *  it would be nice if these were "mapped" by the application
- *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
- *  8 - 255 would be available for bsp/application specific meaning.
- *  This could be used to manage a programmable interrupt controller
- *  via the rtems_task_mode directive.
+ * Port Specific Information:
  *
- *  Port Specific Information:
- *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Set_level( _new_level ) \
   { \
@@ -775,52 +781,53 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 #ifndef ASM
 
 /**
- *  @ingroup CPUInterrupt
- *  Return the current interrupt disable level for this task in
- *  the format used by the interrupt level portion of the task mode.
+ * Return the current interrupt disable level for this task in
+ * the format used by the interrupt level portion of the task mode.
  *
- *  @note This routine usually must be implemented as a subroutine.
+ * @note This routine usually must be implemented as a subroutine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
 
+/** @} */
+
 /* Context handler macros */
 
 /**
- *  @ingroup CPUContext
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
- *
- *     - setting a starting address
- *     - preparing the stack
- *     - preparing the stack and frame pointers
- *     - setting the proper interrupt level in the context
- *     - initializing the floating point context
- *
- *  This routine generally does not set any unnecessary register
- *  in the context.  The state of the "general data" registers is
- *  undefined at task start time.
- *
- *  @param[in] _the_context is the context structure to be initialized
- *  @param[in] _stack_base is the lowest physical address of this task's stack
- *  @param[in] _size is the size of this task's stack
- *  @param[in] _isr is the interrupt disable level
- *  @param[in] _entry_point is the thread's entry point.  This is
- *         always @a _Thread_Handler
- *  @param[in] _is_fp is TRUE if the thread is to be a floating
- *        point thread.  This is typically only used on CPUs where the
- *        FPU may be easily disabled by software such as on the SPARC
- *        where the PSR contains an enable FPU bit.
- *
- *  Port Specific Information:
- *
- *  See implementation in cpu.c
+ * @ingroup CPUContext
+ * Initialize the context to a state suitable for starting a
+ * task after a context restore operation.  Generally, this
+ * involves:
+ *
+ *    - setting a starting address
+ *    - preparing the stack
+ *    - preparing the stack and frame pointers
+ *    - setting the proper interrupt level in the context
+ *    - initializing the floating point context
+ *
+ * This routine generally does not set any unnecessary register
+ * in the context.  The state of the "general data" registers is
+ * undefined at task start time.
+ *
+ * @param[in] _the_context is the context structure to be initialized
+ * @param[in] _stack_base is the lowest physical address of this task's stack
+ * @param[in] _size is the size of this task's stack
+ * @param[in] _isr is the interrupt disable level
+ * @param[in] _entry_point is the thread's entry point.  This is
+ *        always @a _Thread_Handler
+ * @param[in] _is_fp is TRUE if the thread is to be a floating
+ *       point thread.  This is typically only used on CPUs where the
+ *       FPU may be easily disabled by software such as on the SPARC
+ *       where the PSR contains an enable FPU bit.
+ *
+ * Port Specific Information:
+ *
+ * See implementation in cpu.c
  */
 void _CPU_Context_Initialize(
   Context_Control  *the_context,
@@ -832,65 +839,65 @@ void _CPU_Context_Initialize(
 );
 
 /**
- *  This routine is responsible for somehow restarting the currently
- *  executing task.  If you are lucky, then all that is necessary
- *  is restoring the context.  Otherwise, there will need to be
- *  a special assembly routine which does something special in this
- *  case.  For many ports, simply adding a label to the restore path
- *  of @ref _CPU_Context_switch will work.  On other ports, it may be
- *  possibly to load a few arguments and jump to the restore path. It will
- *  not work if restarting self conflicts with the stack frame
- *  assumptions of restoring a context.
+ * This routine is responsible for somehow restarting the currently
+ * executing task.  If you are lucky, then all that is necessary
+ * is restoring the context.  Otherwise, there will need to be
+ * a special assembly routine which does something special in this
+ * case.  For many ports, simply adding a label to the restore path
+ * of @ref _CPU_Context_switch will work.  On other ports, it may be
+ * possibly to load a few arguments and jump to the restore path. It will
+ * not work if restarting self conflicts with the stack frame
+ * assumptions of restoring a context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Restart_self( _the_context ) \
    _CPU_Context_restore( (_the_context) );
 
 /**
- *  @ingroup CPUContext
- *  The purpose of this macro is to allow the initial pointer into
- *  a floating point context area (used to save the floating point
- *  context) to be at an arbitrary place in the floating point
- *  context area.
+ * @ingroup CPUContext
+ * The purpose of this macro is to allow the initial pointer into
+ * a floating point context area (used to save the floating point
+ * context) to be at an arbitrary place in the floating point
+ * context area.
  *
- *  This is necessary because some FP units are designed to have
- *  their context saved as a stack which grows into lower addresses.
- *  Other FP units can be saved by simply moving registers into offsets
- *  from the base of the context area.  Finally some FP units provide
- *  a "dump context" instruction which could fill in from high to low
- *  or low to high based on the whim of the CPU designers.
+ * This is necessary because some FP units are designed to have
+ * their context saved as a stack which grows into lower addresses.
+ * Other FP units can be saved by simply moving registers into offsets
+ * from the base of the context area.  Finally some FP units provide
+ * a "dump context" instruction which could fill in from high to low
+ * or low to high based on the whim of the CPU designers.
  *
- *  @param[in] _base is the lowest physical address of the floating point
- *         context area
- *  @param[in] _offset is the offset into the floating point area
+ * @param[in] _base is the lowest physical address of the floating point
+ *        context area
+ * @param[in] _offset is the offset into the floating point area
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Fp_start( _base, _offset ) \
    ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
 
 /**
- *  This routine initializes the FP context area passed to it to.
- *  There are a few standard ways in which to initialize the
- *  floating point context.  The code included for this macro assumes
- *  that this is a CPU in which a "initial" FP context was saved into
- *  @a _CPU_Null_fp_context and it simply copies it to the destination
- *  context passed to it.
+ * This routine initializes the FP context area passed to it to.
+ * There are a few standard ways in which to initialize the
+ * floating point context.  The code included for this macro assumes
+ * that this is a CPU in which a "initial" FP context was saved into
+ * @a _CPU_Null_fp_context and it simply copies it to the destination
+ * context passed to it.
  *
- *  Other floating point context save/restore models include:
- *    -# not doing anything, and
- *    -# putting a "null FP status word" in the correct place in the FP context.
+ * Other floating point context save/restore models include:
+ *   -# not doing anything, and
+ *   -# putting a "null FP status word" in the correct place in the FP context.
  *
- *  @param[in] _destination is the floating point context area
+ * @param[in] _destination is the floating point context area
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Initialize_fp( _destination ) \
   { \
@@ -902,13 +909,13 @@ void _CPU_Context_Initialize(
 /* Fatal Error manager macros */
 
 /**
- *  This routine copies _error into a known place -- typically a stack
- *  location or a register, optionally disables interrupts, and
- *  halts/stops the CPU.
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Fatal_halt( _error ) \
   { \
@@ -925,68 +932,66 @@ void _CPU_Context_Initialize(
 /* Bitfield handler macros */
 
 /**
- *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
  *
- *  This set of routines are used to implement fast searches for
- *  the most important ready task.
+ * This set of routines are used to implement fast searches for
+ * the most important ready task.
  */
+/**@{**/
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the generic bitfield
- *  manipulation implementation.
+ * This definition is set to TRUE if the port uses the generic bitfield
+ * manipulation implementation.
  */
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the data tables provided
- *  by the generic bitfield manipulation implementation.
- *  This can occur when actually using the generic bitfield manipulation
- *  implementation or when implementing the same algorithm in assembly
- *  language for improved performance.  It is unlikely that a port will use
- *  the data if it has a bitfield scan instruction.
+ * This definition is set to TRUE if the port uses the data tables provided
+ * by the generic bitfield manipulation implementation.
+ * This can occur when actually using the generic bitfield manipulation
+ * implementation or when implementing the same algorithm in assembly
+ * language for improved performance.  It is unlikely that a port will use
+ * the data if it has a bitfield scan instruction.
  */
 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This routine sets @a _output to the bit number of the first bit
- *  set in @a _value.  @a _value is of CPU dependent type
- *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
- *  wide although only the 16 least significant bits will be used.
- *
- *  There are a number of variables in using a "find first bit" type
- *  instruction.
- *
- *    -# What happens when run on a value of zero?
- *    -# Bits may be numbered from MSB to LSB or vice-versa.
- *    -# The numbering may be zero or one based.
- *    -# The "find first bit" instruction may search from MSB or LSB.
- *
- *  RTEMS guarantees that (1) will never happen so it is not a concern.
- *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
- *  @ref _CPU_Priority_bits_index.  These three form a set of routines
- *  which must logically operate together.  Bits in the _value are
- *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
- *  The basic major and minor values calculated by @ref _Priority_Major
- *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
- *  to properly range between the values returned by the "find first bit"
- *  instruction.  This makes it possible for @ref _Priority_Get_highest to
- *  calculate the major and directly index into the minor table.
- *  This mapping is necessary to ensure that 0 (a high priority major/minor)
- *  is the first bit found.
- *
- *  This entire "find first bit" and mapping process depends heavily
- *  on the manner in which a priority is broken into a major and minor
- *  components with the major being the 4 MSB of a priority and minor
- *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
- *  to the lowest priority.
- *
- *  If your CPU does not have a "find first bit" instruction, then
- *  there are ways to make do without it.  Here are a handful of ways
- *  to implement this in software:
+ * This routine sets @a _output to the bit number of the first bit
+ * set in @a _value.  @a _value is of CPU dependent type
+ * @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
+ * wide although only the 16 least significant bits will be used.
+ *
+ * There are a number of variables in using a "find first bit" type
+ * instruction.
+ *
+ *   -# What happens when run on a value of zero?
+ *   -# Bits may be numbered from MSB to LSB or vice-versa.
+ *   -# The numbering may be zero or one based.
+ *   -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ * RTEMS guarantees that (1) will never happen so it is not a concern.
+ * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ * @ref _CPU_Priority_bits_index.  These three form a set of routines
+ * which must logically operate together.  Bits in the _value are
+ * set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ * The basic major and minor values calculated by @ref _Priority_Major
+ * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ * to properly range between the values returned by the "find first bit"
+ * instruction.  This makes it possible for @ref _Priority_Get_highest to
+ * calculate the major and directly index into the minor table.
+ * This mapping is necessary to ensure that 0 (a high priority major/minor)
+ * is the first bit found.
+ *
+ * This entire "find first bit" and mapping process depends heavily
+ * on the manner in which a priority is broken into a major and minor
+ * components with the major being the 4 MSB of a priority and minor
+ * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ * to the lowest priority.
+ *
+ * If your CPU does not have a "find first bit" instruction, then
+ * there are ways to make do without it.  Here are a handful of ways
+ * to implement this in software:
  *
 @verbatim
       - a series of 16 bit test instructions
@@ -1003,15 +1008,15 @@ void _CPU_Context_Initialize(
         _number += bit_set_table[ _value ]
 @endverbatim
 
- *    where bit_set_table[ 16 ] has values which indicate the first
- *      bit set
+ *   where bit_set_table[ 16 ] has values which indicate the first
+ *     bit set
  *
- *  @param[in] _value is the value to be scanned
- *  @param[in] _output is the first bit set
+ * @param[in] _value is the value to be scanned
+ * @param[in] _output is the first bit set
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
@@ -1024,14 +1029,16 @@ void _CPU_Context_Initialize(
 
 /* end of Bitfield handler macros */
 
+/** @} */
+
 /**
- *  This routine builds the mask which corresponds to the bit fields
- *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
- *  for that routine.
+ * This routine builds the mask which corresponds to the bit fields
+ * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
+ * for that routine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1041,17 +1048,17 @@ void _CPU_Context_Initialize(
 #endif
 
 /**
- *  @ingroup CPUBitfield
- *  This routine translates the bit numbers returned by
- *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
- *  a major or minor component of a priority.  See the discussion
- *  for that routine.
+ * @ingroup CPUBitfield
+ * This routine translates the bit numbers returned by
+ * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ * a major or minor component of a priority.  See the discussion
+ * for that routine.
  *
- *  @param[in] _priority is the major or minor number to translate
+ * @param[in] _priority is the major or minor number to translate
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1065,27 +1072,27 @@ void _CPU_Context_Initialize(
 /* functions */
 
 /**
- *  @brief CPU Initialize
- *  This routine performs CPU dependent initialization.
+ * @brief CPU initialize.
+ * This routine performs CPU dependent initialization.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Initialize(void);
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs a "raw" interrupt handler directly into the
- *  processor's vector table.
+ * @ingroup CPUInterrupt
+ * This routine installs a "raw" interrupt handler directly into the
+ * processor's vector table.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the raw ISR handler to install
- *  @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the raw ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
@@ -1094,16 +1101,16 @@ void _CPU_ISR_install_raw_handler(
 );
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs an interrupt vector.
+ * @ingroup CPUInterrupt
+ * This routine installs an interrupt vector.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the RTEMS ISR handler to install
- *  @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the RTEMS ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_ISR_install_vector(
   uint32_t    vector,
@@ -1112,40 +1119,44 @@ void _CPU_ISR_install_vector(
 );
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs the hardware interrupt stack pointer.
+ * @ingroup CPUInterrupt
+ * This routine installs the hardware interrupt stack pointer.
  *
- *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
- *         is TRUE.
+ * @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
+ *        is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Install_interrupt_stack( void );
 
 /**
- *  This routine is the CPU dependent IDLE thread body.
+ * This routine is the CPU dependent IDLE thread body.
  *
- *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
- *         is TRUE.
+ * @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
+ *        is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void *_CPU_Thread_Idle_body( uintptr_t ignored );
 
 /**
- *  @ingroup CPUContext
- *  This routine switches from the run context to the heir context.
+ * @addtogroup CPUContext
+ */
+/**@{**/
+
+/**
+ * This routine switches from the run context to the heir context.
  *
- *  @param[in] run points to the context of the currently executing task
- *  @param[in] heir points to the context of the heir task
+ * @param[in] run points to the context of the currently executing task
+ * @param[in] heir points to the context of the heir task
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_switch(
   Context_Control  *run,
@@ -1153,90 +1164,89 @@ void _CPU_Context_switch(
 );
 
 /**
- *  @ingroup CPUContext
- *  This routine is generally used only to restart self in an
- *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
+ * This routine is generally used only to restart self in an
+ * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
  *
- *  @param[in] new_context points to the context to be restored.
+ * @param[in] new_context points to the context to be restored.
  *
- *  @note May be unnecessary to reload some registers.
+ * @note May be unnecessary to reload some registers.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_restore(
   Context_Control *new_context
 ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
 
 /**
- *  @ingroup CPUContext
- *  This routine saves the floating point context passed to it.
+ * This routine saves the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
- *  point context area
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area
  *
- *  @return on output @a *fp_context_ptr will contain the address that
- *  should be used with @ref _CPU_Context_restore_fp to restore this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_restore_fp to restore this context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_save_fp(
   Context_Control_fp **fp_context_ptr
 );
 
 /**
- *  @ingroup CPUContext
- *  This routine restores the floating point context passed to it.
+ * This routine restores the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
- *  point context area to restore
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area to restore
  *
- *  @return on output @a *fp_context_ptr will contain the address that
- *  should be used with @ref _CPU_Context_save_fp to save this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_save_fp to save this context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_restore_fp(
   Context_Control_fp **fp_context_ptr
 );
 
+/** @} */
+
 /* FIXME */
 typedef CPU_Interrupt_frame CPU_Exception_frame;
 
 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
 
 /**
- *  @ingroup CPUEndian
- *  The following routine swaps the endian format of an unsigned int.
- *  It must be static because it is referenced indirectly.
+ * @ingroup CPUEndian
+ * The following routine swaps the endian format of an unsigned int.
+ * It must be static because it is referenced indirectly.
  *
- *  This version will work on any processor, but if there is a better
- *  way for your CPU PLEASE use it.  The most common way to do this is to:
+ * This version will work on any processor, but if there is a better
+ * way for your CPU PLEASE use it.  The most common way to do this is to:
  *
- *     swap least significant two bytes with 16-bit rotate
- *     swap upper and lower 16-bits
- *     swap most significant two bytes with 16-bit rotate
+ *    swap least significant two bytes with 16-bit rotate
+ *    swap upper and lower 16-bits
+ *    swap most significant two bytes with 16-bit rotate
  *
- *  Some CPUs have special instructions which swap a 32-bit quantity in
- *  a single instruction (e.g. i486).  It is probably best to avoid
- *  an "endian swapping control bit" in the CPU.  One good reason is
- *  that interrupts would probably have to be disabled to ensure that
- *  an interrupt does not try to access the same "chunk" with the wrong
- *  endian.  Another good reason is that on some CPUs, the endian bit
- *  endianness for ALL fetches -- both code and data -- so the code
- *  will be fetched incorrectly.
+ * Some CPUs have special instructions which swap a 32-bit quantity in
+ * a single instruction (e.g. i486).  It is probably best to avoid
+ * an "endian swapping control bit" in the CPU.  One good reason is
+ * that interrupts would probably have to be disabled to ensure that
+ * an interrupt does not try to access the same "chunk" with the wrong
+ * endian.  Another good reason is that on some CPUs, the endian bit
+ * endianness for ALL fetches -- both code and data -- so the code
+ * will be fetched incorrectly.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 static inline uint32_t CPU_swap_u32(
   uint32_t value
@@ -1254,11 +1264,11 @@ static inline uint32_t CPU_swap_u32(
 }
 
 /**
- *  @ingroup CPUEndian
- *  This routine swaps a 16 bir quantity.
+ * @ingroup CPUEndian
+ * This routine swaps a 16 bir quantity.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  */
 #define CPU_swap_u16( value ) \
   (((value&0xff) << 8) | ((value >> 8)&0xff))
diff --git a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h
index 7d23bc5a9a..f9543f15a7 100644
--- a/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/bfin/rtems/score/cpu_asm.h
@@ -1,10 +1,12 @@
 /**
- * @file rtems/score/cpu_asm.h
+ * @file
+ *
+ * @brief Blackfin Assembly File
+ *
+ * Defines a couple of Macros used in cpu_asm.S
  */
 
 /*
- *  Defines a couple of Macros used in cpu_asm.S
- *
  *  COPYRIGHT (c) 2006 by Atos Automacao Industrial Ltda.
  *             written by Alain Schaefer <alain.schaefer@easc.ch>
  *                    and Antonio Giovanini <antonio@atos.com.br>
diff --git a/cpukit/score/cpu/bfin/rtems/score/types.h b/cpukit/score/cpu/bfin/rtems/score/types.h
index 4f734bb033..5d4e12eb95 100644
--- a/cpukit/score/cpu/bfin/rtems/score/types.h
+++ b/cpukit/score/cpu/bfin/rtems/score/types.h
@@ -1,7 +1,13 @@
-/*
- *  This include file contains type definitions pertaining to the
- *  Blackfin processor family.
+/**
+ * @file
+ *
+ * @brief Blackfin CPU Type Definitions
  *
+ * This include file contains type definitions pertaining to the
+ * Blackfin processor family.
+ */
+
+/*
  *  COPYRIGHT (c) 1989-2006.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/h8300/rtems/asm.h b/cpukit/score/cpu/h8300/rtems/asm.h
index 0f4adee915..a9fad26252 100644
--- a/cpukit/score/cpu/h8300/rtems/asm.h
+++ b/cpukit/score/cpu/h8300/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
@@ -69,23 +72,23 @@
  */
 #define	r0	REG(r0)
 #define r1	REG(r1)
-#define r2	REG(r2)	
-#define r3	REG(r3)	
-#define r4	REG(r4)	
-#define r5	REG(r5)	
-#define r6	REG(r6)	
-#define r7	REG(r7)	
+#define r2	REG(r2)
+#define r3	REG(r3)
+#define r4	REG(r4)
+#define r5	REG(r5)
+#define r6	REG(r6)
+#define r7	REG(r7)
 
 #define	er0	REG(er0)
 #define er1	REG(er1)
-#define er2	REG(er2)	
-#define er3	REG(er3)	
-#define er4	REG(er4)	
-#define er5	REG(er5)	
-#define er6	REG(er6)	
-#define er7	REG(er7)	
-
-#define sp	REG(sp)	
+#define er2	REG(er2)
+#define er3	REG(er3)
+#define er4	REG(er4)
+#define er5	REG(er5)
+#define er6	REG(er6)
+#define er7	REG(er7)
+
+#define sp	REG(sp)
 
 /*
  *  Define macros to handle section beginning and ends.
diff --git a/cpukit/score/cpu/h8300/rtems/score/cpu.h b/cpukit/score/cpu/h8300/rtems/score/cpu.h
index f8f41a821e..6031f9689b 100644
--- a/cpukit/score/cpu/h8300/rtems/score/cpu.h
+++ b/cpukit/score/cpu/h8300/rtems/score/cpu.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/cpu.h
+ * @file
+ *
+ * @brief Hitachi H8300 CPU Department Source
+ *
+ * This include file contains information pertaining to the H8300
+ *  processor.
  */
 
 /*
- *  This include file contains information pertaining to the H8300
- *  processor.
- *
  *  COPYRIGHT (c) 1989-2006.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/h8300/rtems/score/h8300.h b/cpukit/score/cpu/h8300/rtems/score/h8300.h
index dd7a3ec11b..3b5e87d626 100644
--- a/cpukit/score/cpu/h8300/rtems/score/h8300.h
+++ b/cpukit/score/cpu/h8300/rtems/score/h8300.h
@@ -1,11 +1,14 @@
 /**
- * @file rtems/score/h8300.h
+ * @file
+ *
+ * @brief Information Required to Build RTEMS for a Particular Member
+ * of the Hitachi H8/300 Family
+ *
+ * This file contains information pertaining to the Hitachi H8/300
+ * processor family.
  */
 
 /*
- *  This file contains information pertaining to the Hitachi H8/300
- *  processor family.
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/h8300/rtems/score/types.h b/cpukit/score/cpu/h8300/rtems/score/types.h
index fae136ab45..f832c186fe 100644
--- a/cpukit/score/cpu/h8300/rtems/score/types.h
+++ b/cpukit/score/cpu/h8300/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief Hitachi H8300 CPU Type Definitions
+ *
+ * This include file contains type definitions pertaining to the Hitachi
+ * h8300 processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the Hitachi
- *  h8300 processor family.
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/i386/rtems/asm.h b/cpukit/score/cpu/i386/rtems/asm.h
index 29594e0844..50b0fd71a0 100644
--- a/cpukit/score/cpu/i386/rtems/asm.h
+++ b/cpukit/score/cpu/i386/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of 
+ * Assemblers and Toolsets
+ * 
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ * 
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
diff --git a/cpukit/score/cpu/i386/rtems/score/cpu.h b/cpukit/score/cpu/i386/rtems/score/cpu.h
index 03d6209981..66676047f8 100644
--- a/cpukit/score/cpu/i386/rtems/score/cpu.h
+++ b/cpukit/score/cpu/i386/rtems/score/cpu.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/cpu.h
+ * @file
+ * 
+ * @brief Intel I386 CPU Dependent Source
+ * 
+ * This include file contains information pertaining to the Intel
+ * i386 processor.
  */
 
 /*
- *  This include file contains information pertaining to the Intel
- *  i386 processor.
- *
  *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/i386/rtems/score/i386.h b/cpukit/score/cpu/i386/rtems/score/i386.h
index 8b98f4ba28..b21fb93957 100644
--- a/cpukit/score/cpu/i386/rtems/score/i386.h
+++ b/cpukit/score/cpu/i386/rtems/score/i386.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/i386.h
+ * @file
+ * 
+ * @brief Intel I386 CPU Dependent Source
+ * 
+ * This include file contains information pertaining to the Intel
+ * i386 processor.
  */
 
 /*
- *  This include file contains information pertaining to the Intel
- *  i386 processor.
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/i386/rtems/score/idtr.h b/cpukit/score/cpu/i386/rtems/score/idtr.h
index 401aebe2fa..8358fd5a16 100644
--- a/cpukit/score/cpu/i386/rtems/score/idtr.h
+++ b/cpukit/score/cpu/i386/rtems/score/idtr.h
@@ -1,19 +1,21 @@
 /**
- * @file rtems/score/idtr.h
- */
-
-/*
+ * @file
+ * 
+ * @brief Intel I386 Data Structures
+ * 
  * This file contains definitions for data structure related
  *          to Intel system programming. More information can be found
  *          on Intel site and more precisely in the following book :
  *
- *		Pentium Processor familly
- *		Developper's Manual
+ *              Pentium Processor familly
+ *              Developper's Manual
  *
- *		Volume 3 : Architecture and Programming Manual
+ *              Volume 3 : Architecture and Programming Manual
  *
  * Formerly contained in and extracted from libcpu/i386/cpu.h.
- *
+ */
+
+/*
  * COPYRIGHT (C) 1998  Eric Valette (valette@crf.canon.fr)
  *                     Canon Centre Recherche France.
  *
diff --git a/cpukit/score/cpu/i386/rtems/score/interrupts.h b/cpukit/score/cpu/i386/rtems/score/interrupts.h
index 08ad2b16c0..bed6330781 100644
--- a/cpukit/score/cpu/i386/rtems/score/interrupts.h
+++ b/cpukit/score/cpu/i386/rtems/score/interrupts.h
@@ -1,12 +1,12 @@
 /**
- * @file rtems/score/interrupts.h
+ * @file
+ * 
+ * @brief Intel I386 Interrupt Macros
+ *
+ * Formerly contained in and extracted from libcpu/i386/cpu.h
  */
 
 /*
- *  i386 interrupt macros.
- *
- *  Formerly contained in and extracted from libcpu/i386/cpu.h
- *
  *  COPYRIGHT (c) 1998 valette@crf.canon.fr
  *
  *  The license and distribution terms for this file may be
@@ -28,9 +28,11 @@ typedef void (*rtems_raw_irq_enable)		(const struct __rtems_raw_irq_connect_data
 typedef void (*rtems_raw_irq_disable)		(const struct __rtems_raw_irq_connect_data__*);
 typedef int  (*rtems_raw_irq_is_enabled)	(const struct __rtems_raw_irq_connect_data__*);
 
-/*
- *  Interrupt Level Macros
+/**
+ * @name Interrupt Level Macros
+ * 
  */
+/**@{**/
 
 #define i386_disable_interrupts( _level ) \
   { \
@@ -73,5 +75,7 @@ typedef int  (*rtems_raw_irq_is_enabled)	(const struct __rtems_raw_irq_connect_d
 #define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
 #define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level )
 
+/** @} */
+
 #endif
 #endif
diff --git a/cpukit/score/cpu/i386/rtems/score/registers.h b/cpukit/score/cpu/i386/rtems/score/registers.h
index 2b8f7700cd..f9754dcedb 100644
--- a/cpukit/score/cpu/i386/rtems/score/registers.h
+++ b/cpukit/score/cpu/i386/rtems/score/registers.h
@@ -1,10 +1,12 @@
 /**
- * @file rtems/score/registers.h
+ * @file
+ * 
+ * @brief Intel CPU Constants and Definitions
+ * 
+ * This file contains definition and constants related to Intel Cpu
  */
 
 /*
- *  This file contains definition and constants related to Intel Cpu
- *
  *  COPYRIGHT (c) 1998 valette@crf.canon.fr
  *
  *  The license and distribution terms for this file may be
diff --git a/cpukit/score/cpu/i386/rtems/score/types.h b/cpukit/score/cpu/i386/rtems/score/types.h
index b2c9d3ec57..104b0fcc92 100644
--- a/cpukit/score/cpu/i386/rtems/score/types.h
+++ b/cpukit/score/cpu/i386/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ * 
+ * @brief Intel I386 CPU Type Definitions
+ * 
+ * This include file contains type definitions pertaining to the Intel
+ * i386 processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the Intel
- *  i386 processor family.
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/lm32/rtems/asm.h b/cpukit/score/cpu/lm32/rtems/asm.h
index df16e4efdc..15046df81c 100644
--- a/cpukit/score/cpu/lm32/rtems/asm.h
+++ b/cpukit/score/cpu/lm32/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
@@ -38,24 +41,24 @@
 
 #ifndef __USER_LABEL_PREFIX__
 /**
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents.  If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
  *
- *  This symbol is prefixed to all C program symbols.
+ * This symbol is prefixed to all C program symbols.
  */
 #define __USER_LABEL_PREFIX__ _
 #endif
 
 #ifndef __REGISTER_PREFIX__
 /**
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents.  If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
  *
- *  This symbol is prefixed to all register names.
+ * This symbol is prefixed to all register names.
  */
 #define __REGISTER_PREFIX__
 #endif
@@ -95,8 +98,9 @@
 #define BEGIN_DATA
 /** This macro is used to denote the end of a data section. */
 #define END_DATA
-/** This macro is used to denote the beginning of the
- *  unitialized data section.
+/**
+ * This macro is used to denote the beginning of the
+ * unitialized data section.
  */
 #define BEGIN_BSS
 /** This macro is used to denote the end of the unitialized data section.  */
@@ -105,18 +109,18 @@
 #define END
 
 /**
- *  This macro is used to declare a public global symbol.
+ * This macro is used to declare a public global symbol.
  *
- *  @note This must be tailored for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
+ * NOTE: This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
  */
 #define PUBLIC(sym) .globl SYM (sym)
 
 /**
- *  This macro is used to prototype a public global symbol.
+ * This macro is used to prototype a public global symbol.
  *
- *  @note This must be tailored for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
+ * NOTE: This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
  */
 #define EXTERN(sym) .globl SYM (sym)
 
diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu.h b/cpukit/score/cpu/lm32/rtems/score/cpu.h
index 7f10a53820..1f8a370700 100644
--- a/cpukit/score/cpu/lm32/rtems/score/cpu.h
+++ b/cpukit/score/cpu/lm32/rtems/score/cpu.h
@@ -1,10 +1,10 @@
 /**
- * @file rtems/score/cpu.h
- */
-
-/*
- *  This include file contains information pertaining to the LM32
- *  processor.
+ * @file
+ *
+ * @brief LM32 CPU Department Source
+ *
+ * This include file contains information pertaining to the LM32
+ * processor.
  */
 
 /*
@@ -29,363 +29,365 @@ extern "C" {
 /* conditional compilation parameters */
 
 /**
- *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ * Should the calls to @ref _Thread_Enable_dispatch be inlined?
  *
- *  If TRUE, then they are inlined.
- *  If FALSE, then a subroutine call is made.
+ * If TRUE, then they are inlined.
+ * If FALSE, then a subroutine call is made.
  *
- *  This conditional is an example of the classic trade-off of size
- *  versus speed.  Inlining the call (TRUE) typically increases the
- *  size of RTEMS while speeding up the enabling of dispatching.
+ * This conditional is an example of the classic trade-off of size
+ * versus speed.  Inlining the call (TRUE) typically increases the
+ * size of RTEMS while speeding up the enabling of dispatching.
  *
- *  @note In general, the @ref _Thread_Dispatch_disable_level will
- *  only be 0 or 1 unless you are in an interrupt handler and that
- *  interrupt handler invokes the executive.]  When not inlined
- *  something calls @ref _Thread_Enable_dispatch which in turns calls
- *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
- *  one subroutine call is avoided entirely.
+ * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
+ * only be 0 or 1 unless you are in an interrupt handler and that
+ * interrupt handler invokes the executive.]  When not inlined
+ * something calls @ref _Thread_Enable_dispatch which in turns calls
+ * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
+ * one subroutine call is avoided entirely.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INLINE_ENABLE_DISPATCH       FALSE
 
 /**
- *  Should the body of the search loops in _Thread_queue_Enqueue_priority
- *  be unrolled one time?  In unrolled each iteration of the loop examines
- *  two "nodes" on the chain being searched.  Otherwise, only one node
- *  is examined per iteration.
+ * Should the body of the search loops in _Thread_queue_Enqueue_priority
+ * be unrolled one time?  In unrolled each iteration of the loop examines
+ * two "nodes" on the chain being searched.  Otherwise, only one node
+ * is examined per iteration.
  *
- *  If TRUE, then the loops are unrolled.
- *  If FALSE, then the loops are not unrolled.
+ * If TRUE, then the loops are unrolled.
+ * If FALSE, then the loops are not unrolled.
  *
- *  The primary factor in making this decision is the cost of disabling
- *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- *  body of the loop.  On some CPUs, the flash is more expensive than
- *  one iteration of the loop body.  In this case, it might be desirable
- *  to unroll the loop.  It is important to note that on some CPUs, this
- *  code is the longest interrupt disable period in RTEMS.  So it is
- *  necessary to strike a balance when setting this parameter.
+ * The primary factor in making this decision is the cost of disabling
+ * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ * body of the loop.  On some CPUs, the flash is more expensive than
+ * one iteration of the loop body.  In this case, it might be desirable
+ * to unroll the loop.  It is important to note that on some CPUs, this
+ * code is the longest interrupt disable period in RTEMS.  So it is
+ * necessary to strike a balance when setting this parameter.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
 
 /**
- *  Does RTEMS manage a dedicated interrupt stack in software?
+ * Does RTEMS manage a dedicated interrupt stack in software?
  *
- *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
- *  If FALSE, nothing is done.
+ * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ * If FALSE, nothing is done.
  *
- *  If the CPU supports a dedicated interrupt stack in hardware,
- *  then it is generally the responsibility of the BSP to allocate it
- *  and set it up.
+ * If the CPU supports a dedicated interrupt stack in hardware,
+ * then it is generally the responsibility of the BSP to allocate it
+ * and set it up.
  *
- *  If the CPU does not support a dedicated interrupt stack, then
- *  the porter has two options: (1) execute interrupts on the
- *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
- *  interrupt stack.
+ * If the CPU does not support a dedicated interrupt stack, then
+ * the porter has two options: (1) execute interrupts on the
+ * stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ * interrupt stack.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
 
 /**
- *  Does the CPU follow the simple vectored interrupt model?
+ * Does the CPU follow the simple vectored interrupt model?
  *
- *  If TRUE, then RTEMS allocates the vector table it internally manages.
- *  If FALSE, then the BSP is assumed to allocate and manage the vector
- *  table
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
 
 /**
- *  Does this CPU have hardware support for a dedicated interrupt stack?
+ * Does this CPU have hardware support for a dedicated interrupt stack?
  *
- *  If TRUE, then it must be installed during initialization.
- *  If FALSE, then no installation is performed.
+ * If TRUE, then it must be installed during initialization.
+ * If FALSE, then no installation is performed.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
 
 /**
- *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
  *
- *  If TRUE, then the memory is allocated during initialization.
- *  If FALSE, then the memory is allocated during initialization.
+ * If TRUE, then the memory is allocated during initialization.
+ * If FALSE, then the memory is allocated during initialization.
  *
- *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
 
 /**
- *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector
- *  number (0)?
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ISR_PASSES_FRAME_POINTER 1
 
 /**
- *  @def CPU_HARDWARE_FP
+ * @def CPU_HARDWARE_FP
  *
- *  Does the CPU have hardware floating point?
+ * Does the CPU have hardware floating point?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
  *
- *  If there is a FP coprocessor such as the i387 or mc68881, then
- *  the answer is TRUE.
+ * If there is a FP coprocessor such as the i387 or mc68881, then
+ * the answer is TRUE.
  *
- *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
- *  It indicates whether or not this CPU model has FP support.  For
- *  example, it would be possible to have an i386_nofp CPU model
- *  which set this to false to indicate that you have an i386 without
- *  an i387 and wish to leave floating point support out of RTEMS.
+ * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
+ * It indicates whether or not this CPU model has FP support.  For
+ * example, it would be possible to have an i386_nofp CPU model
+ * which set this to false to indicate that you have an i386 without
+ * an i387 and wish to leave floating point support out of RTEMS.
  */
 
 /**
- *  @def CPU_SOFTWARE_FP
+ * @def CPU_SOFTWARE_FP
  *
- *  Does the CPU have no hardware floating point and GCC provides a
- *  software floating point implementation which must be context
- *  switched?
+ * Does the CPU have no hardware floating point and GCC provides a
+ * software floating point implementation which must be context
+ * switched?
  *
- *  This feature conditional is used to indicate whether or not there
- *  is software implemented floating point that must be context
- *  switched.  The determination of whether or not this applies
- *  is very tool specific and the state saved/restored is also
- *  compiler specific.
+ * This feature conditional is used to indicate whether or not there
+ * is software implemented floating point that must be context
+ * switched.  The determination of whether or not this applies
+ * is very tool specific and the state saved/restored is also
+ * compiler specific.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HARDWARE_FP     FALSE
 #define CPU_SOFTWARE_FP     FALSE
 
 /**
- *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
  *
- *  So far, the only CPUs in which this option has been used are the
- *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
- *  gcc both implicitly used the floating point registers to perform
- *  integer multiplies.  Similarly, the PowerPC port of gcc has been
- *  seen to allocate floating point local variables and touch the FPU
- *  even when the flow through a subroutine (like vfprintf()) might
- *  not use floating point formats.
+ * So far, the only CPUs in which this option has been used are the
+ * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
+ * gcc both implicitly used the floating point registers to perform
+ * integer multiplies.  Similarly, the PowerPC port of gcc has been
+ * seen to allocate floating point local variables and touch the FPU
+ * even when the flow through a subroutine (like vfprintf()) might
+ * not use floating point formats.
  *
- *  If a function which you would not think utilize the FP unit DOES,
- *  then one can not easily predict which tasks will use the FP hardware.
- *  In this case, this option should be TRUE.
+ * If a function which you would not think utilize the FP unit DOES,
+ * then one can not easily predict which tasks will use the FP hardware.
+ * In this case, this option should be TRUE.
  *
- *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALL_TASKS_ARE_FP     FALSE
 
 /**
- *  Should the IDLE task have a floating point context?
+ * Should the IDLE task have a floating point context?
  *
- *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- *  and it has a floating point context which is switched in and out.
- *  If FALSE, then the IDLE task does not have a floating point context.
+ * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ * and it has a floating point context which is switched in and out.
+ * If FALSE, then the IDLE task does not have a floating point context.
  *
- *  Setting this to TRUE negatively impacts the time required to preempt
- *  the IDLE task from an interrupt because the floating point context
- *  must be saved as part of the preemption.
+ * Setting this to TRUE negatively impacts the time required to preempt
+ * the IDLE task from an interrupt because the floating point context
+ * must be saved as part of the preemption.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_IDLE_TASK_IS_FP      FALSE
 
 /**
- *  Should the saving of the floating point registers be deferred
- *  until a context switch is made to another different floating point
- *  task?
+ * Should the saving of the floating point registers be deferred
+ * until a context switch is made to another different floating point
+ * task?
  *
- *  If TRUE, then the floating point context will not be stored until
- *  necessary.  It will remain in the floating point registers and not
- *  disturned until another floating point task is switched to.
+ * If TRUE, then the floating point context will not be stored until
+ * necessary.  It will remain in the floating point registers and not
+ * disturned until another floating point task is switched to.
  *
- *  If FALSE, then the floating point context is saved when a floating
- *  point task is switched out and restored when the next floating point
- *  task is restored.  The state of the floating point registers between
- *  those two operations is not specified.
+ * If FALSE, then the floating point context is saved when a floating
+ * point task is switched out and restored when the next floating point
+ * task is restored.  The state of the floating point registers between
+ * those two operations is not specified.
  *
- *  If the floating point context does NOT have to be saved as part of
- *  interrupt dispatching, then it should be safe to set this to TRUE.
+ * If the floating point context does NOT have to be saved as part of
+ * interrupt dispatching, then it should be safe to set this to TRUE.
  *
- *  Setting this flag to TRUE results in using a different algorithm
- *  for deciding when to save and restore the floating point context.
- *  The deferred FP switch algorithm minimizes the number of times
- *  the FP context is saved and restored.  The FP context is not saved
- *  until a context switch is made to another, different FP task.
- *  Thus in a system with only one FP task, the FP context will never
- *  be saved or restored.
+ * Setting this flag to TRUE results in using a different algorithm
+ * for deciding when to save and restore the floating point context.
+ * The deferred FP switch algorithm minimizes the number of times
+ * the FP context is saved and restored.  The FP context is not saved
+ * until a context switch is made to another, different FP task.
+ * Thus in a system with only one FP task, the FP context will never
+ * be saved or restored.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_USE_DEFERRED_FP_SWITCH       TRUE
 
 /**
- *  Does this port provide a CPU dependent IDLE task implementation?
+ * Does this port provide a CPU dependent IDLE task implementation?
  *
- *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
- *  must be provided and is the default IDLE thread body instead of
- *  @ref _CPU_Thread_Idle_body.
+ * If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ * must be provided and is the default IDLE thread body instead of
+ * @ref _CPU_Thread_Idle_body.
  *
- *  If FALSE, then use the generic IDLE thread body if the BSP does
- *  not provide one.
+ * If FALSE, then use the generic IDLE thread body if the BSP does
+ * not provide one.
  *
- *  This is intended to allow for supporting processors which have
- *  a low power or idle mode.  When the IDLE thread is executed, then
- *  the CPU can be powered down.
+ * This is intended to allow for supporting processors which have
+ * a low power or idle mode.  When the IDLE thread is executed, then
+ * the CPU can be powered down.
  *
- *  The order of precedence for selecting the IDLE thread body is:
+ * The order of precedence for selecting the IDLE thread body is:
  *
- *    -#  BSP provided
- *    -#  CPU dependent (if provided)
- *    -#  generic (if no BSP and no CPU dependent)
+ *   -#  BSP provided
+ *   -#  CPU dependent (if provided)
+ *   -#  generic (if no BSP and no CPU dependent)
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
 
 /**
- *  Does the stack grow up (toward higher addresses) or down
- *  (toward lower addresses)?
+ * Does the stack grow up (toward higher addresses) or down
+ * (toward lower addresses)?
  *
- *  If TRUE, then the grows upward.
- *  If FALSE, then the grows toward smaller addresses.
+ * If TRUE, then the grows upward.
+ * If FALSE, then the grows toward smaller addresses.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_GROWS_UP               FALSE
 
 /**
- *  The following is the variable attribute used to force alignment
- *  of critical RTEMS structures.  On some processors it may make
- *  sense to have these aligned on tighter boundaries than
- *  the minimum requirements of the compiler in order to have as
- *  much of the critical data area as possible in a cache line.
+ * The following is the variable attribute used to force alignment
+ * of critical RTEMS structures.  On some processors it may make
+ * sense to have these aligned on tighter boundaries than
+ * the minimum requirements of the compiler in order to have as
+ * much of the critical data area as possible in a cache line.
  *
- *  The placement of this macro in the declaration of the variables
- *  is based on the syntactically requirements of the GNU C
- *  "__attribute__" extension.  For example with GNU C, use
- *  the following to force a structures to a 32 byte boundary.
+ * The placement of this macro in the declaration of the variables
+ * is based on the syntactically requirements of the GNU C
+ * "__attribute__" extension.  For example with GNU C, use
+ * the following to force a structures to a 32 byte boundary.
  *
- *      __attribute__ ((aligned (32)))
+ *     __attribute__ ((aligned (32)))
  *
- *  @note Currently only the Priority Bit Map table uses this feature.
- *        To benefit from using this, the data must be heavily
- *        used so it will stay in the cache and used frequently enough
- *        in the executive to justify turning this on.
+ * NOTE: Currently only the Priority Bit Map table uses this feature.
+ *       To benefit from using this, the data must be heavily
+ *       used so it will stay in the cache and used frequently enough
+ *       in the executive to justify turning this on.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  L2 cache lines are 32 bytes in Milkymist SoC
+ * L2 cache lines are 32 bytes in Milkymist SoC
  */
 #define CPU_STRUCTURE_ALIGNMENT __attribute__ ((aligned (32)))
 
 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
 
 /**
- *  @defgroup CPUEndian Processor Dependent Endianness Support
+ * @defgroup CPUEndian Processor Dependent Endianness Support
+ *
+ * This group assists in issues related to processor endianness.
  *
- *  This group assists in issues related to processor endianness.
  */
+/**@{**/
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_LITTLE_ENDIAN
+ * @see CPU_LITTLE_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_BIG_ENDIAN                           TRUE
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_BIG_ENDIAN
+ * @see CPU_BIG_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_LITTLE_ENDIAN                        FALSE
 
+/** @} */
+
 /**
- *  @ingroup CPUInterrupt
- *  The following defines the number of bits actually used in the
- *  interrupt field of the task mode.  How those bits map to the
- *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ * @ingroup CPUInterrupt
+ * The following defines the number of bits actually used in the
+ * interrupt field of the task mode.  How those bits map to the
+ * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_MODES_INTERRUPT_MASK   0x00000001
 
@@ -402,50 +404,50 @@ extern "C" {
 /**
  * @defgroup CPUContext Processor Dependent Context Management
  *
- *  From the highest level viewpoint, there are 2 types of context to save.
+ * From the highest level viewpoint, there are 2 types of context to save.
  *
- *     -# Interrupt registers to save
- *     -# Task level registers to save
+ *    -# Interrupt registers to save
+ *    -# Task level registers to save
  *
- *  Since RTEMS handles integer and floating point contexts separately, this
- *  means we have the following 3 context items:
+ * Since RTEMS handles integer and floating point contexts separately, this
+ * means we have the following 3 context items:
  *
- *     -# task level context stuff::  Context_Control
- *     -# floating point task stuff:: Context_Control_fp
- *     -# special interrupt level context :: CPU_Interrupt_frame
+ *    -# task level context stuff::  Context_Control
+ *    -# floating point task stuff:: Context_Control_fp
+ *    -# special interrupt level context :: CPU_Interrupt_frame
  *
- *  On some processors, it is cost-effective to save only the callee
- *  preserved registers during a task context switch.  This means
- *  that the ISR code needs to save those registers which do not
- *  persist across function calls.  It is not mandatory to make this
- *  distinctions between the caller/callee saves registers for the
- *  purpose of minimizing context saved during task switch and on interrupts.
- *  If the cost of saving extra registers is minimal, simplicity is the
- *  choice.  Save the same context on interrupt entry as for tasks in
- *  this case.
+ * On some processors, it is cost-effective to save only the callee
+ * preserved registers during a task context switch.  This means
+ * that the ISR code needs to save those registers which do not
+ * persist across function calls.  It is not mandatory to make this
+ * distinctions between the caller/callee saves registers for the
+ * purpose of minimizing context saved during task switch and on interrupts.
+ * If the cost of saving extra registers is minimal, simplicity is the
+ * choice.  Save the same context on interrupt entry as for tasks in
+ * this case.
  *
- *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- *  care should be used in designing the context area.
+ * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ * care should be used in designing the context area.
  *
- *  On some CPUs with hardware floating point support, the Context_Control_fp
- *  structure will not be used or it simply consist of an array of a
- *  fixed number of bytes.   This is done when the floating point context
- *  is dumped by a "FP save context" type instruction and the format
- *  is not really defined by the CPU.  In this case, there is no need
- *  to figure out the exact format -- only the size.  Of course, although
- *  this is enough information for RTEMS, it is probably not enough for
- *  a debugger such as gdb.  But that is another problem.
+ * On some CPUs with hardware floating point support, the Context_Control_fp
+ * structure will not be used or it simply consist of an array of a
+ * fixed number of bytes.   This is done when the floating point context
+ * is dumped by a "FP save context" type instruction and the format
+ * is not really defined by the CPU.  In this case, there is no need
+ * to figure out the exact format -- only the size.  Of course, although
+ * this is enough information for RTEMS, it is probably not enough for
+ * a debugger such as gdb.  But that is another problem.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
+/**@{**/
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the minimal set of integer and processor state registers
- *  that must be saved during a voluntary context switch from one thread
- *  to another.
+ * This defines the minimal set of integer and processor state registers
+ * that must be saved during a voluntary context switch from one thread
+ * to another.
  */
 typedef struct {
   uint32_t r11;
@@ -472,30 +474,27 @@ typedef struct {
 } Context_Control;
 
 /**
- *  @ingroup CPUContext Management
  *
- *  This macro returns the stack pointer associated with @a _context.
+ * This macro returns the stack pointer associated with @a _context.
  *
- *  @param[in] _context is the thread context area to access
+ * @param[in] _context is the thread context area to access
  *
- *  @return This method returns the stack pointer.
+ * @return This method returns the stack pointer.
  */
 #define _CPU_Context_Get_SP( _context ) \
   (_context)->sp
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the complete set of floating point registers that must
- *  be saved during any context switch from one thread to another.
+ * This defines the complete set of floating point registers that must
+ * be saved during any context switch from one thread to another.
  */
 typedef struct {
 } Context_Control_fp;
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the set of integer and processor state registers that must
- *  be saved during an interrupt.  This set does not include any which are
- *  in @ref Context_Control.
+ * This defines the set of integer and processor state registers that must
+ * be saved during an interrupt.  This set does not include any which are
+ * in @ref Context_Control.
  */
 typedef struct {
   uint32_t r1;
@@ -514,173 +513,175 @@ typedef struct {
 } CPU_Interrupt_frame;
 
 /**
- *  This variable is optional.  It is used on CPUs on which it is difficult
- *  to generate an "uninitialized" FP context.  It is filled in by
- *  @ref _CPU_Initialize and copied into the task's FP context area during
- *  @ref _CPU_Context_Initialize.
+ * This variable is optional.  It is used on CPUs on which it is difficult
+ * to generate an "uninitialized" FP context.  It is filled in by
+ * @ref _CPU_Initialize and copied into the task's FP context area during
+ * @ref _CPU_Context_Initialize.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if 0
 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 #endif
 
+/** @} */
+
 /**
- *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ * @defgroup CPUInterrupt Processor Dependent Interrupt Management
  *
- *  On some CPUs, RTEMS supports a software managed interrupt stack.
- *  This stack is allocated by the Interrupt Manager and the switch
- *  is performed in @ref _ISR_Handler.  These variables contain pointers
- *  to the lowest and highest addresses in the chunk of memory allocated
- *  for the interrupt stack.  Since it is unknown whether the stack
- *  grows up or down (in general), this give the CPU dependent
- *  code the option of picking the version it wants to use.
+ * On some CPUs, RTEMS supports a software managed interrupt stack.
+ * This stack is allocated by the Interrupt Manager and the switch
+ * is performed in @ref _ISR_Handler.  These variables contain pointers
+ * to the lowest and highest addresses in the chunk of memory allocated
+ * for the interrupt stack.  Since it is unknown whether the stack
+ * grows up or down (in general), this give the CPU dependent
+ * code the option of picking the version it wants to use.
  *
- *  @note These two variables are required if the macro
- *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ * NOTE: These two variables are required if the macro
+ *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
+/**@{**/
 
 /*
- *  Nothing prevents the porter from declaring more CPU specific variables.
+ * Nothing prevents the porter from declaring more CPU specific variables.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 
 /* XXX: if needed, put more variables here */
 
 /**
- *  @ingroup CPUContext
- *  The size of the floating point context area.  On some CPUs this
- *  will not be a "sizeof" because the format of the floating point
- *  area is not defined -- only the size is.  This is usually on
- *  CPUs with a "floating point save context" instruction.
+ * @ingroup CPUContext
+ * The size of the floating point context area.  On some CPUs this
+ * will not be a "sizeof" because the format of the floating point
+ * area is not defined -- only the size is.  This is usually on
+ * CPUs with a "floating point save context" instruction.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
 
 /**
- *  Amount of extra stack (above minimum stack size) required by
- *  MPCI receive server thread.  Remember that in a multiprocessor
- *  system this thread must exist and be able to process all directives.
+ * Amount of extra stack (above minimum stack size) required by
+ * MPCI receive server thread.  Remember that in a multiprocessor
+ * system this thread must exist and be able to process all directives.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
 
 /**
- *  @ingroup CPUInterrupt
- *  This defines the number of entries in the @ref _ISR_Vector_table managed
- *  by RTEMS.
+ * This defines the number of entries in the @ref _ISR_Vector_table managed
+ * by RTEMS.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
 
 /**
- *  @ingroup CPUInterrupt
- *  This defines the highest interrupt vector number for this port.
+ * This defines the highest interrupt vector number for this port.
  */
 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
 /**
- *  @ingroup CPUInterrupt
- *  This is defined if the port has a special way to report the ISR nesting
- *  level.  Most ports maintain the variable @a _ISR_Nest_level.
+ * This is defined if the port has a special way to report the ISR nesting
+ * level.  Most ports maintain the variable @a _ISR_Nest_level.
  */
 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
+/** @} */
+
 /**
- *  @ingroup CPUContext
- *  Should be large enough to run all RTEMS tests.  This ensures
- *  that a "reasonable" small application should not have any problems.
+ * @ingroup CPUContext
+ * Should be large enough to run all RTEMS tests.  This ensures
+ * that a "reasonable" small application should not have any problems.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_MINIMUM_SIZE          (1024*4)
 
 #define CPU_SIZEOF_POINTER 4
 
 /**
- *  CPU's worst alignment requirement for data types on a byte boundary.  This
- *  alignment does not take into account the requirements for the stack.
+ * CPU's worst alignment requirement for data types on a byte boundary.  This
+ * alignment does not take into account the requirements for the stack.
  *
- *  Port Specific Information:
- *  The LM32 architecture manual simply states: "All memory accesses must be
- *  aligned to the size of the access", and there is no hardware support
- *  whatsoever for 64-bit numbers.
- *  (lm32_archman.pdf, July 2009, p. 15)
+ * Port Specific Information:
+ * The LM32 architecture manual simply states: "All memory accesses must be
+ * aligned to the size of the access", and there is no hardware support
+ * whatsoever for 64-bit numbers.
+ * (lm32_archman.pdf, July 2009, p. 15)
  */
 #define CPU_ALIGNMENT              4
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  heap handler.  This alignment requirement may be stricter than that
- *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
- *  common for the heap to follow the same alignment requirement as
- *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
- *  the heap, then this should be set to @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for the
+ * heap handler.  This alignment requirement may be stricter than that
+ * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
+ * common for the heap to follow the same alignment requirement as
+ * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
+ * the heap, then this should be set to @ref CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2 although it should be
- *         a multiple of 2 greater than or equal to 2.  The requirement
- *         to be a multiple of 2 is because the heap uses the least
- *         significant field of the front and back flags to indicate
- *         that a block is in use or free.  So you do not want any odd
- *         length blocks really putting length data in that bit.
+ * NOTE:  This does not have to be a power of 2 although it should be
+ *        a multiple of 2 greater than or equal to 2.  The requirement
+ *        to be a multiple of 2 is because the heap uses the least
+ *        significant field of the front and back flags to indicate
+ *        that a block is in use or free.  So you do not want any odd
+ *        length blocks really putting length data in that bit.
  *
- *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
- *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
- *         elements allocated from the heap meet all restrictions.
+ *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ *        elements allocated from the heap meet all restrictions.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for memory
- *  buffers allocated by the partition manager.  This alignment requirement
- *  may be stricter than that for the data types alignment specified by
- *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
- *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
- *  strict enough for the partition, then this should be set to
- *  @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for memory
+ * buffers allocated by the partition manager.  This alignment requirement
+ * may be stricter than that for the data types alignment specified by
+ * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
+ * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
+ * strict enough for the partition, then this should be set to
+ * @ref CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than @ref CPU_ALIGNMENT.
+ * NOTE:  This does not have to be a power of 2.  It does have to
+ *        be greater or equal to than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  stack.  This alignment requirement may be stricter than that for the
- *  data types alignment specified by @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for the
+ * stack.  This alignment requirement may be stricter than that for the
+ * data types alignment specified by @ref CPU_ALIGNMENT.
  *
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  Stack is software-managed
+ * Stack is software-managed
  */
 #define CPU_STACK_ALIGNMENT        CPU_ALIGNMENT
 
@@ -689,76 +690,75 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
  */
 
 /**
- *  @ingroup CPUInterrupt
- *  Support routine to initialize the RTEMS vector table after it is allocated.
+ * @addtogroup CPUInterrupt
+ */
+/**@{**/
+
+/**
+ * Support routine to initialize the RTEMS vector table after it is allocated.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Initialize_vectors()
 
 /**
- *  @ingroup CPUInterrupt
- *  Disable all interrupts for an RTEMS critical section.  The previous
- *  level is returned in @a _isr_cookie.
+ * Disable all interrupts for an RTEMS critical section.  The previous
+ * level is returned in @a _isr_cookie.
  *
- *  @param[out] _isr_cookie will contain the previous level cookie
+ * @param[out] _isr_cookie will contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Disable( _isr_cookie ) \
   lm32_disable_interrupts( _isr_cookie );
 
 /**
- *  @ingroup CPUInterrupt
- *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- *  This indicates the end of an RTEMS critical section.  The parameter
- *  @a _isr_cookie is not modified.
+ * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ * This indicates the end of an RTEMS critical section.  The parameter
+ * @a _isr_cookie is not modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Enable( _isr_cookie ) \
   lm32_enable_interrupts( _isr_cookie );
 
 /**
- *  @ingroup CPUInterrupt
- *  This temporarily restores the interrupt to @a _isr_cookie before immediately
- *  disabling them again.  This is used to divide long RTEMS critical
- *  sections into two or more parts.  The parameter @a _isr_cookie is not
- *  modified.
+ * This temporarily restores the interrupt to @a _isr_cookie before immediately
+ * disabling them again.  This is used to divide long RTEMS critical
+ * sections into two or more parts.  The parameter @a _isr_cookie is not
+ * modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Flash( _isr_cookie ) \
   lm32_flash_interrupts( _isr_cookie );
 
 /**
- *  @ingroup CPUInterrupt
+ * This routine and @ref _CPU_ISR_Get_level
+ * Map the interrupt level in task mode onto the hardware that the CPU
+ * actually provides.  Currently, interrupt levels which do not
+ * map onto the CPU in a generic fashion are undefined.  Someday,
+ * it would be nice if these were "mapped" by the application
+ * via a callout.  For example, m68k has 8 levels 0 - 7, levels
+ * 8 - 255 would be available for bsp/application specific meaning.
+ * This could be used to manage a programmable interrupt controller
+ * via the rtems_task_mode directive.
  *
- *  This routine and @ref _CPU_ISR_Get_level
- *  Map the interrupt level in task mode onto the hardware that the CPU
- *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a generic fashion are undefined.  Someday,
- *  it would be nice if these were "mapped" by the application
- *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
- *  8 - 255 would be available for bsp/application specific meaning.
- *  This could be used to manage a programmable interrupt controller
- *  via the rtems_task_mode directive.
- *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Set_level( new_level ) \
   { \
@@ -766,52 +766,53 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
   }
 
 /**
- *  @ingroup CPUInterrupt
- *  Return the current interrupt disable level for this task in
- *  the format used by the interrupt level portion of the task mode.
+ * Return the current interrupt disable level for this task in
+ * the format used by the interrupt level portion of the task mode.
  *
- *  @note This routine usually must be implemented as a subroutine.
+ * NOTE: This routine usually must be implemented as a subroutine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
 
+/** @} */
+
 /* Context handler macros */
 
 /**
- *  @ingroup CPUContext
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
- *
- *     - setting a starting address
- *     - preparing the stack
- *     - preparing the stack and frame pointers
- *     - setting the proper interrupt level in the context
- *     - initializing the floating point context
- *
- *  This routine generally does not set any unnecessary register
- *  in the context.  The state of the "general data" registers is
- *  undefined at task start time.
- *
- *  @param[in] _the_context is the context structure to be initialized
- *  @param[in] _stack_base is the lowest physical address of this task's stack
- *  @param[in] _size is the size of this task's stack
- *  @param[in] _isr is the interrupt disable level
- *  @param[in] _entry_point is the thread's entry point.  This is
- *         always @a _Thread_Handler
- *  @param[in] _is_fp is TRUE if the thread is to be a floating
- *        point thread.  This is typically only used on CPUs where the
- *        FPU may be easily disabled by software such as on the SPARC
- *        where the PSR contains an enable FPU bit.
+ * @ingroup CPUContext
+ * Initialize the context to a state suitable for starting a
+ * task after a context restore operation.  Generally, this
+ * involves:
  *
- *  Port Specific Information:
+ *    - setting a starting address
+ *    - preparing the stack
+ *    - preparing the stack and frame pointers
+ *    - setting the proper interrupt level in the context
+ *    - initializing the floating point context
  *
- *  XXX document implementation including references if appropriate
+ * This routine generally does not set any unnecessary register
+ * in the context.  The state of the "general data" registers is
+ * undefined at task start time.
+ *
+ * @param[in] _the_context is the context structure to be initialized
+ * @param[in] _stack_base is the lowest physical address of this task's stack
+ * @param[in] _size is the size of this task's stack
+ * @param[in] _isr is the interrupt disable level
+ * @param[in] _entry_point is the thread's entry point.  This is
+ *        always @a _Thread_Handler
+ * @param[in] _is_fp is TRUE if the thread is to be a floating
+ *       point thread.  This is typically only used on CPUs where the
+ *       FPU may be easily disabled by software such as on the SPARC
+ *       where the PSR contains an enable FPU bit.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 extern char _gp[];
 
@@ -826,44 +827,44 @@ extern char _gp[];
    } while ( 0 )
 
 /**
- *  This routine is responsible for somehow restarting the currently
- *  executing task.  If you are lucky, then all that is necessary
- *  is restoring the context.  Otherwise, there will need to be
- *  a special assembly routine which does something special in this
- *  case.  For many ports, simply adding a label to the restore path
- *  of @ref _CPU_Context_switch will work.  On other ports, it may be
- *  possibly to load a few arguments and jump to the restore path. It will
- *  not work if restarting self conflicts with the stack frame
- *  assumptions of restoring a context.
+ * This routine is responsible for somehow restarting the currently
+ * executing task.  If you are lucky, then all that is necessary
+ * is restoring the context.  Otherwise, there will need to be
+ * a special assembly routine which does something special in this
+ * case.  For many ports, simply adding a label to the restore path
+ * of @ref _CPU_Context_switch will work.  On other ports, it may be
+ * possibly to load a few arguments and jump to the restore path. It will
+ * not work if restarting self conflicts with the stack frame
+ * assumptions of restoring a context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Restart_self( _the_context ) \
    _CPU_Context_restore( (_the_context) );
 
 /**
- *  @ingroup CPUContext
- *  The purpose of this macro is to allow the initial pointer into
- *  a floating point context area (used to save the floating point
- *  context) to be at an arbitrary place in the floating point
- *  context area.
+ * @ingroup CPUContext
+ * The purpose of this macro is to allow the initial pointer into
+ * a floating point context area (used to save the floating point
+ * context) to be at an arbitrary place in the floating point
+ * context area.
  *
- *  This is necessary because some FP units are designed to have
- *  their context saved as a stack which grows into lower addresses.
- *  Other FP units can be saved by simply moving registers into offsets
- *  from the base of the context area.  Finally some FP units provide
- *  a "dump context" instruction which could fill in from high to low
- *  or low to high based on the whim of the CPU designers.
+ * This is necessary because some FP units are designed to have
+ * their context saved as a stack which grows into lower addresses.
+ * Other FP units can be saved by simply moving registers into offsets
+ * from the base of the context area.  Finally some FP units provide
+ * a "dump context" instruction which could fill in from high to low
+ * or low to high based on the whim of the CPU designers.
  *
- *  @param[in] _base is the lowest physical address of the floating point
- *         context area
- *  @param[in] _offset is the offset into the floating point area
+ * @param[in] _base is the lowest physical address of the floating point
+ *        context area
+ * @param[in] _offset is the offset into the floating point area
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Fp_start( _base, _offset )
 #if 0
@@ -871,22 +872,22 @@ extern char _gp[];
 #endif
 
 /**
- *  This routine initializes the FP context area passed to it to.
- *  There are a few standard ways in which to initialize the
- *  floating point context.  The code included for this macro assumes
- *  that this is a CPU in which a "initial" FP context was saved into
- *  @a _CPU_Null_fp_context and it simply copies it to the destination
- *  context passed to it.
+ * This routine initializes the FP context area passed to it to.
+ * There are a few standard ways in which to initialize the
+ * floating point context.  The code included for this macro assumes
+ * that this is a CPU in which a "initial" FP context was saved into
+ * @a _CPU_Null_fp_context and it simply copies it to the destination
+ * context passed to it.
  *
- *  Other floating point context save/restore models include:
- *    -# not doing anything, and
- *    -# putting a "null FP status word" in the correct place in the FP context.
+ * Other floating point context save/restore models include:
+ *   -# not doing anything, and
+ *   -# putting a "null FP status word" in the correct place in the FP context.
  *
- *  @param[in] _destination is the floating point context area
+ * @param[in] _destination is the floating point context area
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Initialize_fp( _destination )
 #if 0
@@ -900,13 +901,13 @@ extern char _gp[];
 /* Fatal Error manager macros */
 
 /**
- *  This routine copies _error into a known place -- typically a stack
- *  location or a register, optionally disables interrupts, and
- *  halts/stops the CPU.
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Fatal_halt( _error ) \
   { \
@@ -917,68 +918,66 @@ extern char _gp[];
 /* Bitfield handler macros */
 
 /**
- *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
  *
- *  This set of routines are used to implement fast searches for
- *  the most important ready task.
+ * This set of routines are used to implement fast searches for
+ * the most important ready task.
  */
+/**@{**/
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the generic bitfield
- *  manipulation implementation.
+ * This definition is set to TRUE if the port uses the generic bitfield
+ * manipulation implementation.
  */
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the data tables provided
- *  by the generic bitfield manipulation implementation.
- *  This can occur when actually using the generic bitfield manipulation
- *  implementation or when implementing the same algorithm in assembly
- *  language for improved performance.  It is unlikely that a port will use
- *  the data if it has a bitfield scan instruction.
+ * This definition is set to TRUE if the port uses the data tables provided
+ * by the generic bitfield manipulation implementation.
+ * This can occur when actually using the generic bitfield manipulation
+ * implementation or when implementing the same algorithm in assembly
+ * language for improved performance.  It is unlikely that a port will use
+ * the data if it has a bitfield scan instruction.
  */
 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This routine sets @a _output to the bit number of the first bit
- *  set in @a _value.  @a _value is of CPU dependent type
- *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
- *  wide although only the 16 least significant bits will be used.
- *
- *  There are a number of variables in using a "find first bit" type
- *  instruction.
- *
- *    -# What happens when run on a value of zero?
- *    -# Bits may be numbered from MSB to LSB or vice-versa.
- *    -# The numbering may be zero or one based.
- *    -# The "find first bit" instruction may search from MSB or LSB.
- *
- *  RTEMS guarantees that (1) will never happen so it is not a concern.
- *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
- *  @ref _CPU_Priority_bits_index.  These three form a set of routines
- *  which must logically operate together.  Bits in the _value are
- *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
- *  The basic major and minor values calculated by @ref _Priority_Major
- *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
- *  to properly range between the values returned by the "find first bit"
- *  instruction.  This makes it possible for @ref _Priority_Get_highest to
- *  calculate the major and directly index into the minor table.
- *  This mapping is necessary to ensure that 0 (a high priority major/minor)
- *  is the first bit found.
- *
- *  This entire "find first bit" and mapping process depends heavily
- *  on the manner in which a priority is broken into a major and minor
- *  components with the major being the 4 MSB of a priority and minor
- *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
- *  to the lowest priority.
- *
- *  If your CPU does not have a "find first bit" instruction, then
- *  there are ways to make do without it.  Here are a handful of ways
- *  to implement this in software:
+ * This routine sets @a _output to the bit number of the first bit
+ * set in @a _value.  @a _value is of CPU dependent type
+ * @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
+ * wide although only the 16 least significant bits will be used.
+ *
+ * There are a number of variables in using a "find first bit" type
+ * instruction.
+ *
+ *   -# What happens when run on a value of zero?
+ *   -# Bits may be numbered from MSB to LSB or vice-versa.
+ *   -# The numbering may be zero or one based.
+ *   -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ * RTEMS guarantees that (1) will never happen so it is not a concern.
+ * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ * @ref _CPU_Priority_bits_index.  These three form a set of routines
+ * which must logically operate together.  Bits in the _value are
+ * set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ * The basic major and minor values calculated by @ref _Priority_Major
+ * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ * to properly range between the values returned by the "find first bit"
+ * instruction.  This makes it possible for @ref _Priority_Get_highest to
+ * calculate the major and directly index into the minor table.
+ * This mapping is necessary to ensure that 0 (a high priority major/minor)
+ * is the first bit found.
+ *
+ * This entire "find first bit" and mapping process depends heavily
+ * on the manner in which a priority is broken into a major and minor
+ * components with the major being the 4 MSB of a priority and minor
+ * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ * to the lowest priority.
+ *
+ * If your CPU does not have a "find first bit" instruction, then
+ * there are ways to make do without it.  Here are a handful of ways
+ * to implement this in software:
  *
 @verbatim
       - a series of 16 bit test instructions
@@ -995,15 +994,15 @@ extern char _gp[];
         _number += bit_set_table[ _value ]
 @endverbatim
 
- *    where bit_set_table[ 16 ] has values which indicate the first
- *      bit set
+ *   where bit_set_table[ 16 ] has values which indicate the first
+ *     bit set
  *
- *  @param[in] _value is the value to be scanned
- *  @param[in] _output is the first bit set
+ * @param[in] _value is the value to be scanned
+ * @param[in] _output is the first bit set
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
@@ -1015,14 +1014,16 @@ extern char _gp[];
 
 /* end of Bitfield handler macros */
 
+/** @} */
+
 /**
- *  This routine builds the mask which corresponds to the bit fields
- *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
- *  for that routine.
+ * This routine builds the mask which corresponds to the bit fields
+ * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
+ * for that routine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1032,17 +1033,17 @@ extern char _gp[];
 #endif
 
 /**
- *  @ingroup CPUBitfield
- *  This routine translates the bit numbers returned by
- *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
- *  a major or minor component of a priority.  See the discussion
- *  for that routine.
+ * @ingroup CPUBitfield
+ * This routine translates the bit numbers returned by
+ * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ * a major or minor component of a priority.  See the discussion
+ * for that routine.
  *
- *  @param[in] _priority is the major or minor number to translate
+ * @param[in] _priority is the major or minor number to translate
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1056,26 +1057,30 @@ extern char _gp[];
 /* functions */
 
 /**
- *  This routine performs CPU dependent initialization.
+ * This routine performs CPU dependent initialization.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Initialize(void);
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs a "raw" interrupt handler directly into the
- *  processor's vector table.
+ * @addtogroup CPUInterrupt
+ */
+/**@{**/
+
+/**
+ * This routine installs a "raw" interrupt handler directly into the
+ * processor's vector table.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the raw ISR handler to install
- *  @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the raw ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
@@ -1084,16 +1089,15 @@ void _CPU_ISR_install_raw_handler(
 );
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs an interrupt vector.
+ * This routine installs an interrupt vector.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the RTEMS ISR handler to install
- *  @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the RTEMS ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_ISR_install_vector(
   uint32_t    vector,
@@ -1102,40 +1106,41 @@ void _CPU_ISR_install_vector(
 );
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs the hardware interrupt stack pointer.
+ * This routine installs the hardware interrupt stack pointer.
  *
- *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
- *         is TRUE.
+ * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
+ *        is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Install_interrupt_stack( void );
 
+/** @} */
+
 /**
- *  This routine is the CPU dependent IDLE thread body.
+ * This routine is the CPU dependent IDLE thread body.
  *
- *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
- *         is TRUE.
+ * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
+ *        is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void *_CPU_Thread_Idle_body( uintptr_t ignored );
 
 /**
- *  @ingroup CPUContext
- *  This routine switches from the run context to the heir context.
+ * @ingroup CPUContext
+ * This routine switches from the run context to the heir context.
  *
- *  @param[in] run points to the context of the currently executing task
- *  @param[in] heir points to the context of the heir task
+ * @param[in] run points to the context of the currently executing task
+ * @param[in] heir points to the context of the heir task
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_switch(
   Context_Control  *run,
@@ -1143,90 +1148,94 @@ void _CPU_Context_switch(
 );
 
 /**
- *  @ingroup CPUContext
- *  This routine is generally used only to restart self in an
- *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
+ * @addtogroup CPUContext
+ */
+/**@{**/
+
+/**
+ * This routine is generally used only to restart self in an
+ * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
  *
- *  @param[in] new_context points to the context to be restored.
+ * @param[in] new_context points to the context to be restored.
  *
- *  @note May be unnecessary to reload some registers.
+ * NOTE: May be unnecessary to reload some registers.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_restore(
   Context_Control *new_context
 ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
 
 /**
- *  @ingroup CPUContext
- *  This routine saves the floating point context passed to it.
+ * This routine saves the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
- *  point context area
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area
  *
- *  @return on output @a *fp_context_ptr will contain the address that
- *  should be used with @ref _CPU_Context_restore_fp to restore this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_restore_fp to restore this context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_save_fp(
   Context_Control_fp **fp_context_ptr
 );
 
 /**
- *  @ingroup CPUContext
- *  This routine restores the floating point context passed to it.
+ * This routine restores the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
- *  point context area to restore
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area to restore
  *
- *  @return on output @a *fp_context_ptr will contain the address that
- *  should be used with @ref _CPU_Context_save_fp to save this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_save_fp to save this context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_restore_fp(
   Context_Control_fp **fp_context_ptr
 );
 
+/** @} */
+
 /* FIXME */
 typedef CPU_Interrupt_frame CPU_Exception_frame;
 
 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
 
 /**
- *  @ingroup CPUEndian
- *  The following routine swaps the endian format of an unsigned int.
- *  It must be static because it is referenced indirectly.
+ * @ingroup CPUEndian
+ * The following routine swaps the endian format of an unsigned int.
+ * It must be static because it is referenced indirectly.
  *
- *  This version will work on any processor, but if there is a better
- *  way for your CPU PLEASE use it.  The most common way to do this is to:
+ * This version will work on any processor, but if there is a better
+ * way for your CPU PLEASE use it.  The most common way to do this is to:
  *
- *     swap least significant two bytes with 16-bit rotate
- *     swap upper and lower 16-bits
- *     swap most significant two bytes with 16-bit rotate
+ *    swap least significant two bytes with 16-bit rotate
+ *    swap upper and lower 16-bits
+ *    swap most significant two bytes with 16-bit rotate
  *
- *  Some CPUs have special instructions which swap a 32-bit quantity in
- *  a single instruction (e.g. i486).  It is probably best to avoid
- *  an "endian swapping control bit" in the CPU.  One good reason is
- *  that interrupts would probably have to be disabled to ensure that
- *  an interrupt does not try to access the same "chunk" with the wrong
- *  endian.  Another good reason is that on some CPUs, the endian bit
- *  endianness for ALL fetches -- both code and data -- so the code
- *  will be fetched incorrectly.
+ * Some CPUs have special instructions which swap a 32-bit quantity in
+ * a single instruction (e.g. i486).  It is probably best to avoid
+ * an "endian swapping control bit" in the CPU.  One good reason is
+ * that interrupts would probably have to be disabled to ensure that
+ * an interrupt does not try to access the same "chunk" with the wrong
+ * endian.  Another good reason is that on some CPUs, the endian bit
+ * endianness for ALL fetches -- both code and data -- so the code
+ * will be fetched incorrectly.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 static inline uint32_t CPU_swap_u32(
   uint32_t value
@@ -1244,11 +1253,11 @@ static inline uint32_t CPU_swap_u32(
 }
 
 /**
- *  @ingroup CPUEndian
- *  This routine swaps a 16 bir quantity.
+ * @ingroup CPUEndian
+ * This routine swaps a 16 bir quantity.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  */
 static inline uint16_t CPU_swap_u16(uint16_t v)
 {
diff --git a/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h b/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h
index 7eada7827d..49d0aed5f3 100644
--- a/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/lm32/rtems/score/cpu_asm.h
@@ -1,12 +1,14 @@
 /**
- * @file rtems/score/cpu_asm.h
+ * @file
+ *
+ * @brief LM32 CPU Assembly File
+ *
+ * Very loose template for an include file for the cpu_asm.? file
+ * if it is implemented as a ".S" file (preprocessed by cpp) instead
+ * of a ".s" file (preprocessed by gm4 or gasp).
  */
 
 /*
- *  Very loose template for an include file for the cpu_asm.? file
- *  if it is implemented as a ".S" file (preprocessed by cpp) instead
- *  of a ".s" file (preprocessed by gm4 or gasp).
- *
  *  COPYRIGHT (c) 1989-2008.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/lm32/rtems/score/lm32.h b/cpukit/score/cpu/lm32/rtems/score/lm32.h
index b1d5edd688..4d03d953ed 100644
--- a/cpukit/score/cpu/lm32/rtems/score/lm32.h
+++ b/cpukit/score/cpu/lm32/rtems/score/lm32.h
@@ -1,11 +1,14 @@
-/*  lm32.h
- *
- *  This file sets up basic CPU dependency settings based on
- *  compiler settings.  For example, it can determine if
- *  floating point is available.  This particular implementation
- *  is specified to the NO CPU port.
+/**
+ * @file
  *
+ * @brief LM32 Set up Basic CPU Dependency Settings Based on Compiler Settings
  *
+ * This file sets up basic CPU dependency settings based on
+ * compiler settings.  For example, it can determine if
+ * floating point is available.  This particular implementation
+ * is specified to the NO CPU port.
+ */
+/*
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/lm32/rtems/score/types.h b/cpukit/score/cpu/lm32/rtems/score/types.h
index aee9f923c1..7caae46e61 100644
--- a/cpukit/score/cpu/lm32/rtems/score/types.h
+++ b/cpukit/score/cpu/lm32/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief LM32 CPU Type Definitions
+ *
+ * This include file contains type definitions pertaining to the
+ * Lattice lm32 processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the
- *  Lattice lm32 processor family.
- *
  *  COPYRIGHT (c) 1989-2006.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/m32c/rtems/asm.h b/cpukit/score/cpu/m32c/rtems/asm.h
index 6d9dcb75b6..f3f244d066 100644
--- a/cpukit/score/cpu/m32c/rtems/asm.h
+++ b/cpukit/score/cpu/m32c/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
+ * 
+ * @brief Address the Problems Caused by Incompatible Flavor of 
+ * Assemblers and Toolsets
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ * 
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
@@ -38,24 +41,21 @@
 
 #ifndef __USER_LABEL_PREFIX__
 /**
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents.  If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
  *
- *  This symbol is prefixed to all C program symbols.
+ * This symbol is prefixed to all C program symbols.
  */
 #define __USER_LABEL_PREFIX__ _
 #endif
 
 #ifndef __REGISTER_PREFIX__
 /**
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
+ * @see __USER_LABEL_PREFIX__
  *
- *  This symbol is prefixed to all register names.
+ * This symbol is prefixed to all register names.
  */
 #define __REGISTER_PREFIX__
 #endif
@@ -83,7 +83,9 @@
 #define BEGIN_CODE_DCL .text
 /** This macro is used to denote the end of a code declaration. */
 #define END_CODE_DCL
-/** This macro is used to denote the beginning of a data declaration section. */
+/** 
+ * This macro is used to denote the beginning of a data declaration section.
+ */
 #define BEGIN_DATA_DCL .data
 /** This macro is used to denote the end of a data declaration section. */
 #define END_DATA_DCL
@@ -105,18 +107,17 @@
 #define END
 
 /**
- *  This macro is used to declare a public global symbol.
+ * This macro is used to declare a public global symbol.
  *
- *  @note This must be tailored for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
+ * NOTE: This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
  */
 #define PUBLIC(sym) .globl SYM (sym)
 
 /**
- *  This macro is used to prototype a public global symbol.
+ * This macro is used to prototype a public global symbol.
  *
- *  @note This must be tailored for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
+ * @see PUBLIC(sym) .globl SYM (sym)
  */
 #define EXTERN(sym) .globl SYM (sym)
 
diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu.h b/cpukit/score/cpu/m32c/rtems/score/cpu.h
index 10cdc5b60a..8d9acc37f3 100644
--- a/cpukit/score/cpu/m32c/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m32c/rtems/score/cpu.h
@@ -1,5 +1,7 @@
 /**
- * @file rtems/score/cpu.h
+ * @file
+ * 
+ * @brief M32C CPU Dependent Source
  */
 
 /*
@@ -43,172 +45,172 @@ extern "C" {
 #define RTEMS_USE_16_BIT_OBJECT
 
 /**
- *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ * Should the calls to @ref _Thread_Enable_dispatch be inlined?
  *
- *  If TRUE, then they are inlined.
- *  If FALSE, then a subroutine call is made.
+ * If TRUE, then they are inlined.
+ * If FALSE, then a subroutine call is made.
  *
- *  This conditional is an example of the classic trade-off of size
- *  versus speed.  Inlining the call (TRUE) typically increases the
- *  size of RTEMS while speeding up the enabling of dispatching.
+ * This conditional is an example of the classic trade-off of size
+ * versus speed.  Inlining the call (TRUE) typically increases the
+ * size of RTEMS while speeding up the enabling of dispatching.
  *
- *  @note In general, the @ref _Thread_Dispatch_disable_level will
- *  only be 0 or 1 unless you are in an interrupt handler and that
- *  interrupt handler invokes the executive.]  When not inlined
- *  something calls @ref _Thread_Enable_dispatch which in turns calls
- *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
- *  one subroutine call is avoided entirely.
+ * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
+ * only be 0 or 1 unless you are in an interrupt handler and that
+ * interrupt handler invokes the executive.]  When not inlined
+ * something calls @ref _Thread_Enable_dispatch which in turns calls
+ * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
+ * one subroutine call is avoided entirely.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INLINE_ENABLE_DISPATCH       FALSE
 
 /**
- *  Should the body of the search loops in _Thread_queue_Enqueue_priority
- *  be unrolled one time?  In unrolled each iteration of the loop examines
- *  two "nodes" on the chain being searched.  Otherwise, only one node
- *  is examined per iteration.
- *
- *  If TRUE, then the loops are unrolled.
- *  If FALSE, then the loops are not unrolled.
- *
- *  The primary factor in making this decision is the cost of disabling
- *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- *  body of the loop.  On some CPUs, the flash is more expensive than
- *  one iteration of the loop body.  In this case, it might be desirable
- *  to unroll the loop.  It is important to note that on some CPUs, this
- *  code is the longest interrupt disable period in RTEMS.  So it is
- *  necessary to strike a balance when setting this parameter.
+ * Should the body of the search loops in _Thread_queue_Enqueue_priority
+ * be unrolled one time?  In unrolled each iteration of the loop examines
+ * two "nodes" on the chain being searched.  Otherwise, only one node
+ * is examined per iteration.
  *
- *  Port Specific Information:
+ * If TRUE, then the loops are unrolled.
+ * If FALSE, then the loops are not unrolled.
  *
- *  XXX document implementation including references if appropriate
+ * The primary factor in making this decision is the cost of disabling
+ * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ * body of the loop.  On some CPUs, the flash is more expensive than
+ * one iteration of the loop body.  In this case, it might be desirable
+ * to unroll the loop.  It is important to note that on some CPUs, this
+ * code is the longest interrupt disable period in RTEMS.  So it is
+ * necessary to strike a balance when setting this parameter.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 #define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
 
 /**
- *  Does RTEMS manage a dedicated interrupt stack in software?
+ * Does RTEMS manage a dedicated interrupt stack in software?
  *
- *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
- *  If FALSE, nothing is done.
+ * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ * If FALSE, nothing is done.
  *
- *  If the CPU supports a dedicated interrupt stack in hardware,
- *  then it is generally the responsibility of the BSP to allocate it
- *  and set it up.
+ * If the CPU supports a dedicated interrupt stack in hardware,
+ * then it is generally the responsibility of the BSP to allocate it
+ * and set it up.
  *
- *  If the CPU does not support a dedicated interrupt stack, then
- *  the porter has two options: (1) execute interrupts on the
- *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
- *  interrupt stack.
+ * If the CPU does not support a dedicated interrupt stack, then
+ * the porter has two options: (1) execute interrupts on the
+ * stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ * interrupt stack.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
 
 /**
- *  Does the CPU follow the simple vectored interrupt model?
+ * Does the CPU follow the simple vectored interrupt model?
  *
- *  If TRUE, then RTEMS allocates the vector table it internally manages.
- *  If FALSE, then the BSP is assumed to allocate and manage the vector
- *  table
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
 
 /**
- *  Does this CPU have hardware support for a dedicated interrupt stack?
+ * Does this CPU have hardware support for a dedicated interrupt stack?
  *
- *  If TRUE, then it must be installed during initialization.
- *  If FALSE, then no installation is performed.
+ * If TRUE, then it must be installed during initialization.
+ * If FALSE, then no installation is performed.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
 
 /**
- *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
  *
- *  If TRUE, then the memory is allocated during initialization.
- *  If FALSE, then the memory is allocated during initialization.
+ * If TRUE, then the memory is allocated during initialization.
+ * If FALSE, then the memory is allocated during initialization.
  *
- *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
 
 /**
- *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector
- *  number (0)?
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ISR_PASSES_FRAME_POINTER 0
 
 /**
- *  @def CPU_HARDWARE_FP
+ * @def CPU_HARDWARE_FP
  *
- *  Does the CPU have hardware floating point?
+ * Does the CPU have hardware floating point?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
  *
- *  If there is a FP coprocessor such as the i387 or mc68881, then
- *  the answer is TRUE.
+ * If there is a FP coprocessor such as the i387 or mc68881, then
+ * the answer is TRUE.
  *
- *  The macro name "M32C_HAS_FPU" should be made CPU specific.
- *  It indicates whether or not this CPU model has FP support.  For
- *  example, it would be possible to have an i386_nofp CPU model
- *  which set this to false to indicate that you have an i386 without
- *  an i387 and wish to leave floating point support out of RTEMS.
+ * The macro name "M32C_HAS_FPU" should be made CPU specific.
+ * It indicates whether or not this CPU model has FP support.  For
+ * example, it would be possible to have an i386_nofp CPU model
+ * which set this to false to indicate that you have an i386 without
+ * an i387 and wish to leave floating point support out of RTEMS.
  */
 
 /**
- *  @def CPU_SOFTWARE_FP
+ * @def CPU_SOFTWARE_FP
  *
- *  Does the CPU have no hardware floating point and GCC provides a
- *  software floating point implementation which must be context
- *  switched?
+ * Does the CPU have no hardware floating point and GCC provides a
+ * software floating point implementation which must be context
+ * switched?
  *
- *  This feature conditional is used to indicate whether or not there
- *  is software implemented floating point that must be context
- *  switched.  The determination of whether or not this applies
- *  is very tool specific and the state saved/restored is also
- *  compiler specific.
+ * This feature conditional is used to indicate whether or not there
+ * is software implemented floating point that must be context
+ * switched.  The determination of whether or not this applies
+ * is very tool specific and the state saved/restored is also
+ * compiler specific.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if ( M32C_HAS_FPU == 1 )
 #define CPU_HARDWARE_FP     TRUE
@@ -220,192 +222,195 @@ extern "C" {
 #define CPU_CONTEXT_FP_SIZE 0
 
 /**
- *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
  *
- *  So far, the only CPUs in which this option has been used are the
- *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
- *  gcc both implicitly used the floating point registers to perform
- *  integer multiplies.  Similarly, the PowerPC port of gcc has been
- *  seen to allocate floating point local variables and touch the FPU
- *  even when the flow through a subroutine (like vfprintf()) might
- *  not use floating point formats.
+ * So far, the only CPUs in which this option has been used are the
+ * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
+ * gcc both implicitly used the floating point registers to perform
+ * integer multiplies.  Similarly, the PowerPC port of gcc has been
+ * seen to allocate floating point local variables and touch the FPU
+ * even when the flow through a subroutine (like vfprintf()) might
+ * not use floating point formats.
  *
- *  If a function which you would not think utilize the FP unit DOES,
- *  then one can not easily predict which tasks will use the FP hardware.
- *  In this case, this option should be TRUE.
+ * If a function which you would not think utilize the FP unit DOES,
+ * then one can not easily predict which tasks will use the FP hardware.
+ * In this case, this option should be TRUE.
  *
- *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALL_TASKS_ARE_FP     TRUE
 
 /**
- *  Should the IDLE task have a floating point context?
+ * Should the IDLE task have a floating point context?
  *
- *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- *  and it has a floating point context which is switched in and out.
- *  If FALSE, then the IDLE task does not have a floating point context.
+ * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ * and it has a floating point context which is switched in and out.
+ * If FALSE, then the IDLE task does not have a floating point context.
  *
- *  Setting this to TRUE negatively impacts the time required to preempt
- *  the IDLE task from an interrupt because the floating point context
- *  must be saved as part of the preemption.
+ * Setting this to TRUE negatively impacts the time required to preempt
+ * the IDLE task from an interrupt because the floating point context
+ * must be saved as part of the preemption.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_IDLE_TASK_IS_FP      FALSE
 
 /**
- *  Should the saving of the floating point registers be deferred
- *  until a context switch is made to another different floating point
- *  task?
- *
- *  If TRUE, then the floating point context will not be stored until
- *  necessary.  It will remain in the floating point registers and not
- *  disturned until another floating point task is switched to.
- *
- *  If FALSE, then the floating point context is saved when a floating
- *  point task is switched out and restored when the next floating point
- *  task is restored.  The state of the floating point registers between
- *  those two operations is not specified.
- *
- *  If the floating point context does NOT have to be saved as part of
- *  interrupt dispatching, then it should be safe to set this to TRUE.
- *
- *  Setting this flag to TRUE results in using a different algorithm
- *  for deciding when to save and restore the floating point context.
- *  The deferred FP switch algorithm minimizes the number of times
- *  the FP context is saved and restored.  The FP context is not saved
- *  until a context switch is made to another, different FP task.
- *  Thus in a system with only one FP task, the FP context will never
- *  be saved or restored.
+ * Should the saving of the floating point registers be deferred
+ * until a context switch is made to another different floating point
+ * task?
  *
- *  Port Specific Information:
+ * If TRUE, then the floating point context will not be stored until
+ * necessary.  It will remain in the floating point registers and not
+ * disturned until another floating point task is switched to.
  *
- *  XXX document implementation including references if appropriate
+ * If FALSE, then the floating point context is saved when a floating
+ * point task is switched out and restored when the next floating point
+ * task is restored.  The state of the floating point registers between
+ * those two operations is not specified.
+ *
+ * If the floating point context does NOT have to be saved as part of
+ * interrupt dispatching, then it should be safe to set this to TRUE.
+ *
+ * Setting this flag to TRUE results in using a different algorithm
+ * for deciding when to save and restore the floating point context.
+ * The deferred FP switch algorithm minimizes the number of times
+ * the FP context is saved and restored.  The FP context is not saved
+ * until a context switch is made to another, different FP task.
+ * Thus in a system with only one FP task, the FP context will never
+ * be saved or restored.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 #define CPU_USE_DEFERRED_FP_SWITCH       TRUE
 
 /**
- *  Does this port provide a CPU dependent IDLE task implementation?
+ * Does this port provide a CPU dependent IDLE task implementation?
  *
- *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
- *  must be provided and is the default IDLE thread body instead of
- *  @ref _CPU_Thread_Idle_body.
+ * If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ * must be provided and is the default IDLE thread body instead of
+ * @ref _CPU_Thread_Idle_body.
  *
- *  If FALSE, then use the generic IDLE thread body if the BSP does
- *  not provide one.
+ * If FALSE, then use the generic IDLE thread body if the BSP does
+ * not provide one.
  *
- *  This is intended to allow for supporting processors which have
- *  a low power or idle mode.  When the IDLE thread is executed, then
- *  the CPU can be powered down.
+ * This is intended to allow for supporting processors which have
+ * a low power or idle mode.  When the IDLE thread is executed, then
+ * the CPU can be powered down.
  *
- *  The order of precedence for selecting the IDLE thread body is:
+ * The order of precedence for selecting the IDLE thread body is:
  *
- *    -#  BSP provided
- *    -#  CPU dependent (if provided)
- *    -#  generic (if no BSP and no CPU dependent)
+ *   -#  BSP provided
+ *   -#  CPU dependent (if provided)
+ *   -#  generic (if no BSP and no CPU dependent)
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
 
 /**
- *  Does the stack grow up (toward higher addresses) or down
- *  (toward lower addresses)?
+ * Does the stack grow up (toward higher addresses) or down
+ * (toward lower addresses)?
  *
- *  If TRUE, then the grows upward.
- *  If FALSE, then the grows toward smaller addresses.
+ * If TRUE, then the grows upward.
+ * If FALSE, then the grows toward smaller addresses.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_GROWS_UP               TRUE
 
 /**
- *  The following is the variable attribute used to force alignment
- *  of critical RTEMS structures.  On some processors it may make
- *  sense to have these aligned on tighter boundaries than
- *  the minimum requirements of the compiler in order to have as
- *  much of the critical data area as possible in a cache line.
+ * The following is the variable attribute used to force alignment
+ * of critical RTEMS structures.  On some processors it may make
+ * sense to have these aligned on tighter boundaries than
+ * the minimum requirements of the compiler in order to have as
+ * much of the critical data area as possible in a cache line.
  *
- *  The placement of this macro in the declaration of the variables
- *  is based on the syntactically requirements of the GNU C
- *  "__attribute__" extension.  For example with GNU C, use
- *  the following to force a structures to a 32 byte boundary.
+ * The placement of this macro in the declaration of the variables
+ * is based on the syntactically requirements of the GNU C
+ * "__attribute__" extension.  For example with GNU C, use
+ * the following to force a structures to a 32 byte boundary.
  *
- *      __attribute__ ((aligned (32)))
+ *     __attribute__ ((aligned (32)))
  *
- *  @note Currently only the Priority Bit Map table uses this feature.
- *        To benefit from using this, the data must be heavily
- *        used so it will stay in the cache and used frequently enough
- *        in the executive to justify turning this on.
+ * NOTE: Currently only the Priority Bit Map table uses this feature.
+ *       To benefit from using this, the data must be heavily
+ *       used so it will stay in the cache and used frequently enough
+ *       in the executive to justify turning this on.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (2)))
 
 #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
 
 /**
- *  @defgroup CPUEndian Processor Dependent Endianness Support
+ * @defgroup CPUEndian Processor Dependent Endianness Support
  *
- *  This group assists in issues related to processor endianness.
+ * This group assists in issues related to processor endianness.
+ * 
  */
+/**@{**/
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_LITTLE_ENDIAN
+ * @see CPU_LITTLE_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_BIG_ENDIAN                           TRUE
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_BIG_ENDIAN
+ * @see CPU_BIG_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_LITTLE_ENDIAN                        FALSE
 
+/** @} */
+
 /**
- *  @ingroup CPUInterrupt
- *  The following defines the number of bits actually used in the
- *  interrupt field of the task mode.  How those bits map to the
- *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ * @ingroup CPUInterrupt
+ * 
+ * The following defines the number of bits actually used in the
+ * interrupt field of the task mode.  How those bits map to the
+ * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_MODES_INTERRUPT_MASK   0x00000001
 
@@ -422,50 +427,52 @@ extern "C" {
 /**
  * @defgroup CPUContext Processor Dependent Context Management
  *
- *  From the highest level viewpoint, there are 2 types of context to save.
+ * From the highest level viewpoint, there are 2 types of context to save.
  *
- *     -# Interrupt registers to save
- *     -# Task level registers to save
+ *    -# Interrupt registers to save
+ *    -# Task level registers to save
  *
- *  Since RTEMS handles integer and floating point contexts separately, this
- *  means we have the following 3 context items:
+ * Since RTEMS handles integer and floating point contexts separately, this
+ * means we have the following 3 context items:
  *
- *     -# task level context stuff::  Context_Control
- *     -# floating point task stuff:: Context_Control_fp
- *     -# special interrupt level context :: CPU_Interrupt_frame
+ *    -# task level context stuff::  Context_Control
+ *    -# floating point task stuff:: Context_Control_fp
+ *    -# special interrupt level context :: CPU_Interrupt_frame
  *
- *  On some processors, it is cost-effective to save only the callee
- *  preserved registers during a task context switch.  This means
- *  that the ISR code needs to save those registers which do not
- *  persist across function calls.  It is not mandatory to make this
- *  distinctions between the caller/callee saves registers for the
- *  purpose of minimizing context saved during task switch and on interrupts.
- *  If the cost of saving extra registers is minimal, simplicity is the
- *  choice.  Save the same context on interrupt entry as for tasks in
- *  this case.
+ * On some processors, it is cost-effective to save only the callee
+ * preserved registers during a task context switch.  This means
+ * that the ISR code needs to save those registers which do not
+ * persist across function calls.  It is not mandatory to make this
+ * distinctions between the caller/callee saves registers for the
+ * purpose of minimizing context saved during task switch and on interrupts.
+ * If the cost of saving extra registers is minimal, simplicity is the
+ * choice.  Save the same context on interrupt entry as for tasks in
+ * this case.
  *
- *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- *  care should be used in designing the context area.
+ * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ * care should be used in designing the context area.
  *
- *  On some CPUs with hardware floating point support, the Context_Control_fp
- *  structure will not be used or it simply consist of an array of a
- *  fixed number of bytes.   This is done when the floating point context
- *  is dumped by a "FP save context" type instruction and the format
- *  is not really defined by the CPU.  In this case, there is no need
- *  to figure out the exact format -- only the size.  Of course, although
- *  this is enough information for RTEMS, it is probably not enough for
- *  a debugger such as gdb.  But that is another problem.
+ * On some CPUs with hardware floating point support, the Context_Control_fp
+ * structure will not be used or it simply consist of an array of a
+ * fixed number of bytes.   This is done when the floating point context
+ * is dumped by a "FP save context" type instruction and the format
+ * is not really defined by the CPU.  In this case, there is no need
+ * to figure out the exact format -- only the size.  Of course, although
+ * this is enough information for RTEMS, it is probably not enough for
+ * a debugger such as gdb.  But that is another problem.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
+/**@{**/
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the minimal set of integer and processor state registers
- *  that must be saved during a voluntary context switch from one thread
- *  to another.
+ * @ingroup Management
+ * 
+ * This defines the minimal set of integer and processor state registers
+ * that must be saved during a voluntary context switch from one thread
+ * to another.
  */
 typedef struct {
   /** This will contain the stack pointer. */
@@ -475,49 +482,55 @@ typedef struct {
 } Context_Control;
 
 /**
- *  @ingroup CPUContext Management
+ * @ingroup Management
  *
- *  This macro returns the stack pointer associated with @a _context.
+ * This macro returns the stack pointer associated with @a _context.
  *
- *  @param[in] _context is the thread context area to access
+ * @param[in] _context is the thread context area to access
  *
- *  @return This method returns the stack pointer.
+ * @return This method returns the stack pointer.
  */
 #define _CPU_Context_Get_SP( _context ) \
   (_context)->sp
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the set of integer and processor state registers that must
- *  be saved during an interrupt.  This set does not include any which are
- *  in @ref Context_Control.
+ * @ingroup Management
+ * 
+ * This defines the set of integer and processor state registers that must
+ * be saved during an interrupt.  This set does not include any which are
+ * in @ref Context_Control.
  */
 typedef struct {
-    /** This field is a hint that a port will have a number of integer
-     *  registers that need to be saved when an interrupt occurs or
-     *  when a context switch occurs at the end of an ISR.
+    /** 
+     * This field is a hint that a port will have a number of integer
+     * registers that need to be saved when an interrupt occurs or
+     * when a context switch occurs at the end of an ISR.
      */
     uint32_t   special_interrupt_register;
 } CPU_Interrupt_frame;
 
+/** @} */
+
 /**
- *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ * @defgroup CPUInterrupt Processor Dependent Interrupt Management
  *
- *  On some CPUs, RTEMS supports a software managed interrupt stack.
- *  This stack is allocated by the Interrupt Manager and the switch
- *  is performed in @ref _ISR_Handler.  These variables contain pointers
- *  to the lowest and highest addresses in the chunk of memory allocated
- *  for the interrupt stack.  Since it is unknown whether the stack
- *  grows up or down (in general), this give the CPU dependent
- *  code the option of picking the version it wants to use.
+ * On some CPUs, RTEMS supports a software managed interrupt stack.
+ * This stack is allocated by the Interrupt Manager and the switch
+ * is performed in @ref _ISR_Handler.  These variables contain pointers
+ * to the lowest and highest addresses in the chunk of memory allocated
+ * for the interrupt stack.  Since it is unknown whether the stack
+ * grows up or down (in general), this give the CPU dependent
+ * code the option of picking the version it wants to use.
  *
- *  @note These two variables are required if the macro
- *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ * NOTE: These two variables are required if the macro
+ *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
+ * 
  */
+/**@{**/
 
 /*
  *  Nothing prevents the porter from declaring more CPU specific variables.
@@ -530,48 +543,46 @@ typedef struct {
 /* XXX: if needed, put more variables here */
 
 /**
- *  Amount of extra stack (above minimum stack size) required by
- *  MPCI receive server thread.  Remember that in a multiprocessor
- *  system this thread must exist and be able to process all directives.
+ * Amount of extra stack (above minimum stack size) required by
+ * MPCI receive server thread.  Remember that in a multiprocessor
+ * system this thread must exist and be able to process all directives.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
 
 /**
- *  @ingroup CPUInterrupt
- *  This defines the number of entries in the @ref _ISR_Vector_table managed
- *  by RTEMS.
+ * This defines the number of entries in the @ref _ISR_Vector_table managed
+ * by RTEMS.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
 
-/**
- *  @ingroup CPUInterrupt
- *  This defines the highest interrupt vector number for this port.
- */
+/** This defines the highest interrupt vector number for this port. */
 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
 /**
- *  @ingroup CPUInterrupt
- *  This is defined if the port has a special way to report the ISR nesting
- *  level.  Most ports maintain the variable @a _ISR_Nest_level.
+ * This is defined if the port has a special way to report the ISR nesting
+ * level.  Most ports maintain the variable @a _ISR_Nest_level.
  */
 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
+/** @} */
+
 /**
- *  @ingroup CPUContext
- *  Should be large enough to run all RTEMS tests.  This ensures
- *  that a "reasonable" small application should not have any problems.
+ * @ingroup CPUContext
+ * 
+ * Should be large enough to run all RTEMS tests.  This ensures
+ * that a "reasonable" small application should not have any problems.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_MINIMUM_SIZE          (2048L)
 
@@ -582,70 +593,70 @@ typedef struct {
 #endif
 
 /**
- *  CPU's worst alignment requirement for data types on a byte boundary.  This
- *  alignment does not take into account the requirements for the stack.
+ * CPU's worst alignment requirement for data types on a byte boundary.  This
+ * alignment does not take into account the requirements for the stack.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALIGNMENT              2
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  heap handler.  This alignment requirement may be stricter than that
- *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
- *  common for the heap to follow the same alignment requirement as
- *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
- *  the heap, then this should be set to @ref CPU_ALIGNMENT.
- *
- *  @note  This does not have to be a power of 2 although it should be
- *         a multiple of 2 greater than or equal to 2.  The requirement
- *         to be a multiple of 2 is because the heap uses the least
- *         significant field of the front and back flags to indicate
- *         that a block is in use or free.  So you do not want any odd
- *         length blocks really putting length data in that bit.
- *
- *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
- *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
- *         elements allocated from the heap meet all restrictions.
+ * This number corresponds to the byte alignment requirement for the
+ * heap handler.  This alignment requirement may be stricter than that
+ * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
+ * common for the heap to follow the same alignment requirement as
+ * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
+ * the heap, then this should be set to @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * NOTE:  This does not have to be a power of 2 although it should be
+ *        a multiple of 2 greater than or equal to 2.  The requirement
+ *        to be a multiple of 2 is because the heap uses the least
+ *        significant field of the front and back flags to indicate
+ *        that a block is in use or free.  So you do not want any odd
+ *        length blocks really putting length data in that bit.
  *
- *  XXX document implementation including references if appropriate
+ *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ *        elements allocated from the heap meet all restrictions.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HEAP_ALIGNMENT         4
 
 /**
- *  This number corresponds to the byte alignment requirement for memory
- *  buffers allocated by the partition manager.  This alignment requirement
- *  may be stricter than that for the data types alignment specified by
- *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
- *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
- *  strict enough for the partition, then this should be set to
- *  @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for memory
+ * buffers allocated by the partition manager.  This alignment requirement
+ * may be stricter than that for the data types alignment specified by
+ * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
+ * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
+ * strict enough for the partition, then this should be set to
+ * @ref CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than @ref CPU_ALIGNMENT.
+ * NOTE:  This does not have to be a power of 2.  It does have to
+ *        be greater or equal to than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  stack.  This alignment requirement may be stricter than that for the
- *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
- *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
- *  set to 0.
+ * This number corresponds to the byte alignment requirement for the
+ * stack.  This alignment requirement may be stricter than that for the
+ * data types alignment specified by @ref CPU_ALIGNMENT.  If the
+ * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
+ * set to 0.
  *
- *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
+ * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_ALIGNMENT        0
 
@@ -654,25 +665,27 @@ typedef struct {
  */
 
 /**
- *  @ingroup CPUInterrupt
- *  Support routine to initialize the RTEMS vector table after it is allocated.
+ * @ingroup CPUInterrupt
+ * 
+ * Support routine to initialize the RTEMS vector table after it is allocated.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Initialize_vectors()
 
 /**
- *  @ingroup CPUInterrupt
- *  Disable all interrupts for an RTEMS critical section.  The previous
- *  level is returned in @a _isr_cookie.
+ * @ingroup CPUInterrupt
+ * 
+ * Disable all interrupts for an RTEMS critical section.  The previous
+ * level is returned in @a _isr_cookie.
  *
- *  @param[out] _isr_cookie will contain the previous level cookie
+ * @param[out] _isr_cookie will contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Disable( _isr_cookie ) \
   do { \
@@ -683,16 +696,17 @@ typedef struct {
   } while(0)
 
 /**
- *  @ingroup CPUInterrupt
- *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- *  This indicates the end of an RTEMS critical section.  The parameter
- *  @a _isr_cookie is not modified.
+ * @ingroup CPUInterrupt
+ * 
+ * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ * This indicates the end of an RTEMS critical section.  The parameter
+ * @a _isr_cookie is not modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Enable(_isr_cookie) \
   do { \
@@ -701,17 +715,18 @@ typedef struct {
   } while(0)
 
 /**
- *  @ingroup CPUInterrupt
- *  This temporarily restores the interrupt to @a _isr_cookie before immediately
- *  disabling them again.  This is used to divide long RTEMS critical
- *  sections into two or more parts.  The parameter @a _isr_cookie is not
- *  modified.
+ * @ingroup CPUInterrupt
+ * 
+ * This temporarily restores the interrupt to @a _isr_cookie before immediately
+ * disabling them again.  This is used to divide long RTEMS critical
+ * sections into two or more parts.  The parameter @a _isr_cookie is not
+ * modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Flash( _isr_cookie ) \
   do { \
@@ -721,21 +736,21 @@ typedef struct {
   } while(0)
 
 /**
- *  @ingroup CPUInterrupt
- *
- *  This routine and @ref _CPU_ISR_Get_level
- *  Map the interrupt level in task mode onto the hardware that the CPU
- *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a generic fashion are undefined.  Someday,
- *  it would be nice if these were "mapped" by the application
- *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
- *  8 - 255 would be available for bsp/application specific meaning.
- *  This could be used to manage a programmable interrupt controller
- *  via the rtems_task_mode directive.
+ * @ingroup CPUInterrupt
  *
- *  Port Specific Information:
+ * This routine and @ref _CPU_ISR_Get_level
+ * Map the interrupt level in task mode onto the hardware that the CPU
+ * actually provides.  Currently, interrupt levels which do not
+ * map onto the CPU in a generic fashion are undefined.  Someday,
+ * it would be nice if these were "mapped" by the application
+ * via a callout.  For example, m68k has 8 levels 0 - 7, levels
+ * 8 - 255 would be available for bsp/application specific meaning.
+ *This could be used to manage a programmable interrupt controller
+ * via the rtems_task_mode directive.
  *
- *  XXX document implementation including references if appropriate
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Set_level( _new_level ) \
   do { \
@@ -744,15 +759,16 @@ typedef struct {
   } while(0)
 
 /**
- *  @ingroup CPUInterrupt
- *  Return the current interrupt disable level for this task in
- *  the format used by the interrupt level portion of the task mode.
+ * @ingroup CPUInterrupt
+ * 
+ * Return the current interrupt disable level for this task in
+ * the format used by the interrupt level portion of the task mode.
  *
- *  @note This routine usually must be implemented as a subroutine.
+ * NOTE: This routine usually must be implemented as a subroutine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 uint32_t   _CPU_ISR_Get_level( void );
 
@@ -761,35 +777,36 @@ uint32_t   _CPU_ISR_Get_level( void );
 /* Context handler macros */
 
 /**
- *  @ingroup CPUContext
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
- *
- *     - setting a starting address
- *     - preparing the stack
- *     - preparing the stack and frame pointers
- *     - setting the proper interrupt level in the context
- *     - initializing the floating point context
- *
- *  This routine generally does not set any unnecessary register
- *  in the context.  The state of the "general data" registers is
- *  undefined at task start time.
- *
- *  @param[in] _the_context is the context structure to be initialized
- *  @param[in] _stack_base is the lowest physical address of this task's stack
- *  @param[in] _size is the size of this task's stack
- *  @param[in] _isr is the interrupt disable level
- *  @param[in] _entry_point is the thread's entry point.  This is
- *         always @a _Thread_Handler
- *  @param[in] _is_fp is TRUE if the thread is to be a floating
- *        point thread.  This is typically only used on CPUs where the
- *        FPU may be easily disabled by software such as on the SPARC
- *        where the PSR contains an enable FPU bit.
- *
- *  Port Specific Information:
- *
- *  XXX document implementation including references if appropriate
+ * @ingroup CPUContext
+ * 
+ * Initialize the context to a state suitable for starting a
+ * task after a context restore operation.  Generally, this
+ * involves:
+ *
+ *    - setting a starting address
+ *    - preparing the stack
+ *    - preparing the stack and frame pointers
+ *    - setting the proper interrupt level in the context
+ *    - initializing the floating point context
+ *
+ * This routine generally does not set any unnecessary register
+ * in the context.  The state of the "general data" registers is
+ * undefined at task start time.
+ *
+ * @param[in] _the_context is the context structure to be initialized
+ * @param[in] _stack_base is the lowest physical address of this task's stack
+ * @param[in] _size is the size of this task's stack
+ * @param[in] _isr is the interrupt disable level
+ * @param[in] _entry_point is the thread's entry point.  This is
+ *        always @a _Thread_Handler
+ * @param[in] _is_fp is TRUE if the thread is to be a floating
+ *       point thread.  This is typically only used on CPUs where the
+ *       FPU may be easily disabled by software such as on the SPARC
+ *       where the PSR contains an enable FPU bit.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_Initialize(
   Context_Control  *the_context,
@@ -801,66 +818,67 @@ void _CPU_Context_Initialize(
 );
 
 /**
- *  This routine is responsible for somehow restarting the currently
- *  executing task.  If you are lucky, then all that is necessary
- *  is restoring the context.  Otherwise, there will need to be
- *  a special assembly routine which does something special in this
- *  case.  For many ports, simply adding a label to the restore path
- *  of @ref _CPU_Context_switch will work.  On other ports, it may be
- *  possibly to load a few arguments and jump to the restore path. It will
- *  not work if restarting self conflicts with the stack frame
- *  assumptions of restoring a context.
+ * This routine is responsible for somehow restarting the currently
+ * executing task.  If you are lucky, then all that is necessary
+ * is restoring the context.  Otherwise, there will need to be
+ * a special assembly routine which does something special in this
+ * case.  For many ports, simply adding a label to the restore path
+ * of @ref _CPU_Context_switch will work.  On other ports, it may be
+ * possibly to load a few arguments and jump to the restore path. It will
+ * not work if restarting self conflicts with the stack frame
+ * assumptions of restoring a context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_Restart_self(
   Context_Control  *the_context
 );
 
 /**
- *  @ingroup CPUContext
- *  The purpose of this macro is to allow the initial pointer into
- *  a floating point context area (used to save the floating point
- *  context) to be at an arbitrary place in the floating point
- *  context area.
- *
- *  This is necessary because some FP units are designed to have
- *  their context saved as a stack which grows into lower addresses.
- *  Other FP units can be saved by simply moving registers into offsets
- *  from the base of the context area.  Finally some FP units provide
- *  a "dump context" instruction which could fill in from high to low
- *  or low to high based on the whim of the CPU designers.
- *
- *  @param[in] _base is the lowest physical address of the floating point
- *         context area
- *  @param[in] _offset is the offset into the floating point area
+ * @ingroup CPUContext
+ * 
+ * The purpose of this macro is to allow the initial pointer into
+ * a floating point context area (used to save the floating point
+ * context) to be at an arbitrary place in the floating point
+ * context area.
  *
- *  Port Specific Information:
+ * This is necessary because some FP units are designed to have
+ * their context saved as a stack which grows into lower addresses.
+ * Other FP units can be saved by simply moving registers into offsets
+ * from the base of the context area.  Finally some FP units provide
+ * a "dump context" instruction which could fill in from high to low
+ * or low to high based on the whim of the CPU designers.
  *
- *  XXX document implementation including references if appropriate
+ * @param[in] _base is the lowest physical address of the floating point
+ *        context area
+ * @param[in] _offset is the offset into the floating point area
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Fp_start( _base, _offset ) \
    ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
 
 /**
- *  This routine initializes the FP context area passed to it to.
- *  There are a few standard ways in which to initialize the
- *  floating point context.  The code included for this macro assumes
- *  that this is a CPU in which a "initial" FP context was saved into
- *  @a _CPU_Null_fp_context and it simply copies it to the destination
- *  context passed to it.
+ * This routine initializes the FP context area passed to it to.
+ * There are a few standard ways in which to initialize the
+ * floating point context.  The code included for this macro assumes
+ * that this is a CPU in which a "initial" FP context was saved into
+ * @a _CPU_Null_fp_context and it simply copies it to the destination
+ * context passed to it.
  *
- *  Other floating point context save/restore models include:
- *    -# not doing anything, and
- *    -# putting a "null FP status word" in the correct place in the FP context.
+ * Other floating point context save/restore models include:
+ *   -# not doing anything, and
+ *   -# putting a "null FP status word" in the correct place in the FP context.
  *
- *  @param[in] _destination is the floating point context area
+ * @param[in] _destination is the floating point context area
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Initialize_fp( _destination ) \
   { \
@@ -872,13 +890,13 @@ void _CPU_Context_Restart_self(
 /* Fatal Error manager macros */
 
 /**
- *  This routine copies _error into a known place -- typically a stack
- *  location or a register, optionally disables interrupts, and
- *  halts/stops the CPU.
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Fatal_halt( _error ) \
   { \
@@ -889,68 +907,66 @@ void _CPU_Context_Restart_self(
 /* Bitfield handler macros */
 
 /**
- *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
  *
- *  This set of routines are used to implement fast searches for
- *  the most important ready task.
+ * This set of routines are used to implement fast searches for
+ * the most important ready task.
  */
+/**@{**/
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the generic bitfield
- *  manipulation implementation.
+ * This definition is set to TRUE if the port uses the generic bitfield
+ * manipulation implementation.
  */
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the data tables provided
- *  by the generic bitfield manipulation implementation.
- *  This can occur when actually using the generic bitfield manipulation
- *  implementation or when implementing the same algorithm in assembly
- *  language for improved performance.  It is unlikely that a port will use
- *  the data if it has a bitfield scan instruction.
+ * This definition is set to TRUE if the port uses the data tables provided
+ * by the generic bitfield manipulation implementation.
+ * This can occur when actually using the generic bitfield manipulation
+ * implementation or when implementing the same algorithm in assembly
+ * language for improved performance.  It is unlikely that a port will use
+ * the data if it has a bitfield scan instruction.
  */
 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This routine sets @a _output to the bit number of the first bit
- *  set in @a _value.  @a _value is of CPU dependent type
- *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
- *  wide although only the 16 least significant bits will be used.
- *
- *  There are a number of variables in using a "find first bit" type
- *  instruction.
- *
- *    -# What happens when run on a value of zero?
- *    -# Bits may be numbered from MSB to LSB or vice-versa.
- *    -# The numbering may be zero or one based.
- *    -# The "find first bit" instruction may search from MSB or LSB.
- *
- *  RTEMS guarantees that (1) will never happen so it is not a concern.
- *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
- *  @ref _CPU_Priority_bits_index.  These three form a set of routines
- *  which must logically operate together.  Bits in the _value are
- *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
- *  The basic major and minor values calculated by @ref _Priority_Major
- *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
- *  to properly range between the values returned by the "find first bit"
- *  instruction.  This makes it possible for @ref _Priority_Get_highest to
- *  calculate the major and directly index into the minor table.
- *  This mapping is necessary to ensure that 0 (a high priority major/minor)
- *  is the first bit found.
- *
- *  This entire "find first bit" and mapping process depends heavily
- *  on the manner in which a priority is broken into a major and minor
- *  components with the major being the 4 MSB of a priority and minor
- *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
- *  to the lowest priority.
- *
- *  If your CPU does not have a "find first bit" instruction, then
- *  there are ways to make do without it.  Here are a handful of ways
- *  to implement this in software:
+ * This routine sets @a _output to the bit number of the first bit
+ * set in @a _value.  @a _value is of CPU dependent type
+ * @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
+ * wide although only the 16 least significant bits will be used.
+ *
+ * There are a number of variables in using a "find first bit" type
+ * instruction.
+ *
+ *   -# What happens when run on a value of zero?
+ *   -# Bits may be numbered from MSB to LSB or vice-versa.
+ *   -# The numbering may be zero or one based.
+ *   -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ * RTEMS guarantees that (1) will never happen so it is not a concern.
+ * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ * @ref _CPU_Priority_bits_index.  These three form a set of routines
+ * which must logically operate together.  Bits in the _value are
+ * set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ * The basic major and minor values calculated by @ref _Priority_Major
+ * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ * to properly range between the values returned by the "find first bit"
+ * instruction.  This makes it possible for @ref _Priority_Get_highest to
+ * calculate the major and directly index into the minor table.
+ * This mapping is necessary to ensure that 0 (a high priority major/minor)
+ * is the first bit found.
+ *
+ * This entire "find first bit" and mapping process depends heavily
+ * on the manner in which a priority is broken into a major and minor
+ * components with the major being the 4 MSB of a priority and minor
+ * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ * to the lowest priority.
+ *
+ * If your CPU does not have a "find first bit" instruction, then
+ * there are ways to make do without it.  Here are a handful of ways
+ * to implement this in software:
  *
 @verbatim
       - a series of 16 bit test instructions
@@ -967,15 +983,15 @@ void _CPU_Context_Restart_self(
         _number += bit_set_table[ _value ]
 @endverbatim
 
- *    where bit_set_table[ 16 ] has values which indicate the first
- *      bit set
+ *   where bit_set_table[ 16 ] has values which indicate the first
+ *     bit set
  *
- *  @param[in] _value is the value to be scanned
- *  @param[in] _output is the first bit set
+ * @param[in] _value is the value to be scanned
+ * @param[in] _output is the first bit set
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
@@ -988,13 +1004,13 @@ void _CPU_Context_Restart_self(
 /* end of Bitfield handler macros */
 
 /**
- *  This routine builds the mask which corresponds to the bit fields
- *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
- *  for that routine.
+ * This routine builds the mask which corresponds to the bit fields
+ * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
+ * for that routine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1004,17 +1020,16 @@ void _CPU_Context_Restart_self(
 #endif
 
 /**
- *  @ingroup CPUBitfield
- *  This routine translates the bit numbers returned by
- *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
- *  a major or minor component of a priority.  See the discussion
- *  for that routine.
+ * This routine translates the bit numbers returned by
+ * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ * a major or minor component of a priority.  See the discussion
+ * for that routine.
  *
- *  @param[in] _priority is the major or minor number to translate
+ * @param[in] _priority is the major or minor number to translate
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1023,31 +1038,34 @@ void _CPU_Context_Restart_self(
 
 #endif
 
+/** @} */
+
 /* end of Priority handler macros */
 
 /* functions */
 
 /**
- *  This routine performs CPU dependent initialization.
+ * This routine performs CPU dependent initialization.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Initialize(void);
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs a "raw" interrupt handler directly into the
- *  processor's vector table.
+ * @ingroup CPUInterrupt
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the raw ISR handler to install
- *  @param[in] old_handler is the previously installed ISR Handler
+ * This routine installs a "raw" interrupt handler directly into the
+ * processor's vector table.
  *
- *  Port Specific Information:
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the raw ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
  *
- *  XXX document implementation including references if appropriate
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
@@ -1056,16 +1074,17 @@ void _CPU_ISR_install_raw_handler(
 );
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs an interrupt vector.
+ * @ingroup CPUInterrupt
+ * 
+ * This routine installs an interrupt vector.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the RTEMS ISR handler to install
- *  @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the RTEMS ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_ISR_install_vector(
   uint32_t    vector,
@@ -1074,40 +1093,42 @@ void _CPU_ISR_install_vector(
 );
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs the hardware interrupt stack pointer.
+ * @ingroup CPUInterrupt
  *
- *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
- *         is TRUE.
+ * This routine installs the hardware interrupt stack pointer.
  *
- *  Port Specific Information:
+ * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
+ *        is TRUE.
  *
- *  XXX document implementation including references if appropriate
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Install_interrupt_stack( void );
 
 /**
- *  This routine is the CPU dependent IDLE thread body.
+ * This routine is the CPU dependent IDLE thread body.
  *
- *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
- *         is TRUE.
+ * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
+ *        is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void *_CPU_Thread_Idle_body( uintptr_t ignored );
 
 /**
- *  @ingroup CPUContext
- *  This routine switches from the run context to the heir context.
+ * @ingroup CPUContext
+ * 
+ * This routine switches from the run context to the heir context.
  *
- *  @param[in] run points to the context of the currently executing task
- *  @param[in] heir points to the context of the heir task
+ * @param[in] run points to the context of the currently executing task
+ * @param[in] heir points to the context of the heir task
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_switch(
   Context_Control  *run,
@@ -1115,17 +1136,18 @@ void _CPU_Context_switch(
 );
 
 /**
- *  @ingroup CPUContext
- *  This routine is generally used only to restart self in an
- *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
+ * @ingroup CPUContext
+ * 
+ * This routine is generally used only to restart self in an
+ * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
  *
- *  @param[in] new_context points to the context to be restored.
+ * @param[in] new_context points to the context to be restored.
  *
- *  @note May be unnecessary to reload some registers.
+ * NOTE: May be unnecessary to reload some registers.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_restore(
   Context_Control *new_context
@@ -1137,32 +1159,33 @@ typedef CPU_Interrupt_frame CPU_Exception_frame;
 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
 
 /**
- *  @ingroup CPUEndian
- *  The following routine swaps the endian format of an unsigned int.
- *  It must be static because it is referenced indirectly.
+ * @ingroup CPUEndian
+ * 
+ * The following routine swaps the endian format of an unsigned int.
+ * It must be static because it is referenced indirectly.
  *
- *  This version will work on any processor, but if there is a better
- *  way for your CPU PLEASE use it.  The most common way to do this is to:
+ * This version will work on any processor, but if there is a better
+ * way for your CPU PLEASE use it.  The most common way to do this is to:
  *
- *     swap least significant two bytes with 16-bit rotate
- *     swap upper and lower 16-bits
- *     swap most significant two bytes with 16-bit rotate
+ *    swap least significant two bytes with 16-bit rotate
+ *    swap upper and lower 16-bits
+ *    swap most significant two bytes with 16-bit rotate
  *
- *  Some CPUs have special instructions which swap a 32-bit quantity in
- *  a single instruction (e.g. i486).  It is probably best to avoid
- *  an "endian swapping control bit" in the CPU.  One good reason is
- *  that interrupts would probably have to be disabled to ensure that
- *  an interrupt does not try to access the same "chunk" with the wrong
- *  endian.  Another good reason is that on some CPUs, the endian bit
- *  endianness for ALL fetches -- both code and data -- so the code
- *  will be fetched incorrectly.
+ * Some CPUs have special instructions which swap a 32-bit quantity in
+ * a single instruction (e.g. i486).  It is probably best to avoid
+ * an "endian swapping control bit" in the CPU.  One good reason is
+ * that interrupts would probably have to be disabled to ensure that
+ * an interrupt does not try to access the same "chunk" with the wrong
+ * endian.  Another good reason is that on some CPUs, the endian bit
+ * endianness for ALL fetches -- both code and data -- so the code
+ * will be fetched incorrectly.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 static inline uint32_t CPU_swap_u32(
   uint32_t value
@@ -1180,11 +1203,12 @@ static inline uint32_t CPU_swap_u32(
 }
 
 /**
- *  @ingroup CPUEndian
- *  This routine swaps a 16 bir quantity.
+ * @ingroup CPUEndian
+ * 
+ * This routine swaps a 16 bir quantity.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  */
 #define CPU_swap_u16( value ) \
   (((value&0xff) << 8) | ((value >> 8)&0xff))
diff --git a/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h b/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h
index e3797a93f9..1519fbb6f3 100644
--- a/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/m32c/rtems/score/cpu_asm.h
@@ -1,12 +1,14 @@
 /**
- * @file rtems/score/cpu_asm.h
+ * @file
+ * 
+ * @brief M32C CPU Assembly File
+ * 
+ * Very loose template for an include file for the cpu_asm.? file
+ * if it is implemented as a ".S" file (preprocessed by cpp) instead
+ * of a ".s" file (preprocessed by gm4 or gasp).
  */
 
 /*
- *  Very loose template for an include file for the cpu_asm.? file
- *  if it is implemented as a ".S" file (preprocessed by cpp) instead
- *  of a ".s" file (preprocessed by gm4 or gasp).
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/m32c/rtems/score/m32c.h b/cpukit/score/cpu/m32c/rtems/score/m32c.h
index 5cd3e71103..9be83e71e4 100644
--- a/cpukit/score/cpu/m32c/rtems/score/m32c.h
+++ b/cpukit/score/cpu/m32c/rtems/score/m32c.h
@@ -1,9 +1,15 @@
-/*
- *  This file sets up basic CPU dependency settings based on
- *  compiler settings.  For example, it can determine if
- *  floating point is available.  This particular implementation
- *  is specified to the NO CPU port.
+/**
+ * @file
+ *
+ * @brief M32C Set up Basic CPU Dependency Settings Based on Compiler Settings
  *
+ * This file sets up basic CPU dependency settings based on
+ * compiler settings.  For example, it can determine if
+ * floating point is available.  This particular implementation
+ * is specified to the NO CPU port.
+ */
+
+/*
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/m32c/rtems/score/types.h b/cpukit/score/cpu/m32c/rtems/score/types.h
index b9636ad780..4f1e7fe519 100644
--- a/cpukit/score/cpu/m32c/rtems/score/types.h
+++ b/cpukit/score/cpu/m32c/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ * 
+ * @brief M32C CPU Type Definitions
+ * 
+ * This include file contains type definitions pertaining to the Intel
+ * m32c processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the Intel
- *  m32c processor family.
- *
  *  COPYRIGHT (c) 1989-2006.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/m32c/varvects.h b/cpukit/score/cpu/m32c/varvects.h
index 30884edbd8..7168482b54 100644
--- a/cpukit/score/cpu/m32c/varvects.h
+++ b/cpukit/score/cpu/m32c/varvects.h
@@ -1,37 +1,41 @@
-/*
-
-Copyright (c) 2008 Red Hat Incorporated.
-All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-    Redistributions of source code must retain the above copyright
-    notice, this list of conditions and the following disclaimer.
-
-    Redistributions in binary form must reproduce the above copyright
-    notice, this list of conditions and the following disclaimer in the
-    documentation and/or other materials provided with the distribution.
+/**
+ * @file
+ *
+ * @brief M32C Built-in Variable Vector Table Interface
+ *
+ * This file defines the interface to the built-in variable vector
+ * table in R8C/M16C/M32C chips.
+ */
 
-    The name of Red Hat Incorporated may not be used to endorse
-    or promote products derived from this software without specific
-    prior written permission.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
-DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
-ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-*/
-
-/* This file defines the interface to the built-in variable vector
-   table in R8C/M16C/M32C chips.  */
+/*
+ * Copyright (c) 2008 Red Hat Incorporated.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ *     Redistributions of source code must retain the above copyright
+ *     notice, this list of conditions and the following disclaimer.
+ *
+ *     Redistributions in binary form must reproduce the above copyright
+ *     notice, this list of conditions and the following disclaimer in the
+ *     documentation and/or other materials provided with the distribution.
+ *
+ *     The name of Red Hat Incorporated may not be used to endorse
+ *     or promote products derived from this software without specific
+ *     prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED.  IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY
+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
 
 #ifndef _VARVECTS_H_
 #define _VARVECTS_H_
diff --git a/cpukit/score/cpu/m32r/rtems/asm.h b/cpukit/score/cpu/m32r/rtems/asm.h
index cd258c513b..11f5b876b9 100644
--- a/cpukit/score/cpu/m32r/rtems/asm.h
+++ b/cpukit/score/cpu/m32r/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
@@ -38,24 +41,24 @@
 
 #ifndef __USER_LABEL_PREFIX__
 /**
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents.  If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
  *
- *  This symbol is prefixed to all C program symbols.
+ * This symbol is prefixed to all C program symbols.
  */
 #define __USER_LABEL_PREFIX__ _
 #endif
 
 #ifndef __REGISTER_PREFIX__
 /**
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents.  If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
  *
- *  This symbol is prefixed to all register names.
+ * This symbol is prefixed to all register names.
  */
 #define __REGISTER_PREFIX__
 #endif
@@ -95,8 +98,9 @@
 #define BEGIN_DATA
 /** This macro is used to denote the end of a data section. */
 #define END_DATA
-/** This macro is used to denote the beginning of the
- *  unitialized data section.
+/**
+ * This macro is used to denote the beginning of the
+ * unitialized data section.
  */
 #define BEGIN_BSS
 /** This macro is used to denote the end of the unitialized data section.  */
@@ -105,18 +109,18 @@
 #define END
 
 /**
- *  This macro is used to declare a public global symbol.
+ * This macro is used to declare a public global symbol.
  *
- *  @note This must be tailored for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
+ * NOTE: This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
  */
 #define PUBLIC(sym) .globl SYM (sym)
 
 /**
- *  This macro is used to prototype a public global symbol.
+ * This macro is used to prototype a public global symbol.
  *
- *  @note This must be tailored for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
+ * NOTE: This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
  */
 #define EXTERN(sym) .globl SYM (sym)
 
diff --git a/cpukit/score/cpu/m32r/rtems/score/cpu.h b/cpukit/score/cpu/m32r/rtems/score/cpu.h
index d6886ffefc..8c8a9c1c30 100644
--- a/cpukit/score/cpu/m32r/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m32r/rtems/score/cpu.h
@@ -1,22 +1,22 @@
 /**
- * @file rtems/score/cpu.h
- */
-
-/*
- *  This include file contains information pertaining to the XXX
- *  processor.
+ * @file
+ *
+ * @brief Intel M32R CPU Dependent Source
+ *
+ * This include file contains information pertaining to the XXX
+ * processor.
  *
- *  @note This file is part of a porting template that is intended
- *  to be used as the starting point when porting RTEMS to a new
- *  CPU family.  The following needs to be done when using this as
- *  the starting point for a new port:
+ * NOTE: This file is part of a porting template that is intended
+ * to be used as the starting point when porting RTEMS to a new
+ * CPU family.  The following needs to be done when using this as
+ * the starting point for a new port:
  *
- *  + Anywhere there is an XXX, it should be replaced
- *    with information about the CPU family being ported to.
+ * + Anywhere there is an XXX, it should be replaced
+ *   with information about the CPU family being ported to.
  *
- *  + At the end of each comment section, there is a heading which
- *    says "Port Specific Information:".  When porting to RTEMS,
- *    add CPU family specific information in this section
+ * + At the end of each comment section, there is a heading which
+ *   says "Port Specific Information:".  When porting to RTEMS,
+ *   add CPU family specific information in this section
  */
 
 /*
@@ -41,172 +41,172 @@ extern "C" {
 /* conditional compilation parameters */
 
 /**
- *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ * Should the calls to @ref _Thread_Enable_dispatch be inlined?
  *
- *  If TRUE, then they are inlined.
- *  If FALSE, then a subroutine call is made.
+ * If TRUE, then they are inlined.
+ * If FALSE, then a subroutine call is made.
  *
- *  This conditional is an example of the classic trade-off of size
- *  versus speed.  Inlining the call (TRUE) typically increases the
- *  size of RTEMS while speeding up the enabling of dispatching.
+ * This conditional is an example of the classic trade-off of size
+ * versus speed.  Inlining the call (TRUE) typically increases the
+ * size of RTEMS while speeding up the enabling of dispatching.
  *
- *  @note In general, the @ref _Thread_Dispatch_disable_level will
- *  only be 0 or 1 unless you are in an interrupt handler and that
- *  interrupt handler invokes the executive.]  When not inlined
- *  something calls @ref _Thread_Enable_dispatch which in turns calls
- *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
- *  one subroutine call is avoided entirely.
+ * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
+ * only be 0 or 1 unless you are in an interrupt handler and that
+ * interrupt handler invokes the executive.]  When not inlined
+ * something calls @ref _Thread_Enable_dispatch which in turns calls
+ * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
+ * one subroutine call is avoided entirely.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INLINE_ENABLE_DISPATCH       FALSE
 
 /**
- *  Should the body of the search loops in _Thread_queue_Enqueue_priority
- *  be unrolled one time?  In unrolled each iteration of the loop examines
- *  two "nodes" on the chain being searched.  Otherwise, only one node
- *  is examined per iteration.
+ * Should the body of the search loops in _Thread_queue_Enqueue_priority
+ * be unrolled one time?  In unrolled each iteration of the loop examines
+ * two "nodes" on the chain being searched.  Otherwise, only one node
+ * is examined per iteration.
  *
- *  If TRUE, then the loops are unrolled.
- *  If FALSE, then the loops are not unrolled.
+ * If TRUE, then the loops are unrolled.
+ * If FALSE, then the loops are not unrolled.
  *
- *  The primary factor in making this decision is the cost of disabling
- *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- *  body of the loop.  On some CPUs, the flash is more expensive than
- *  one iteration of the loop body.  In this case, it might be desirable
- *  to unroll the loop.  It is important to note that on some CPUs, this
- *  code is the longest interrupt disable period in RTEMS.  So it is
- *  necessary to strike a balance when setting this parameter.
+ * The primary factor in making this decision is the cost of disabling
+ * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ * body of the loop.  On some CPUs, the flash is more expensive than
+ * one iteration of the loop body.  In this case, it might be desirable
+ * to unroll the loop.  It is important to note that on some CPUs, this
+ * code is the longest interrupt disable period in RTEMS.  So it is
+ * necessary to strike a balance when setting this parameter.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
 
 /**
- *  Does RTEMS manage a dedicated interrupt stack in software?
+ * Does RTEMS manage a dedicated interrupt stack in software?
  *
- *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
- *  If FALSE, nothing is done.
+ * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ * If FALSE, nothing is done.
  *
- *  If the CPU supports a dedicated interrupt stack in hardware,
- *  then it is generally the responsibility of the BSP to allocate it
- *  and set it up.
+ * If the CPU supports a dedicated interrupt stack in hardware,
+ * then it is generally the responsibility of the BSP to allocate it
+ * and set it up.
  *
- *  If the CPU does not support a dedicated interrupt stack, then
- *  the porter has two options: (1) execute interrupts on the
- *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
- *  interrupt stack.
+ * If the CPU does not support a dedicated interrupt stack, then
+ * the porter has two options: (1) execute interrupts on the
+ * stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ * interrupt stack.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
 
 /**
- *  Does the CPU follow the simple vectored interrupt model?
+ * Does the CPU follow the simple vectored interrupt model?
  *
- *  If TRUE, then RTEMS allocates the vector table it internally manages.
- *  If FALSE, then the BSP is assumed to allocate and manage the vector
- *  table
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
 
 /**
- *  Does this CPU have hardware support for a dedicated interrupt stack?
+ * Does this CPU have hardware support for a dedicated interrupt stack?
  *
- *  If TRUE, then it must be installed during initialization.
- *  If FALSE, then no installation is performed.
+ * If TRUE, then it must be installed during initialization.
+ * If FALSE, then no installation is performed.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
 
 /**
- *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
  *
- *  If TRUE, then the memory is allocated during initialization.
- *  If FALSE, then the memory is allocated during initialization.
+ * If TRUE, then the memory is allocated during initialization.
+ * If FALSE, then the memory is allocated during initialization.
  *
- *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
 
 /**
- *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector
- *  number (0)?
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ISR_PASSES_FRAME_POINTER 0
 
 /**
- *  @def CPU_HARDWARE_FP
+ * @def CPU_HARDWARE_FP
  *
- *  Does the CPU have hardware floating point?
+ * Does the CPU have hardware floating point?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
  *
- *  If there is a FP coprocessor such as the i387 or mc68881, then
- *  the answer is TRUE.
+ * If there is a FP coprocessor such as the i387 or mc68881, then
+ * the answer is TRUE.
  *
- *  The macro name "M32R_HAS_FPU" should be made CPU specific.
- *  It indicates whether or not this CPU model has FP support.  For
- *  example, it would be possible to have an i386_nofp CPU model
- *  which set this to false to indicate that you have an i386 without
- *  an i387 and wish to leave floating point support out of RTEMS.
+ * The macro name "M32R_HAS_FPU" should be made CPU specific.
+ * It indicates whether or not this CPU model has FP support.  For
+ * example, it would be possible to have an i386_nofp CPU model
+ * which set this to false to indicate that you have an i386 without
+ * an i387 and wish to leave floating point support out of RTEMS.
  */
 
 /**
- *  @def CPU_SOFTWARE_FP
+ * @def CPU_SOFTWARE_FP
  *
- *  Does the CPU have no hardware floating point and GCC provides a
- *  software floating point implementation which must be context
- *  switched?
+ * Does the CPU have no hardware floating point and GCC provides a
+ * software floating point implementation which must be context
+ * switched?
  *
- *  This feature conditional is used to indicate whether or not there
- *  is software implemented floating point that must be context
- *  switched.  The determination of whether or not this applies
- *  is very tool specific and the state saved/restored is also
- *  compiler specific.
+ * This feature conditional is used to indicate whether or not there
+ * is software implemented floating point that must be context
+ * switched.  The determination of whether or not this applies
+ * is very tool specific and the state saved/restored is also
+ * compiler specific.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if ( M32R_HAS_FPU == 1 )
 #define CPU_HARDWARE_FP     TRUE
@@ -216,201 +216,203 @@ extern "C" {
 #define CPU_SOFTWARE_FP     FALSE
 
 /**
- *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
  *
- *  So far, the only CPUs in which this option has been used are the
- *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
- *  gcc both implicitly used the floating point registers to perform
- *  integer multiplies.  Similarly, the PowerPC port of gcc has been
- *  seen to allocate floating point local variables and touch the FPU
- *  even when the flow through a subroutine (like vfprintf()) might
- *  not use floating point formats.
+ * So far, the only CPUs in which this option has been used are the
+ * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
+ * gcc both implicitly used the floating point registers to perform
+ * integer multiplies.  Similarly, the PowerPC port of gcc has been
+ * seen to allocate floating point local variables and touch the FPU
+ * even when the flow through a subroutine (like vfprintf()) might
+ * not use floating point formats.
  *
- *  If a function which you would not think utilize the FP unit DOES,
- *  then one can not easily predict which tasks will use the FP hardware.
- *  In this case, this option should be TRUE.
+ * If a function which you would not think utilize the FP unit DOES,
+ * then one can not easily predict which tasks will use the FP hardware.
+ * In this case, this option should be TRUE.
  *
- *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALL_TASKS_ARE_FP     TRUE
 
 /**
- *  Should the IDLE task have a floating point context?
+ * Should the IDLE task have a floating point context?
  *
- *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- *  and it has a floating point context which is switched in and out.
- *  If FALSE, then the IDLE task does not have a floating point context.
+ * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ * and it has a floating point context which is switched in and out.
+ * If FALSE, then the IDLE task does not have a floating point context.
  *
- *  Setting this to TRUE negatively impacts the time required to preempt
- *  the IDLE task from an interrupt because the floating point context
- *  must be saved as part of the preemption.
+ * Setting this to TRUE negatively impacts the time required to preempt
+ * the IDLE task from an interrupt because the floating point context
+ * must be saved as part of the preemption.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_IDLE_TASK_IS_FP      FALSE
 
 /**
- *  Should the saving of the floating point registers be deferred
- *  until a context switch is made to another different floating point
- *  task?
+ * Should the saving of the floating point registers be deferred
+ * until a context switch is made to another different floating point
+ * task?
  *
- *  If TRUE, then the floating point context will not be stored until
- *  necessary.  It will remain in the floating point registers and not
- *  disturned until another floating point task is switched to.
+ * If TRUE, then the floating point context will not be stored until
+ * necessary.  It will remain in the floating point registers and not
+ * disturned until another floating point task is switched to.
  *
- *  If FALSE, then the floating point context is saved when a floating
- *  point task is switched out and restored when the next floating point
- *  task is restored.  The state of the floating point registers between
- *  those two operations is not specified.
+ * If FALSE, then the floating point context is saved when a floating
+ * point task is switched out and restored when the next floating point
+ * task is restored.  The state of the floating point registers between
+ * those two operations is not specified.
  *
- *  If the floating point context does NOT have to be saved as part of
- *  interrupt dispatching, then it should be safe to set this to TRUE.
+ * If the floating point context does NOT have to be saved as part of
+ * interrupt dispatching, then it should be safe to set this to TRUE.
  *
- *  Setting this flag to TRUE results in using a different algorithm
- *  for deciding when to save and restore the floating point context.
- *  The deferred FP switch algorithm minimizes the number of times
- *  the FP context is saved and restored.  The FP context is not saved
- *  until a context switch is made to another, different FP task.
- *  Thus in a system with only one FP task, the FP context will never
- *  be saved or restored.
+ * Setting this flag to TRUE results in using a different algorithm
+ * for deciding when to save and restore the floating point context.
+ * The deferred FP switch algorithm minimizes the number of times
+ * the FP context is saved and restored.  The FP context is not saved
+ * until a context switch is made to another, different FP task.
+ * Thus in a system with only one FP task, the FP context will never
+ * be saved or restored.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_USE_DEFERRED_FP_SWITCH       TRUE
 
 /**
- *  Does this port provide a CPU dependent IDLE task implementation?
+ * Does this port provide a CPU dependent IDLE task implementation?
  *
- *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
- *  must be provided and is the default IDLE thread body instead of
- *  @ref _CPU_Thread_Idle_body.
+ * If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ * must be provided and is the default IDLE thread body instead of
+ * @ref _CPU_Thread_Idle_body.
  *
- *  If FALSE, then use the generic IDLE thread body if the BSP does
- *  not provide one.
+ * If FALSE, then use the generic IDLE thread body if the BSP does
+ * not provide one.
  *
- *  This is intended to allow for supporting processors which have
- *  a low power or idle mode.  When the IDLE thread is executed, then
- *  the CPU can be powered down.
+ * This is intended to allow for supporting processors which have
+ * a low power or idle mode.  When the IDLE thread is executed, then
+ * the CPU can be powered down.
  *
- *  The order of precedence for selecting the IDLE thread body is:
+ * The order of precedence for selecting the IDLE thread body is:
  *
- *    -#  BSP provided
- *    -#  CPU dependent (if provided)
- *    -#  generic (if no BSP and no CPU dependent)
+ *   -#  BSP provided
+ *   -#  CPU dependent (if provided)
+ *   -#  generic (if no BSP and no CPU dependent)
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
 
 /**
- *  Does the stack grow up (toward higher addresses) or down
- *  (toward lower addresses)?
+ * Does the stack grow up (toward higher addresses) or down
+ * (toward lower addresses)?
  *
- *  If TRUE, then the grows upward.
- *  If FALSE, then the grows toward smaller addresses.
+ * If TRUE, then the grows upward.
+ * If FALSE, then the grows toward smaller addresses.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_GROWS_UP               TRUE
 
 /**
- *  The following is the variable attribute used to force alignment
- *  of critical RTEMS structures.  On some processors it may make
- *  sense to have these aligned on tighter boundaries than
- *  the minimum requirements of the compiler in order to have as
- *  much of the critical data area as possible in a cache line.
+ * The following is the variable attribute used to force alignment
+ * of critical RTEMS structures.  On some processors it may make
+ * sense to have these aligned on tighter boundaries than
+ * the minimum requirements of the compiler in order to have as
+ * much of the critical data area as possible in a cache line.
  *
- *  The placement of this macro in the declaration of the variables
- *  is based on the syntactically requirements of the GNU C
- *  "__attribute__" extension.  For example with GNU C, use
- *  the following to force a structures to a 32 byte boundary.
+ * The placement of this macro in the declaration of the variables
+ * is based on the syntactically requirements of the GNU C
+ * "__attribute__" extension.  For example with GNU C, use
+ * the following to force a structures to a 32 byte boundary.
  *
- *      __attribute__ ((aligned (32)))
+ *     __attribute__ ((aligned (32)))
  *
- *  @note Currently only the Priority Bit Map table uses this feature.
- *        To benefit from using this, the data must be heavily
- *        used so it will stay in the cache and used frequently enough
- *        in the executive to justify turning this on.
+ * NOTE: Currently only the Priority Bit Map table uses this feature.
+ *       To benefit from using this, the data must be heavily
+ *       used so it will stay in the cache and used frequently enough
+ *       in the executive to justify turning this on.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STRUCTURE_ALIGNMENT
 
 #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
 
 /**
- *  @defgroup CPUEndian Processor Dependent Endianness Support
+ * @defgroup CPUEndian Processor Dependent Endianness Support
+ *
+ * This group assists in issues related to processor endianness.
  *
- *  This group assists in issues related to processor endianness.
  */
+/**@{**/
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_LITTLE_ENDIAN
+ * @see CPU_LITTLE_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_BIG_ENDIAN                           TRUE
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_BIG_ENDIAN
+ * @see CPU_BIG_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_LITTLE_ENDIAN                        FALSE
 
+/** @} */
+
 /**
- *  @ingroup CPUInterrupt
- *  The following defines the number of bits actually used in the
- *  interrupt field of the task mode.  How those bits map to the
- *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ * @ingroup CPUInterrupt
+ * The following defines the number of bits actually used in the
+ * interrupt field of the task mode.  How those bits map to the
+ * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_MODES_INTERRUPT_MASK   0x00000001
 
 /*
- *  Processor defined structures required for cpukit/score.
+ * Processor defined structures required for cpukit/score.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 
 /* may need to put some structures here.  */
@@ -418,50 +420,50 @@ extern "C" {
 /**
  * @defgroup CPUContext Processor Dependent Context Management
  *
- *  From the highest level viewpoint, there are 2 types of context to save.
+ * From the highest level viewpoint, there are 2 types of context to save.
  *
- *     -# Interrupt registers to save
- *     -# Task level registers to save
+ *    -# Interrupt registers to save
+ *    -# Task level registers to save
  *
- *  Since RTEMS handles integer and floating point contexts separately, this
- *  means we have the following 3 context items:
+ * Since RTEMS handles integer and floating point contexts separately, this
+ * means we have the following 3 context items:
  *
- *     -# task level context stuff::  Context_Control
- *     -# floating point task stuff:: Context_Control_fp
- *     -# special interrupt level context :: CPU_Interrupt_frame
+ *    -# task level context stuff::  Context_Control
+ *    -# floating point task stuff:: Context_Control_fp
+ *    -# special interrupt level context :: CPU_Interrupt_frame
  *
- *  On some processors, it is cost-effective to save only the callee
- *  preserved registers during a task context switch.  This means
- *  that the ISR code needs to save those registers which do not
- *  persist across function calls.  It is not mandatory to make this
- *  distinctions between the caller/callee saves registers for the
- *  purpose of minimizing context saved during task switch and on interrupts.
- *  If the cost of saving extra registers is minimal, simplicity is the
- *  choice.  Save the same context on interrupt entry as for tasks in
- *  this case.
+ * On some processors, it is cost-effective to save only the callee
+ * preserved registers during a task context switch.  This means
+ * that the ISR code needs to save those registers which do not
+ * persist across function calls.  It is not mandatory to make this
+ * distinctions between the caller/callee saves registers for the
+ * purpose of minimizing context saved during task switch and on interrupts.
+ * If the cost of saving extra registers is minimal, simplicity is the
+ * choice.  Save the same context on interrupt entry as for tasks in
+ * this case.
  *
- *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- *  care should be used in designing the context area.
+ * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ * care should be used in designing the context area.
  *
- *  On some CPUs with hardware floating point support, the Context_Control_fp
- *  structure will not be used or it simply consist of an array of a
- *  fixed number of bytes.   This is done when the floating point context
- *  is dumped by a "FP save context" type instruction and the format
- *  is not really defined by the CPU.  In this case, there is no need
- *  to figure out the exact format -- only the size.  Of course, although
- *  this is enough information for RTEMS, it is probably not enough for
- *  a debugger such as gdb.  But that is another problem.
+ * On some CPUs with hardware floating point support, the Context_Control_fp
+ * structure will not be used or it simply consist of an array of a
+ * fixed number of bytes.   This is done when the floating point context
+ * is dumped by a "FP save context" type instruction and the format
+ * is not really defined by the CPU.  In this case, there is no need
+ * to figure out the exact format -- only the size.  Of course, although
+ * this is enough information for RTEMS, it is probably not enough for
+ * a debugger such as gdb.  But that is another problem.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
+/**@{**/
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the minimal set of integer and processor state registers
- *  that must be saved during a voluntary context switch from one thread
- *  to another.
+ * This defines the minimal set of integer and processor state registers
+ * that must be saved during a voluntary context switch from one thread
+ * to another.
  */
 typedef struct {
   /** r8 -- temporary register */
@@ -487,21 +489,18 @@ typedef struct {
 } Context_Control;
 
 /**
- *  @ingroup CPUContext Management
+ * This macro returns the stack pointer associated with @a _context.
  *
- *  This macro returns the stack pointer associated with @a _context.
+ * @param[in] _context is the thread context area to access
  *
- *  @param[in] _context is the thread context area to access
- *
- *  @return This method returns the stack pointer.
+ * @return This method returns the stack pointer.
  */
 #define _CPU_Context_Get_SP( _context ) \
   (_context)->r15_sp
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the complete set of floating point registers that must
- *  be saved during any context switch from one thread to another.
+ * This defines the complete set of floating point registers that must
+ * be saved during any context switch from one thread to another.
  */
 typedef struct {
     /** FPU registers are listed here */
@@ -509,49 +508,51 @@ typedef struct {
 } Context_Control_fp;
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the set of integer and processor state registers that must
- *  be saved during an interrupt.  This set does not include any which are
- *  in @ref Context_Control.
+ * This defines the set of integer and processor state registers that must
+ * be saved during an interrupt.  This set does not include any which are
+ * in @ref Context_Control.
  */
 typedef struct {
     /** This field is a hint that a port will have a number of integer
-     *  registers that need to be saved when an interrupt occurs or
-     *  when a context switch occurs at the end of an ISR.
+     * registers that need to be saved when an interrupt occurs or
+     * when a context switch occurs at the end of an ISR.
      */
     uint32_t   special_interrupt_register;
 } CPU_Interrupt_frame;
 
 /**
- *  This variable is optional.  It is used on CPUs on which it is difficult
- *  to generate an "uninitialized" FP context.  It is filled in by
- *  @ref _CPU_Initialize and copied into the task's FP context area during
- *  @ref _CPU_Context_Initialize.
+ * This variable is optional.  It is used on CPUs on which it is difficult
+ * to generate an "uninitialized" FP context.  It is filled in by
+ * @ref _CPU_Initialize and copied into the task's FP context area during
+ * @ref _CPU_Context_Initialize.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 
+/** @} */
+
 /**
- *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ * @defgroup CPUInterrupt Processor Dependent Interrupt Management
  *
- *  On some CPUs, RTEMS supports a software managed interrupt stack.
- *  This stack is allocated by the Interrupt Manager and the switch
- *  is performed in @ref _ISR_Handler.  These variables contain pointers
- *  to the lowest and highest addresses in the chunk of memory allocated
- *  for the interrupt stack.  Since it is unknown whether the stack
- *  grows up or down (in general), this give the CPU dependent
- *  code the option of picking the version it wants to use.
+ * On some CPUs, RTEMS supports a software managed interrupt stack.
+ * This stack is allocated by the Interrupt Manager and the switch
+ * is performed in @ref _ISR_Handler.  These variables contain pointers
+ * to the lowest and highest addresses in the chunk of memory allocated
+ * for the interrupt stack.  Since it is unknown whether the stack
+ * grows up or down (in general), this give the CPU dependent
+ * code the option of picking the version it wants to use.
  *
- *  @note These two variables are required if the macro
- *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ * NOTE: These two variables are required if the macro
+ *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
+/**@{**/
 
 /*
  *  Nothing prevents the porter from declaring more CPU specific variables.
@@ -564,131 +565,130 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 /* XXX: if needed, put more variables here */
 
 /**
- *  @ingroup CPUContext
- *  The size of the floating point context area.  On some CPUs this
- *  will not be a "sizeof" because the format of the floating point
- *  area is not defined -- only the size is.  This is usually on
- *  CPUs with a "floating point save context" instruction.
+ * @ingroup CPUContext
+ * The size of the floating point context area.  On some CPUs this
+ * will not be a "sizeof" because the format of the floating point
+ * area is not defined -- only the size is.  This is usually on
+ * CPUs with a "floating point save context" instruction.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
 
 /**
- *  Amount of extra stack (above minimum stack size) required by
- *  MPCI receive server thread.  Remember that in a multiprocessor
- *  system this thread must exist and be able to process all directives.
+ * Amount of extra stack (above minimum stack size) required by
+ * MPCI receive server thread.  Remember that in a multiprocessor
+ * system this thread must exist and be able to process all directives.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
 
 /**
- *  @ingroup CPUInterrupt
- *  This defines the number of entries in the @ref _ISR_Vector_table managed
- *  by RTEMS.
+ * This defines the number of entries in the @ref _ISR_Vector_table managed
+ * by RTEMS.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
 
 /**
- *  @ingroup CPUInterrupt
- *  This defines the highest interrupt vector number for this port.
+ * This defines the highest interrupt vector number for this port.
  */
 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
 /**
- *  @ingroup CPUInterrupt
- *  This is defined if the port has a special way to report the ISR nesting
- *  level.  Most ports maintain the variable @a _ISR_Nest_level.
+ * This is defined if the port has a special way to report the ISR nesting
+ * level.  Most ports maintain the variable @a _ISR_Nest_level.
  */
 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
+/** @} */
+
 /**
- *  @ingroup CPUContext
- *  Should be large enough to run all RTEMS tests.  This ensures
- *  that a "reasonable" small application should not have any problems.
+ * @ingroup CPUContext
+ * Should be large enough to run all RTEMS tests.  This ensures
+ * that a "reasonable" small application should not have any problems.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_MINIMUM_SIZE          (1024)
 
 #define CPU_SIZEOF_POINTER 4
 
 /**
- *  CPU's worst alignment requirement for data types on a byte boundary.  This
- *  alignment does not take into account the requirements for the stack.
+ * CPU's worst alignment requirement for data types on a byte boundary.  This
+ * alignment does not take into account the requirements for the stack.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALIGNMENT              8
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  heap handler.  This alignment requirement may be stricter than that
- *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
- *  common for the heap to follow the same alignment requirement as
- *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
- *  the heap, then this should be set to @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for the
+ * heap handler.  This alignment requirement may be stricter than that
+ * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
+ * common for the heap to follow the same alignment requirement as
+ * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
+ * the heap, then this should be set to @ref CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2 although it should be
- *         a multiple of 2 greater than or equal to 2.  The requirement
- *         to be a multiple of 2 is because the heap uses the least
- *         significant field of the front and back flags to indicate
- *         that a block is in use or free.  So you do not want any odd
- *         length blocks really putting length data in that bit.
+ * NOTE:  This does not have to be a power of 2 although it should be
+ *        a multiple of 2 greater than or equal to 2.  The requirement
+ *        to be a multiple of 2 is because the heap uses the least
+ *        significant field of the front and back flags to indicate
+ *        that a block is in use or free.  So you do not want any odd
+ *        length blocks really putting length data in that bit.
  *
- *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
- *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
- *         elements allocated from the heap meet all restrictions.
+ *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ *        elements allocated from the heap meet all restrictions.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for memory
- *  buffers allocated by the partition manager.  This alignment requirement
- *  may be stricter than that for the data types alignment specified by
- *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
- *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
- *  strict enough for the partition, then this should be set to
- *  @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for memory
+ * buffers allocated by the partition manager.  This alignment requirement
+ * may be stricter than that for the data types alignment specified by
+ * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
+ * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
+ * strict enough for the partition, then this should be set to
+ * @ref CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than @ref CPU_ALIGNMENT.
+ * NOTE:  This does not have to be a power of 2.  It does have to
+ *        be greater or equal to than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  stack.  This alignment requirement may be stricter than that for the
- *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
- *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
- *  set to 0.
+ * This number corresponds to the byte alignment requirement for the
+ * stack.  This alignment requirement may be stricter than that for the
+ * data types alignment specified by @ref CPU_ALIGNMENT.  If the
+ * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
+ * set to 0.
  *
- *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
+ * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_ALIGNMENT        0
 
@@ -697,25 +697,28 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
  */
 
 /**
- *  @ingroup CPUInterrupt
- *  Support routine to initialize the RTEMS vector table after it is allocated.
+ * @addtogroup CPUInterrupt
+ */
+/**@{**/
+
+/**
+ * Support routine to initialize the RTEMS vector table after it is allocated.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Initialize_vectors()
 
 /**
- *  @ingroup CPUInterrupt
- *  Disable all interrupts for an RTEMS critical section.  The previous
- *  level is returned in @a _isr_cookie.
+ * Disable all interrupts for an RTEMS critical section.  The previous
+ * level is returned in @a _isr_cookie.
  *
- *  @param[out] _isr_cookie will contain the previous level cookie
+ * @param[out] _isr_cookie will contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Disable( _isr_cookie ) \
   { \
@@ -723,16 +726,15 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
   }
 
 /**
- *  @ingroup CPUInterrupt
- *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- *  This indicates the end of an RTEMS critical section.  The parameter
- *  @a _isr_cookie is not modified.
+ * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ * This indicates the end of an RTEMS critical section.  The parameter
+ * @a _isr_cookie is not modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Enable( _isr_cookie )  \
   { \
@@ -740,91 +742,90 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
   }
 
 /**
- *  @ingroup CPUInterrupt
- *  This temporarily restores the interrupt to @a _isr_cookie before immediately
- *  disabling them again.  This is used to divide long RTEMS critical
- *  sections into two or more parts.  The parameter @a _isr_cookie is not
- *  modified.
+ * This temporarily restores the interrupt to @a _isr_cookie before immediately
+ * disabling them again.  This is used to divide long RTEMS critical
+ * sections into two or more parts.  The parameter @a _isr_cookie is not
+ * modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Flash( _isr_cookie ) \
   { \
   }
 
 /**
- *  @ingroup CPUInterrupt
+ * This routine and @ref _CPU_ISR_Get_level
+ * Map the interrupt level in task mode onto the hardware that the CPU
+ * actually provides.  Currently, interrupt levels which do not
+ * map onto the CPU in a generic fashion are undefined.  Someday,
+ * it would be nice if these were "mapped" by the application
+ * via a callout.  For example, m68k has 8 levels 0 - 7, levels
+ * 8 - 255 would be available for bsp/application specific meaning.
+ * This could be used to manage a programmable interrupt controller
+ * via the rtems_task_mode directive.
  *
- *  This routine and @ref _CPU_ISR_Get_level
- *  Map the interrupt level in task mode onto the hardware that the CPU
- *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a generic fashion are undefined.  Someday,
- *  it would be nice if these were "mapped" by the application
- *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
- *  8 - 255 would be available for bsp/application specific meaning.
- *  This could be used to manage a programmable interrupt controller
- *  via the rtems_task_mode directive.
- *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Set_level( new_level ) \
   { \
   }
 
 /**
- *  @ingroup CPUInterrupt
- *  Return the current interrupt disable level for this task in
- *  the format used by the interrupt level portion of the task mode.
+ * Return the current interrupt disable level for this task in
+ * the format used by the interrupt level portion of the task mode.
  *
- *  @note This routine usually must be implemented as a subroutine.
+ * NOTE: This routine usually must be implemented as a subroutine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
 
+/** @} */
+
 /* Context handler macros */
 
 /**
- *  @brief CPU Context Initialize
- *  @ingroup CPUContext
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
- *
- *     - setting a starting address
- *     - preparing the stack
- *     - preparing the stack and frame pointers
- *     - setting the proper interrupt level in the context
- *     - initializing the floating point context
- *
- *  This routine generally does not set any unnecessary register
- *  in the context.  The state of the "general data" registers is
- *  undefined at task start time.
- *
- *  @param[in] _the_context is the context structure to be initialized
- *  @param[in] _stack_base is the lowest physical address of this task's stack
- *  @param[in] _size is the size of this task's stack
- *  @param[in] _isr is the interrupt disable level
- *  @param[in] _entry_point is the thread's entry point.  This is
- *         always @a _Thread_Handler
- *  @param[in] _is_fp is TRUE if the thread is to be a floating
- *        point thread.  This is typically only used on CPUs where the
- *        FPU may be easily disabled by software such as on the SPARC
- *        where the PSR contains an enable FPU bit.
+ * @brief Initialize CPU context.
  *
- *  Port Specific Information:
+ * @ingroup CPUContext
+ * Initialize the context to a state suitable for starting a
+ * task after a context restore operation.  Generally, this
+ * involves:
  *
- *  XXX document implementation including references if appropriate
+ *    - setting a starting address
+ *    - preparing the stack
+ *    - preparing the stack and frame pointers
+ *    - setting the proper interrupt level in the context
+ *    - initializing the floating point context
+ *
+ * This routine generally does not set any unnecessary register
+ * in the context.  The state of the "general data" registers is
+ * undefined at task start time.
+ *
+ * @param[in] _the_context is the context structure to be initialized
+ * @param[in] _stack_base is the lowest physical address of this task's stack
+ * @param[in] _size is the size of this task's stack
+ * @param[in] _isr is the interrupt disable level
+ * @param[in] _entry_point is the thread's entry point.  This is
+ *        always @a _Thread_Handler
+ * @param[in] _is_fp is TRUE if the thread is to be a floating
+ *       point thread.  This is typically only used on CPUs where the
+ *       FPU may be easily disabled by software such as on the SPARC
+ *       where the PSR contains an enable FPU bit.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_Initialize(
   Context_Control  *the_context,
@@ -836,66 +837,66 @@ void _CPU_Context_Initialize(
 );
 
 /**
- *  This routine is responsible for somehow restarting the currently
- *  executing task.  If you are lucky, then all that is necessary
- *  is restoring the context.  Otherwise, there will need to be
- *  a special assembly routine which does something special in this
- *  case.  For many ports, simply adding a label to the restore path
- *  of @ref _CPU_Context_switch will work.  On other ports, it may be
- *  possibly to load a few arguments and jump to the restore path. It will
- *  not work if restarting self conflicts with the stack frame
- *  assumptions of restoring a context.
+ * This routine is responsible for somehow restarting the currently
+ * executing task.  If you are lucky, then all that is necessary
+ * is restoring the context.  Otherwise, there will need to be
+ * a special assembly routine which does something special in this
+ * case.  For many ports, simply adding a label to the restore path
+ * of @ref _CPU_Context_switch will work.  On other ports, it may be
+ * possibly to load a few arguments and jump to the restore path. It will
+ * not work if restarting self conflicts with the stack frame
+ * assumptions of restoring a context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_Restart_self(
   Context_Control  *the_context
 );
 
 /**
- *  @ingroup CPUContext
- *  The purpose of this macro is to allow the initial pointer into
- *  a floating point context area (used to save the floating point
- *  context) to be at an arbitrary place in the floating point
- *  context area.
+ * @ingroup CPUContext
+ * The purpose of this macro is to allow the initial pointer into
+ * a floating point context area (used to save the floating point
+ * context) to be at an arbitrary place in the floating point
+ * context area.
  *
- *  This is necessary because some FP units are designed to have
- *  their context saved as a stack which grows into lower addresses.
- *  Other FP units can be saved by simply moving registers into offsets
- *  from the base of the context area.  Finally some FP units provide
- *  a "dump context" instruction which could fill in from high to low
- *  or low to high based on the whim of the CPU designers.
+ * This is necessary because some FP units are designed to have
+ * their context saved as a stack which grows into lower addresses.
+ * Other FP units can be saved by simply moving registers into offsets
+ * from the base of the context area.  Finally some FP units provide
+ * a "dump context" instruction which could fill in from high to low
+ * or low to high based on the whim of the CPU designers.
  *
- *  @param[in] _base is the lowest physical address of the floating point
- *         context area
- *  @param[in] _offset is the offset into the floating point area
+ * @param[in] _base is the lowest physical address of the floating point
+ *        context area
+ * @param[in] _offset is the offset into the floating point area
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Fp_start( _base, _offset ) \
    ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
 
 /**
- *  This routine initializes the FP context area passed to it to.
- *  There are a few standard ways in which to initialize the
- *  floating point context.  The code included for this macro assumes
- *  that this is a CPU in which a "initial" FP context was saved into
- *  @a _CPU_Null_fp_context and it simply copies it to the destination
- *  context passed to it.
+ * This routine initializes the FP context area passed to it to.
+ * There are a few standard ways in which to initialize the
+ * floating point context.  The code included for this macro assumes
+ * that this is a CPU in which a "initial" FP context was saved into
+ * @a _CPU_Null_fp_context and it simply copies it to the destination
+ * context passed to it.
  *
- *  Other floating point context save/restore models include:
- *    -# not doing anything, and
- *    -# putting a "null FP status word" in the correct place in the FP context.
+ * Other floating point context save/restore models include:
+ *   -# not doing anything, and
+ *   -# putting a "null FP status word" in the correct place in the FP context.
  *
- *  @param[in] _destination is the floating point context area
+ * @param[in] _destination is the floating point context area
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Initialize_fp( _destination ) \
   { \
@@ -907,13 +908,13 @@ void _CPU_Context_Restart_self(
 /* Fatal Error manager macros */
 
 /**
- *  This routine copies _error into a known place -- typically a stack
- *  location or a register, optionally disables interrupts, and
- *  halts/stops the CPU.
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Fatal_halt( _error ) \
   { \
@@ -924,68 +925,66 @@ void _CPU_Context_Restart_self(
 /* Bitfield handler macros */
 
 /**
- *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
  *
- *  This set of routines are used to implement fast searches for
- *  the most important ready task.
+ * This set of routines are used to implement fast searches for
+ * the most important ready task.
  */
+/**@{**/
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the generic bitfield
- *  manipulation implementation.
+ * This definition is set to TRUE if the port uses the generic bitfield
+ * manipulation implementation.
  */
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the data tables provided
- *  by the generic bitfield manipulation implementation.
- *  This can occur when actually using the generic bitfield manipulation
- *  implementation or when implementing the same algorithm in assembly
- *  language for improved performance.  It is unlikely that a port will use
- *  the data if it has a bitfield scan instruction.
+ * This definition is set to TRUE if the port uses the data tables provided
+ * by the generic bitfield manipulation implementation.
+ * This can occur when actually using the generic bitfield manipulation
+ * implementation or when implementing the same algorithm in assembly
+ * language for improved performance.  It is unlikely that a port will use
+ * the data if it has a bitfield scan instruction.
  */
 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This routine sets @a _output to the bit number of the first bit
- *  set in @a _value.  @a _value is of CPU dependent type
- *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
- *  wide although only the 16 least significant bits will be used.
- *
- *  There are a number of variables in using a "find first bit" type
- *  instruction.
- *
- *    -# What happens when run on a value of zero?
- *    -# Bits may be numbered from MSB to LSB or vice-versa.
- *    -# The numbering may be zero or one based.
- *    -# The "find first bit" instruction may search from MSB or LSB.
- *
- *  RTEMS guarantees that (1) will never happen so it is not a concern.
- *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
- *  @ref _CPU_Priority_bits_index.  These three form a set of routines
- *  which must logically operate together.  Bits in the _value are
- *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
- *  The basic major and minor values calculated by @ref _Priority_Major
- *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
- *  to properly range between the values returned by the "find first bit"
- *  instruction.  This makes it possible for @ref _Priority_Get_highest to
- *  calculate the major and directly index into the minor table.
- *  This mapping is necessary to ensure that 0 (a high priority major/minor)
- *  is the first bit found.
- *
- *  This entire "find first bit" and mapping process depends heavily
- *  on the manner in which a priority is broken into a major and minor
- *  components with the major being the 4 MSB of a priority and minor
- *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
- *  to the lowest priority.
- *
- *  If your CPU does not have a "find first bit" instruction, then
- *  there are ways to make do without it.  Here are a handful of ways
- *  to implement this in software:
+ * This routine sets @a _output to the bit number of the first bit
+ * set in @a _value.  @a _value is of CPU dependent type
+ * @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
+ * wide although only the 16 least significant bits will be used.
+ *
+ * There are a number of variables in using a "find first bit" type
+ * instruction.
+ *
+ *   -# What happens when run on a value of zero?
+ *   -# Bits may be numbered from MSB to LSB or vice-versa.
+ *   -# The numbering may be zero or one based.
+ *   -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ * RTEMS guarantees that (1) will never happen so it is not a concern.
+ * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ * @ref _CPU_Priority_bits_index.  These three form a set of routines
+ * which must logically operate together.  Bits in the _value are
+ * set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ * The basic major and minor values calculated by @ref _Priority_Major
+ * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ * to properly range between the values returned by the "find first bit"
+ * instruction.  This makes it possible for @ref _Priority_Get_highest to
+ * calculate the major and directly index into the minor table.
+ * This mapping is necessary to ensure that 0 (a high priority major/minor)
+ * is the first bit found.
+ *
+ * This entire "find first bit" and mapping process depends heavily
+ * on the manner in which a priority is broken into a major and minor
+ * components with the major being the 4 MSB of a priority and minor
+ * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ * to the lowest priority.
+ *
+ * If your CPU does not have a "find first bit" instruction, then
+ * there are ways to make do without it.  Here are a handful of ways
+ * to implement this in software:
  *
 @verbatim
       - a series of 16 bit test instructions
@@ -1002,15 +1001,15 @@ void _CPU_Context_Restart_self(
         _number += bit_set_table[ _value ]
 @endverbatim
 
- *    where bit_set_table[ 16 ] has values which indicate the first
- *      bit set
+ *   where bit_set_table[ 16 ] has values which indicate the first
+ *     bit set
  *
- *  @param[in] _value is the value to be scanned
- *  @param[in] _output is the first bit set
+ * @param[in] _value is the value to be scanned
+ * @param[in] _output is the first bit set
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
@@ -1023,13 +1022,13 @@ void _CPU_Context_Restart_self(
 /* end of Bitfield handler macros */
 
 /**
- *  This routine builds the mask which corresponds to the bit fields
- *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
- *  for that routine.
+ * This routine builds the mask which corresponds to the bit fields
+ * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
+ * for that routine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1039,17 +1038,16 @@ void _CPU_Context_Restart_self(
 #endif
 
 /**
- *  @ingroup CPUBitfield
- *  This routine translates the bit numbers returned by
- *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
- *  a major or minor component of a priority.  See the discussion
- *  for that routine.
+ * This routine translates the bit numbers returned by
+ * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ * a major or minor component of a priority.  See the discussion
+ * for that routine.
  *
- *  @param[in] _priority is the major or minor number to translate
+ * @param[in] _priority is the major or minor number to translate
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1060,30 +1058,33 @@ void _CPU_Context_Restart_self(
 
 /* end of Priority handler macros */
 
+/** @} */
+
 /* functions */
 
 /**
- *  @brief CPU Initialize
- *  This routine performs CPU dependent initialization.
+ * @brief CPU initialization.
  *
- *  Port Specific Information:
+ * This routine performs CPU dependent initialization.
  *
- *  XXX document implementation including references if appropriate
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Initialize(void);
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs a "raw" interrupt handler directly into the
- *  processor's vector table.
+ * @ingroup CPUInterrupt
+ * This routine installs a "raw" interrupt handler directly into the
+ * processor's vector table.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the raw ISR handler to install
- *  @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the raw ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
@@ -1092,16 +1093,16 @@ void _CPU_ISR_install_raw_handler(
 );
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs an interrupt vector.
+ * @ingroup CPUInterrupt
+ * This routine installs an interrupt vector.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the RTEMS ISR handler to install
- *  @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the RTEMS ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_ISR_install_vector(
   uint32_t    vector,
@@ -1110,28 +1111,28 @@ void _CPU_ISR_install_vector(
 );
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs the hardware interrupt stack pointer.
+ * @ingroup CPUInterrupt
+ * This routine installs the hardware interrupt stack pointer.
  *
- *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
- *         is TRUE.
+ * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
+ *        is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Install_interrupt_stack( void );
 
 /**
- *  @ingroup CPUContext
- *  This routine switches from the run context to the heir context.
+ * @ingroup CPUContext
+ * This routine switches from the run context to the heir context.
  *
- *  @param[in] run points to the context of the currently executing task
- *  @param[in] heir points to the context of the heir task
+ * @param[in] run points to the context of the currently executing task
+ * @param[in] heir points to the context of the heir task
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_switch(
   Context_Control  *run,
@@ -1139,90 +1140,94 @@ void _CPU_Context_switch(
 );
 
 /**
- *  @ingroup CPUContext
- *  This routine is generally used only to restart self in an
- *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
+ * @addtogroup CPUContext
+ */
+/**@{**/
+
+/**
+ * This routine is generally used only to restart self in an
+ * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
  *
- *  @param[in] new_context points to the context to be restored.
+ * @param[in] new_context points to the context to be restored.
  *
- *  @note May be unnecessary to reload some registers.
+ * NOTE: May be unnecessary to reload some registers.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_restore(
   Context_Control *new_context
 ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
 
 /**
- *  @ingroup CPUContext
- *  This routine saves the floating point context passed to it.
+ * This routine saves the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
- *  point context area
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area
  *
- *  @return on output @a *fp_context_ptr will contain the address that
- *  should be used with @ref _CPU_Context_restore_fp to restore this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_restore_fp to restore this context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_save_fp(
   Context_Control_fp **fp_context_ptr
 );
 
 /**
- *  @ingroup CPUContext
- *  This routine restores the floating point context passed to it.
+ * This routine restores the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
- *  point context area to restore
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area to restore
  *
- *  @return on output @a *fp_context_ptr will contain the address that
- *  should be used with @ref _CPU_Context_save_fp to save this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_save_fp to save this context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_restore_fp(
   Context_Control_fp **fp_context_ptr
 );
 
+/** @} */
+
 /* FIXME */
 typedef CPU_Interrupt_frame CPU_Exception_frame;
 
 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
 
 /**
- *  @ingroup CPUEndian
- *  The following routine swaps the endian format of an unsigned int.
- *  It must be static because it is referenced indirectly.
+ * @ingroup CPUEndian
+ * The following routine swaps the endian format of an unsigned int.
+ * It must be static because it is referenced indirectly.
  *
- *  This version will work on any processor, but if there is a better
- *  way for your CPU PLEASE use it.  The most common way to do this is to:
+ * This version will work on any processor, but if there is a better
+ * way for your CPU PLEASE use it.  The most common way to do this is to:
  *
- *     swap least significant two bytes with 16-bit rotate
- *     swap upper and lower 16-bits
- *     swap most significant two bytes with 16-bit rotate
+ *    swap least significant two bytes with 16-bit rotate
+ *    swap upper and lower 16-bits
+ *    swap most significant two bytes with 16-bit rotate
  *
- *  Some CPUs have special instructions which swap a 32-bit quantity in
- *  a single instruction (e.g. i486).  It is probably best to avoid
- *  an "endian swapping control bit" in the CPU.  One good reason is
- *  that interrupts would probably have to be disabled to ensure that
- *  an interrupt does not try to access the same "chunk" with the wrong
- *  endian.  Another good reason is that on some CPUs, the endian bit
- *  endianness for ALL fetches -- both code and data -- so the code
- *  will be fetched incorrectly.
+ * Some CPUs have special instructions which swap a 32-bit quantity in
+ * a single instruction (e.g. i486).  It is probably best to avoid
+ * an "endian swapping control bit" in the CPU.  One good reason is
+ * that interrupts would probably have to be disabled to ensure that
+ * an interrupt does not try to access the same "chunk" with the wrong
+ * endian.  Another good reason is that on some CPUs, the endian bit
+ * endianness for ALL fetches -- both code and data -- so the code
+ * will be fetched incorrectly.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 static inline uint32_t CPU_swap_u32(
   uint32_t value
@@ -1240,11 +1245,11 @@ static inline uint32_t CPU_swap_u32(
 }
 
 /**
- *  @ingroup CPUEndian
- *  This routine swaps a 16 bir quantity.
+ * @ingroup CPUEndian
+ * This routine swaps a 16 bir quantity.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  */
 #define CPU_swap_u16( value ) \
   (((value&0xff) << 8) | ((value >> 8)&0xff))
diff --git a/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h b/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h
index e3797a93f9..51648b1597 100644
--- a/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/m32r/rtems/score/cpu_asm.h
@@ -1,12 +1,14 @@
 /**
- * @file rtems/score/cpu_asm.h
+ * @file
+ *
+ * @brief Intel M32R Assembly File
+ *
+ * Very loose template for an include file for the cpu_asm.? file
+ * if it is implemented as a ".S" file (preprocessed by cpp) instead
+ * of a ".s" file (preprocessed by gm4 or gasp).
  */
 
 /*
- *  Very loose template for an include file for the cpu_asm.? file
- *  if it is implemented as a ".S" file (preprocessed by cpp) instead
- *  of a ".s" file (preprocessed by gm4 or gasp).
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/m32r/rtems/score/m32r.h b/cpukit/score/cpu/m32r/rtems/score/m32r.h
index d4dbe69744..98461dfa37 100644
--- a/cpukit/score/cpu/m32r/rtems/score/m32r.h
+++ b/cpukit/score/cpu/m32r/rtems/score/m32r.h
@@ -1,9 +1,15 @@
-/*
- *  This file sets up basic CPU dependency settings based on
- *  compiler settings.  For example, it can determine if
- *  floating point is available.  This particular implementation
- *  is specified to the NO CPU port.
+/**
+ * @file
+ *
+ * @brief Set up Basic CPU Dependency Settings Based on Compiler Settings
  *
+ * This file sets up basic CPU dependency settings based on
+ * compiler settings.  For example, it can determine if
+ * floating point is available.  This particular implementation
+ * is specified to the NO CPU port.
+ */
+
+/*
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/m32r/rtems/score/types.h b/cpukit/score/cpu/m32r/rtems/score/types.h
index 839ac98cc6..829b668f69 100644
--- a/cpukit/score/cpu/m32r/rtems/score/types.h
+++ b/cpukit/score/cpu/m32r/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief Intel M32R CPU Type Definitions
+ *
+ * This include file contains type definitions pertaining to the Intel
+ * m32r processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the Intel
- *  m32r processor family.
- *
  *  COPYRIGHT (c) 1989-2006.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/m68k/rtems/asm.h b/cpukit/score/cpu/m68k/rtems/asm.h
index f6abbd6d32..cbd2a7f8b2 100644
--- a/cpukit/score/cpu/m68k/rtems/asm.h
+++ b/cpukit/score/cpu/m68k/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
+ * 
+ * @brief Address the Problems Caused by Incompatible Flavor of 
+ * Assemblers and Toolsets
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ * 
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
diff --git a/cpukit/score/cpu/m68k/rtems/m68k/m68302.h b/cpukit/score/cpu/m68k/rtems/m68k/m68302.h
index bcda554948..acf55f50c5 100644
--- a/cpukit/score/cpu/m68k/rtems/m68k/m68302.h
+++ b/cpukit/score/cpu/m68k/rtems/m68k/m68302.h
@@ -1,7 +1,7 @@
-/*
- *------------------------------------------------------------------
+/**
+ * @file
  *
- *	m68302.h - Definitions for Motorola MC68302 processor.
+ * @brief Definitions for Motorola MC68302 Processor
  *
  * Section references in this file refer to revision 2 of Motorola's
  * "MC68302 Integrated Multiprotocol Processor User's Manual".
@@ -9,7 +9,9 @@
  *
  * Based on Don Meyer's cpu68302.h that was posted in comp.sys.m68k
  * on 17 February, 1993.
- *
+ */
+
+/*
  * COPYRIGHT 1995 David W. Glessner.
  *
  * Redistribution and use in source and binary forms are permitted
diff --git a/cpukit/score/cpu/m68k/rtems/m68k/m68360.h b/cpukit/score/cpu/m68k/rtems/m68k/m68360.h
index 5c7b90691f..dc181d0cdf 100644
--- a/cpukit/score/cpu/m68k/rtems/m68k/m68360.h
+++ b/cpukit/score/cpu/m68k/rtems/m68k/m68360.h
@@ -1,3 +1,8 @@
+/**
+ * @file
+ *
+ * @brief Definitions for Motorola MC68360 Processor
+ */
 /*
  **************************************************************************
  **************************************************************************
@@ -707,7 +712,7 @@ typedef struct m360_ {
 	unsigned char		_pad14[0xF0-0xD0];
 	unsigned char		_pad15[0x100-0xF0];
 	unsigned char		_pad16[0x500-0x100];
-	
+
 	/*
 	 * IDMA1 Block
 	 */
@@ -725,7 +730,7 @@ typedef struct m360_ {
 	unsigned char		csr1;
 	unsigned char		_pad21;
 	unsigned short		_pad22;
-	
+
 	/*
 	 * SDMA Block
 	 */
@@ -733,7 +738,7 @@ typedef struct m360_ {
 	unsigned char		_pad23;
 	unsigned short		sdcr;
 	unsigned long		sdar;
-	
+
 	/*
 	 * IDMA2 Block
 	 */
@@ -750,7 +755,7 @@ typedef struct m360_ {
 	unsigned char		_pad28;
 	unsigned short		_pad29;
 	unsigned long		_pad30;
-	
+
 	/*
 	 * CPIC Block
 	 */
@@ -774,7 +779,7 @@ typedef struct m360_ {
 	unsigned short		pcint;
 	unsigned short		_pad32;
 	unsigned long		_pad33[5];
-	
+
 	/*
 	 * TIMER Block
 	 */
@@ -802,7 +807,7 @@ typedef struct m360_ {
 	unsigned short		ter3;
 	unsigned short		ter4;
 	unsigned long		_pad36[2];
-	
+
 	/*
 	 * CP Block
 	 */
diff --git a/cpukit/score/cpu/m68k/rtems/m68k/qsm.h b/cpukit/score/cpu/m68k/rtems/m68k/qsm.h
index 312dfa8325..32dbc1d5f9 100644
--- a/cpukit/score/cpu/m68k/rtems/m68k/qsm.h
+++ b/cpukit/score/cpu/m68k/rtems/m68k/qsm.h
@@ -1,7 +1,7 @@
-/*
- *-------------------------------------------------------------------
+/**
+ * @file
  *
- *   QSM -- Queued Serial Module
+ * @brief Motorola M68K Queued Serial Module
  *
  * The QSM contains two serial interfaces: (a) the queued serial
  * peripheral interface (QSPI) and the serial communication interface
@@ -15,7 +15,9 @@
  * For more information, refer to Motorola's "Modular Microcontroller
  * Family Queued Serial Module Reference Manual" (Motorola document
  * QSMRM/AD).
- *
+ */
+
+/*
  * This file was created by John S. Gwynne to support Motorola's 68332 MCU.
  *
  * Redistribution and use in source and binary forms are permitted
diff --git a/cpukit/score/cpu/m68k/rtems/m68k/sim.h b/cpukit/score/cpu/m68k/rtems/m68k/sim.h
index 42eae109d9..cec6b84cc1 100644
--- a/cpukit/score/cpu/m68k/rtems/m68k/sim.h
+++ b/cpukit/score/cpu/m68k/rtems/m68k/sim.h
@@ -1,7 +1,7 @@
-/*
- *-------------------------------------------------------------------
+/**
+ * @file
  *
- *   SIM -- System Integration Module
+ * @brief Motorola M68K System Integration Module
  *
  * The system integration module (SIM) is used on many Motorola 16-
  * and 32-bit MCUs for the following functions:
@@ -23,7 +23,9 @@
  * For more information, refer to Motorola's "Modular Microcontroller
  * Family System Integration Module Reference Manual" (Motorola document
  * SIMRM/AD).
- *
+ */
+
+/*
  * This file was created by John S. Gwynne to support Motorola's 68332 MCU.
  *
  * Redistribution and use in source and binary forms are permitted
diff --git a/cpukit/score/cpu/m68k/rtems/score/cpu.h b/cpukit/score/cpu/m68k/rtems/score/cpu.h
index fb970eb108..8575f90e19 100644
--- a/cpukit/score/cpu/m68k/rtems/score/cpu.h
+++ b/cpukit/score/cpu/m68k/rtems/score/cpu.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/cpu.h
+ * @file 
+ * 
+ * @brief Motorola M68K CPU Dependent Source
+ * 
+ * This include file contains information pertaining to the Motorola
+ * m68xxx processor family.
  */
 
 /*
- *  This include file contains information pertaining to the Motorola
- *  m68xxx processor family.
- *
  *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/m68k/rtems/score/m68k.h b/cpukit/score/cpu/m68k/rtems/score/m68k.h
index cc2f11dc40..2c646c5bcf 100644
--- a/cpukit/score/cpu/m68k/rtems/score/m68k.h
+++ b/cpukit/score/cpu/m68k/rtems/score/m68k.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/m68k.h
+ * @file
+ * 
+ * @brief Motorola M68K CPU Dependent Source
+ * 
+ * This include file contains information pertaining to the Motorola
+ * m68xxx processor family.
  */
 
 /*
- *  This include file contains information pertaining to the Motorola
- *  m68xxx processor family.
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/m68k/rtems/score/types.h b/cpukit/score/cpu/m68k/rtems/score/types.h
index 8591511075..a901c90542 100644
--- a/cpukit/score/cpu/m68k/rtems/score/types.h
+++ b/cpukit/score/cpu/m68k/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ * 
+ * @brief Motorola M68K CPU Type Definitions
+ * 
+ * This include file contains type definitions pertaining to the Motorola
+ * m68xxx processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the Motorola
- *  m68xxx processor family.
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/mips/rtems/asm.h b/cpukit/score/cpu/mips/rtems/asm.h
index 73e4366b87..9c84f61990 100644
--- a/cpukit/score/cpu/mips/rtems/asm.h
+++ b/cpukit/score/cpu/mips/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
diff --git a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
index c1a934098f..927bbec133 100644
--- a/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
+++ b/cpukit/score/cpu/mips/rtems/mips/idtcpu.h
@@ -1,33 +1,46 @@
-/*
-
-Based upon IDT provided code with the following release:
-
-This source code has been made available to you by IDT on an AS-IS
-basis. Anyone receiving this source is licensed under IDT copyrights
-to use it in any way he or she deems fit, including copying it,
-modifying it, compiling it, and redistributing it either with or
-without modifications.  No license under IDT patents or patent
-applications is to be implied by the copyright license.
-
-Any user of this software should understand that IDT cannot provide
-technical support for this software and will not be responsible for
-any consequences resulting from the use of this software.
-
-Any person who transfers this source code or any derivative work must
-include the IDT copyright notice, this paragraph, and the preceeding
-two paragraphs in the transferred software.
-
-COPYRIGHT IDT CORPORATION 1996
-LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
-*/
+/**
+ *  @file idtcpu.h
+ *
+ *  @brief CPU Related Definitions
+ *
+ * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves
+ *         added Register definition for XContext reg.
+ *         Look towards end of this file.
+ */
 
 /*
-** idtcpu.h -- cpu related defines
-*/
+ * Based upon IDT provided code with the following release:
+ *
+ * This source code has been made available to you by IDT on an AS-IS
+ * basis. Anyone receiving this source is licensed under IDT copyrights
+ * to use it in any way he or she deems fit, including copying it,
+ * modifying it, compiling it, and redistributing it either with or
+ * without modifications.  No license under IDT patents or patent
+ * applications is to be implied by the copyright license.
+ *
+ * Any user of this software should understand that IDT cannot provide
+ * technical support for this software and will not be responsible for
+ * any consequences resulting from the use of this software.
+ *
+ * Any person who transfers this source code or any derivative work must
+ * include the IDT copyright notice, this paragraph, and the preceeding
+ * two paragraphs in the transferred software.
+ *
+ * COPYRIGHT IDT CORPORATION 1996
+ * LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+ */
 
 #ifndef _RTEMS_MIPS_IDTCPU_H
 #define _RTEMS_MIPS_IDTCPU_H
 
+/**
+ *  @defgroup MipsSet_idtcpu CPU Related Definitions
+ *
+ *  @ingroup MIPS
+ *
+ */
+/**@{*/
+
 /*
  * 950313: Ketan added Register definition for XContext reg.
  *               added define for WAIT instruction.
@@ -92,7 +105,7 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 **	Cache size constants
 */
 #define	MINCACHE	0x200		/* 512       For 3041. */
-#define	MAXCACHE	0x40000		/* 256*1024   256k */	
+#define	MAXCACHE	0x40000		/* 256*1024   256k */
 
 #if  __mips == 32
 /* R4000 configuration register definitions */
@@ -691,5 +704,5 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 #define CALG	$17
 #endif
 
+/**@}*/
 #endif /* _RTEMS_MIPS_IDTCPU_H */
-
diff --git a/cpukit/score/cpu/mips/rtems/mips/iregdef.h b/cpukit/score/cpu/mips/rtems/mips/iregdef.h
index 631e5aa178..5d41074184 100644
--- a/cpukit/score/cpu/mips/rtems/mips/iregdef.h
+++ b/cpukit/score/cpu/mips/rtems/mips/iregdef.h
@@ -1,44 +1,51 @@
-/*
-
-Based upon IDT provided code with the following release:
-
-This source code has been made available to you by IDT on an AS-IS
-basis. Anyone receiving this source is licensed under IDT copyrights
-to use it in any way he or she deems fit, including copying it,
-modifying it, compiling it, and redistributing it either with or
-without modifications.  No license under IDT patents or patent
-applications is to be implied by the copyright license.
-
-Any user of this software should understand that IDT cannot provide
-technical support for this software and will not be responsible for
-any consequences resulting from the use of this software.
-
-Any person who transfers this source code or any derivative work must
-include the IDT copyright notice, this paragraph, and the preceeding
-two paragraphs in the transferred software.
-
-COPYRIGHT IDT CORPORATION 1996
-LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
-
+/**
+ *  @file iregdef.h
+ *
+ *  @brief IDT R3000 Register Structure
+ *
+ * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves
+ *         added Register definition for XContext reg.
+ *         Look towards end of this file.
+ */
 
 /*
-**	iregdef.h - IDT R3000 register structure header file
-**
-**	Copyright 1989 Integrated Device Technology, Inc
-**	All Rights Reserved
-**
-*/
+ *	Copyright 1989 Integrated Device Technology, Inc
+ *	All Rights Reserved
+ *
+ * Based upon IDT provided code with the following release:
+ *
+ * This source code has been made available to you by IDT on an AS-IS
+ * basis. Anyone receiving this source is licensed under IDT copyrights
+ * to use it in any way he or she deems fit, including copying it,
+ * modifying it, compiling it, and redistributing it either with or
+ * without modifications.  No license under IDT patents or patent
+ * applications is to be implied by the copyright license.
+ *
+ * Any user of this software should understand that IDT cannot provide
+ * technical support for this software and will not be responsible for
+ * any consequences resulting from the use of this software.
+ *
+ * Any person who transfers this source code or any derivative work must
+ * include the IDT copyright notice, this paragraph, and the preceeding
+ * two paragraphs in the transferred software.
+ *
+ * COPYRIGHT IDT CORPORATION 1996
+ * LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
+ */
+
 #ifndef _RTEMS_MIPS_IREGDEF_H
 #define _RTEMS_MIPS_IREGDEF_H
 
-/*
- * 950313: Ketan added sreg/lreg and R_SZ for 64-bit saves
- *         added Register definition for XContext reg.
- *         Look towards end of this file.
+/**
+ *  @defgroup MipsSet_iregdef Register Structure
+ *
+ *  @ingroup MIPS
+ *
  */
-/*
-** register names
-*/
+/**@{*/
+
+/* register names */
+
 #define r0	$0
 #define r1	$1
 #define r2	$2
@@ -326,5 +333,5 @@ LICENSED MATERIAL - PROGRAM PROPERTY OF IDT
 /* Ketan till here */
 #endif
 
+/**@}*/
 #endif /* _RTEMS_MIPS_IREGDEF_H */
-
diff --git a/cpukit/score/cpu/mips/rtems/score/cpu.h b/cpukit/score/cpu/mips/rtems/score/cpu.h
index 1da23db423..b4d040e72b 100644
--- a/cpukit/score/cpu/mips/rtems/score/cpu.h
+++ b/cpukit/score/cpu/mips/rtems/score/cpu.h
@@ -1,7 +1,7 @@
 /**
  *  @file
- *  
- *  Mips CPU Dependent Header File
+ *
+ *  @brief Mips CPU Dependent Header File
  *
  *  Conversion to MIPS port by Alan Cudmore <alanc@linuxstart.com> and
  *           Joel Sherrill <joel@OARcorp.com>.
@@ -42,6 +42,14 @@
 #ifndef _RTEMS_SCORE_CPU_H
 #define _RTEMS_SCORE_CPU_H
 
+/**
+ *  @defgroup ScoreCPU CPU CPU
+ *
+ *  @ingroup Score
+ *
+ */
+/**@{*/
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -211,7 +219,7 @@ extern "C" {
  *  all tasks floating point.
  */
 
-#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP 
+#define CPU_ALL_TASKS_ARE_FP CPU_HARDWARE_FP
 
 /*
  *  Should the IDLE task have a floating point context?
@@ -1172,4 +1180,5 @@ static inline uint32_t CPU_swap_u32(
 }
 #endif
 
+/**@}*/
 #endif
diff --git a/cpukit/score/cpu/mips/rtems/score/mips.h b/cpukit/score/cpu/mips/rtems/score/mips.h
index f81fd32ec2..8348501e30 100644
--- a/cpukit/score/cpu/mips/rtems/score/mips.h
+++ b/cpukit/score/cpu/mips/rtems/score/mips.h
@@ -1,5 +1,14 @@
 /**
  * @file rtems/score/mips.h
+ *
+ * @brief Information to build RTEMS for a "no cpu" while in protected mode.
+ *
+ *  This file contains the information required to build
+ *  RTEMS for a particular member of the "no cpu"
+ *  family when executing in protected mode.  It does
+ *  this by setting variables to indicate which implementation
+ *  dependent features are present in a particular member
+ *  of the family.
  */
 
 /*
@@ -14,6 +23,14 @@
 #ifndef _RTEMS_SCORE_MIPS_H
 #define _RTEMS_SCORE_MIPS_H
 
+/**
+ *  @defgroup ScoreMips RTEMS no cpu Build Information
+ *
+ *  @ingroup Score
+ *
+ */
+/**@{*/
+
 #ifdef __cplusplus
 extern "C" {
 #endif
@@ -277,5 +294,6 @@ extern "C" {
 }
 #endif
 
+/**@}*/
 #endif /* _RTEMS_SCORE_MIPS_H */
 /* end of include file */
diff --git a/cpukit/score/cpu/mips/rtems/score/types.h b/cpukit/score/cpu/mips/rtems/score/types.h
index f26819a739..f935389271 100644
--- a/cpukit/score/cpu/mips/rtems/score/types.h
+++ b/cpukit/score/cpu/mips/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
  * @file rtems/score/types.h
+ *
+ * @brief Type Definitions Pertaining to the MIPS Processor Family
+ *
+ *  This include file contains type definitions pertaining to the MIPS
+ *  processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the MIPS
- *  processor family.
- *
  *  COPYRIGHT (c) 1989-2001.
  *  On-Line Applications Research Corporation (OAR).
  *
@@ -18,6 +20,14 @@
 #ifndef _RTEMS_SCORE_TYPES_H
 #define _RTEMS_SCORE_TYPES_H
 
+/**
+ *  @defgroup ScoreTypes MIPS Processor Family Type Definitions
+ *
+ *  @ingroup Score
+ *
+ */
+/**@{*/
+
 #include <rtems/score/basedefs.h>
 
 #ifndef ASM
@@ -40,4 +50,5 @@ typedef void ( *mips_isr_entry )( void );
 
 #endif  /* !ASM */
 
+/**@}*/
 #endif
diff --git a/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S b/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
index 42da434da6..f214f4ddef 100644
--- a/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
+++ b/cpukit/score/cpu/nios2/nios2-eic-il-low-level.S
@@ -160,7 +160,6 @@ do_thread_dispatch:
 	ldw	r10, FRAME_OFFSET_R10(sp)
 	ldw	r11, FRAME_OFFSET_R11(sp)
 	ldw	r12, FRAME_OFFSET_R12(sp)
-	ldw	r13, FRAME_OFFSET_R13(sp)
 
 	/*
 	 * Disable interrupts.
@@ -180,15 +179,16 @@ do_thread_dispatch:
 	wrctl	status, r15
 
 	/* Load thread dispatch necessary */
-	ldb	r12, %gprel(_Per_CPU_Information + PER_CPU_DISPATCH_NEEDED)(gp)
+	ldb	r13, %gprel(_Per_CPU_Information + PER_CPU_DISPATCH_NEEDED)(gp)
 
 	/* Is thread dispatch necessary? */
-	bne	r12, zero, enable_interrupts_before_thread_dispatch
+	bne	r13, zero, enable_interrupts_before_thread_dispatch
 
 	/* Enable Nios II specific thread dispatch */
 	stw	zero, %gprel(_Nios2_Thread_dispatch_disabled)(gp)
 
 	/* Restore remaining volatile register */
+	ldw	r13, FRAME_OFFSET_R13(sp)
 	ldw	r14, FRAME_OFFSET_R14(sp)
 	ldw	r15, FRAME_OFFSET_R15(sp)
 
diff --git a/cpukit/score/cpu/nios2/rtems/asm.h b/cpukit/score/cpu/nios2/rtems/asm.h
index 0725d7c0ed..45ccd8b050 100644
--- a/cpukit/score/cpu/nios2/rtems/asm.h
+++ b/cpukit/score/cpu/nios2/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * @note The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu.h b/cpukit/score/cpu/nios2/rtems/score/cpu.h
index 7beb4ec06f..6db6d1d46c 100644
--- a/cpukit/score/cpu/nios2/rtems/score/cpu.h
+++ b/cpukit/score/cpu/nios2/rtems/score/cpu.h
@@ -1,3 +1,9 @@
+/**
+ * @file
+ *
+ * @brief Altera Nios II CPU Department Source
+ */
+
 /*
  *  Copyright (c) 2011 embedded brains GmbH
  *
@@ -253,8 +259,8 @@ void _CPU_Initialize_vectors( void );
  * _CPU_ISR_Disable().  The value is not modified.
  *
  * This flash code is optimal for all Nios II configurations.  The rdctl does
- * not flush the pipeline and has only a late result penalty.  The wrctl on the
- * other hand leads to a pipeline flush.
+ * not flush the pipeline and has only a late result penalty.  The wrctl on
+ * the other hand leads to a pipeline flush.
  */
 #define _CPU_ISR_Flash( _isr_cookie ) \
   do { \
@@ -319,14 +325,12 @@ void _CPU_Context_Initialize(
 void _CPU_Fatal_halt( uint32_t _error ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
 
 /**
- * @brief CPU Initialize
- *
+ * @brief CPU initialization.
  */
 void _CPU_Initialize( void );
 
 /**
- * @brief CPU ISR Install Raw Handler
- *
+ * @brief CPU ISR install raw handler.
  */
 void _CPU_ISR_install_raw_handler(
   uint32_t vector,
@@ -335,8 +339,7 @@ void _CPU_ISR_install_raw_handler(
 );
 
 /**
- * @brief CPU ISR Install Vector.
- *
+ * @brief CPU ISR install vector.
  */
 void _CPU_ISR_install_vector(
   uint32_t vector,
diff --git a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h b/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h
index d0572d8b2a..8c0e046c34 100644
--- a/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/nios2/rtems/score/cpu_asm.h
@@ -1,12 +1,14 @@
 /**
- * @file rtems/score/cpu_asm.h
+ * @file
+ *
+ * @brief Altera Nios II Assembly File
+ *
+ * Very loose template for an include file for the cpu_asm.? file
+ * if it is implemented as a ".S" file (preprocessed by cpp) instead
+ * of a ".s" file (preprocessed by gm4 or gasp).
  */
 
 /*
- *  Very loose template for an include file for the cpu_asm.? file
- *  if it is implemented as a ".S" file (preprocessed by cpp) instead
- *  of a ".s" file (preprocessed by gm4 or gasp).
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h b/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h
index b99dd02cd2..078484fe6b 100644
--- a/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h
+++ b/cpukit/score/cpu/nios2/rtems/score/nios2-utility.h
@@ -1,3 +1,8 @@
+/**
+ * @file
+ *
+ * @brief NIOS II Utility
+ */
 /*
  * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
  *
@@ -496,9 +501,8 @@ static inline void _Nios2_MPU_Restore( uint32_t config )
   _Nios2_Set_ctlreg_config( config );
 }
 
-/*
- *  @brief Nios2 MPU Disable Protected
- *
+/**
+ * @brief Nios2 MPU disable protected.
  */
 uint32_t _Nios2_MPU_Disable_protected( void );
 
diff --git a/cpukit/score/cpu/nios2/rtems/score/nios2.h b/cpukit/score/cpu/nios2/rtems/score/nios2.h
index 9fd8bff0f3..9a8e232eee 100644
--- a/cpukit/score/cpu/nios2/rtems/score/nios2.h
+++ b/cpukit/score/cpu/nios2/rtems/score/nios2.h
@@ -1,11 +1,16 @@
-/*  nios2.h
- *
- *  This file sets up basic CPU dependency settings based on
- *  compiler settings.  For example, it can determine if
- *  floating point is available.  This particular implementation
- *  is specific to the NIOS2 port.
+/**
+ * @file
  *
+ * @brief NIOS II Set up Basic CPU Dependency Settings Based on
+ * Compiler Settings
  *
+ * This file sets up basic CPU dependency settings based on
+ * compiler settings.  For example, it can determine if
+ * floating point is available.  This particular implementation
+ * is specific to the NIOS2 port.
+ */
+
+/*
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/nios2/rtems/score/types.h b/cpukit/score/cpu/nios2/rtems/score/types.h
index 48c1ebacb9..13a4ecba94 100644
--- a/cpukit/score/cpu/nios2/rtems/score/types.h
+++ b/cpukit/score/cpu/nios2/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief Altera Nios II CPU Type Definitions
+ *
+ * This include file contains type definitions pertaining to the
+ * Altera Nios II processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the
- *  Altera Nios II processor family.
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/no_cpu/rtems/asm.h b/cpukit/score/cpu/no_cpu/rtems/asm.h
index 90708e3cfc..926e3964e5 100644
--- a/cpukit/score/cpu/no_cpu/rtems/asm.h
+++ b/cpukit/score/cpu/no_cpu/rtems/asm.h
@@ -1,17 +1,19 @@
 /**
  * @file rtems/asm.h
  *
+ * @brief Addresses Incompatible Flavors Problems
+ *
  *  This include file attempts to address the problems
  *  caused by incompatible flavors of assemblers and
  *  toolsets.  It primarily addresses variations in the
  *  use of leading underscores on symbols and the requirement
  *  that register names be preceded by a %.
+ *
+ *  NOTE: The spacing in the use of these macros
+ *        is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
@@ -26,6 +28,13 @@
 #ifndef _RTEMS_ASM_H
 #define _RTEMS_ASM_H
 
+/**
+ *  @defgroup no_cpuAsm Address Incompatible Flavors Problems
+ *
+ *  @ingroup no_cpu
+ */
+/**@{*/
+
 /*
  *  Indicate we are in an assembly file and get the basic CPU definitions.
  */
@@ -120,4 +129,5 @@
  */
 #define EXTERN(sym) .globl SYM (sym)
 
+/**@}*/
 #endif
diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
index fe63aea3fc..8c4a61bbb4 100644
--- a/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
+++ b/cpukit/score/cpu/no_cpu/rtems/score/cpu.h
@@ -41,172 +41,172 @@ extern "C" {
 /* conditional compilation parameters */
 
 /**
- *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ * Should the calls to @ref _Thread_Enable_dispatch be inlined?
  *
- *  If TRUE, then they are inlined.
- *  If FALSE, then a subroutine call is made.
+ * If TRUE, then they are inlined.
+ * If FALSE, then a subroutine call is made.
  *
- *  This conditional is an example of the classic trade-off of size
- *  versus speed.  Inlining the call (TRUE) typically increases the
- *  size of RTEMS while speeding up the enabling of dispatching.
+ * This conditional is an example of the classic trade-off of size
+ * versus speed.  Inlining the call (TRUE) typically increases the
+ * size of RTEMS while speeding up the enabling of dispatching.
  *
- *  @note In general, the @ref _Thread_Dispatch_disable_level will
- *  only be 0 or 1 unless you are in an interrupt handler and that
- *  interrupt handler invokes the executive.]  When not inlined
- *  something calls @ref _Thread_Enable_dispatch which in turns calls
- *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
- *  one subroutine call is avoided entirely.
+ * NOTE: In general, the @ref _Thread_Dispatch_disable_level will
+ * only be 0 or 1 unless you are in an interrupt handler and that
+ * interrupt handler invokes the executive.]  When not inlined
+ * something calls @ref _Thread_Enable_dispatch which in turns calls
+ * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
+ * one subroutine call is avoided entirely.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INLINE_ENABLE_DISPATCH       FALSE
 
 /**
- *  Should the body of the search loops in _Thread_queue_Enqueue_priority
- *  be unrolled one time?  In unrolled each iteration of the loop examines
- *  two "nodes" on the chain being searched.  Otherwise, only one node
- *  is examined per iteration.
+ * Should the body of the search loops in _Thread_queue_Enqueue_priority
+ * be unrolled one time?  In unrolled each iteration of the loop examines
+ * two "nodes" on the chain being searched.  Otherwise, only one node
+ * is examined per iteration.
  *
- *  If TRUE, then the loops are unrolled.
- *  If FALSE, then the loops are not unrolled.
+ * If TRUE, then the loops are unrolled.
+ * If FALSE, then the loops are not unrolled.
  *
- *  The primary factor in making this decision is the cost of disabling
- *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- *  body of the loop.  On some CPUs, the flash is more expensive than
- *  one iteration of the loop body.  In this case, it might be desirable
- *  to unroll the loop.  It is important to note that on some CPUs, this
- *  code is the longest interrupt disable period in RTEMS.  So it is
- *  necessary to strike a balance when setting this parameter.
+ * The primary factor in making this decision is the cost of disabling
+ * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ * body of the loop.  On some CPUs, the flash is more expensive than
+ * one iteration of the loop body.  In this case, it might be desirable
+ * to unroll the loop.  It is important to note that on some CPUs, this
+ * code is the longest interrupt disable period in RTEMS.  So it is
+ * necessary to strike a balance when setting this parameter.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
 
 /**
- *  Does RTEMS manage a dedicated interrupt stack in software?
+ * Does RTEMS manage a dedicated interrupt stack in software?
  *
- *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
- *  If FALSE, nothing is done.
+ * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ * If FALSE, nothing is done.
  *
- *  If the CPU supports a dedicated interrupt stack in hardware,
- *  then it is generally the responsibility of the BSP to allocate it
- *  and set it up.
+ * If the CPU supports a dedicated interrupt stack in hardware,
+ * then it is generally the responsibility of the BSP to allocate it
+ * and set it up.
  *
- *  If the CPU does not support a dedicated interrupt stack, then
- *  the porter has two options: (1) execute interrupts on the
- *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
- *  interrupt stack.
+ * If the CPU does not support a dedicated interrupt stack, then
+ * the porter has two options: (1) execute interrupts on the
+ * stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ * interrupt stack.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK FALSE
 
 /**
- *  Does the CPU follow the simple vectored interrupt model?
+ * Does the CPU follow the simple vectored interrupt model?
  *
- *  If TRUE, then RTEMS allocates the vector table it internally manages.
- *  If FALSE, then the BSP is assumed to allocate and manage the vector
- *  table
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
 
 /**
- *  Does this CPU have hardware support for a dedicated interrupt stack?
+ * Does this CPU have hardware support for a dedicated interrupt stack?
  *
- *  If TRUE, then it must be installed during initialization.
- *  If FALSE, then no installation is performed.
+ * If TRUE, then it must be installed during initialization.
+ * If FALSE, then no installation is performed.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HAS_HARDWARE_INTERRUPT_STACK TRUE
 
 /**
- *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
  *
- *  If TRUE, then the memory is allocated during initialization.
- *  If FALSE, then the memory is allocated during initialization.
+ * If TRUE, then the memory is allocated during initialization.
+ * If FALSE, then the memory is allocated during initialization.
  *
- *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
 
 /**
- *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector
- *  number (0)?
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ISR_PASSES_FRAME_POINTER 0
 
 /**
- *  @def CPU_HARDWARE_FP
+ * @def CPU_HARDWARE_FP
  *
- *  Does the CPU have hardware floating point?
+ * Does the CPU have hardware floating point?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
  *
- *  If there is a FP coprocessor such as the i387 or mc68881, then
- *  the answer is TRUE.
+ * If there is a FP coprocessor such as the i387 or mc68881, then
+ * the answer is TRUE.
  *
- *  The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
- *  It indicates whether or not this CPU model has FP support.  For
- *  example, it would be possible to have an i386_nofp CPU model
- *  which set this to false to indicate that you have an i386 without
- *  an i387 and wish to leave floating point support out of RTEMS.
+ * The macro name "NO_CPU_HAS_FPU" should be made CPU specific.
+ * It indicates whether or not this CPU model has FP support.  For
+ * example, it would be possible to have an i386_nofp CPU model
+ * which set this to false to indicate that you have an i386 without
+ * an i387 and wish to leave floating point support out of RTEMS.
  */
 
 /**
- *  @def CPU_SOFTWARE_FP
+ * @def CPU_SOFTWARE_FP
  *
- *  Does the CPU have no hardware floating point and GCC provides a
- *  software floating point implementation which must be context
- *  switched?
+ * Does the CPU have no hardware floating point and GCC provides a
+ * software floating point implementation which must be context
+ * switched?
  *
- *  This feature conditional is used to indicate whether or not there
- *  is software implemented floating point that must be context
- *  switched.  The determination of whether or not this applies
- *  is very tool specific and the state saved/restored is also
- *  compiler specific.
+ * This feature conditional is used to indicate whether or not there
+ * is software implemented floating point that must be context
+ * switched.  The determination of whether or not this applies
+ * is very tool specific and the state saved/restored is also
+ * compiler specific.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if ( NO_CPU_HAS_FPU == 1 )
 #define CPU_HARDWARE_FP     TRUE
@@ -216,260 +216,261 @@ extern "C" {
 #define CPU_SOFTWARE_FP     FALSE
 
 /**
- *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
  *
- *  So far, the only CPUs in which this option has been used are the
- *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
- *  gcc both implicitly used the floating point registers to perform
- *  integer multiplies.  Similarly, the PowerPC port of gcc has been
- *  seen to allocate floating point local variables and touch the FPU
- *  even when the flow through a subroutine (like vfprintf()) might
- *  not use floating point formats.
+ * So far, the only CPUs in which this option has been used are the
+ * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
+ * gcc both implicitly used the floating point registers to perform
+ * integer multiplies.  Similarly, the PowerPC port of gcc has been
+ * seen to allocate floating point local variables and touch the FPU
+ * even when the flow through a subroutine (like vfprintf()) might
+ * not use floating point formats.
  *
- *  If a function which you would not think utilize the FP unit DOES,
- *  then one can not easily predict which tasks will use the FP hardware.
- *  In this case, this option should be TRUE.
+ * If a function which you would not think utilize the FP unit DOES,
+ * then one can not easily predict which tasks will use the FP hardware.
+ * In this case, this option should be TRUE.
  *
- *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALL_TASKS_ARE_FP     TRUE
 
 /**
- *  Should the IDLE task have a floating point context?
+ * Should the IDLE task have a floating point context?
  *
- *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- *  and it has a floating point context which is switched in and out.
- *  If FALSE, then the IDLE task does not have a floating point context.
+ * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ * and it has a floating point context which is switched in and out.
+ * If FALSE, then the IDLE task does not have a floating point context.
  *
- *  Setting this to TRUE negatively impacts the time required to preempt
- *  the IDLE task from an interrupt because the floating point context
- *  must be saved as part of the preemption.
+ * Setting this to TRUE negatively impacts the time required to preempt
+ * the IDLE task from an interrupt because the floating point context
+ * must be saved as part of the preemption.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_IDLE_TASK_IS_FP      FALSE
 
 /**
- *  Should the saving of the floating point registers be deferred
- *  until a context switch is made to another different floating point
- *  task?
+ * Should the saving of the floating point registers be deferred
+ * until a context switch is made to another different floating point
+ * task?
  *
- *  If TRUE, then the floating point context will not be stored until
- *  necessary.  It will remain in the floating point registers and not
- *  disturned until another floating point task is switched to.
+ * If TRUE, then the floating point context will not be stored until
+ * necessary.  It will remain in the floating point registers and not
+ * disturned until another floating point task is switched to.
  *
- *  If FALSE, then the floating point context is saved when a floating
- *  point task is switched out and restored when the next floating point
- *  task is restored.  The state of the floating point registers between
- *  those two operations is not specified.
+ * If FALSE, then the floating point context is saved when a floating
+ * point task is switched out and restored when the next floating point
+ * task is restored.  The state of the floating point registers between
+ * those two operations is not specified.
  *
- *  If the floating point context does NOT have to be saved as part of
- *  interrupt dispatching, then it should be safe to set this to TRUE.
+ * If the floating point context does NOT have to be saved as part of
+ * interrupt dispatching, then it should be safe to set this to TRUE.
  *
- *  Setting this flag to TRUE results in using a different algorithm
- *  for deciding when to save and restore the floating point context.
- *  The deferred FP switch algorithm minimizes the number of times
- *  the FP context is saved and restored.  The FP context is not saved
- *  until a context switch is made to another, different FP task.
- *  Thus in a system with only one FP task, the FP context will never
- *  be saved or restored.
+ * Setting this flag to TRUE results in using a different algorithm
+ * for deciding when to save and restore the floating point context.
+ * The deferred FP switch algorithm minimizes the number of times
+ * the FP context is saved and restored.  The FP context is not saved
+ * until a context switch is made to another, different FP task.
+ * Thus in a system with only one FP task, the FP context will never
+ * be saved or restored.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_USE_DEFERRED_FP_SWITCH       TRUE
 
 /**
- *  Does this port provide a CPU dependent IDLE task implementation?
+ * Does this port provide a CPU dependent IDLE task implementation?
  *
- *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
- *  must be provided and is the default IDLE thread body instead of
- *  @ref _CPU_Thread_Idle_body.
+ * If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ * must be provided and is the default IDLE thread body instead of
+ * @ref _CPU_Thread_Idle_body.
  *
- *  If FALSE, then use the generic IDLE thread body if the BSP does
- *  not provide one.
+ * If FALSE, then use the generic IDLE thread body if the BSP does
+ * not provide one.
  *
- *  This is intended to allow for supporting processors which have
- *  a low power or idle mode.  When the IDLE thread is executed, then
- *  the CPU can be powered down.
+ * This is intended to allow for supporting processors which have
+ * a low power or idle mode.  When the IDLE thread is executed, then
+ * the CPU can be powered down.
  *
- *  The order of precedence for selecting the IDLE thread body is:
+ * The order of precedence for selecting the IDLE thread body is:
  *
- *    -#  BSP provided
- *    -#  CPU dependent (if provided)
- *    -#  generic (if no BSP and no CPU dependent)
+ *   -#  BSP provided
+ *   -#  CPU dependent (if provided)
+ *   -#  generic (if no BSP and no CPU dependent)
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
 
 /**
- *  Does the stack grow up (toward higher addresses) or down
- *  (toward lower addresses)?
+ * Does the stack grow up (toward higher addresses) or down
+ * (toward lower addresses)?
  *
- *  If TRUE, then the grows upward.
- *  If FALSE, then the grows toward smaller addresses.
+ * If TRUE, then the grows upward.
+ * If FALSE, then the grows toward smaller addresses.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_GROWS_UP               TRUE
 
 /**
- *  The following is the variable attribute used to force alignment
- *  of critical RTEMS structures.  On some processors it may make
- *  sense to have these aligned on tighter boundaries than
- *  the minimum requirements of the compiler in order to have as
- *  much of the critical data area as possible in a cache line.
+ * The following is the variable attribute used to force alignment
+ * of critical RTEMS structures.  On some processors it may make
+ * sense to have these aligned on tighter boundaries than
+ * the minimum requirements of the compiler in order to have as
+ * much of the critical data area as possible in a cache line.
  *
- *  The placement of this macro in the declaration of the variables
- *  is based on the syntactically requirements of the GNU C
- *  "__attribute__" extension.  For example with GNU C, use
- *  the following to force a structures to a 32 byte boundary.
+ * The placement of this macro in the declaration of the variables
+ * is based on the syntactically requirements of the GNU C
+ * "__attribute__" extension.  For example with GNU C, use
+ * the following to force a structures to a 32 byte boundary.
  *
- *      __attribute__ ((aligned (32)))
+ *     __attribute__ ((aligned (32)))
  *
- *  @note Currently only the Priority Bit Map table uses this feature.
- *        To benefit from using this, the data must be heavily
- *        used so it will stay in the cache and used frequently enough
- *        in the executive to justify turning this on.
+ * NOTE: Currently only the Priority Bit Map table uses this feature.
+ *       To benefit from using this, the data must be heavily
+ *       used so it will stay in the cache and used frequently enough
+ *       in the executive to justify turning this on.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STRUCTURE_ALIGNMENT
 
 /**
- *  @defgroup CPUTimestamp Processor Dependent Timestamp Support
+ * @defgroup CPUTimestamp Processor Dependent Timestamp Support
  *
- *  This group assists in issues related to timestamp implementation.
+ * This group assists in issues related to timestamp implementation.
  *
- *  The port must choose exactly one of the following defines:
- *  - #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
- *  - #define CPU_TIMESTAMP_USE_INT64 TRUE
- *  - #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
+ * The port must choose exactly one of the following defines:
+ * - #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
+ * - #define CPU_TIMESTAMP_USE_INT64 TRUE
+ * - #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
  *
- *  Performance of int64_t versus struct timespec
- *  =============================================
+ * Performance of int64_t versus struct timespec
+ * =============================================
  *
- *  On PowerPC/psim, inlined int64_t saves ~50 instructions on each
- *    _Thread_Dispatch operation which results in a context switch.
- *    This works out to be about 10% faster dispatches and 7.5% faster
- *    blocking semaphore obtains.  The following numbers are in instructions
- *    and from tm02 and tm26.
+ * On PowerPC/psim, inlined int64_t saves ~50 instructions on each
+ *   _Thread_Dispatch operation which results in a context switch.
+ *   This works out to be about 10% faster dispatches and 7.5% faster
+ *   blocking semaphore obtains.  The following numbers are in instructions
+ *   and from tm02 and tm26.
  *
- *                         timespec  int64  inlined int64
- *    dispatch:              446      446      400
- *    blocking sem obtain:   627      626      581
+ *                        timespec  int64  inlined int64
+ *   dispatch:              446      446      400
+ *   blocking sem obtain:   627      626      581
  *
- *  On SPARC/sis, inlined int64_t shows the same percentage gains.
- *    The following numbers are in microseconds and from tm02 and tm26.
+ * On SPARC/sis, inlined int64_t shows the same percentage gains.
+ *   The following numbers are in microseconds and from tm02 and tm26.
  *
- *                         timespec  int64  inlined int64
- *    dispatch:               59       61       53
- *    blocking sem obtain:    98      100       92
+ *                        timespec  int64  inlined int64
+ *   dispatch:               59       61       53
+ *   blocking sem obtain:    98      100       92
  *
- *  Inlining appears to have a tendency to increase the size of
- *    some executables.
- *  Not inlining reduces the execution improvement but does not seem to
- *    be an improvement on the PowerPC and SPARC. The struct timespec
- *    and the executables with int64 not inlined are about the same size.
+ * Inlining appears to have a tendency to increase the size of
+ *   some executables.
+ * Not inlining reduces the execution improvement but does not seem to
+ *   be an improvement on the PowerPC and SPARC. The struct timespec
+ *   and the executables with int64 not inlined are about the same size.
+ * 
  */
+/**@{**/
 
 /**
- *  @ingroup CPUTimestamp
- *
- *  Selects the timestamp implementation using struct timespec.
+ * Selects the timestamp implementation using struct timespec.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_TIMESTAMP_USE_STRUCT_TIMESPEC TRUE
 
 /**
- *  @ingroup CPUTimestamp
+ * Selects the timestamp implementation using int64_t and no inlined methods.
  *
- *  Selects the timestamp implementation using int64_t and no inlined methods.
- *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_TIMESTAMP_USE_INT64 TRUE
 
 /**
- *  @ingroup CPUTimestamp
- *
- *  Selects the timestamp implementation using int64_t and inlined methods.
+ * Selects the timestamp implementation using int64_t and inlined methods.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
 
+/** @} */
+
 /**
- *  @defgroup CPUEndian Processor Dependent Endianness Support
+ * @defgroup CPUEndian Processor Dependent Endianness Support
  *
- *  This group assists in issues related to processor endianness.
+ * This group assists in issues related to processor endianness.
+ * 
  */
+/**@{**/
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * NOTE: @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_LITTLE_ENDIAN
+ * @see CPU_LITTLE_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_BIG_ENDIAN                           TRUE
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * NOTE: @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_BIG_ENDIAN
+ * @see CPU_BIG_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_LITTLE_ENDIAN                        FALSE
 
+/** @} */
+
 /**
- *  @ingroup CPUInterrupt
- *  The following defines the number of bits actually used in the
- *  interrupt field of the task mode.  How those bits map to the
- *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ * @ingroup CPUInterrupt
+ * 
+ * The following defines the number of bits actually used in the
+ * interrupt field of the task mode.  How those bits map to the
+ * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_MODES_INTERRUPT_MASK   0x00000001
 
@@ -486,83 +487,89 @@ extern "C" {
 /**
  * @defgroup CPUContext Processor Dependent Context Management
  *
- *  From the highest level viewpoint, there are 2 types of context to save.
+ * From the highest level viewpoint, there are 2 types of context to save.
  *
- *     -# Interrupt registers to save
- *     -# Task level registers to save
+ *    -# Interrupt registers to save
+ *    -# Task level registers to save
  *
- *  Since RTEMS handles integer and floating point contexts separately, this
- *  means we have the following 3 context items:
+ * Since RTEMS handles integer and floating point contexts separately, this
+ * means we have the following 3 context items:
  *
- *     -# task level context stuff::  Context_Control
- *     -# floating point task stuff:: Context_Control_fp
- *     -# special interrupt level context :: CPU_Interrupt_frame
+ *    -# task level context stuff::  Context_Control
+ *    -# floating point task stuff:: Context_Control_fp
+ *    -# special interrupt level context :: CPU_Interrupt_frame
  *
- *  On some processors, it is cost-effective to save only the callee
- *  preserved registers during a task context switch.  This means
- *  that the ISR code needs to save those registers which do not
- *  persist across function calls.  It is not mandatory to make this
- *  distinctions between the caller/callee saves registers for the
- *  purpose of minimizing context saved during task switch and on interrupts.
- *  If the cost of saving extra registers is minimal, simplicity is the
- *  choice.  Save the same context on interrupt entry as for tasks in
- *  this case.
+ * On some processors, it is cost-effective to save only the callee
+ * preserved registers during a task context switch.  This means
+ * that the ISR code needs to save those registers which do not
+ * persist across function calls.  It is not mandatory to make this
+ * distinctions between the caller/callee saves registers for the
+ * purpose of minimizing context saved during task switch and on interrupts.
+ * If the cost of saving extra registers is minimal, simplicity is the
+ * choice.  Save the same context on interrupt entry as for tasks in
+ * this case.
  *
- *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- *  care should be used in designing the context area.
+ * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ * care should be used in designing the context area.
  *
- *  On some CPUs with hardware floating point support, the Context_Control_fp
- *  structure will not be used or it simply consist of an array of a
- *  fixed number of bytes.   This is done when the floating point context
- *  is dumped by a "FP save context" type instruction and the format
- *  is not really defined by the CPU.  In this case, there is no need
- *  to figure out the exact format -- only the size.  Of course, although
- *  this is enough information for RTEMS, it is probably not enough for
- *  a debugger such as gdb.  But that is another problem.
+ * On some CPUs with hardware floating point support, the Context_Control_fp
+ * structure will not be used or it simply consist of an array of a
+ * fixed number of bytes.   This is done when the floating point context
+ * is dumped by a "FP save context" type instruction and the format
+ * is not really defined by the CPU.  In this case, there is no need
+ * to figure out the exact format -- only the size.  Of course, although
+ * this is enough information for RTEMS, it is probably not enough for
+ * a debugger such as gdb.  But that is another problem.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
+ * 
  */
+/**@{**/
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the minimal set of integer and processor state registers
- *  that must be saved during a voluntary context switch from one thread
- *  to another.
+ * @ingroup Management
+ * This defines the minimal set of integer and processor state registers
+ * that must be saved during a voluntary context switch from one thread
+ * to another.
  */
 typedef struct {
-    /** This field is a hint that a port will have a number of integer
-     *  registers that need to be saved at a context switch.
+    /**
+     * This field is a hint that a port will have a number of integer
+     * registers that need to be saved at a context switch.
      */
     uint32_t   some_integer_register;
-    /** This field is a hint that a port will have a number of system
-     *  registers that need to be saved at a context switch.
+    /**
+     * This field is a hint that a port will have a number of system
+     * registers that need to be saved at a context switch.
      */
     uint32_t   some_system_register;
 
-    /** This field is a hint that a port will have a register that
-     *  is the stack pointer.
+    /**
+     * This field is a hint that a port will have a register that
+     * is the stack pointer.
      */
     uint32_t   stack_pointer;
 } Context_Control;
 
 /**
- *  @ingroup CPUContext Management
+ * @ingroup Management
  *
- *  This macro returns the stack pointer associated with @a _context.
+ * This macro returns the stack pointer associated with @a _context.
  *
- *  @param[in] _context is the thread context area to access
+ * @param[in] _context is the thread context area to access
  *
- *  @return This method returns the stack pointer.
+ * @return This method returns the stack pointer.
  */
 #define _CPU_Context_Get_SP( _context ) \
   (_context)->stack_pointer
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the complete set of floating point registers that must
- *  be saved during any context switch from one thread to another.
+ * @ingroup Management
+ * 
+ * This defines the complete set of floating point registers that must
+ * be saved during any context switch from one thread to another.
  */
 typedef struct {
     /** FPU registers are listed here */
@@ -570,48 +577,52 @@ typedef struct {
 } Context_Control_fp;
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the set of integer and processor state registers that must
- *  be saved during an interrupt.  This set does not include any which are
- *  in @ref Context_Control.
+ * @ingroup Management
+ * 
+ * This defines the set of integer and processor state registers that must
+ * be saved during an interrupt.  This set does not include any which are
+ * in @ref Context_Control.
  */
 typedef struct {
-    /** This field is a hint that a port will have a number of integer
-     *  registers that need to be saved when an interrupt occurs or
-     *  when a context switch occurs at the end of an ISR.
+    /** 
+     * This field is a hint that a port will have a number of integer
+     * registers that need to be saved when an interrupt occurs or
+     * when a context switch occurs at the end of an ISR.
      */
     uint32_t   special_interrupt_register;
 } CPU_Interrupt_frame;
 
 /**
- *  This variable is optional.  It is used on CPUs on which it is difficult
- *  to generate an "uninitialized" FP context.  It is filled in by
- *  @ref _CPU_Initialize and copied into the task's FP context area during
- *  @ref _CPU_Context_Initialize.
+ * This variable is optional.  It is used on CPUs on which it is difficult
+ * to generate an "uninitialized" FP context.  It is filled in by
+ * @ref _CPU_Initialize and copied into the task's FP context area during
+ * @ref _CPU_Context_Initialize.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 
+/** @} */
+
 /**
- *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ * @defgroup CPUInterrupt Processor Dependent Interrupt Management
  *
- *  On some CPUs, RTEMS supports a software managed interrupt stack.
- *  This stack is allocated by the Interrupt Manager and the switch
- *  is performed in @ref _ISR_Handler.  These variables contain pointers
- *  to the lowest and highest addresses in the chunk of memory allocated
- *  for the interrupt stack.  Since it is unknown whether the stack
- *  grows up or down (in general), this give the CPU dependent
- *  code the option of picking the version it wants to use.
+ * On some CPUs, RTEMS supports a software managed interrupt stack.
+ * This stack is allocated by the Interrupt Manager and the switch
+ * is performed in @ref _ISR_Handler.  These variables contain pointers
+ * to the lowest and highest addresses in the chunk of memory allocated
+ * for the interrupt stack.  Since it is unknown whether the stack
+ * grows up or down (in general), this give the CPU dependent
+ * code the option of picking the version it wants to use.
  *
- *  @note These two variables are required if the macro
- *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ * NOTE: These two variables are required if the macro
+ *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 
 /*
@@ -625,138 +636,143 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
 /* XXX: if needed, put more variables here */
 
 /**
- *  @ingroup CPUContext
- *  The size of the floating point context area.  On some CPUs this
- *  will not be a "sizeof" because the format of the floating point
- *  area is not defined -- only the size is.  This is usually on
- *  CPUs with a "floating point save context" instruction.
+ * @ingroup CPUContext
+ * 
+ * The size of the floating point context area.  On some CPUs this
+ * will not be a "sizeof" because the format of the floating point
+ * area is not defined -- only the size is.  This is usually on
+ * CPUs with a "floating point save context" instruction.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
 
 /**
- *  Amount of extra stack (above minimum stack size) required by
- *  MPCI receive server thread.  Remember that in a multiprocessor
- *  system this thread must exist and be able to process all directives.
+ * Amount of extra stack (above minimum stack size) required by
+ * MPCI receive server thread.  Remember that in a multiprocessor
+ * system this thread must exist and be able to process all directives.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
 
 /**
- *  @ingroup CPUInterrupt
- *  This defines the number of entries in the @ref _ISR_Vector_table managed
- *  by RTEMS.
+ * @ingroup CPUInterrupt
+ * 
+ * This defines the number of entries in the @ref _ISR_Vector_table managed
+ * by RTEMS.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
 
 /**
- *  @ingroup CPUInterrupt
- *  This defines the highest interrupt vector number for this port.
+ * @ingroup CPUInterrupt
+ * 
+ * This defines the highest interrupt vector number for this port.
  */
 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
 /**
- *  @ingroup CPUInterrupt
- *  This is defined if the port has a special way to report the ISR nesting
- *  level.  Most ports maintain the variable @a _ISR_Nest_level.
+ * @ingroup CPUInterrupt
+ * 
+ * This is defined if the port has a special way to report the ISR nesting
+ * level.  Most ports maintain the variable @a _ISR_Nest_level.
  */
 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
 /**
- *  @ingroup CPUContext
- *  Should be large enough to run all RTEMS tests.  This ensures
- *  that a "reasonable" small application should not have any problems.
+ * @ingroup CPUContext
+ * 
+ * Should be large enough to run all RTEMS tests.  This ensures
+ * that a "reasonable" small application should not have any problems.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_MINIMUM_SIZE          (1024*4)
 
 /**
- *  Size of a pointer.
+ * Size of a pointer.
  *
- *  This must be an integer literal that can be used by the assembler.  This
- *  value will be used to calculate offsets of structure members.  These
- *  offsets will be used in assembler code.
+ * This must be an integer literal that can be used by the assembler.  This
+ * value will be used to calculate offsets of structure members.  These
+ * offsets will be used in assembler code.
  */
 #define CPU_SIZEOF_POINTER         4
 
 /**
- *  CPU's worst alignment requirement for data types on a byte boundary.  This
- *  alignment does not take into account the requirements for the stack.
+ * CPU's worst alignment requirement for data types on a byte boundary.  This
+ * alignment does not take into account the requirements for the stack.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALIGNMENT              8
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  heap handler.  This alignment requirement may be stricter than that
- *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
- *  common for the heap to follow the same alignment requirement as
- *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
- *  the heap, then this should be set to @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for the
+ * heap handler.  This alignment requirement may be stricter than that
+ * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
+ * common for the heap to follow the same alignment requirement as
+ * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
+ * the heap, then this should be set to @ref CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2 although it should be
- *         a multiple of 2 greater than or equal to 2.  The requirement
- *         to be a multiple of 2 is because the heap uses the least
- *         significant field of the front and back flags to indicate
- *         that a block is in use or free.  So you do not want any odd
- *         length blocks really putting length data in that bit.
+ * NOTE:  This does not have to be a power of 2 although it should be
+ *        a multiple of 2 greater than or equal to 2.  The requirement
+ *        to be a multiple of 2 is because the heap uses the least
+ *        significant field of the front and back flags to indicate
+ *        that a block is in use or free.  So you do not want any odd
+ *        length blocks really putting length data in that bit.
  *
- *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
- *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
- *         elements allocated from the heap meet all restrictions.
+ *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ *        elements allocated from the heap meet all restrictions.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for memory
- *  buffers allocated by the partition manager.  This alignment requirement
- *  may be stricter than that for the data types alignment specified by
- *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
- *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
- *  strict enough for the partition, then this should be set to
- *  @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for memory
+ * buffers allocated by the partition manager.  This alignment requirement
+ * may be stricter than that for the data types alignment specified by
+ * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
+ * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
+ * strict enough for the partition, then this should be set to
+ * @ref CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than @ref CPU_ALIGNMENT.
+ * NOTE:  This does not have to be a power of 2.  It does have to
+ *        be greater or equal to than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  stack.  This alignment requirement may be stricter than that for the
- *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
- *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
- *  set to 0.
+ * This number corresponds to the byte alignment requirement for the
+ * stack.  This alignment requirement may be stricter than that for the
+ * data types alignment specified by @ref CPU_ALIGNMENT.  If the
+ * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
+ * set to 0.
  *
- *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
+ * NOTE: This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_STACK_ALIGNMENT        0
 
@@ -765,25 +781,27 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
  */
 
 /**
- *  @ingroup CPUInterrupt
- *  Support routine to initialize the RTEMS vector table after it is allocated.
+ * @ingroup CPUInterrupt
+ * 
+ * Support routine to initialize the RTEMS vector table after it is allocated.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Initialize_vectors()
 
 /**
- *  @ingroup CPUInterrupt
- *  Disable all interrupts for an RTEMS critical section.  The previous
- *  level is returned in @a _isr_cookie.
+ * @ingroup CPUInterrupt
+ * 
+ * Disable all interrupts for an RTEMS critical section.  The previous
+ * level is returned in @a _isr_cookie.
  *
- *  @param[out] _isr_cookie will contain the previous level cookie
+ * @param[out] _isr_cookie will contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Disable( _isr_cookie ) \
   { \
@@ -791,69 +809,72 @@ SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context;
   }
 
 /**
- *  @ingroup CPUInterrupt
- *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- *  This indicates the end of an RTEMS critical section.  The parameter
- *  @a _isr_cookie is not modified.
+ * @ingroup CPUInterrupt
+ * 
+ * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ * This indicates the end of an RTEMS critical section.  The parameter
+ * @a _isr_cookie is not modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Enable( _isr_cookie )  \
   { \
   }
 
 /**
- *  @ingroup CPUInterrupt
- *  This temporarily restores the interrupt to @a _isr_cookie before immediately
- *  disabling them again.  This is used to divide long RTEMS critical
- *  sections into two or more parts.  The parameter @a _isr_cookie is not
- *  modified.
+ * @ingroup CPUInterrupt
+ * 
+ * This temporarily restores the interrupt to @a _isr_cookie before immediately
+ * disabling them again.  This is used to divide long RTEMS critical
+ * sections into two or more parts.  The parameter @a _isr_cookie is not
+ * modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Flash( _isr_cookie ) \
   { \
   }
 
 /**
- *  @ingroup CPUInterrupt
+ * @ingroup CPUInterrupt
  *
- *  This routine and @ref _CPU_ISR_Get_level
- *  Map the interrupt level in task mode onto the hardware that the CPU
- *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a generic fashion are undefined.  Someday,
- *  it would be nice if these were "mapped" by the application
- *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
- *  8 - 255 would be available for bsp/application specific meaning.
- *  This could be used to manage a programmable interrupt controller
- *  via the rtems_task_mode directive.
+ * This routine and @ref _CPU_ISR_Get_level
+ * Map the interrupt level in task mode onto the hardware that the CPU
+ * actually provides.  Currently, interrupt levels which do not
+ * map onto the CPU in a generic fashion are undefined.  Someday,
+ * it would be nice if these were "mapped" by the application
+ * via a callout.  For example, m68k has 8 levels 0 - 7, levels
+ * 8 - 255 would be available for bsp/application specific meaning.
+ * This could be used to manage a programmable interrupt controller
+ * via the rtems_task_mode directive.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_ISR_Set_level( new_level ) \
   { \
   }
 
 /**
- *  @ingroup CPUInterrupt
- *  Return the current interrupt disable level for this task in
- *  the format used by the interrupt level portion of the task mode.
+ * @ingroup CPUInterrupt
+ * 
+ * Return the current interrupt disable level for this task in
+ * the format used by the interrupt level portion of the task mode.
  *
- *  @note This routine usually must be implemented as a subroutine.
+ * NOTE: This routine usually must be implemented as a subroutine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 uint32_t   _CPU_ISR_Get_level( void );
 
@@ -863,34 +884,35 @@ uint32_t   _CPU_ISR_Get_level( void );
 
 /**
  *  @ingroup CPUContext
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
- *
- *     - setting a starting address
- *     - preparing the stack
- *     - preparing the stack and frame pointers
- *     - setting the proper interrupt level in the context
- *     - initializing the floating point context
- *
- *  This routine generally does not set any unnecessary register
- *  in the context.  The state of the "general data" registers is
- *  undefined at task start time.
- *
- *  @param[in] _the_context is the context structure to be initialized
- *  @param[in] _stack_base is the lowest physical address of this task's stack
- *  @param[in] _size is the size of this task's stack
- *  @param[in] _isr is the interrupt disable level
- *  @param[in] _entry_point is the thread's entry point.  This is
- *         always @a _Thread_Handler
- *  @param[in] _is_fp is TRUE if the thread is to be a floating
- *        point thread.  This is typically only used on CPUs where the
- *        FPU may be easily disabled by software such as on the SPARC
- *        where the PSR contains an enable FPU bit.
- *
- *  Port Specific Information:
- *
- *  XXX document implementation including references if appropriate
+ * 
+ * Initialize the context to a state suitable for starting a
+ * task after a context restore operation.  Generally, this
+ * involves:
+ *
+ *    - setting a starting address
+ *    - preparing the stack
+ *    - preparing the stack and frame pointers
+ *    - setting the proper interrupt level in the context
+ *    - initializing the floating point context
+ *
+ * This routine generally does not set any unnecessary register
+ * in the context.  The state of the "general data" registers is
+ * undefined at task start time.
+ *
+ * @param[in] _the_context is the context structure to be initialized
+ * @param[in] _stack_base is the lowest physical address of this task's stack
+ * @param[in] _size is the size of this task's stack
+ * @param[in] _isr is the interrupt disable level
+ * @param[in] _entry_point is the thread's entry point.  This is
+ *        always @a _Thread_Handler
+ * @param[in] _is_fp is TRUE if the thread is to be a floating
+ *       point thread.  This is typically only used on CPUs where the
+ *       FPU may be easily disabled by software such as on the SPARC
+ *       where the PSR contains an enable FPU bit.
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, \
                                  _isr, _entry_point, _is_fp ) \
@@ -898,65 +920,66 @@ uint32_t   _CPU_ISR_Get_level( void );
   }
 
 /**
- *  This routine is responsible for somehow restarting the currently
- *  executing task.  If you are lucky, then all that is necessary
- *  is restoring the context.  Otherwise, there will need to be
- *  a special assembly routine which does something special in this
- *  case.  For many ports, simply adding a label to the restore path
- *  of @ref _CPU_Context_switch will work.  On other ports, it may be
- *  possibly to load a few arguments and jump to the restore path. It will
- *  not work if restarting self conflicts with the stack frame
- *  assumptions of restoring a context.
+ * This routine is responsible for somehow restarting the currently
+ * executing task.  If you are lucky, then all that is necessary
+ * is restoring the context.  Otherwise, there will need to be
+ * a special assembly routine which does something special in this
+ * case.  For many ports, simply adding a label to the restore path
+ * of @ref _CPU_Context_switch will work.  On other ports, it may be
+ * possibly to load a few arguments and jump to the restore path. It will
+ * not work if restarting self conflicts with the stack frame
+ * assumptions of restoring a context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Restart_self( _the_context ) \
    _CPU_Context_restore( (_the_context) );
 
 /**
- *  @ingroup CPUContext
- *  The purpose of this macro is to allow the initial pointer into
- *  a floating point context area (used to save the floating point
- *  context) to be at an arbitrary place in the floating point
- *  context area.
- *
- *  This is necessary because some FP units are designed to have
- *  their context saved as a stack which grows into lower addresses.
- *  Other FP units can be saved by simply moving registers into offsets
- *  from the base of the context area.  Finally some FP units provide
- *  a "dump context" instruction which could fill in from high to low
- *  or low to high based on the whim of the CPU designers.
- *
- *  @param[in] _base is the lowest physical address of the floating point
- *         context area
- *  @param[in] _offset is the offset into the floating point area
+ * @ingroup CPUContext
+ * 
+ * The purpose of this macro is to allow the initial pointer into
+ * a floating point context area (used to save the floating point
+ * context) to be at an arbitrary place in the floating point
+ *context area.
  *
- *  Port Specific Information:
+ * This is necessary because some FP units are designed to have
+ * their context saved as a stack which grows into lower addresses.
+ * Other FP units can be saved by simply moving registers into offsets
+ * from the base of the context area.  Finally some FP units provide
+ * a "dump context" instruction which could fill in from high to low
+ * or low to high based on the whim of the CPU designers.
  *
- *  XXX document implementation including references if appropriate
+ * @param[in] _base is the lowest physical address of the floating point
+ *        context area
+ * @param[in] _offset is the offset into the floating point area
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Fp_start( _base, _offset ) \
    ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
 
 /**
- *  This routine initializes the FP context area passed to it to.
- *  There are a few standard ways in which to initialize the
- *  floating point context.  The code included for this macro assumes
- *  that this is a CPU in which a "initial" FP context was saved into
- *  @a _CPU_Null_fp_context and it simply copies it to the destination
- *  context passed to it.
+ * This routine initializes the FP context area passed to it to.
+ * There are a few standard ways in which to initialize the
+ * floating point context.  The code included for this macro assumes
+ * that this is a CPU in which a "initial" FP context was saved into
+ * @a _CPU_Null_fp_context and it simply copies it to the destination
+ * context passed to it.
  *
- *  Other floating point context save/restore models include:
- *    -# not doing anything, and
- *    -# putting a "null FP status word" in the correct place in the FP context.
+ * Other floating point context save/restore models include:
+ *   -# not doing anything, and
+ *   -# putting a "null FP status word" in the correct place in the FP context.
  *
- *  @param[in] _destination is the floating point context area
+ * @param[in] _destination is the floating point context area
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Initialize_fp( _destination ) \
   { \
@@ -968,13 +991,13 @@ uint32_t   _CPU_ISR_Get_level( void );
 /* Fatal Error manager macros */
 
 /**
- *  This routine copies _error into a known place -- typically a stack
- *  location or a register, optionally disables interrupts, and
- *  halts/stops the CPU.
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Fatal_halt( _error ) \
   { \
@@ -985,68 +1008,67 @@ uint32_t   _CPU_ISR_Get_level( void );
 /* Bitfield handler macros */
 
 /**
- *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
  *
- *  This set of routines are used to implement fast searches for
- *  the most important ready task.
+ * This set of routines are used to implement fast searches for
+ * the most important ready task.
+ * 
  */
+/**@{**/
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the generic bitfield
- *  manipulation implementation.
+ * This definition is set to TRUE if the port uses the generic bitfield
+ * manipulation implementation.
  */
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the data tables provided
- *  by the generic bitfield manipulation implementation.
- *  This can occur when actually using the generic bitfield manipulation
- *  implementation or when implementing the same algorithm in assembly
- *  language for improved performance.  It is unlikely that a port will use
- *  the data if it has a bitfield scan instruction.
+ * This definition is set to TRUE if the port uses the data tables provided
+ * by the generic bitfield manipulation implementation.
+ * This can occur when actually using the generic bitfield manipulation
+ * implementation or when implementing the same algorithm in assembly
+ * language for improved performance.  It is unlikely that a port will use
+ * the data if it has a bitfield scan instruction.
  */
 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This routine sets @a _output to the bit number of the first bit
- *  set in @a _value.  @a _value is of CPU dependent type
- *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
- *  wide although only the 16 least significant bits will be used.
- *
- *  There are a number of variables in using a "find first bit" type
- *  instruction.
- *
- *    -# What happens when run on a value of zero?
- *    -# Bits may be numbered from MSB to LSB or vice-versa.
- *    -# The numbering may be zero or one based.
- *    -# The "find first bit" instruction may search from MSB or LSB.
- *
- *  RTEMS guarantees that (1) will never happen so it is not a concern.
- *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
- *  @ref _CPU_Priority_bits_index.  These three form a set of routines
- *  which must logically operate together.  Bits in the _value are
- *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
- *  The basic major and minor values calculated by @ref _Priority_Major
- *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
- *  to properly range between the values returned by the "find first bit"
- *  instruction.  This makes it possible for @ref _Priority_Get_highest to
- *  calculate the major and directly index into the minor table.
- *  This mapping is necessary to ensure that 0 (a high priority major/minor)
- *  is the first bit found.
- *
- *  This entire "find first bit" and mapping process depends heavily
- *  on the manner in which a priority is broken into a major and minor
- *  components with the major being the 4 MSB of a priority and minor
- *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
- *  to the lowest priority.
- *
- *  If your CPU does not have a "find first bit" instruction, then
- *  there are ways to make do without it.  Here are a handful of ways
- *  to implement this in software:
+ * This routine sets @a _output to the bit number of the first bit
+ * set in @a _value.  @a _value is of CPU dependent type
+ * @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
+ * wide although only the 16 least significant bits will be used.
+ *
+ * There are a number of variables in using a "find first bit" type
+ * instruction.
+ *
+ *   -# What happens when run on a value of zero?
+ *   -# Bits may be numbered from MSB to LSB or vice-versa.
+ *   -# The numbering may be zero or one based.
+ *   -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ * RTEMS guarantees that (1) will never happen so it is not a concern.
+ * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ * @ref _CPU_Priority_bits_index.  These three form a set of routines
+ * which must logically operate together.  Bits in the _value are
+ * set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ * The basic major and minor values calculated by @ref _Priority_Major
+ * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ * to properly range between the values returned by the "find first bit"
+ * instruction.  This makes it possible for @ref _Priority_Get_highest to
+ * calculate the major and directly index into the minor table.
+ * This mapping is necessary to ensure that 0 (a high priority major/minor)
+ * is the first bit found.
+ *
+ * This entire "find first bit" and mapping process depends heavily
+ * on the manner in which a priority is broken into a major and minor
+ * components with the major being the 4 MSB of a priority and minor
+ * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ * to the lowest priority.
+ *
+ * If your CPU does not have a "find first bit" instruction, then
+ * there are ways to make do without it.  Here are a handful of ways
+ * to implement this in software:
  *
 @verbatim
       - a series of 16 bit test instructions
@@ -1063,15 +1085,15 @@ uint32_t   _CPU_ISR_Get_level( void );
         _number += bit_set_table[ _value ]
 @endverbatim
 
- *    where bit_set_table[ 16 ] has values which indicate the first
- *      bit set
+ *   where bit_set_table[ 16 ] has values which indicate the first
+ *     bit set
  *
- *  @param[in] _value is the value to be scanned
- *  @param[in] _output is the first bit set
+ * @param[in] _value is the value to be scanned
+ * @param[in] _output is the first bit set
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
@@ -1081,16 +1103,18 @@ uint32_t   _CPU_ISR_Get_level( void );
   }
 #endif
 
+/** @} */
+
 /* end of Bitfield handler macros */
 
 /**
- *  This routine builds the mask which corresponds to the bit fields
- *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
- *  for that routine.
+ * This routine builds the mask which corresponds to the bit fields
+ * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
+ * for that routine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1100,17 +1124,18 @@ uint32_t   _CPU_ISR_Get_level( void );
 #endif
 
 /**
- *  @ingroup CPUBitfield
- *  This routine translates the bit numbers returned by
- *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
- *  a major or minor component of a priority.  See the discussion
- *  for that routine.
+ * @ingroup CPUBitfield
+ * 
+ * This routine translates the bit numbers returned by
+ * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ * a major or minor component of a priority.  See the discussion
+ * for that routine.
  *
- *  @param[in] _priority is the major or minor number to translate
+ * @param[in] _priority is the major or minor number to translate
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1124,26 +1149,27 @@ uint32_t   _CPU_ISR_Get_level( void );
 /* functions */
 
 /**
- *  This routine performs CPU dependent initialization.
+ * This routine performs CPU dependent initialization.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Initialize(void);
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs a "raw" interrupt handler directly into the
- *  processor's vector table.
+ * @ingroup CPUInterrupt
+ * 
+ * This routine installs a "raw" interrupt handler directly into the
+ * processor's vector table.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the raw ISR handler to install
- *  @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the raw ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
@@ -1152,16 +1178,17 @@ void _CPU_ISR_install_raw_handler(
 );
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs an interrupt vector.
+ * @ingroup CPUInterrupt
+ * 
+ * This routine installs an interrupt vector.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the RTEMS ISR handler to install
- *  @param[in] old_handler is the previously installed ISR Handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the RTEMS ISR handler to install
+ * @param[in] old_handler is the previously installed ISR Handler
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_ISR_install_vector(
   uint32_t    vector,
@@ -1170,40 +1197,41 @@ void _CPU_ISR_install_vector(
 );
 
 /**
- *  @ingroup CPUInterrupt
- *  This routine installs the hardware interrupt stack pointer.
+ * @ingroup CPUInterrupt
+ * This routine installs the hardware interrupt stack pointer.
  *
- *  @note  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
- *         is TRUE.
+ * NOTE:  It need only be provided if @ref CPU_HAS_HARDWARE_INTERRUPT_STACK
+ *        is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Install_interrupt_stack( void );
 
 /**
- *  This routine is the CPU dependent IDLE thread body.
+ * This routine is the CPU dependent IDLE thread body.
  *
- *  @note  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
+ * NOTE:  It need only be provided if @ref CPU_PROVIDES_IDLE_THREAD_BODY
  *         is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void *_CPU_Thread_Idle_body( uintptr_t ignored );
 
 /**
- *  @ingroup CPUContext
- *  This routine switches from the run context to the heir context.
+ * @ingroup CPUContext
+ * 
+ * This routine switches from the run context to the heir context.
  *
- *  @param[in] run points to the context of the currently executing task
- *  @param[in] heir points to the context of the heir task
+ * @param[in] run points to the context of the currently executing task
+ * @param[in] heir points to the context of the heir task
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_switch(
   Context_Control  *run,
@@ -1211,66 +1239,69 @@ void _CPU_Context_switch(
 );
 
 /**
- *  @ingroup CPUContext
- *  This routine is generally used only to restart self in an
- *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
+ * @ingroup CPUContext
+ * 
+ * This routine is generally used only to restart self in an
+ * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
  *
- *  @param[in] new_context points to the context to be restored.
+ * @param[in] new_context points to the context to be restored.
  *
- *  @note May be unnecessary to reload some registers.
+ * NOTE: May be unnecessary to reload some registers.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_restore(
   Context_Control *new_context
 ) RTEMS_COMPILER_NO_RETURN_ATTRIBUTE;
 
 /**
- *  @ingroup CPUContext
- *  This routine saves the floating point context passed to it.
+ * @ingroup CPUContext
+ * 
+ * This routine saves the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
- *  point context area
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area
  *
- *  @return on output @a *fp_context_ptr will contain the address that
- *  should be used with @ref _CPU_Context_restore_fp to restore this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_restore_fp to restore this context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_save_fp(
   Context_Control_fp **fp_context_ptr
 );
 
 /**
- *  @ingroup CPUContext
- *  This routine restores the floating point context passed to it.
+ * @ingroup CPUContext
+ * 
+ * This routine restores the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
- *  point context area to restore
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area to restore
  *
- *  @return on output @a *fp_context_ptr will contain the address that
- *  should be used with @ref _CPU_Context_save_fp to save this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_save_fp to save this context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_restore_fp(
   Context_Control_fp **fp_context_ptr
 );
 
 /**
- *  @brief The set of registers that specifies the complete processor state.
+ * @brief The set of registers that specifies the complete processor state.
  *
- *  The CPU exception frame may be available in fatal error conditions like for
- *  example illegal opcodes, instruction fetch errors, or data access errors.
+ * The CPU exception frame may be available in fatal error conditions like for
+ * example illegal opcodes, instruction fetch errors, or data access errors.
  *
- *  @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
- *  rtems_exception_frame_print().
+ * @see rtems_fatal(), RTEMS_FATAL_SOURCE_EXCEPTION, and
+ * rtems_exception_frame_print().
  */
 typedef struct {
   uint32_t processor_state_register;
@@ -1279,39 +1310,40 @@ typedef struct {
 } CPU_Exception_frame;
 
 /**
- *  @brief Prints the exception frame via printk().
+ * @brief Prints the exception frame via printk().
  *
- *  @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
+ * @see rtems_fatal() and RTEMS_FATAL_SOURCE_EXCEPTION.
  */
 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
 
 /**
- *  @ingroup CPUEndian
- *  The following routine swaps the endian format of an unsigned int.
- *  It must be static because it is referenced indirectly.
+ * @ingroup CPUEndian
+ * 
+ * The following routine swaps the endian format of an unsigned int.
+ * It must be static because it is referenced indirectly.
  *
- *  This version will work on any processor, but if there is a better
- *  way for your CPU PLEASE use it.  The most common way to do this is to:
+ * This version will work on any processor, but if there is a better
+ * way for your CPU PLEASE use it.  The most common way to do this is to:
  *
- *     swap least significant two bytes with 16-bit rotate
- *     swap upper and lower 16-bits
- *     swap most significant two bytes with 16-bit rotate
+ *    swap least significant two bytes with 16-bit rotate
+ *    swap upper and lower 16-bits
+ *    swap most significant two bytes with 16-bit rotate
  *
- *  Some CPUs have special instructions which swap a 32-bit quantity in
- *  a single instruction (e.g. i486).  It is probably best to avoid
- *  an "endian swapping control bit" in the CPU.  One good reason is
- *  that interrupts would probably have to be disabled to ensure that
- *  an interrupt does not try to access the same "chunk" with the wrong
- *  endian.  Another good reason is that on some CPUs, the endian bit
- *  endianness for ALL fetches -- both code and data -- so the code
- *  will be fetched incorrectly.
+ * Some CPUs have special instructions which swap a 32-bit quantity in
+ * a single instruction (e.g. i486).  It is probably best to avoid
+ * an "endian swapping control bit" in the CPU.  One good reason is
+ * that interrupts would probably have to be disabled to ensure that
+ * an interrupt does not try to access the same "chunk" with the wrong
+ * endian.  Another good reason is that on some CPUs, the endian bit
+ * endianness for ALL fetches -- both code and data -- so the code
+ * will be fetched incorrectly.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 static inline uint32_t CPU_swap_u32(
   uint32_t value
@@ -1329,11 +1361,12 @@ static inline uint32_t CPU_swap_u32(
 }
 
 /**
- *  @ingroup CPUEndian
- *  This routine swaps a 16 bir quantity.
+ * @ingroup CPUEndian
+ * 
+ * This routine swaps a 16 bir quantity.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  */
 #define CPU_swap_u16( value ) \
   (((value&0xff) << 8) | ((value >> 8)&0xff))
diff --git a/cpukit/score/cpu/no_cpu/rtems/score/cpu_asm.h b/cpukit/score/cpu/no_cpu/rtems/score/cpu_asm.h
index e3797a93f9..94dfdc11e8 100644
--- a/cpukit/score/cpu/no_cpu/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/no_cpu/rtems/score/cpu_asm.h
@@ -1,11 +1,15 @@
 /**
- * @file rtems/score/cpu_asm.h
+ * @file
+ * 
+ * @brief No-CPU Assembly File
+ * 
+ * Very loose template for an include file for the cpu_asm.? file
+ * if it is implemented as a ".S" file (preprocessed by cpp) instead
+ * of a ".s" file (preprocessed by gm4 or gasp).
  */
 
 /*
- *  Very loose template for an include file for the cpu_asm.? file
- *  if it is implemented as a ".S" file (preprocessed by cpp) instead
- *  of a ".s" file (preprocessed by gm4 or gasp).
+ *  
  *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
diff --git a/cpukit/score/cpu/no_cpu/rtems/score/types.h b/cpukit/score/cpu/no_cpu/rtems/score/types.h
index 74240aa1e4..81ae8ccf15 100644
--- a/cpukit/score/cpu/no_cpu/rtems/score/types.h
+++ b/cpukit/score/cpu/no_cpu/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ * 
+ * @brief No-CPU Type Definitions
+ * 
+ * This include file contains type definitions pertaining to the Intel
+ * no_cpu processor family. 
  */
 
 /*
- *  This include file contains type definitions pertaining to the Intel
- *  no_cpu processor family.
- *
  *  COPYRIGHT (c) 1989-2006.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/powerpc/rtems/asm.h b/cpukit/score/cpu/powerpc/rtems/asm.h
index 594e3232bb..62571ad4eb 100644
--- a/cpukit/score/cpu/powerpc/rtems/asm.h
+++ b/cpukit/score/cpu/powerpc/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
+ * 
+ * @brief Address the Problems Caused by Incompatible Flavor of 
+ * Assemblers and Toolsets
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ * 
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
diff --git a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
index 7090203a02..a64291ed15 100644
--- a/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
+++ b/cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
@@ -1,6 +1,12 @@
-/*
+/**
+ * @file
+ * 
+ * @brief PowerPc MSR and Registers Access Definitions
+ * 
  * This file contains some powerpc MSR and registers access definitions.
- *
+ */
+
+/*
  * COPYRIGHT (C) 1999  Eric Valette (valette@crf.canon.fr)
  *                     Canon Centre Recherche France.
  *
diff --git a/cpukit/score/cpu/powerpc/rtems/score/cpu.h b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
index e776f3ccf2..37d8c34bb9 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/cpu.h
@@ -1,5 +1,7 @@
 /**
- * @file rtems/score/cpu.h
+ * @file
+ * 
+ * @brief PowerPC CPU Department Source
  */
 
 /*
diff --git a/cpukit/score/cpu/powerpc/rtems/score/powerpc.h b/cpukit/score/cpu/powerpc/rtems/score/powerpc.h
index bee0695000..691c81ce83 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/powerpc.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/powerpc.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/powerpc.h
+ * @file
+ * 
+ * @brief IBM/Motorola Power Pc Definitions
+ * 
+ * This file contains definitions for the IBM/Motorola PowerPC
+ * family members.
  */
 
 /*
- *  This file contains definitions for the IBM/Motorola PowerPC
- *  family members.
- *
  *  Author:	Andrew Bray <andy@i-cubed.co.uk>
  *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
diff --git a/cpukit/score/cpu/powerpc/rtems/score/types.h b/cpukit/score/cpu/powerpc/rtems/score/types.h
index 1f61bfe6ef..0b5f16e6b9 100644
--- a/cpukit/score/cpu/powerpc/rtems/score/types.h
+++ b/cpukit/score/cpu/powerpc/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ * 
+ * @brief PowerPC CPU Type Definitions
+ * 
+ * This include file contains type definitions pertaining to the PowerPC
+ * processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the PowerPC
- *  processor family.
- *
  *  Author:	Andrew Bray <andy@i-cubed.co.uk>
  *
  *  COPYRIGHT (c) 1995 by i-cubed ltd.
diff --git a/cpukit/score/cpu/sh/rtems/asm.h b/cpukit/score/cpu/sh/rtems/asm.h
index b2cbce6020..d7ad694365 100644
--- a/cpukit/score/cpu/sh/rtems/asm.h
+++ b/cpukit/score/cpu/sh/rtems/asm.h
@@ -1,20 +1,23 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * @note The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
  *           Bernd Becker (becker@faw.uni-ulm.de)
  *
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
diff --git a/cpukit/score/cpu/sh/rtems/score/sh.h b/cpukit/score/cpu/sh/rtems/score/sh.h
index 507a812bc7..e7ab9c0850 100644
--- a/cpukit/score/cpu/sh/rtems/score/sh.h
+++ b/cpukit/score/cpu/sh/rtems/score/sh.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/sh.h
+ * @file
+ *
+ * @brief Hitachi SH CPU Department Source
+ *
+ * This include file contains information pertaining to the Hitachi SH
+ * processor.
  */
 
 /*
- *  This include file contains information pertaining to the Hitachi SH
- *  processor.
- *
  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
  *           Bernd Becker (becker@faw.uni-ulm.de)
  *
diff --git a/cpukit/score/cpu/sh/rtems/score/sh_io.h b/cpukit/score/cpu/sh/rtems/score/sh_io.h
index 6cb1ffcb0f..fcbdbcee42 100644
--- a/cpukit/score/cpu/sh/rtems/score/sh_io.h
+++ b/cpukit/score/cpu/sh/rtems/score/sh_io.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/sh_io.h
+ * @file
+ *
+ * @brief Macros to Access Memory Mapped Devices on the SH7000-Architecture
+ *
+ * These are some macros to access memory mapped devices
+ * on the SH7000-architecture.
  */
 
 /*
- * These are some macros to access memory mapped devices
- * on the SH7000-architecture.
- *
  * Inspired from the linux kernel's include/asm/io.h
  *
  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
diff --git a/cpukit/score/cpu/sh/rtems/score/types.h b/cpukit/score/cpu/sh/rtems/score/types.h
index 8f0b06c79c..5943a42bc9 100644
--- a/cpukit/score/cpu/sh/rtems/score/types.h
+++ b/cpukit/score/cpu/sh/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief Hitachi SH CPU Type Definitions
+ *
+ * This include file contains information pertaining to the Hitachi SH
+ * processor.
  */
 
 /*
- *  This include file contains information pertaining to the Hitachi SH
- *  processor.
- *
  *  Authors: Ralf Corsepius (corsepiu@faw.uni-ulm.de) and
  *           Bernd Becker (becker@faw.uni-ulm.de)
  *
diff --git a/cpukit/score/cpu/sparc/rtems/asm.h b/cpukit/score/cpu/sparc/rtems/asm.h
index 530197eeb8..a2b11f63fc 100644
--- a/cpukit/score/cpu/sparc/rtems/asm.h
+++ b/cpukit/score/cpu/sparc/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
diff --git a/cpukit/score/cpu/sparc/rtems/score/cpu.h b/cpukit/score/cpu/sparc/rtems/score/cpu.h
index 6e88b9efcb..610235568b 100644
--- a/cpukit/score/cpu/sparc/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc/rtems/score/cpu.h
@@ -1,8 +1,10 @@
 /**
- *  @file rtems/score/cpu.h
+ * @file
  *
- *  This include file contains information pertaining to the port of
- *  the executive to the SPARC processor.
+ * @brief SPARC CPU Department Source
+ *
+ * This include file contains information pertaining to the port of
+ * the executive to the SPARC processor.
  */
 
 /*
@@ -27,94 +29,94 @@ extern "C" {
 /* conditional compilation parameters */
 
 /**
- *  Should the calls to _Thread_Enable_dispatch be inlined?
+ * Should the calls to _Thread_Enable_dispatch be inlined?
  *
- *  - If TRUE, then they are inlined.
- *  - If FALSE, then a subroutine call is made.
+ * - If TRUE, then they are inlined.
+ * - If FALSE, then a subroutine call is made.
  *
- *  On this port, it is faster to inline _Thread_Enable_dispatch.
+ * On this port, it is faster to inline _Thread_Enable_dispatch.
  */
 #define CPU_INLINE_ENABLE_DISPATCH       TRUE
 
 /**
- *  Should the body of the search loops in _Thread_queue_Enqueue_priority
- *  be unrolled one time?  In unrolled each iteration of the loop examines
- *  two "nodes" on the chain being searched.  Otherwise, only one node
- *  is examined per iteration.
+ * Should the body of the search loops in _Thread_queue_Enqueue_priority
+ * be unrolled one time?  In unrolled each iteration of the loop examines
+ * two "nodes" on the chain being searched.  Otherwise, only one node
+ * is examined per iteration.
  *
- *  - If TRUE, then the loops are unrolled.
- *  - If FALSE, then the loops are not unrolled.
+ * - If TRUE, then the loops are unrolled.
+ * - If FALSE, then the loops are not unrolled.
  *
- *  This parameter could go either way on the SPARC.  The interrupt flash
- *  code is relatively lengthy given the requirements for nops following
- *  writes to the psr.  But if the clock speed were high enough, this would
- *  not represent a great deal of time.
+ * This parameter could go either way on the SPARC.  The interrupt flash
+ * code is relatively lengthy given the requirements for nops following
+ * writes to the psr.  But if the clock speed were high enough, this would
+ * not represent a great deal of time.
  */
 #define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
 
 /**
- *  Does the executive manage a dedicated interrupt stack in software?
+ * Does the executive manage a dedicated interrupt stack in software?
  *
- *  If TRUE, then a stack is allocated in _ISR_Handler_initialization.
- *  If FALSE, nothing is done.
+ * If TRUE, then a stack is allocated in _ISR_Handler_initialization.
+ * If FALSE, nothing is done.
  *
- *  The SPARC does not have a dedicated HW interrupt stack and one has
- *  been implemented in SW.
+ * The SPARC does not have a dedicated HW interrupt stack and one has
+ * been implemented in SW.
  */
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK   TRUE
 
 /**
- *  Does the CPU follow the simple vectored interrupt model?
+ * Does the CPU follow the simple vectored interrupt model?
  *
- *  - If TRUE, then RTEMS allocates the vector table it internally manages.
- *  - If FALSE, then the BSP is assumed to allocate and manage the vector
- *    table
+ * - If TRUE, then RTEMS allocates the vector table it internally manages.
+ * - If FALSE, then the BSP is assumed to allocate and manage the vector
+ *   table
  *
- *  THe SPARC is a simple vectored architecture.  Usually there is no
- *  PIC and the CPU directly vectors the interrupts.
+ * THe SPARC is a simple vectored architecture.  Usually there is no
+ * PIC and the CPU directly vectors the interrupts.
  */
 #define CPU_SIMPLE_VECTORED_INTERRUPTS TRUE
 
-/** 
- *  Does this CPU have hardware support for a dedicated interrupt stack?
+/**
+ * Does this CPU have hardware support for a dedicated interrupt stack?
  *
- *  - If TRUE, then it must be installed during initialization.
- *  - If FALSE, then no installation is performed.
+ * - If TRUE, then it must be installed during initialization.
+ * - If FALSE, then no installation is performed.
  *
- *  The SPARC does not have a dedicated HW interrupt stack.
+ * The SPARC does not have a dedicated HW interrupt stack.
  */
 #define CPU_HAS_HARDWARE_INTERRUPT_STACK  FALSE
 
 /**
- *  Do we allocate a dedicated interrupt stack in the Interrupt Manager?
+ * Do we allocate a dedicated interrupt stack in the Interrupt Manager?
  *
- *  - If TRUE, then the memory is allocated during initialization.
- *  - If FALSE, then the memory is allocated during initialization.
+ * - If TRUE, then the memory is allocated during initialization.
+ * - If FALSE, then the memory is allocated during initialization.
  *
- *  The SPARC does not have hardware support for switching to a 
- *  dedicated interrupt stack.  The port includes support for doing this
- *  in software.
+ * The SPARC does not have hardware support for switching to a
+ * dedicated interrupt stack.  The port includes support for doing this
+ * in software.
  *
  */
 #define CPU_ALLOCATE_INTERRUPT_STACK      TRUE
 
 /**
- *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector
- *  number (0)?
+ * Does the RTEMS invoke the user's ISR with the vector number and
+ * a pointer to the saved interrupt frame (1) or just the vector
+ * number (0)?
  *
- *  The SPARC port does not pass an Interrupt Stack Frame pointer to
- *  interrupt handlers.
+ * The SPARC port does not pass an Interrupt Stack Frame pointer to
+ * interrupt handlers.
  */
 #define CPU_ISR_PASSES_FRAME_POINTER 0
 
 /**
- *  Does the CPU have hardware floating point?
+ * Does the CPU have hardware floating point?
  *
- *  - If TRUE, then the FLOATING_POINT task attribute is supported.
- *  - If FALSE, then the FLOATING_POINT task attribute is ignored.
+ * - If TRUE, then the FLOATING_POINT task attribute is supported.
+ * - If FALSE, then the FLOATING_POINT task attribute is ignored.
  *
- *  This is set based upon the multilib settings.
+ * This is set based upon the multilib settings.
  */
 #if ( SPARC_HAS_FPU == 1 )
   #define CPU_HARDWARE_FP     TRUE
@@ -123,123 +125,123 @@ extern "C" {
 #endif
 
 /**
- *  The SPARC GCC port does not have a software floating point library
- *  that requires RTEMS assistance.
+ * The SPARC GCC port does not have a software floating point library
+ * that requires RTEMS assistance.
  */
 #define CPU_SOFTWARE_FP     FALSE
 
 /**
- *  Are all tasks FLOATING_POINT tasks implicitly?
+ * Are all tasks FLOATING_POINT tasks implicitly?
  *
- *  - If TRUE, then the FLOATING_POINT task attribute is assumed.
- *  - If FALSE, then the FLOATING_POINT task attribute is followed.
+ * - If TRUE, then the FLOATING_POINT task attribute is assumed.
+ * - If FALSE, then the FLOATING_POINT task attribute is followed.
  *
- *  The SPARC GCC port does not implicitly use floating point registers.
+ * The SPARC GCC port does not implicitly use floating point registers.
  */
 #define CPU_ALL_TASKS_ARE_FP     FALSE
 
 /**
- *  Should the IDLE task have a floating point context?
+ * Should the IDLE task have a floating point context?
  *
- *  - If TRUE, then the IDLE task is created as a FLOATING_POINT task
- *    and it has a floating point context which is switched in and out.
- *  - If FALSE, then the IDLE task does not have a floating point context.
+ * - If TRUE, then the IDLE task is created as a FLOATING_POINT task
+ *   and it has a floating point context which is switched in and out.
+ * - If FALSE, then the IDLE task does not have a floating point context.
  *
- *  The IDLE task does not have to be floating point on the SPARC.
+ * The IDLE task does not have to be floating point on the SPARC.
  */
 #define CPU_IDLE_TASK_IS_FP      FALSE
 
 /**
- *  Should the saving of the floating point registers be deferred
- *  until a context switch is made to another different floating point
- *  task?
+ * Should the saving of the floating point registers be deferred
+ * until a context switch is made to another different floating point
+ * task?
  *
- *  - If TRUE, then the floating point context will not be stored until
- *  necessary.  It will remain in the floating point registers and not
- *  disturned until another floating point task is switched to.
+ * - If TRUE, then the floating point context will not be stored until
+ * necessary.  It will remain in the floating point registers and not
+ * disturned until another floating point task is switched to.
  *
- *  - If FALSE, then the floating point context is saved when a floating
- *  point task is switched out and restored when the next floating point
- *  task is restored.  The state of the floating point registers between
- *  those two operations is not specified.
+ * - If FALSE, then the floating point context is saved when a floating
+ * point task is switched out and restored when the next floating point
+ * task is restored.  The state of the floating point registers between
+ * those two operations is not specified.
  *
- *  On the SPARC, we can disable the FPU for integer only tasks so
- *  it is safe to defer floating point context switches.
+ * On the SPARC, we can disable the FPU for integer only tasks so
+ * it is safe to defer floating point context switches.
  */
 #define CPU_USE_DEFERRED_FP_SWITCH       TRUE
 
 /**
- *  Does this port provide a CPU dependent IDLE task implementation?
+ * Does this port provide a CPU dependent IDLE task implementation?
  *
- *  - If TRUE, then the routine _CPU_Thread_Idle_body
- *  must be provided and is the default IDLE thread body instead of
- *  _CPU_Thread_Idle_body.
+ * - If TRUE, then the routine _CPU_Thread_Idle_body
+ * must be provided and is the default IDLE thread body instead of
+ * _CPU_Thread_Idle_body.
  *
- *  - If FALSE, then use the generic IDLE thread body if the BSP does
- *  not provide one.
+ * - If FALSE, then use the generic IDLE thread body if the BSP does
+ * not provide one.
  *
- *  The SPARC architecture does not have a low power or halt instruction.
- *  It is left to the BSP and/or CPU specific code to provide an IDLE
- *  thread body which is aware of low power modes.
+ * The SPARC architecture does not have a low power or halt instruction.
+ * It is left to the BSP and/or CPU specific code to provide an IDLE
+ * thread body which is aware of low power modes.
  */
 #define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
 
 /**
- *  Does the stack grow up (toward higher addresses) or down
- *  (toward lower addresses)?
+ * Does the stack grow up (toward higher addresses) or down
+ * (toward lower addresses)?
  *
- *  - If TRUE, then the grows upward.
- *  - If FALSE, then the grows toward smaller addresses.
+ * - If TRUE, then the grows upward.
+ * - If FALSE, then the grows toward smaller addresses.
  *
- *  The stack grows to lower addresses on the SPARC.
+ * The stack grows to lower addresses on the SPARC.
  */
 #define CPU_STACK_GROWS_UP               FALSE
 
 /**
- *  The following is the variable attribute used to force alignment
- *  of critical data structures.  On some processors it may make
- *  sense to have these aligned on tighter boundaries than
- *  the minimum requirements of the compiler in order to have as
- *  much of the critical data area as possible in a cache line.
+ * The following is the variable attribute used to force alignment
+ * of critical data structures.  On some processors it may make
+ * sense to have these aligned on tighter boundaries than
+ * the minimum requirements of the compiler in order to have as
+ * much of the critical data area as possible in a cache line.
  *
- *  The SPARC does not appear to have particularly strict alignment
- *  requirements.  This value was chosen to take advantages of caches.
+ * The SPARC does not appear to have particularly strict alignment
+ * requirements.  This value was chosen to take advantages of caches.
  */
 #define CPU_STRUCTURE_ALIGNMENT          __attribute__ ((aligned (16)))
 
 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
 
 /**
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  The SPARC is big endian.
+ * The SPARC is big endian.
  */
 #define CPU_BIG_ENDIAN                           TRUE
 
 /**
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  The SPARC is NOT little endian.
+ * The SPARC is NOT little endian.
  */
 #define CPU_LITTLE_ENDIAN                        FALSE
 
 /**
- *  The following defines the number of bits actually used in the
- *  interrupt field of the task mode.  How those bits map to the
- *  CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
+ * The following defines the number of bits actually used in the
+ * interrupt field of the task mode.  How those bits map to the
+ * CPU interrupt levels is defined by the routine _CPU_ISR_Set_level().
  *
- *  The SPARC has 16 interrupt levels in the PIL field of the PSR.
+ * The SPARC has 16 interrupt levels in the PIL field of the PSR.
  */
 #define CPU_MODES_INTERRUPT_MASK   0x0000000F
 
 #ifndef ASM
 /**
- *  This structure represents the organization of the minimum stack frame
- *  for the SPARC.  More framing information is required in certain situaions
- *  such as when there are a large number of out parameters or when the callee
- *  must save floating point registers.
+ * This structure represents the organization of the minimum stack frame
+ * for the SPARC.  More framing information is required in certain situaions
+ * such as when there are a large number of out parameters or when the callee
+ * must save floating point registers.
  */
 typedef struct {
   /** This is the offset of the l0 register. */
@@ -278,8 +280,8 @@ typedef struct {
   void       *structure_return_address;
 
   /*
-   *  The following are for the callee to save the register arguments in
-   *  should this be necessary.
+   * The following are for the callee to save the register arguments in
+   * should this be necessary.
    */
   /** This is the offset of the register for saved argument 0. */
   uint32_t    saved_arg0;
@@ -354,35 +356,36 @@ typedef struct {
 /**
  * @defgroup Contexts SPARC Context Structures
  *
- *  Generally there are 2 types of context to save.
- *     + Interrupt registers to save
- *     + Task level registers to save
+ * @ingroup Score
+ *
+ * Generally there are 2 types of context to save.
+ *    + Interrupt registers to save
+ *    + Task level registers to save
  *
- *  This means we have the following 3 context items:
- *     + task level context stuff::  Context_Control
- *     + floating point task stuff:: Context_Control_fp
- *     + special interrupt level context :: Context_Control_interrupt
+ * This means we have the following 3 context items:
+ *    + task level context stuff::  Context_Control
+ *    + floating point task stuff:: Context_Control_fp
+ *    + special interrupt level context :: Context_Control_interrupt
  *
- *  On the SPARC, we are relatively conservative in that we save most
- *  of the CPU state in the context area.  The ET (enable trap) bit and
- *  the CWP (current window pointer) fields of the PSR are considered
- *  system wide resources and are not maintained on a per-thread basis.
+ * On the SPARC, we are relatively conservative in that we save most
+ * of the CPU state in the context area.  The ET (enable trap) bit and
+ * the CWP (current window pointer) fields of the PSR are considered
+ * system wide resources and are not maintained on a per-thread basis.
  */
+/**@{**/
 
 #ifndef ASM
 /**
- *  @brief SPARC Basic Context
+ * @brief SPARC basic context.
  *
- *  @ingroup Contexts
- *
- *  This structure defines the basic integer and processor state context
- *  for the SPARC architecture.
+ * This structure defines the basic integer and processor state context
+ * for the SPARC architecture.
  */
 typedef struct {
   /**
-   *  Using a double g0_g1 will put everything in this structure on a
-   *  double word boundary which allows us to use double word loads
-   *  and stores safely in the context switch.
+   * Using a double g0_g1 will put everything in this structure on a
+   * double word boundary which allows us to use double word loads
+   * and stores safely in the context switch.
    */
   double     g0_g1;
   /** This will contain the contents of the g2 register. */
@@ -460,9 +463,9 @@ typedef struct {
 } Context_Control;
 
 /**
- *  This macro provides a CPU independent way for RTEMS to access the
- *  stack pointer in a context structure. The actual name and offset is
- *  CPU architecture dependent.
+ * This macro provides a CPU independent way for RTEMS to access the
+ * stack pointer in a context structure. The actual name and offset is
+ * CPU architecture dependent.
  */
 #define _CPU_Context_Get_SP( _context ) \
   (_context)->o6_sp
@@ -551,11 +554,9 @@ typedef struct {
 
 #ifndef ASM
 /**
- *  @brief SPARC Basic Context
- *
- *  @ingroup Contexts
+ * @brief SPARC basic context.
  *
- *  This structure defines floating point context area.
+ * This structure defines floating point context area.
  */
 typedef struct {
   /** This will contain the contents of the f0 and f1 register. */
@@ -640,13 +641,15 @@ typedef struct {
 
 #ifndef ASM
 
+/** @} */
+
 /**
- *  @brief Interrupt Stack Frame (ISF)
+ * @brief Interrupt stack frame (ISF).
  *
- *  Context saved on stack for an interrupt.
+ * Context saved on stack for an interrupt.
  *
- *  @note The PSR, PC, and NPC are only saved in this structure for the
- *        benefit of the user's handler.
+ * NOTE: The PSR, PC, and NPC are only saved in this structure for the
+ *       benefit of the user's handler.
  */
 typedef struct {
   /** On an interrupt, we must save the minimum stack frame. */
@@ -748,27 +751,27 @@ typedef struct {
 
 #ifndef ASM
 /**
- *  This variable is contains the initialize context for the FP unit.
- *  It is filled in by _CPU_Initialize and copied into the task's FP
- *  context area during _CPU_Context_Initialize.
+ * This variable is contains the initialize context for the FP unit.
+ * It is filled in by _CPU_Initialize and copied into the task's FP
+ * context area during _CPU_Context_Initialize.
  */
 SCORE_EXTERN Context_Control_fp  _CPU_Null_fp_context CPU_STRUCTURE_ALIGNMENT;
 
 /**
- *  This flag is context switched with each thread.  It indicates
- *  that THIS thread has an _ISR_Dispatch stack frame on its stack.
- *  By using this flag, we can avoid nesting more interrupt dispatching
- *  attempts on a previously interrupted thread's stack.
+ * This flag is context switched with each thread.  It indicates
+ * that THIS thread has an _ISR_Dispatch stack frame on its stack.
+ * By using this flag, we can avoid nesting more interrupt dispatching
+ * attempts on a previously interrupted thread's stack.
  */
 SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
 
 /**
- *  The following type defines an entry in the SPARC's trap table.
+ * The following type defines an entry in the SPARC's trap table.
  *
- *  @note The instructions chosen are RTEMS dependent although one is
- *        obligated to use two of the four instructions to perform a
- *        long jump.  The other instructions load one register with the
- *        trap type (a.k.a. vector) and another with the psr.
+ * NOTE: The instructions chosen are RTEMS dependent although one is
+ *       obligated to use two of the four instructions to perform a
+ *       long jump.  The other instructions load one register with the
+ *       trap type (a.k.a. vector) and another with the psr.
  */
 typedef struct {
   /** This will contain a "mov %psr, %l0" instruction. */
@@ -782,52 +785,52 @@ typedef struct {
 } CPU_Trap_table_entry;
 
 /**
- *  This is the set of opcodes for the instructions loaded into a trap
- *  table entry.  The routine which installs a handler is responsible
- *  for filling in the fields for the _handler address and the _vector
- *  trap type.
+ * This is the set of opcodes for the instructions loaded into a trap
+ * table entry.  The routine which installs a handler is responsible
+ * for filling in the fields for the _handler address and the _vector
+ * trap type.
  *
- *  The constants following this structure are masks for the fields which
- *  must be filled in when the handler is installed.
+ * The constants following this structure are masks for the fields which
+ * must be filled in when the handler is installed.
  */
 extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
 
 /**
- *  The size of the floating point context area.
+ * The size of the floating point context area.
  */
 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
 
 #endif
 
 /**
- *  Amount of extra stack (above minimum stack size) required by
- *  MPCI receive server thread.  Remember that in a multiprocessor
- *  system this thread must exist and be able to process all directives.
+ * Amount of extra stack (above minimum stack size) required by
+ * MPCI receive server thread.  Remember that in a multiprocessor
+ * system this thread must exist and be able to process all directives.
  */
 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 1024
 
 /**
- *  This defines the number of entries in the ISR_Vector_table managed
- *  by the executive.
- *
- *  On the SPARC, there are really only 256 vectors.  However, the executive
- *  has no easy, fast, reliable way to determine which traps are synchronous
- *  and which are asynchronous.  By default, synchronous traps return to the
- *  instruction which caused the interrupt.  So if you install a software
- *  trap handler as an executive interrupt handler (which is desirable since
- *  RTEMS takes care of window and register issues), then the executive needs
- *  to know that the return address is to the trap rather than the instruction
- *  following the trap.
- *
- *  So vectors 0 through 255 are treated as regular asynchronous traps which
- *  provide the "correct" return address.  Vectors 256 through 512 are assumed
- *  by the executive to be synchronous and to require that the return address
- *  be fudged.
- *
- *  If you use this mechanism to install a trap handler which must reexecute
- *  the instruction which caused the trap, then it should be installed as
- *  an asynchronous trap.  This will avoid the executive changing the return
- *  address.
+ * This defines the number of entries in the ISR_Vector_table managed
+ * by the executive.
+ *
+ * On the SPARC, there are really only 256 vectors.  However, the executive
+ * has no easy, fast, reliable way to determine which traps are synchronous
+ * and which are asynchronous.  By default, synchronous traps return to the
+ * instruction which caused the interrupt.  So if you install a software
+ * trap handler as an executive interrupt handler (which is desirable since
+ * RTEMS takes care of window and register issues), then the executive needs
+ * to know that the return address is to the trap rather than the instruction
+ * following the trap.
+ *
+ * So vectors 0 through 255 are treated as regular asynchronous traps which
+ * provide the "correct" return address.  Vectors 256 through 512 are assumed
+ * by the executive to be synchronous and to require that the return address
+ * be fudged.
+ *
+ * If you use this mechanism to install a trap handler which must reexecute
+ * the instruction which caused the trap, then it should be installed as
+ * an asynchronous trap.  This will avoid the executive changing the return
+ * address.
  */
 #define CPU_INTERRUPT_NUMBER_OF_VECTORS     256
 
@@ -838,18 +841,18 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER 511
 
 /**
- *  This is the bit step in a vector number to indicate it is being installed
- *  as a synchronous trap.
+ * This is the bit step in a vector number to indicate it is being installed
+ * as a synchronous trap.
  */
 #define SPARC_SYNCHRONOUS_TRAP_BIT_MASK     0x100
 
 /**
- *  This macro indicates that @a _trap as an asynchronous trap.
+ * This macro indicates that @a _trap as an asynchronous trap.
  */
 #define SPARC_ASYNCHRONOUS_TRAP( _trap )    (_trap)
 
 /**
- *  This macro indicates that @a _trap as a synchronous trap.
+ * This macro indicates that @a _trap as a synchronous trap.
  */
 #define SPARC_SYNCHRONOUS_TRAP( _trap )     ((_trap) + 256 )
 
@@ -859,69 +862,69 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
 #define SPARC_REAL_TRAP_NUMBER( _trap )     ((_trap) % 256)
 
 /**
- *  This is defined if the port has a special way to report the ISR nesting
- *  level.  Most ports maintain the variable _ISR_Nest_level.
+ * This is defined if the port has a special way to report the ISR nesting
+ * level.  Most ports maintain the variable _ISR_Nest_level.
  */
 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
 /**
- *  Should be large enough to run all tests.  This ensures
- *  that a "reasonable" small application should not have any problems.
+ * Should be large enough to run all tests.  This ensures
+ * that a "reasonable" small application should not have any problems.
  *
- *  This appears to be a fairly generous number for the SPARC since
- *  represents a call depth of about 20 routines based on the minimum
- *  stack frame.
+ * This appears to be a fairly generous number for the SPARC since
+ * represents a call depth of about 20 routines based on the minimum
+ * stack frame.
  */
 #define CPU_STACK_MINIMUM_SIZE  (1024*4)
 
 #define CPU_SIZEOF_POINTER 4
 
 /**
- *  CPU's worst alignment requirement for data types on a byte boundary.  This
- *  alignment does not take into account the requirements for the stack.
+ * CPU's worst alignment requirement for data types on a byte boundary.  This
+ * alignment does not take into account the requirements for the stack.
  *
- *  On the SPARC, this is required for double word loads and stores.
+ * On the SPARC, this is required for double word loads and stores.
  */
 #define CPU_ALIGNMENT      8
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  heap handler.  This alignment requirement may be stricter than that
- *  for the data types alignment specified by CPU_ALIGNMENT.  It is
- *  common for the heap to follow the same alignment requirement as
- *  CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
- *  then this should be set to CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for the
+ * heap handler.  This alignment requirement may be stricter than that
+ * for the data types alignment specified by CPU_ALIGNMENT.  It is
+ * common for the heap to follow the same alignment requirement as
+ * CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict enough for the heap,
+ * then this should be set to CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than CPU_ALIGNMENT.
+ * NOTE:  This does not have to be a power of 2.  It does have to
+ *        be greater or equal to than CPU_ALIGNMENT.
  */
 #define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for memory
- *  buffers allocated by the partition manager.  This alignment requirement
- *  may be stricter than that for the data types alignment specified by
- *  CPU_ALIGNMENT.  It is common for the partition to follow the same
- *  alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
- *  enough for the partition, then this should be set to CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for memory
+ * buffers allocated by the partition manager.  This alignment requirement
+ * may be stricter than that for the data types alignment specified by
+ * CPU_ALIGNMENT.  It is common for the partition to follow the same
+ * alignment requirement as CPU_ALIGNMENT.  If the CPU_ALIGNMENT is strict
+ * enough for the partition, then this should be set to CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than CPU_ALIGNMENT.
+ * NOTE:  This does not have to be a power of 2.  It does have to
+ *        be greater or equal to than CPU_ALIGNMENT.
  */
 #define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  stack.  This alignment requirement may be stricter than that for the
- *  data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
- *  is strict enough for the stack, then this should be set to 0.
+ * This number corresponds to the byte alignment requirement for the
+ * stack.  This alignment requirement may be stricter than that for the
+ * data types alignment specified by CPU_ALIGNMENT.  If the CPU_ALIGNMENT
+ * is strict enough for the stack, then this should be set to 0.
  *
- *  @note  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
+ * NOTE:  This must be a power of 2 either 0 or greater than CPU_ALIGNMENT.
  *
- *  The alignment restrictions for the SPARC are not that strict but this
- *  should unsure that the stack is always sufficiently alignment that the
- *  window overflow, underflow, and flush routines can use double word loads
- *  and stores.
+ * The alignment restrictions for the SPARC are not that strict but this
+ * should unsure that the stack is always sufficiently alignment that the
+ * window overflow, underflow, and flush routines can use double word loads
+ * and stores.
  */
 #define CPU_STACK_ALIGNMENT        16
 
@@ -932,49 +935,49 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
  */
 
 /**
- *  Support routine to initialize the RTEMS vector table after it is allocated.
+ * Support routine to initialize the RTEMS vector table after it is allocated.
  */
 #define _CPU_Initialize_vectors()
 
 /**
- *  Disable all interrupts for a critical section.  The previous
- *  level is returned in _level.
+ * Disable all interrupts for a critical section.  The previous
+ * level is returned in _level.
  */
 #define _CPU_ISR_Disable( _level ) \
   (_level) = sparc_disable_interrupts()
 
 /**
- *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- *  This indicates the end of a critical section.  The parameter
- *  _level is not modified.
+ * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ * This indicates the end of a critical section.  The parameter
+ * _level is not modified.
  */
 #define _CPU_ISR_Enable( _level ) \
   sparc_enable_interrupts( _level )
 
 /**
- *  This temporarily restores the interrupt to _level before immediately
- *  disabling them again.  This is used to divide long critical
- *  sections into two or more parts.  The parameter _level is not
- *  modified.
+ * This temporarily restores the interrupt to _level before immediately
+ * disabling them again.  This is used to divide long critical
+ * sections into two or more parts.  The parameter _level is not
+ * modified.
  */
 #define _CPU_ISR_Flash( _level ) \
   sparc_flash_interrupts( _level )
 
 /**
- *  Map interrupt level in task mode onto the hardware that the CPU
- *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a straight fashion are undefined.
+ * Map interrupt level in task mode onto the hardware that the CPU
+ * actually provides.  Currently, interrupt levels which do not
+ * map onto the CPU in a straight fashion are undefined.
  */
 #define _CPU_ISR_Set_level( _newlevel ) \
    sparc_enable_interrupts( _newlevel << 8)
 
 /**
- *  @brief Obtain the Current Interrupt Disable Level
+ * @brief Obtain the current interrupt disable level.
  *
- *  This method is invoked to return the current interrupt disable level.
+ * This method is invoked to return the current interrupt disable level.
  *
- *  @return This method returns the current interrupt disable level.
- */ 
+ * @return This method returns the current interrupt disable level.
+ */
 uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
@@ -982,15 +985,15 @@ uint32_t   _CPU_ISR_Get_level( void );
 /* Context handler macros */
 
 /**
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
+ * Initialize the context to a state suitable for starting a
+ * task after a context restore operation.  Generally, this
+ * involves:
  *
- *  - setting a starting address
- *  - preparing the stack
- *  - preparing the stack and frame pointers
- *  - setting the proper interrupt level in the context
- *  - initializing the floating point context
+ * - setting a starting address
+ * - preparing the stack
+ * - preparing the stack and frame pointers
+ * - setting the proper interrupt level in the context
+ * - initializing the floating point context
  *
  * @param[in] the_context points to the context area
  * @param[in] stack_base is the low address of the allocated stack area
@@ -999,7 +1002,7 @@ uint32_t   _CPU_ISR_Get_level( void );
  * @param[in] entry_point is the task's entry point
  * @param[in] is_fp is set to TRUE if the task is a floating point task
  *
- *  @note  Implemented as a subroutine for the SPARC port.
+ * NOTE:  Implemented as a subroutine for the SPARC port.
  */
 void _CPU_Context_Initialize(
   Context_Control  *the_context,
@@ -1011,17 +1014,17 @@ void _CPU_Context_Initialize(
 );
 
 /**
- *  This macro is invoked from _Thread_Handler to do whatever CPU
- *  specific magic is required that must be done in the context of
- *  the thread when it starts.
+ * This macro is invoked from _Thread_Handler to do whatever CPU
+ * specific magic is required that must be done in the context of
+ * the thread when it starts.
  *
- *  On the SPARC, this is setting the frame pointer so GDB is happy.
- *  Make GDB stop unwinding at _Thread_Handler, previous register window
- *  Frame pointer is 0 and calling address must be a function with starting
- *  with a SAVE instruction. If return address is leaf-function (no SAVE)
- *  GDB will not look at prev reg window fp.
+ * On the SPARC, this is setting the frame pointer so GDB is happy.
+ * Make GDB stop unwinding at _Thread_Handler, previous register window
+ * Frame pointer is 0 and calling address must be a function with starting
+ * with a SAVE instruction. If return address is leaf-function (no SAVE)
+ * GDB will not look at prev reg window fp.
  *
- *  _Thread_Handler is known to start with SAVE.
+ * _Thread_Handler is known to start with SAVE.
  */
 #define _CPU_Context_Initialization_at_thread_begin() \
   do { \
@@ -1029,30 +1032,30 @@ void _CPU_Context_Initialize(
   } while (0)
 
 /**
- *  This routine is responsible for somehow restarting the currently
- *  executing task.
+ * This routine is responsible for somehow restarting the currently
+ * executing task.
  *
- *  On the SPARC, this is is relatively painless but requires a small
- *  amount of wrapper code before using the regular restore code in
- *  of the context switch.
+ * On the SPARC, this is is relatively painless but requires a small
+ * amount of wrapper code before using the regular restore code in
+ * of the context switch.
  */
 #define _CPU_Context_Restart_self( _the_context ) \
    _CPU_Context_restore( (_the_context) );
 
 /**
- *  The FP context area for the SPARC is a simple structure and nothing
- *  special is required to find the "starting load point"
+ * The FP context area for the SPARC is a simple structure and nothing
+ * special is required to find the "starting load point"
  */
 #define _CPU_Context_Fp_start( _base, _offset ) \
    ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
 
 /**
- *  This routine initializes the FP context area passed to it to.
+ * This routine initializes the FP context area passed to it to.
  *
- *  The SPARC allows us to use the simple initialization model
- *  in which an "initial" FP context was saved into _CPU_Null_fp_context
- *  at CPU initialization and it is simply copied into the destination
- *  context.
+ * The SPARC allows us to use the simple initialization model
+ * in which an "initial" FP context was saved into _CPU_Null_fp_context
+ * at CPU initialization and it is simply copied into the destination
+ * context.
  */
 #define _CPU_Context_Initialize_fp( _destination ) \
   do { \
@@ -1064,9 +1067,9 @@ void _CPU_Context_Initialize(
 /* Fatal Error manager macros */
 
 /**
- *  This routine copies _error into a known place -- typically a stack
- *  location or a register, optionally disables interrupts, and
- *  halts/stops the CPU.
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
  */
 #define _CPU_Fatal_halt( _error ) \
   do { \
@@ -1083,14 +1086,14 @@ void _CPU_Context_Initialize(
 
 #if ( SPARC_HAS_BITSCAN == 0 )
   /**
-   *  The SPARC port uses the generic C algorithm for bitfield scan if the
-   *  CPU model does not have a scan instruction.
+   * The SPARC port uses the generic C algorithm for bitfield scan if the
+   * CPU model does not have a scan instruction.
    */
   #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
   /**
-   *  The SPARC port uses the generic C algorithm for bitfield scan if the
-   *  CPU model does not have a scan instruction.  Thus is needs the generic
-   *  data table used by that algorithm.
+   * The SPARC port uses the generic C algorithm for bitfield scan if the
+   * CPU model does not have a scan instruction.  Thus is needs the generic
+   * data table used by that algorithm.
    */
   #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
 #else
@@ -1102,21 +1105,21 @@ void _CPU_Context_Initialize(
 /* functions */
 
 /**
- *  @brief SPARC Specific Initialization
+ * @brief SPARC specific initialization.
  *
- *  This routine performs CPU dependent initialization.
+ * This routine performs CPU dependent initialization.
  */
 void _CPU_Initialize(void);
 
 /**
- *  @brief SPARC Specific Raw ISR Installer
+ * @brief SPARC specific raw ISR installer.
  *
- *  This routine installs @a new_handler to be directly called from the trap
- *  table.
+ * This routine installs @a new_handler to be directly called from the trap
+ * table.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the new ISR handler
- *  @param[in] old_handler will contain the old ISR handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the new ISR handler
+ * @param[in] old_handler will contain the old ISR handler
  */
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
@@ -1125,13 +1128,13 @@ void _CPU_ISR_install_raw_handler(
 );
 
 /**
- *  @brief SPARC Specific RTEMS ISR Installer
+ * @brief SPARC specific RTEMS ISR installer.
  *
- *  This routine installs an interrupt vector.
+ * This routine installs an interrupt vector.
  *
- *  @param[in] vector is the vector number
- *  @param[in] new_handler is the new ISR handler
- *  @param[in] old_handler will contain the old ISR handler
+ * @param[in] vector is the vector number
+ * @param[in] new_handler is the new ISR handler
+ * @param[in] old_handler will contain the old ISR handler
  */
 
 void _CPU_ISR_install_vector(
@@ -1141,12 +1144,12 @@ void _CPU_ISR_install_vector(
 );
 
 /**
- *  @brief SPARC Specific Context Switch
+ * @brief SPARC specific context switch.
  *
- *  This routine switches from the run context to the heir context.
+ * This routine switches from the run context to the heir context.
  *
- *  @param[in] run is the currently executing thread
- *  @param[in] heir will become the currently executing thread
+ * @param[in] run is the currently executing thread
+ * @param[in] heir will become the currently executing thread
  */
 void _CPU_Context_switch(
   Context_Control  *run,
@@ -1154,12 +1157,12 @@ void _CPU_Context_switch(
 );
 
 /**
- *  @brief SPARC Specific Context Restore
+ * @brief SPARC specific context restore.
  *
- *  This routine is generally used only to restart self in an
- *  efficient manner.
+ * This routine is generally used only to restart self in an
+ * efficient manner.
  *
- *  @param[in] new_context is the context to restore
+ * @param[in] new_context is the context to restore
  */
 void _CPU_Context_restore(
   Context_Control *new_context
@@ -1167,14 +1170,14 @@ void _CPU_Context_restore(
 
 #if defined(RTEMS_SMP)
   /**
-   *  @brief SPARC Specific Method to Switch to First Task 
+   * @brief SPARC specific method to switch to first task.
    *
-   *  This routine is only used to switch to the first task on a
-   *  secondary core in an SMP configuration.  We do not need to
-   *  flush all the windows and, in fact, this can be dangerous
-   *  as they may or may not be initialized properly.
+   * This routine is only used to switch to the first task on a
+   * secondary core in an SMP configuration.  We do not need to
+   * flush all the windows and, in fact, this can be dangerous
+   * as they may or may not be initialized properly.
    *
-   *  @param[in] new_context is the context to restore
+   * @param[in] new_context is the context to restore
    */
   void _CPU_Context_switch_to_first_task_smp(
     Context_Control *new_context
@@ -1183,7 +1186,7 @@ void _CPU_Context_restore(
   /**
    * Macro to access memory and bypass the cache.
    *
-   * @note address space 1 is uncacheable
+   * NOTE: address space 1 is uncacheable
    */
   #define SMP_CPU_SWAP( _address, _value, _previous ) \
     do { \
@@ -1200,22 +1203,22 @@ void _CPU_Context_restore(
 #endif
 
 /**
- *  @brief SPARC Specific Save FPU Method
+ * @brief SPARC specific save FPU method.
  *
- *  This routine saves the floating point context passed to it.
+ * This routine saves the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is the area to save into
+ * @param[in] fp_context_ptr is the area to save into
  */
 void _CPU_Context_save_fp(
   Context_Control_fp **fp_context_ptr
 );
 
 /**
- *  @brief SPARC Specific Rstore FPU Method
+ * @brief SPARC specific restore FPU method.
  *
- *  This routine restores the floating point context passed to it.
+ * This routine restores the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is the area to restore from
+ * @param[in] fp_context_ptr is the area to restore from
  */
 void _CPU_Context_restore_fp(
   Context_Control_fp **fp_context_ptr
@@ -1236,24 +1239,24 @@ static inline void _CPU_Exception_frame_print(
 }
 
 /**
- *  @brief SPARC Specific Method to Endian Swap an uint32_t 
+ * @brief SPARC specific method to endian swap an uint32_t.
  *
- *  The following routine swaps the endian format of an unsigned int.
- *  It must be static because it is referenced indirectly.
+ * The following routine swaps the endian format of an unsigned int.
+ * It must be static because it is referenced indirectly.
  *
- *  @param[in] value is the value to endian swap
+ * @param[in] value is the value to endian swap
  *
- *  This version will work on any processor, but if you come across a better
- *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
- *  entity as shown below is not any more efficient on the SPARC.
+ * This version will work on any processor, but if you come across a better
+ * way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
+ * entity as shown below is not any more efficient on the SPARC.
  *
- *     - swap least significant two bytes with 16-bit rotate
- *     - swap upper and lower 16-bits
- *     - swap most significant two bytes with 16-bit rotate
+ *    - swap least significant two bytes with 16-bit rotate
+ *    - swap upper and lower 16-bits
+ *    - swap most significant two bytes with 16-bit rotate
  *
- *  It is not obvious how the SPARC can do significantly better than the
- *  generic code.  gcc 2.7.0 only generates about 12 instructions for the
- *  following code at optimization level four (i.e. -O4).
+ * It is not obvious how the SPARC can do significantly better than the
+ * generic code.  gcc 2.7.0 only generates about 12 instructions for the
+ * following code at optimization level four (i.e. -O4).
  */
 static inline uint32_t CPU_swap_u32(
   uint32_t value
@@ -1271,11 +1274,11 @@ static inline uint32_t CPU_swap_u32(
 }
 
 /**
- *  @brief SPARC Specific Method to Endian Swap an uint16_t 
+ * @brief SPARC specific method to endian swap an uint16_t.
  *
- *  The following routine swaps the endian format of a uint16_t.
+ * The following routine swaps the endian format of a uint16_t.
  *
- *  @param[in] value is the value to endian swap
+ * @param[in] value is the value to endian swap
  */
 #define CPU_swap_u16( value ) \
   (((value&0xff) << 8) | ((value >> 8)&0xff))
diff --git a/cpukit/score/cpu/sparc/rtems/score/sparc.h b/cpukit/score/cpu/sparc/rtems/score/sparc.h
index 6b7936f2e5..7436cb8d2d 100644
--- a/cpukit/score/cpu/sparc/rtems/score/sparc.h
+++ b/cpukit/score/cpu/sparc/rtems/score/sparc.h
@@ -1,5 +1,8 @@
 /**
- * @file rtems/score/sparc.h
+ * @file
+ *
+ * @brief Information Required to Build RTEMS for a Particular Member
+ * of the SPARC Family
  *
  * This file contains the information required to build
  * RTEMS for a particular member of the SPARC family.  It does
@@ -42,25 +45,25 @@ extern "C" {
  */
 
 /**
- *  Some higher end SPARCs have a bitscan instructions. It would
- *  be nice to take advantage of them.  Right now, there is no
- *  port to a CPU model with this feature and no (untested) code
- *  that is based on this feature flag.
+ * Some higher end SPARCs have a bitscan instructions. It would
+ * be nice to take advantage of them.  Right now, there is no
+ * port to a CPU model with this feature and no (untested) code
+ * that is based on this feature flag.
  */
 #define SPARC_HAS_BITSCAN                0
 
 /**
- *  This should be OK until a port to a higher end SPARC processor
- *  is made that has more than 8 register windows.  If this cannot
- *  be determined based on multilib settings (v7/v8/v9), then the
- *  cpu_asm.S code that depends on this will have to move to libcpu.
+ * This should be OK until a port to a higher end SPARC processor
+ * is made that has more than 8 register windows.  If this cannot
+ * be determined based on multilib settings (v7/v8/v9), then the
+ * cpu_asm.S code that depends on this will have to move to libcpu.
  */
 #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
 
 /**
- *  This macro indicates whether this multilib variation has hardware
- *  floating point or not.  We use the gcc cpp predefine _SOFT_FLOAT
- *  to determine that.
+ * This macro indicates whether this multilib variation has hardware
+ * floating point or not.  We use the gcc cpp predefine _SOFT_FLOAT
+ * to determine that.
  */
 #if defined(_SOFT_FLOAT)
   #define SPARC_HAS_FPU 0
@@ -69,8 +72,8 @@ extern "C" {
 #endif
 
 /**
- *  This macro contains a string describing the multilib variant being
- *  build.
+ * This macro contains a string describing the multilib variant being
+ * build.
  */
 #if SPARC_HAS_FPU
   #define CPU_MODEL_NAME "w/FPU"
@@ -79,7 +82,7 @@ extern "C" {
 #endif
 
 /**
- *  Define the name of the CPU family.
+ * Define the name of the CPU family.
  */
 #define CPU_NAME "SPARC"
 
@@ -88,9 +91,9 @@ extern "C" {
  */
 
 /**
- *  PSR masks and starting bit positions
+ * PSR masks and starting bit positions
  *
- *  @note Reserved bits are ignored.
+ * NOTE: Reserved bits are ignored.
  */
 #if (SPARC_NUMBER_OF_REGISTER_WINDOWS == 8)
   #define SPARC_PSR_CWP_MASK               0x07   /* bits  0 -  4 */
@@ -145,7 +148,7 @@ extern "C" {
 #ifndef ASM
 
 /**
- *  This macro is a standard nop instruction.
+ * This macro is a standard nop instruction.
  */
 #define nop() \
   do { \
@@ -153,9 +156,9 @@ extern "C" {
   } while ( 0 )
 
 /**
- *  @brief Macro to Obtain the PSR
+ * @brief Macro to obtain the PSR.
  *
- *  This macro returns the current contents of the PSR register in @a _psr.
+ * This macro returns the current contents of the PSR register in @a _psr.
  */
 #define sparc_get_psr( _psr ) \
   do { \
@@ -164,9 +167,9 @@ extern "C" {
   } while ( 0 )
 
 /**
- *  @brief Macro to Set the PSR
+ * @brief Macro to set the PSR.
  *
- *  This macro sets the PSR register to the value in @a _psr.
+ * This macro sets the PSR register to the value in @a _psr.
  */
 #define sparc_set_psr( _psr ) \
   do { \
@@ -177,9 +180,9 @@ extern "C" {
   } while ( 0 )
 
 /**
- *  @brief Macro to Obtain the TBR
+ * @brief Macro to obtain the TBR.
  *
- *  This macro returns the current contents of the TBR register in @a _tbr.
+ * This macro returns the current contents of the TBR register in @a _tbr.
  */
 #define sparc_get_tbr( _tbr ) \
   do { \
@@ -188,9 +191,9 @@ extern "C" {
   } while ( 0 )
 
 /**
- *  @brief Macro to Set the TBR
+ * @brief Macro to set the TBR.
  *
- *  This macro sets the TBR register to the value in @a _tbr.
+ * This macro sets the TBR register to the value in @a _tbr.
  */
 #define sparc_set_tbr( _tbr ) \
   do { \
@@ -198,9 +201,9 @@ extern "C" {
   } while ( 0 )
 
 /**
- *  @brief Macro to Obtain the WIM
+ * @brief Macro to obtain the WIM.
  *
- *  This macro returns the current contents of the WIM field in @a _wim.
+ * This macro returns the current contents of the WIM field in @a _wim.
  */
 #define sparc_get_wim( _wim ) \
   do { \
@@ -208,9 +211,9 @@ extern "C" {
   } while ( 0 )
 
 /**
- *  @brief Macro to Set the WIM
+ * @brief Macro to set the WIM.
  *
- *  This macro sets the WIM field to the value in @a _wim.
+ * This macro sets the WIM field to the value in @a _wim.
  */
 #define sparc_set_wim( _wim ) \
   do { \
@@ -221,9 +224,9 @@ extern "C" {
   } while ( 0 )
 
 /**
- *  @brief Macro to Obtain the Y Register
+ * @brief Macro to obtain the Y register.
  *
- *  This macro returns the current contents of the Y register in @a _y.
+ * This macro returns the current contents of the Y register in @a _y.
  */
 #define sparc_get_y( _y ) \
   do { \
@@ -231,9 +234,9 @@ extern "C" {
   } while ( 0 )
 
 /**
- *  @brief Macro to Set the Y Register
+ * @brief Macro to set the Y register.
  *
- *  This macro sets the Y register to the value in @a _y.
+ * This macro sets the Y register to the value in @a _y.
  */
 #define sparc_set_y( _y ) \
   do { \
@@ -241,29 +244,29 @@ extern "C" {
   } while ( 0 )
 
 /**
- *  @brief SPARC Disable Processor Interrupts
+ * @brief SPARC disable processor interrupts.
  *
- *  This method is invoked to disable all maskable interrupts.
+ * This method is invoked to disable all maskable interrupts.
  *
- *  @return This method returns the entire PSR contents.
+ * @return This method returns the entire PSR contents.
  */
 uint32_t sparc_disable_interrupts(void);
 
 /**
- *  @brief SPARC Enable Processor Interrupts
+ * @brief SPARC enable processor interrupts.
  *
- *  This method is invoked to enable all maskable interrupts.
+ * This method is invoked to enable all maskable interrupts.
  *
- *  @param[in] psr is the PSR returned by @ref sparc_disable_interrupts.
+ * @param[in] psr is the PSR returned by @ref sparc_disable_interrupts.
  */
 void sparc_enable_interrupts(uint32_t psr);
 
 /**
- *  @brief SPARC Flash Processor Interrupts
+ * @brief SPARC flash processor interrupts.
  *
- *  This method is invoked to temporarily enable all maskable interrupts.
+ * This method is invoked to temporarily enable all maskable interrupts.
  *
- *  @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts.
+ * @param[in] _psr is the PSR returned by @ref sparc_disable_interrupts.
  */
 #define sparc_flash_interrupts( _psr ) \
   do { \
@@ -272,11 +275,11 @@ void sparc_enable_interrupts(uint32_t psr);
   } while ( 0 )
 
 /**
- *  @brief SPARC Obtain Interrupt Level
+ * @brief SPARC obtain interrupt level.
  *
- *  This method is invoked to obtain the current interrupt disable level.
+ * This method is invoked to obtain the current interrupt disable level.
  *
- *  @param[in] _level is the PSR returned by @ref sparc_disable_interrupts.
+ * @param[in] _level is the PSR returned by @ref sparc_disable_interrupts.
  */
 #define sparc_get_interrupt_level( _level ) \
   do { \
diff --git a/cpukit/score/cpu/sparc/rtems/score/types.h b/cpukit/score/cpu/sparc/rtems/score/types.h
index a8e56b73b2..c684763d1a 100644
--- a/cpukit/score/cpu/sparc/rtems/score/types.h
+++ b/cpukit/score/cpu/sparc/rtems/score/types.h
@@ -1,5 +1,7 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief SPARC CPU Type Definitions
  *
  * This include file contains type definitions pertaining to the
  * SPARC processor family.
@@ -26,7 +28,7 @@ extern "C" {
 #endif
 
 /**
- * @brief Priority Bit Map Type
+ * @brief Priority bit map type.
  *
  * On the SPARC, there is no bitscan instruction and no penalty associated
  * for using 16-bit variables.  With no overriding architectural factors,
@@ -35,16 +37,16 @@ extern "C" {
 typedef uint16_t Priority_bit_map_Control;
 
 /**
- *  @brief SPARC ISR Handler Return Type
+ * @brief SPARC ISR handler return type.
  *
- *  This is the type which SPARC ISR Handlers return.
+ * This is the type which SPARC ISR Handlers return.
  */
 typedef void sparc_isr;
 
 /**
- *  @brief SPARC ISR Handler Prototype
+ * @brief SPARC ISR handler prototype.
  *
- *  This is the prototype for SPARC ISR Handlers.
+ * This is the prototype for SPARC ISR Handlers.
  */
 typedef void ( *sparc_isr_entry )( void );
 
diff --git a/cpukit/score/cpu/sparc64/rtems/asm.h b/cpukit/score/cpu/sparc64/rtems/asm.h
index d670fc6149..f4448b03a5 100644
--- a/cpukit/score/cpu/sparc64/rtems/asm.h
+++ b/cpukit/score/cpu/sparc64/rtems/asm.h
@@ -1,17 +1,20 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ *  NOTE: The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
diff --git a/cpukit/score/cpu/sparc64/rtems/score/cpu.h b/cpukit/score/cpu/sparc64/rtems/score/cpu.h
index f78400f564..36c7144a19 100644
--- a/cpukit/score/cpu/sparc64/rtems/score/cpu.h
+++ b/cpukit/score/cpu/sparc64/rtems/score/cpu.h
@@ -1,15 +1,19 @@
 /**
- * @file rtems/score/cpu.h
+ * @file
+ *
+ * @brief SPARC64 CPU Department Source
+ *
+ * This include file contains information pertaining to the port of
+ * the executive to the SPARC64 processor.
  */
 
 /*
- *  This include file contains information pertaining to the port of 
- *  the executive to the SPARC64 processor.
+ *
  *
  *  COPYRIGHT (c) 1989-2006.
  *  On-Line Applications Research Corporation (OAR).
  *
- *  This file is based on the SPARC cpu.h file. Modifications are made 
+ *  This file is based on the SPARC cpu.h file. Modifications are made
  *  to support the SPARC64 processor.
  *    COPYRIGHT (c) 2010. Gedare Bloom.
  *
@@ -103,7 +107,7 @@ extern "C" {
 
 /*
  *  Does the RTEMS invoke the user's ISR with the vector number and
- *  a pointer to the saved interrupt frame (1) or just the vector 
+ *  a pointer to the saved interrupt frame (1) or just the vector
  *  number (0)?
  */
 
@@ -191,10 +195,10 @@ extern "C" {
  *  the minimum requirements of the compiler in order to have as
  *  much of the critical data area as possible in a cache line.
  *
- *  The SPARC does not appear to have particularly strict alignment 
+ *  The SPARC does not appear to have particularly strict alignment
  *  requirements.  This value (16) was chosen to take advantages of caches.
  *
- *  SPARC 64 requirements on floating point alignment is at least 8, 
+ *  SPARC 64 requirements on floating point alignment is at least 8,
  *  and is 16 if quad-word fp instructions are available (e.g. LDQF).
  */
 
@@ -221,7 +225,7 @@ extern "C" {
 #define CPU_MODES_INTERRUPT_MASK   0x0000000F
 
 /*
- *  This structure represents the organization of the minimum stack frame 
+ *  This structure represents the organization of the minimum stack frame
  *  for the SPARC.  More framing information is required in certain situaions
  *  such as when there are a large number of out parameters or when the callee
  *  must save floating point registers.
@@ -490,7 +494,7 @@ typedef struct {
  *  NOTE:  The tstate, tpc, and tnpc are saved in this structure
  *  	   to allow resetting the TL while still being able to return
  *  	   from a trap later.  The PIL is saved because
- *         if this is an external interrupt, we will mask lower 
+ *         if this is an external interrupt, we will mask lower
  *         priority interrupts until finishing. Even though the y register
  *         is deprecated, gcc still uses it.
  */
@@ -549,11 +553,11 @@ typedef struct {
 #define ISF_O7_OFFSET          CPU_MINIMUM_STACK_FRAME_SIZE + 0x98
 #define ISF_TVEC_OFFSET        CPU_MINIMUM_STACK_FRAME_SIZE + 0xA0
 
-#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0xA8 
+#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0xA8
 #ifndef ASM
 /*
  *  This variable is contains the initialize context for the FP unit.
- *  It is filled in by _CPU_Initialize and copied into the task's FP 
+ *  It is filled in by _CPU_Initialize and copied into the task's FP
  *  context area during _CPU_Context_Initialize.
  */
 
@@ -592,9 +596,9 @@ SCORE_EXTERN volatile uint32_t _CPU_ISR_Dispatch_disable;
  *        long jump.  The other instructions load one register with the
  *        trap type (a.k.a. vector) and another with the psr.
  */
-/* For SPARC V9, we must use 6 of these instructions to perform a long 
- * jump, because the _handler value is now 64-bits. We also need to store 
- * temporary values in the global register set at this trap level. Because 
+/* For SPARC V9, we must use 6 of these instructions to perform a long
+ * jump, because the _handler value is now 64-bits. We also need to store
+ * temporary values in the global register set at this trap level. Because
  * the handler runs at TL > 0 with GL > 0, it should be OK to use g2 and g3
  * to pass parameters to ISR_Handler.
  *
@@ -614,7 +618,7 @@ typedef struct {
   uint32_t     jmp_to_low_of_handler_plus_g3;	/* jmp   %g3 + %lo(_handler) */
   uint32_t     mov_vector_g2;			/* mov   _vector, %g2        */
 } CPU_Trap_table_entry;
- 
+
 /*
  *  This is the set of opcodes for the instructions loaded into a trap
  *  table entry.  The routine which installs a handler is responsible
@@ -624,11 +628,11 @@ typedef struct {
  *  The constants following this structure are masks for the fields which
  *  must be filled in when the handler is installed.
  */
- 
+
 extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
 
 /*
- *  The size of the floating point context area.  
+ *  The size of the floating point context area.
  */
 
 #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp )
@@ -666,7 +670,7 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
  *  an asynchronous trap.  This will avoid the executive changing the return
  *  address.
  */
-/* On SPARC v9, there are 512 vectors. The same philosophy applies to 
+/* On SPARC v9, there are 512 vectors. The same philosophy applies to
  * vector installation and use, we just provide a larger table.
  */
 #define CPU_INTERRUPT_NUMBER_OF_VECTORS     512
@@ -796,14 +800,14 @@ extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
 /*
  *  Map interrupt level in task mode onto the hardware that the CPU
  *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a straight fashion are undefined.  
+ *  map onto the CPU in a straight fashion are undefined.
  */
 
 #define _CPU_ISR_Set_level( _newlevel ) \
    sparc_enable_interrupts( _newlevel)
 
 uint32_t   _CPU_ISR_Get_level( void );
- 
+
 /* end of ISR handler macros */
 
 /* Context handler macros */
@@ -839,7 +843,7 @@ void _CPU_Context_Initialize(
  *  On the SPARC, this is setting the frame pointer so GDB is happy.
  *  Make GDB stop unwinding at _Thread_Handler, previous register window
  *  Frame pointer is 0 and calling address must be a function with starting
- *  with a SAVE instruction. If return address is leaf-function (no SAVE) 
+ *  with a SAVE instruction. If return address is leaf-function (no SAVE)
  *  GDB will not look at prev reg window fp.
  *
  *  _Thread_Handler is known to start with SAVE.
@@ -852,7 +856,7 @@ void _CPU_Context_Initialize(
 
 /*
  *  This routine is responsible for somehow restarting the currently
- *  executing task.  
+ *  executing task.
  *
  *  On the SPARC, this is is relatively painless but requires a small
  *  amount of wrapper code before using the regular restore code in
@@ -874,7 +878,7 @@ void _CPU_Context_Initialize(
  *  This routine initializes the FP context area passed to it to.
  *
  *  The SPARC allows us to use the simple initialization model
- *  in which an "initial" FP context was saved into _CPU_Null_fp_context 
+ *  in which an "initial" FP context was saved into _CPU_Null_fp_context
  *  at CPU initialization and it is simply copied into the destination
  *  context.
  */
@@ -950,7 +954,7 @@ void _CPU_Initialize(void);
  *  This routine installs new_handler to be directly called from the trap
  *  table.
  */
- 
+
 void _CPU_ISR_install_raw_handler(
   uint32_t    vector,
   proc_ptr    new_handler,
@@ -970,14 +974,14 @@ void _CPU_ISR_install_vector(
 );
 
 #if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
- 
+
 /*
  *  _CPU_Thread_Idle_body
  *
  *  Some SPARC implementations have low power, sleep, or idle modes.  This
  *  tries to take advantage of those models.
  */
- 
+
 void *_CPU_Thread_Idle_body( uintptr_t ignored );
 
 #endif /* CPU_PROVIDES_IDLE_THREAD_BODY */
@@ -1036,7 +1040,7 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
  *  It must be static because it is referenced indirectly.
  *
  *  This version will work on any processor, but if you come across a better
- *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit 
+ *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
  *  entity as shown below is not any more efficient on the SPARC.
  *
  *     swap least significant two bytes with 16-bit rotate
@@ -1047,18 +1051,18 @@ void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
  *  generic code.  gcc 2.7.0 only generates about 12 instructions for the
  *  following code at optimization level four (i.e. -O4).
  */
- 
+
 static inline uint32_t CPU_swap_u32(
   uint32_t value
 )
 {
   uint32_t   byte1, byte2, byte3, byte4, swapped;
- 
+
   byte4 = (value >> 24) & 0xff;
   byte3 = (value >> 16) & 0xff;
   byte2 = (value >> 8)  & 0xff;
   byte1 =  value        & 0xff;
- 
+
   swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
   return( swapped );
 }
diff --git a/cpukit/score/cpu/sparc64/rtems/score/sparc64.h b/cpukit/score/cpu/sparc64/rtems/score/sparc64.h
index b7ac2c5137..b2df9c17a5 100644
--- a/cpukit/score/cpu/sparc64/rtems/score/sparc64.h
+++ b/cpukit/score/cpu/sparc64/rtems/score/sparc64.h
@@ -1,15 +1,18 @@
 /**
- * @file rtems/score/sparc64.h
+ * @file
+ *
+ * @brief Information Required to Build RTEMS for a Particular Member
+ * of the SPARC Family
+ *
+ * This include file contains information pertaining to the SPARC
+ * processor family.
  */
 
 /*
- *  This include file contains information pertaining to the SPARC 
- *  processor family.
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
- *  This file is based on the SPARC sparc.h file. Modifications are made 
+ *  This file is based on the SPARC sparc.h file. Modifications are made
  *  to support the SPARC64 processor.
  *    COPYRIGHT (c) 2010. Gedare Bloom.
  *
@@ -34,19 +37,19 @@ extern "C" {
  *
  *  Currently recognized feature flags:
  *
- *    + SPARC_HAS_FPU 
+ *    + SPARC_HAS_FPU
  *        0 - no HW FPU
  *        1 - has HW FPU (assumed to be compatible w/90C602)
  *
- *    + SPARC_HAS_BITSCAN 
+ *    + SPARC_HAS_BITSCAN
  *        0 - does not have scan instructions
  *        1 - has scan instruction  (not currently implemented)
- * 
+ *
  *    + SPARC_NUMBER_OF_REGISTER_WINDOWS
  *        8 is the most common number supported by SPARC implementations.
  *        SPARC_PSR_CWP_MASK is derived from this value.
  */
- 
+
 /*
  *  Some higher end SPARCs have a bitscan instructions. It would
  *  be nice to take advantage of them.  Right now, there is no
@@ -67,9 +70,9 @@ extern "C" {
  */
 
 #define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
- 
+
 /*
- *  This should be determined based on some soft float derived 
+ *  This should be determined based on some soft float derived
  *  cpp predefine but gcc does not currently give us that information.
  */
 
@@ -96,7 +99,7 @@ extern "C" {
  *  Miscellaneous constants
  */
 
-/* 
+/*
  * The PSR is deprecated and deleted.
  *
  * The following registers represent fields of the PSR:
@@ -145,7 +148,7 @@ extern "C" {
 
 #ifdef ASM
 
-/* 
+/*
  * To enable the FPU we need to set both PSTATE.pef and FPRS.fef
  */
 
@@ -237,9 +240,9 @@ extern "C" {
 /*
  * read the stick register
  *
- * Note: 
+ * Note:
  * stick asr=24, mnemonic=stick
- * Note: stick does not appear to be a valid ASR for US3, although it is 
+ * Note: stick does not appear to be a valid ASR for US3, although it is
  * implemented in US3i.
  */
 #define sparc64_read_stick( _stick ) \
@@ -249,11 +252,11 @@ extern "C" {
   } while ( 0 )
 
 /*
- * write the stick_cmpr register 
+ * write the stick_cmpr register
  *
- * Note: 
+ * Note:
  * stick_cmpr asr=25, mnemonic=stick_cmpr
- * Note: stick_cmpr does not appear to be a valid ASR for US3, although it is 
+ * Note: stick_cmpr does not appear to be a valid ASR for US3, although it is
  * implemented in US3i.
  */
 #define sparc64_write_stick_cmpr( _stick_cmpr ) \
@@ -280,7 +283,7 @@ extern "C" {
                                              :  "0" (_tick_cmpr) ); \
   } while ( 0 )
 
-/* 
+/*
  * Clear the softint register.
  *
  * sun4u and sun4v: softint_clr asr = 21, with mnemonic clear_softint
@@ -296,12 +299,12 @@ extern "C" {
 /*
  *  Get and set the Y
  */
- 
+
 #define sparc_get_y( _y ) \
   do { \
     __asm__ volatile( "rd %%y, %0" :  "=r" (_y) : "0" (_y) ); \
   } while ( 0 )
- 
+
 #define sparc_set_y( _y ) \
   do { \
     __asm__ volatile( "wr %0, %%y" :  "=r" (_y) : "0" (_y) ); \
@@ -310,12 +313,12 @@ extern "C" {
 /************* /DEPRECATED ****************/
 
 /*
- *  Manipulate the interrupt level in the pstate 
+ *  Manipulate the interrupt level in the pstate
  */
 
 uint32_t sparc_disable_interrupts(void);
 void sparc_enable_interrupts(uint32_t);
-  
+
 #define sparc_flash_interrupts( _level ) \
   do { \
     register uint32_t   _ignored = 0; \
diff --git a/cpukit/score/cpu/sparc64/rtems/score/types.h b/cpukit/score/cpu/sparc64/rtems/score/types.h
index 3d289a586a..06b7844042 100644
--- a/cpukit/score/cpu/sparc64/rtems/score/types.h
+++ b/cpukit/score/cpu/sparc64/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief SPARC64 CPU Type Definitions
+ *
+ * This include file contains type definitions pertaining to the
+ * SPARC-v9 processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the 
- *  SPARC-v9 processor family.
- *
  *  COPYRIGHT (c) 1989-1999.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/v850/rtems/asm.h b/cpukit/score/cpu/v850/rtems/asm.h
index 09e64da442..265e4967ae 100644
--- a/cpukit/score/cpu/v850/rtems/asm.h
+++ b/cpukit/score/cpu/v850/rtems/asm.h
@@ -1,26 +1,27 @@
 /**
- * @file rtems/asm.h
+ * @file
  *
- *  This include file attempts to address the problems
- *  caused by incompatible flavors of assemblers and
- *  toolsets.  It primarily addresses variations in the
- *  use of leading underscores on symbols and the requirement
- *  that register names be preceded by a %.
+ * @brief Address the Problems Caused by Incompatible Flavor of
+ * Assemblers and Toolsets
+ *
+ * This include file attempts to address the problems
+ * caused by incompatible flavors of assemblers and
+ * toolsets.  It primarily addresses variations in the
+ * use of leading underscores on symbols and the requirement
+ * that register names be preceded by a %.
+ *
+ * @note The spacing in the use of these macros
+ *       is critical to them working as advertised.
  */
 
 /*
- *  NOTE: The spacing in the use of these macros
- *        is critical to them working as advertised.
- *
  *  COPYRIGHT:
  *
  *  This file is based on similar code found in newlib available
  *  from ftp.cygnus.com.  The file which was used had no copyright
  *  notice.  This file is freely distributable as long as the source
  *  of the file is noted.  This file is:
- */
-
-/*
+ *
  *  COPYRIGHT (c) 1994-2012.
  *  On-Line Applications Research Corporation (OAR).
  */
@@ -40,24 +41,24 @@
 
 #ifndef __USER_LABEL_PREFIX__
 /**
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents.  If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
  *
- *  This symbol is prefixed to all C program symbols.
+ * This symbol is prefixed to all C program symbols.
  */
 #define __USER_LABEL_PREFIX__ _
 #endif
 
 #ifndef __REGISTER_PREFIX__
 /**
- *  Recent versions of GNU cpp define variables which indicate the
- *  need for underscores and percents.  If not using GNU cpp or
- *  the version does not support this, then you will obviously
- *  have to define these as appropriate.
+ * Recent versions of GNU cpp define variables which indicate the
+ * need for underscores and percents.  If not using GNU cpp or
+ * the version does not support this, then you will obviously
+ * have to define these as appropriate.
  *
- *  This symbol is prefixed to all register names.
+ * This symbol is prefixed to all register names.
  */
 #define __REGISTER_PREFIX__
 #endif
@@ -97,8 +98,9 @@
 #define BEGIN_DATA
 /** This macro is used to denote the end of a data section. */
 #define END_DATA
-/** This macro is used to denote the beginning of the
- *  unitialized data section.
+/**
+ * This macro is used to denote the beginning of the
+ * unitialized data section.
  */
 #define BEGIN_BSS
 /** This macro is used to denote the end of the unitialized data section.  */
@@ -107,18 +109,18 @@
 #define END
 
 /**
- *  This macro is used to declare a public global symbol.
+ * This macro is used to declare a public global symbol.
  *
- *  @note This must be tailored for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
  */
 #define PUBLIC(sym) .globl SYM (sym)
 
 /**
- *  This macro is used to prototype a public global symbol.
+ * This macro is used to prototype a public global symbol.
  *
- *  @note This must be tailored for a particular flavor of the C compiler.
- *  They may need to put underscores in front of the symbols.
+ * @note This must be tailored for a particular flavor of the C compiler.
+ * They may need to put underscores in front of the symbols.
  */
 #define EXTERN(sym) .globl SYM (sym)
 
diff --git a/cpukit/score/cpu/v850/rtems/score/cpu.h b/cpukit/score/cpu/v850/rtems/score/cpu.h
index b6fb59d7b6..c0b6f9e2ca 100644
--- a/cpukit/score/cpu/v850/rtems/score/cpu.h
+++ b/cpukit/score/cpu/v850/rtems/score/cpu.h
@@ -1,10 +1,10 @@
 /**
- * @file rtems/score/cpu.h
- */
-
-/*
- *  This include file contains information pertaining to the v850
- *  processor.
+ * @file
+ *
+ * @brief V850 CPU Department Source
+ *
+ * This include file contains information pertaining to the v850
+ * processor.
  */
 
 /*
@@ -29,418 +29,420 @@ extern "C" {
 /* conditional compilation parameters */
 
 /**
- *  Should the calls to @ref _Thread_Enable_dispatch be inlined?
+ * Should the calls to @ref _Thread_Enable_dispatch be inlined?
  *
- *  If TRUE, then they are inlined.
- *  If FALSE, then a subroutine call is made.
+ * If TRUE, then they are inlined.
+ * If FALSE, then a subroutine call is made.
  *
- *  This conditional is an example of the classic trade-off of size
- *  versus speed.  Inlining the call (TRUE) typically increases the
- *  size of RTEMS while speeding up the enabling of dispatching.
+ * This conditional is an example of the classic trade-off of size
+ * versus speed.  Inlining the call (TRUE) typically increases the
+ * size of RTEMS while speeding up the enabling of dispatching.
  *
- *  @note In general, the @ref _Thread_Dispatch_disable_level will
- *  only be 0 or 1 unless you are in an interrupt handler and that
- *  interrupt handler invokes the executive.]  When not inlined
- *  something calls @ref _Thread_Enable_dispatch which in turns calls
- *  @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
- *  one subroutine call is avoided entirely.
+ * @note In general, the @ref _Thread_Dispatch_disable_level will
+ * only be 0 or 1 unless you are in an interrupt handler and that
+ * interrupt handler invokes the executive.]  When not inlined
+ * something calls @ref _Thread_Enable_dispatch which in turns calls
+ * @ref _Thread_Dispatch.  If the enable dispatch is inlined, then
+ * one subroutine call is avoided entirely.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 is a RISC CPU which typically has enough memory to justify
- *  the inlining of this method.
+ * The v850 is a RISC CPU which typically has enough memory to justify
+ * the inlining of this method.
  */
 #define CPU_INLINE_ENABLE_DISPATCH       TRUE
 
 /**
- *  Should the body of the search loops in _Thread_queue_Enqueue_priority
- *  be unrolled one time?  In unrolled each iteration of the loop examines
- *  two "nodes" on the chain being searched.  Otherwise, only one node
- *  is examined per iteration.
- *
- *  If TRUE, then the loops are unrolled.
- *  If FALSE, then the loops are not unrolled.
- *
- *  The primary factor in making this decision is the cost of disabling
- *  and enabling interrupts (_ISR_Flash) versus the cost of rest of the
- *  body of the loop.  On some CPUs, the flash is more expensive than
- *  one iteration of the loop body.  In this case, it might be desirable
- *  to unroll the loop.  It is important to note that on some CPUs, this
- *  code is the longest interrupt disable period in RTEMS.  So it is
- *  necessary to strike a balance when setting this parameter.
- *
- *  Port Specific Information:
- *
- *  The v850 is a RISC CPU which typically has enough memory to justify
- *  the unrolling of this method.
+ * Should the body of the search loops in _Thread_queue_Enqueue_priority
+ * be unrolled one time?  In unrolled each iteration of the loop examines
+ * two "nodes" on the chain being searched.  Otherwise, only one node
+ * is examined per iteration.
+ *
+ * If TRUE, then the loops are unrolled.
+ * If FALSE, then the loops are not unrolled.
+ *
+ * The primary factor in making this decision is the cost of disabling
+ * and enabling interrupts (_ISR_Flash) versus the cost of rest of the
+ * body of the loop.  On some CPUs, the flash is more expensive than
+ * one iteration of the loop body.  In this case, it might be desirable
+ * to unroll the loop.  It is important to note that on some CPUs, this
+ * code is the longest interrupt disable period in RTEMS.  So it is
+ * necessary to strike a balance when setting this parameter.
+ *
+ * Port Specific Information:
+ *
+ * The v850 is a RISC CPU which typically has enough memory to justify
+ * the unrolling of this method.
  */
 #define CPU_UNROLL_ENQUEUE_PRIORITY      TRUE
 
 /**
- *  Does RTEMS manage a dedicated interrupt stack in software?
+ * Does RTEMS manage a dedicated interrupt stack in software?
  *
- *  If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
- *  If FALSE, nothing is done.
+ * If TRUE, then a stack is allocated in @ref _ISR_Handler_initialization.
+ * If FALSE, nothing is done.
  *
- *  If the CPU supports a dedicated interrupt stack in hardware,
- *  then it is generally the responsibility of the BSP to allocate it
- *  and set it up.
+ * If the CPU supports a dedicated interrupt stack in hardware,
+ * then it is generally the responsibility of the BSP to allocate it
+ * and set it up.
  *
- *  If the CPU does not support a dedicated interrupt stack, then
- *  the porter has two options: (1) execute interrupts on the
- *  stack of the interrupted task, and (2) have RTEMS manage a dedicated
- *  interrupt stack.
+ * If the CPU does not support a dedicated interrupt stack, then
+ * the porter has two options: (1) execute interrupts on the
+ * stack of the interrupted task, and (2) have RTEMS manage a dedicated
+ * interrupt stack.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 does not have support for a hardware interrupt stack.
+ * The v850 does not have support for a hardware interrupt stack.
  */
 #define CPU_HAS_SOFTWARE_INTERRUPT_STACK TRUE
 
 /**
- *  Does the CPU follow the simple vectored interrupt model?
+ * Does the CPU follow the simple vectored interrupt model?
  *
- *  If TRUE, then RTEMS allocates the vector table it internally manages.
- *  If FALSE, then the BSP is assumed to allocate and manage the vector
- *  table
+ * If TRUE, then RTEMS allocates the vector table it internally manages.
+ * If FALSE, then the BSP is assumed to allocate and manage the vector
+ * table
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  This port uses the Progammable Interrupt Controller interrupt model.
+ * This port uses the Progammable Interrupt Controller interrupt model.
  */
 #define CPU_SIMPLE_VECTORED_INTERRUPTS FALSE
 
 /**
- *  Does this CPU have hardware support for a dedicated interrupt stack?
+ * Does this CPU have hardware support for a dedicated interrupt stack?
  *
- *  If TRUE, then it must be installed during initialization.
- *  If FALSE, then no installation is performed.
+ * If TRUE, then it must be installed during initialization.
+ * If FALSE, then no installation is performed.
  *
- *  If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
+ * If this is TRUE, @ref CPU_ALLOCATE_INTERRUPT_STACK should also be TRUE.
  *
- *  Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
- *  @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
- *  possible that both are FALSE for a particular CPU.  Although it
- *  is unclear what that would imply about the interrupt processing
- *  procedure on that CPU.
+ * Only one of @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK and
+ * @ref CPU_HAS_HARDWARE_INTERRUPT_STACK should be set to TRUE.  It is
+ * possible that both are FALSE for a particular CPU.  Although it
+ * is unclear what that would imply about the interrupt processing
+ * procedure on that CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 does not have support for a hardware interrupt stack.
+ * The v850 does not have support for a hardware interrupt stack.
  */
 #define CPU_HAS_HARDWARE_INTERRUPT_STACK FALSE
 
 /**
- *  Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
+ * Does RTEMS allocate a dedicated interrupt stack in the Interrupt Manager?
  *
- *  If TRUE, then the memory is allocated during initialization.
- *  If FALSE, then the memory is allocated during initialization.
+ * If TRUE, then the memory is allocated during initialization.
+ * If FALSE, then the memory is allocated during initialization.
  *
- *  This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
+ * This should be TRUE is CPU_HAS_SOFTWARE_INTERRUPT_STACK is TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_ALLOCATE_INTERRUPT_STACK TRUE
 
 /**
- *  @def CPU_HARDWARE_FP
+ * @def CPU_HARDWARE_FP
  *
- *  Does the CPU have hardware floating point?
+ * Does the CPU have hardware floating point?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is supported.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is ignored.
  *
- *  If there is a FP coprocessor such as the i387 or mc68881, then
- *  the answer is TRUE.
+ * If there is a FP coprocessor such as the i387 or mc68881, then
+ * the answer is TRUE.
  *
- *  The macro name "V850_HAS_FPU" should be made CPU specific.
- *  It indicates whether or not this CPU model has FP support.  For
- *  example, it would be possible to have an i386_nofp CPU model
- *  which set this to false to indicate that you have an i386 without
- *  an i387 and wish to leave floating point support out of RTEMS.
+ * The macro name "V850_HAS_FPU" should be made CPU specific.
+ * It indicates whether or not this CPU model has FP support.  For
+ * example, it would be possible to have an i386_nofp CPU model
+ * which set this to false to indicate that you have an i386 without
+ * an i387 and wish to leave floating point support out of RTEMS.
  */
 
 /**
- *  @def CPU_SOFTWARE_FP
- *
- *  Does the CPU have no hardware floating point and GCC provides a
- *  software floating point implementation which must be context
- *  switched?
- *
- *  This feature conditional is used to indicate whether or not there
- *  is software implemented floating point that must be context
- *  switched.  The determination of whether or not this applies
- *  is very tool specific and the state saved/restored is also
- *  compiler specific.
- *
- *  Port Specific Information:
- *
- *  Some v850 models do have IEEE hardware floating point support but
- *  they do not have any special registers to save or bit(s) which
- *  determine if the FPU is enabled. In short, there appears to be nothing
- *  related to the floating point operations which impact the RTEMS
- *  thread context switch. Thus from an RTEMS perspective, there is really
- *  no FPU to manage.
+ * @def CPU_SOFTWARE_FP
+ *
+ * Does the CPU have no hardware floating point and GCC provides a
+ * software floating point implementation which must be context
+ * switched?
+ *
+ * This feature conditional is used to indicate whether or not there
+ * is software implemented floating point that must be context
+ * switched.  The determination of whether or not this applies
+ * is very tool specific and the state saved/restored is also
+ * compiler specific.
+ *
+ * Port Specific Information:
+ *
+ * Some v850 models do have IEEE hardware floating point support but
+ * they do not have any special registers to save or bit(s) which
+ * determine if the FPU is enabled. In short, there appears to be nothing
+ * related to the floating point operations which impact the RTEMS
+ * thread context switch. Thus from an RTEMS perspective, there is really
+ * no FPU to manage.
  */
 #define CPU_HARDWARE_FP     FALSE
 #define CPU_SOFTWARE_FP     FALSE
 
 /**
- *  Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
+ * Are all tasks RTEMS_FLOATING_POINT tasks implicitly?
  *
- *  If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
- *  If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
+ * If TRUE, then the RTEMS_FLOATING_POINT task attribute is assumed.
+ * If FALSE, then the RTEMS_FLOATING_POINT task attribute is followed.
  *
- *  So far, the only CPUs in which this option has been used are the
- *  HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
- *  gcc both implicitly used the floating point registers to perform
- *  integer multiplies.  Similarly, the PowerPC port of gcc has been
- *  seen to allocate floating point local variables and touch the FPU
- *  even when the flow through a subroutine (like vfprintf()) might
- *  not use floating point formats.
+ * So far, the only CPUs in which this option has been used are the
+ * HP PA-RISC and PowerPC.  On the PA-RISC, The HP C compiler and
+ * gcc both implicitly used the floating point registers to perform
+ * integer multiplies.  Similarly, the PowerPC port of gcc has been
+ * seen to allocate floating point local variables and touch the FPU
+ * even when the flow through a subroutine (like vfprintf()) might
+ * not use floating point formats.
  *
- *  If a function which you would not think utilize the FP unit DOES,
- *  then one can not easily predict which tasks will use the FP hardware.
- *  In this case, this option should be TRUE.
+ * If a function which you would not think utilize the FP unit DOES,
+ * then one can not easily predict which tasks will use the FP hardware.
+ * In this case, this option should be TRUE.
  *
- *  If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
+ * If @ref CPU_HARDWARE_FP is FALSE, then this should be FALSE as well.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  This should be false until it has been demonstrated that gcc for the
- *  v850 generates FPU code when it is unexpected. But even this would
- *  not matter since there are no FP specific registers or bits which
- *  would be corrupted if an FP operation occurred in an integer only
- *  thread.
+ * This should be false until it has been demonstrated that gcc for the
+ * v850 generates FPU code when it is unexpected. But even this would
+ * not matter since there are no FP specific registers or bits which
+ * would be corrupted if an FP operation occurred in an integer only
+ * thread.
  */
 #define CPU_ALL_TASKS_ARE_FP     FALSE
 
 /**
- *  Should the IDLE task have a floating point context?
+ * Should the IDLE task have a floating point context?
  *
- *  If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
- *  and it has a floating point context which is switched in and out.
- *  If FALSE, then the IDLE task does not have a floating point context.
+ * If TRUE, then the IDLE task is created as a RTEMS_FLOATING_POINT task
+ * and it has a floating point context which is switched in and out.
+ * If FALSE, then the IDLE task does not have a floating point context.
  *
- *  Setting this to TRUE negatively impacts the time required to preempt
- *  the IDLE task from an interrupt because the floating point context
- *  must be saved as part of the preemption.
+ * Setting this to TRUE negatively impacts the time required to preempt
+ * the IDLE task from an interrupt because the floating point context
+ * must be saved as part of the preemption.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The IDLE thread should not be using the FPU. Leave this off.
+ * The IDLE thread should not be using the FPU. Leave this off.
  */
 #define CPU_IDLE_TASK_IS_FP      FALSE
 
 /**
- *  Should the saving of the floating point registers be deferred
- *  until a context switch is made to another different floating point
- *  task?
+ * Should the saving of the floating point registers be deferred
+ * until a context switch is made to another different floating point
+ * task?
  *
- *  If TRUE, then the floating point context will not be stored until
- *  necessary.  It will remain in the floating point registers and not
- *  disturned until another floating point task is switched to.
+ * If TRUE, then the floating point context will not be stored until
+ * necessary.  It will remain in the floating point registers and not
+ * disturned until another floating point task is switched to.
  *
- *  If FALSE, then the floating point context is saved when a floating
- *  point task is switched out and restored when the next floating point
- *  task is restored.  The state of the floating point registers between
- *  those two operations is not specified.
+ * If FALSE, then the floating point context is saved when a floating
+ * point task is switched out and restored when the next floating point
+ * task is restored.  The state of the floating point registers between
+ * those two operations is not specified.
  *
- *  If the floating point context does NOT have to be saved as part of
- *  interrupt dispatching, then it should be safe to set this to TRUE.
+ * If the floating point context does NOT have to be saved as part of
+ * interrupt dispatching, then it should be safe to set this to TRUE.
  *
- *  Setting this flag to TRUE results in using a different algorithm
- *  for deciding when to save and restore the floating point context.
- *  The deferred FP switch algorithm minimizes the number of times
- *  the FP context is saved and restored.  The FP context is not saved
- *  until a context switch is made to another, different FP task.
- *  Thus in a system with only one FP task, the FP context will never
- *  be saved or restored.
+ * Setting this flag to TRUE results in using a different algorithm
+ * for deciding when to save and restore the floating point context.
+ * The deferred FP switch algorithm minimizes the number of times
+ * the FP context is saved and restored.  The FP context is not saved
+ * until a context switch is made to another, different FP task.
+ * Thus in a system with only one FP task, the FP context will never
+ * be saved or restored.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  See earlier comments. There is no FPU state to manage.
+ * See earlier comments. There is no FPU state to manage.
  */
 #define CPU_USE_DEFERRED_FP_SWITCH       TRUE
 
 /**
- *  Does this port provide a CPU dependent IDLE task implementation?
+ * Does this port provide a CPU dependent IDLE task implementation?
  *
- *  If TRUE, then the routine @ref _CPU_Thread_Idle_body
- *  must be provided and is the default IDLE thread body instead of
- *  @ref _CPU_Thread_Idle_body.
+ * If TRUE, then the routine @ref _CPU_Thread_Idle_body
+ * must be provided and is the default IDLE thread body instead of
+ * @ref _CPU_Thread_Idle_body.
  *
- *  If FALSE, then use the generic IDLE thread body if the BSP does
- *  not provide one.
+ * If FALSE, then use the generic IDLE thread body if the BSP does
+ * not provide one.
  *
- *  This is intended to allow for supporting processors which have
- *  a low power or idle mode.  When the IDLE thread is executed, then
- *  the CPU can be powered down.
+ * This is intended to allow for supporting processors which have
+ * a low power or idle mode.  When the IDLE thread is executed, then
+ * the CPU can be powered down.
  *
- *  The order of precedence for selecting the IDLE thread body is:
+ * The order of precedence for selecting the IDLE thread body is:
  *
- *    -#  BSP provided
- *    -#  CPU dependent (if provided)
- *    -#  generic (if no BSP and no CPU dependent)
+ *   -#  BSP provided
+ *   -#  CPU dependent (if provided)
+ *   -#  generic (if no BSP and no CPU dependent)
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  There does not appear to be a reason for the v850 port itself to provide
- *  a special idle task.
+ * There does not appear to be a reason for the v850 port itself to provide
+ * a special idle task.
  */
 #define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
 
 /**
- *  Does the stack grow up (toward higher addresses) or down
- *  (toward lower addresses)?
+ * Does the stack grow up (toward higher addresses) or down
+ * (toward lower addresses)?
  *
- *  If TRUE, then the grows upward.
- *  If FALSE, then the grows toward smaller addresses.
+ * If TRUE, then the grows upward.
+ * If FALSE, then the grows toward smaller addresses.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 stack grows from high addresses to low addresses.
+ * The v850 stack grows from high addresses to low addresses.
  */
 #define CPU_STACK_GROWS_UP               FALSE
 
 /**
- *  The following is the variable attribute used to force alignment
- *  of critical RTEMS structures.  On some processors it may make
- *  sense to have these aligned on tighter boundaries than
- *  the minimum requirements of the compiler in order to have as
- *  much of the critical data area as possible in a cache line.
+ * The following is the variable attribute used to force alignment
+ * of critical RTEMS structures.  On some processors it may make
+ * sense to have these aligned on tighter boundaries than
+ * the minimum requirements of the compiler in order to have as
+ * much of the critical data area as possible in a cache line.
  *
- *  The placement of this macro in the declaration of the variables
- *  is based on the syntactically requirements of the GNU C
- *  "__attribute__" extension.  For example with GNU C, use
- *  the following to force a structures to a 32 byte boundary.
+ * The placement of this macro in the declaration of the variables
+ * is based on the syntactically requirements of the GNU C
+ * "__attribute__" extension.  For example with GNU C, use
+ * the following to force a structures to a 32 byte boundary.
  *
- *      __attribute__ ((aligned (32)))
+ *     __attribute__ ((aligned (32)))
  *
- *  @note Currently only the Priority Bit Map table uses this feature.
- *        To benefit from using this, the data must be heavily
- *        used so it will stay in the cache and used frequently enough
- *        in the executive to justify turning this on.
+ * @note Currently only the Priority Bit Map table uses this feature.
+ *       To benefit from using this, the data must be heavily
+ *       used so it will stay in the cache and used frequently enough
+ *       in the executive to justify turning this on.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  Until proven otherwise, use the compiler default.
+ * Until proven otherwise, use the compiler default.
  */
 #define CPU_STRUCTURE_ALIGNMENT
 
 /**
- *  The v850 should use 64-bit timestamps and inline them.
+ * The v850 should use 64-bit timestamps and inline them.
  */
 #define CPU_TIMESTAMP_USE_INT64_INLINE TRUE
 
 /**
- *  @defgroup CPUEndian Processor Dependent Endianness Support
+ * @defgroup CPUEndian Processor Dependent Endianness Support
+ *
+ * This group assists in issues related to processor endianness.
  *
- *  This group assists in issues related to processor endianness.
  */
+/**@{**/
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * @note @a CPU_BIG_ENDIAN and @a CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_LITTLE_ENDIAN
+ * @see CPU_LITTLE_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 is little endian.
+ * The v850 is little endian.
  */
 #define CPU_BIG_ENDIAN  FALSE
 
 /**
- *  @ingroup CPUEndian
- *  Define what is required to specify how the network to host conversion
- *  routines are handled.
+ * Define what is required to specify how the network to host conversion
+ * routines are handled.
  *
- *  @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
- *  same values.
+ * @note @ref CPU_BIG_ENDIAN and @ref CPU_LITTLE_ENDIAN should NOT have the
+ * same values.
  *
- *  @see CPU_BIG_ENDIAN
+ * @see CPU_BIG_ENDIAN
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 is little endian.
+ * The v850 is little endian.
  */
 #define CPU_LITTLE_ENDIAN TRUE
 
+/** @} */
+
 /**
- *  @ingroup CPUInterrupt
- *  The following defines the number of bits actually used in the
- *  interrupt field of the task mode.  How those bits map to the
- *  CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
+ * @ingroup CPUInterrupt
+ * The following defines the number of bits actually used in the
+ * interrupt field of the task mode.  How those bits map to the
+ * CPU interrupt levels is defined by the routine @ref _CPU_ISR_Set_level.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 only has a single bit in the CPU for interrupt disable/enable.
+ * The v850 only has a single bit in the CPU for interrupt disable/enable.
  */
 #define CPU_MODES_INTERRUPT_MASK   0x00000001
 
 /**
  * @defgroup CPUContext Processor Dependent Context Management
  *
- *  From the highest level viewpoint, there are 2 types of context to save.
+ * From the highest level viewpoint, there are 2 types of context to save.
  *
- *     -# Interrupt registers to save
- *     -# Task level registers to save
+ *    -# Interrupt registers to save
+ *    -# Task level registers to save
  *
- *  Since RTEMS handles integer and floating point contexts separately, this
- *  means we have the following 3 context items:
+ * Since RTEMS handles integer and floating point contexts separately, this
+ * means we have the following 3 context items:
  *
- *     -# task level context stuff::  Context_Control
- *     -# floating point task stuff:: Context_Control_fp
- *     -# special interrupt level context :: CPU_Interrupt_frame
+ *    -# task level context stuff::  Context_Control
+ *    -# floating point task stuff:: Context_Control_fp
+ *    -# special interrupt level context :: CPU_Interrupt_frame
  *
- *  On some processors, it is cost-effective to save only the callee
- *  preserved registers during a task context switch.  This means
- *  that the ISR code needs to save those registers which do not
- *  persist across function calls.  It is not mandatory to make this
- *  distinctions between the caller/callee saves registers for the
- *  purpose of minimizing context saved during task switch and on interrupts.
- *  If the cost of saving extra registers is minimal, simplicity is the
- *  choice.  Save the same context on interrupt entry as for tasks in
- *  this case.
+ * On some processors, it is cost-effective to save only the callee
+ * preserved registers during a task context switch.  This means
+ * that the ISR code needs to save those registers which do not
+ * persist across function calls.  It is not mandatory to make this
+ * distinctions between the caller/callee saves registers for the
+ * purpose of minimizing context saved during task switch and on interrupts.
+ * If the cost of saving extra registers is minimal, simplicity is the
+ * choice.  Save the same context on interrupt entry as for tasks in
+ * this case.
  *
- *  Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
- *  care should be used in designing the context area.
+ * Additionally, if gdb is to be made aware of RTEMS tasks for this CPU, then
+ * care should be used in designing the context area.
  *
- *  On some CPUs with hardware floating point support, the Context_Control_fp
- *  structure will not be used or it simply consist of an array of a
- *  fixed number of bytes.   This is done when the floating point context
- *  is dumped by a "FP save context" type instruction and the format
- *  is not really defined by the CPU.  In this case, there is no need
- *  to figure out the exact format -- only the size.  Of course, although
- *  this is enough information for RTEMS, it is probably not enough for
- *  a debugger such as gdb.  But that is another problem.
+ * On some CPUs with hardware floating point support, the Context_Control_fp
+ * structure will not be used or it simply consist of an array of a
+ * fixed number of bytes.   This is done when the floating point context
+ * is dumped by a "FP save context" type instruction and the format
+ * is not really defined by the CPU.  In this case, there is no need
+ * to figure out the exact format -- only the size.  Of course, although
+ * this is enough information for RTEMS, it is probably not enough for
+ * a debugger such as gdb.  But that is another problem.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  On the v850, this port saves special registers and those that are
- *  callee saved.
+ * On the v850, this port saves special registers and those that are
+ * callee saved.
  */
+/**@{**/
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the minimal set of integer and processor state registers
- *  that must be saved during a voluntary context switch from one thread
- *  to another.
+ * This defines the minimal set of integer and processor state registers
+ * that must be saved during a voluntary context switch from one thread
+ * to another.
  */
 typedef struct {
     uint32_t   r1;
@@ -461,21 +463,18 @@ typedef struct {
 } Context_Control;
 
 /**
- *  @ingroup CPUContext Management
- *
- *  This macro returns the stack pointer associated with @a _context.
+ * This macro returns the stack pointer associated with @a _context.
  *
- *  @param[in] _context is the thread context area to access
+ * @param[in] _context is the thread context area to access
  *
- *  @return This method returns the stack pointer.
+ * @return This method returns the stack pointer.
  */
 #define _CPU_Context_Get_SP( _context ) \
   (_context)->r3_stack_pointer
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the complete set of floating point registers that must
- *  be saved during any context switch from one thread to another.
+ * This defines the complete set of floating point registers that must
+ * be saved during any context switch from one thread to another.
  */
 typedef struct {
     /** FPU registers are listed here */
@@ -483,62 +482,64 @@ typedef struct {
 } Context_Control_fp;
 
 /**
- *  @ingroup CPUContext Management
- *  This defines the set of integer and processor state registers that must
- *  be saved during an interrupt.  This set does not include any which are
- *  in @ref Context_Control.
+ * This defines the set of integer and processor state registers that must
+ * be saved during an interrupt.  This set does not include any which are
+ * in @ref Context_Control.
  */
 typedef struct {
     /** This field is a hint that a port will have a number of integer
-     *  registers that need to be saved when an interrupt occurs or
-     *  when a context switch occurs at the end of an ISR.
+     * registers that need to be saved when an interrupt occurs or
+     * when a context switch occurs at the end of an ISR.
      */
     uint32_t   special_interrupt_register;
 } CPU_Interrupt_frame;
 
+/** @} */
+
 /**
- *  @defgroup CPUInterrupt Processor Dependent Interrupt Management
+ * @defgroup CPUInterrupt Processor Dependent Interrupt Management
  *
- *  On some CPUs, RTEMS supports a software managed interrupt stack.
- *  This stack is allocated by the Interrupt Manager and the switch
- *  is performed in @ref _ISR_Handler.  These variables contain pointers
- *  to the lowest and highest addresses in the chunk of memory allocated
- *  for the interrupt stack.  Since it is unknown whether the stack
- *  grows up or down (in general), this give the CPU dependent
- *  code the option of picking the version it wants to use.
+ * On some CPUs, RTEMS supports a software managed interrupt stack.
+ * This stack is allocated by the Interrupt Manager and the switch
+ * is performed in @ref _ISR_Handler.  These variables contain pointers
+ * to the lowest and highest addresses in the chunk of memory allocated
+ * for the interrupt stack.  Since it is unknown whether the stack
+ * grows up or down (in general), this give the CPU dependent
+ * code the option of picking the version it wants to use.
  *
- *  @note These two variables are required if the macro
- *        @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
+ * @note These two variables are required if the macro
+ *       @ref CPU_HAS_SOFTWARE_INTERRUPT_STACK is defined as TRUE.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
+/**@{**/
 
 /**
- *  @ingroup CPUContext
- *  The size of the floating point context area.  On some CPUs this
- *  will not be a "sizeof" because the format of the floating point
- *  area is not defined -- only the size is.  This is usually on
- *  CPUs with a "floating point save context" instruction.
+ * @ingroup CPUContext
+ * The size of the floating point context area.  On some CPUs this
+ * will not be a "sizeof" because the format of the floating point
+ * area is not defined -- only the size is.  This is usually on
+ * CPUs with a "floating point save context" instruction.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 does not need a floating point context but this needs to be
- *  defined so confdefs.h.
+ * The v850 does not need a floating point context but this needs to be
+ * defined so confdefs.h.
  */
 /* #define CPU_CONTEXT_FP_SIZE sizeof( Context_Control_fp ) */
 #define CPU_CONTEXT_FP_SIZE 0
 
 /**
- *  Amount of extra stack (above minimum stack size) required by
- *  MPCI receive server thread.  Remember that in a multiprocessor
- *  system this thread must exist and be able to process all directives.
+ * Amount of extra stack (above minimum stack size) required by
+ * MPCI receive server thread.  Remember that in a multiprocessor
+ * system this thread must exist and be able to process all directives.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  There is no reason to think the v850 needs extra MPCI receive
- *  server stack.
+ * There is no reason to think the v850 needs extra MPCI receive
+ * server stack.
  */
 #define CPU_MPCI_RECEIVE_SERVER_EXTRA_STACK 0
 
@@ -546,109 +547,108 @@ typedef struct {
 /* XXX evaluate removing it */
 #if 0
 /**
- *  @ingroup CPUInterrupt
- *  This defines the number of entries in the @ref _ISR_Vector_table managed
- *  by RTEMS.
+ * This defines the number of entries in the @ref _ISR_Vector_table managed
+ * by RTEMS.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      32
 #endif
 
 /**
- *  @ingroup CPUInterrupt
- *  This defines the highest interrupt vector number for this port.
+ * This defines the highest interrupt vector number for this port.
  */
 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
 
 /**
- *  @ingroup CPUInterrupt
- *  This is defined if the port has a special way to report the ISR nesting
- *  level.  Most ports maintain the variable @a _ISR_Nest_level.
+ * This is defined if the port has a special way to report the ISR nesting
+ * level.  Most ports maintain the variable @a _ISR_Nest_level.
  */
 #define CPU_PROVIDES_ISR_IS_IN_PROGRESS FALSE
 
+/** @} */
+
 /**
- *  @ingroup CPUContext
- *  Should be large enough to run all RTEMS tests.  This ensures
- *  that a "reasonable" small application should not have any problems.
+ * @ingroup CPUContext
+ * Should be large enough to run all RTEMS tests.  This ensures
+ * that a "reasonable" small application should not have any problems.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  This should be very conservative on the v850.
+ * This should be very conservative on the v850.
  */
 #define CPU_STACK_MINIMUM_SIZE          (1024*4)
 
 #define CPU_SIZEOF_POINTER 4
 
 /**
- *  CPU's worst alignment requirement for data types on a byte boundary.  This
- *  alignment does not take into account the requirements for the stack.
+ * CPU's worst alignment requirement for data types on a byte boundary.  This
+ * alignment does not take into account the requirements for the stack.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  There is no apparent reason why this should be larger than 8.
+ * There is no apparent reason why this should be larger than 8.
  */
 #define CPU_ALIGNMENT              8
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  heap handler.  This alignment requirement may be stricter than that
- *  for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
- *  common for the heap to follow the same alignment requirement as
- *  @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
- *  the heap, then this should be set to @ref CPU_ALIGNMENT.
- *
- *  @note  This does not have to be a power of 2 although it should be
- *         a multiple of 2 greater than or equal to 2.  The requirement
- *         to be a multiple of 2 is because the heap uses the least
- *         significant field of the front and back flags to indicate
- *         that a block is in use or free.  So you do not want any odd
- *         length blocks really putting length data in that bit.
- *
- *         On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
- *         have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
- *         elements allocated from the heap meet all restrictions.
- *
- *  Port Specific Information:
- *
- *  There is no apparent reason why this should be larger than CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for the
+ * heap handler.  This alignment requirement may be stricter than that
+ * for the data types alignment specified by @ref CPU_ALIGNMENT.  It is
+ * common for the heap to follow the same alignment requirement as
+ * @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is strict enough for
+ * the heap, then this should be set to @ref CPU_ALIGNMENT.
+ *
+ * @note  This does not have to be a power of 2 although it should be
+ *        a multiple of 2 greater than or equal to 2.  The requirement
+ *        to be a multiple of 2 is because the heap uses the least
+ *        significant field of the front and back flags to indicate
+ *        that a block is in use or free.  So you do not want any odd
+ *        length blocks really putting length data in that bit.
+ *
+ *        On byte oriented architectures, @ref CPU_HEAP_ALIGNMENT normally will
+ *        have to be greater or equal to than @ref CPU_ALIGNMENT to ensure that
+ *        elements allocated from the heap meet all restrictions.
+ *
+ * Port Specific Information:
+ *
+ * There is no apparent reason why this should be larger than CPU_ALIGNMENT.
  */
 #define CPU_HEAP_ALIGNMENT         CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for memory
- *  buffers allocated by the partition manager.  This alignment requirement
- *  may be stricter than that for the data types alignment specified by
- *  @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
- *  alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
- *  strict enough for the partition, then this should be set to
- *  @ref CPU_ALIGNMENT.
+ * This number corresponds to the byte alignment requirement for memory
+ * buffers allocated by the partition manager.  This alignment requirement
+ * may be stricter than that for the data types alignment specified by
+ * @ref CPU_ALIGNMENT.  It is common for the partition to follow the same
+ * alignment requirement as @ref CPU_ALIGNMENT.  If the @ref CPU_ALIGNMENT is
+ * strict enough for the partition, then this should be set to
+ * @ref CPU_ALIGNMENT.
  *
- *  @note  This does not have to be a power of 2.  It does have to
- *         be greater or equal to than @ref CPU_ALIGNMENT.
+ * @note  This does not have to be a power of 2.  It does have to
+ *        be greater or equal to than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  There is no apparent reason why this should be larger than CPU_ALIGNMENT.
+ * There is no apparent reason why this should be larger than CPU_ALIGNMENT.
  */
 #define CPU_PARTITION_ALIGNMENT    CPU_ALIGNMENT
 
 /**
- *  This number corresponds to the byte alignment requirement for the
- *  stack.  This alignment requirement may be stricter than that for the
- *  data types alignment specified by @ref CPU_ALIGNMENT.  If the
- *  @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
- *  set to 0.
+ * This number corresponds to the byte alignment requirement for the
+ * stack.  This alignment requirement may be stricter than that for the
+ * data types alignment specified by @ref CPU_ALIGNMENT.  If the
+ * @ref CPU_ALIGNMENT is strict enough for the stack, then this should be
+ * set to 0.
  *
- *  @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
+ * @note This must be a power of 2 either 0 or greater than @ref CPU_ALIGNMENT.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 has enough RAM where alignment to 16 may be desirable depending
- *  on the cache properties. But this remains to be demonstrated.
+ * The v850 has enough RAM where alignment to 16 may be desirable depending
+ * on the cache properties. But this remains to be demonstrated.
  */
 #define CPU_STACK_ALIGNMENT        4
 
@@ -657,15 +657,19 @@ typedef struct {
  */
 
 /**
- *  @ingroup CPUInterrupt
- *  Disable all interrupts for an RTEMS critical section.  The previous
- *  level is returned in @a _isr_cookie.
+ * @addtogroup CPUInterrupt
+ */
+/**@{**/
+
+/**
+ * Disable all interrupts for an RTEMS critical section.  The previous
+ * level is returned in @a _isr_cookie.
  *
- *  @param[out] _isr_cookie will contain the previous level cookie
+ * @param[out] _isr_cookie will contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  On the v850, we need to save the PSW and use "di" to disable interrupts.
+ * On the v850, we need to save the PSW and use "di" to disable interrupts.
  */
 #define _CPU_ISR_Disable( _isr_cookie ) \
   do { \
@@ -677,16 +681,15 @@ typedef struct {
   } while (0)
 
 /**
- *  @ingroup CPUInterrupt
- *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
- *  This indicates the end of an RTEMS critical section.  The parameter
- *  @a _isr_cookie is not modified.
+ * Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
+ * This indicates the end of an RTEMS critical section.  The parameter
+ * @a _isr_cookie is not modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  On the v850, we simply need to restore the PSW.
+ * On the v850, we simply need to restore the PSW.
  */
 #define _CPU_ISR_Enable( _isr_cookie )  \
   do { \
@@ -696,17 +699,16 @@ typedef struct {
   } while (0)
 
 /**
- *  @ingroup CPUInterrupt
- *  This temporarily restores the interrupt to @a _isr_cookie before immediately
- *  disabling them again.  This is used to divide long RTEMS critical
- *  sections into two or more parts.  The parameter @a _isr_cookie is not
- *  modified.
+ * This temporarily restores the interrupt to @a _isr_cookie before immediately
+ * disabling them again.  This is used to divide long RTEMS critical
+ * sections into two or more parts.  The parameter @a _isr_cookie is not
+ * modified.
  *
- *  @param[in] _isr_cookie contain the previous level cookie
+ * @param[in] _isr_cookie contain the previous level cookie
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  This saves at least one instruction over using enable/disable back to back.
+ * This saves at least one instruction over using enable/disable back to back.
  */
 #define _CPU_ISR_Flash( _isr_cookie ) \
   do { \
@@ -716,21 +718,19 @@ typedef struct {
   } while (0)
 
 /**
- *  @ingroup CPUInterrupt
- *
- *  This routine and @ref _CPU_ISR_Get_level
- *  Map the interrupt level in task mode onto the hardware that the CPU
- *  actually provides.  Currently, interrupt levels which do not
- *  map onto the CPU in a generic fashion are undefined.  Someday,
- *  it would be nice if these were "mapped" by the application
- *  via a callout.  For example, m68k has 8 levels 0 - 7, levels
- *  8 - 255 would be available for bsp/application specific meaning.
- *  This could be used to manage a programmable interrupt controller
- *  via the rtems_task_mode directive.
- *
- *  Port Specific Information:
- *
- *  On the v850, level 0 is enabled. Non-zero is disabled.
+ * This routine and @ref _CPU_ISR_Get_level
+ * Map the interrupt level in task mode onto the hardware that the CPU
+ * actually provides.  Currently, interrupt levels which do not
+ * map onto the CPU in a generic fashion are undefined.  Someday,
+ * it would be nice if these were "mapped" by the application
+ * via a callout.  For example, m68k has 8 levels 0 - 7, levels
+ * 8 - 255 would be available for bsp/application specific meaning.
+ * This could be used to manage a programmable interrupt controller
+ * via the rtems_task_mode directive.
+ *
+ * Port Specific Information:
+ *
+ * On the v850, level 0 is enabled. Non-zero is disabled.
  */
 #define _CPU_ISR_Set_level( new_level ) \
   do { \
@@ -741,52 +741,53 @@ typedef struct {
   } while (0)
 
 /**
- *  @ingroup CPUInterrupt
- *  Return the current interrupt disable level for this task in
- *  the format used by the interrupt level portion of the task mode.
+ * Return the current interrupt disable level for this task in
+ * the format used by the interrupt level portion of the task mode.
  *
- *  @note This routine usually must be implemented as a subroutine.
+ * @note This routine usually must be implemented as a subroutine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  This method is implemented in C on the v850.
+ * This method is implemented in C on the v850.
  */
 uint32_t   _CPU_ISR_Get_level( void );
 
 /* end of ISR handler macros */
 
+/** @} */
+
 /* Context handler macros */
 
 /**
- *  @ingroup CPUContext
- *  Initialize the context to a state suitable for starting a
- *  task after a context restore operation.  Generally, this
- *  involves:
- *
- *     - setting a starting address
- *     - preparing the stack
- *     - preparing the stack and frame pointers
- *     - setting the proper interrupt level in the context
- *     - initializing the floating point context
- *
- *  This routine generally does not set any unnecessary register
- *  in the context.  The state of the "general data" registers is
- *  undefined at task start time.
- *
- *  @param[in] _the_context is the context structure to be initialized
- *  @param[in] _stack_base is the lowest physical address of this task's stack
- *  @param[in] _size is the size of this task's stack
- *  @param[in] _isr is the interrupt disable level
- *  @param[in] _entry_point is the thread's entry point.  This is
- *         always @a _Thread_Handler
- *  @param[in] _is_fp is TRUE if the thread is to be a floating
- *        point thread.  This is typically only used on CPUs where the
- *        FPU may be easily disabled by software such as on the SPARC
- *        where the PSR contains an enable FPU bit.
- *
- *  Port Specific Information:
- *
- *  This method is implemented in C on the v850.
+ * @ingroup CPUContext
+ * Initialize the context to a state suitable for starting a
+ * task after a context restore operation.  Generally, this
+ * involves:
+ *
+ *    - setting a starting address
+ *    - preparing the stack
+ *    - preparing the stack and frame pointers
+ *    - setting the proper interrupt level in the context
+ *    - initializing the floating point context
+ *
+ * This routine generally does not set any unnecessary register
+ * in the context.  The state of the "general data" registers is
+ * undefined at task start time.
+ *
+ * @param[in] _the_context is the context structure to be initialized
+ * @param[in] _stack_base is the lowest physical address of this task's stack
+ * @param[in] _size is the size of this task's stack
+ * @param[in] _isr is the interrupt disable level
+ * @param[in] _entry_point is the thread's entry point.  This is
+ *        always @a _Thread_Handler
+ * @param[in] _is_fp is TRUE if the thread is to be a floating
+ *       point thread.  This is typically only used on CPUs where the
+ *       FPU may be easily disabled by software such as on the SPARC
+ *       where the PSR contains an enable FPU bit.
+ *
+ * Port Specific Information:
+ *
+ * This method is implemented in C on the v850.
  */
 void _CPU_Context_Initialize(
   Context_Control  *the_context,
@@ -798,19 +799,19 @@ void _CPU_Context_Initialize(
 );
 
 /**
- *  This routine is responsible for somehow restarting the currently
- *  executing task.  If you are lucky, then all that is necessary
- *  is restoring the context.  Otherwise, there will need to be
- *  a special assembly routine which does something special in this
- *  case.  For many ports, simply adding a label to the restore path
- *  of @ref _CPU_Context_switch will work.  On other ports, it may be
- *  possibly to load a few arguments and jump to the restore path. It will
- *  not work if restarting self conflicts with the stack frame
- *  assumptions of restoring a context.
- *
- *  Port Specific Information:
- *
- *  On the v850, we require a special entry point to restart a task.
+ * This routine is responsible for somehow restarting the currently
+ * executing task.  If you are lucky, then all that is necessary
+ * is restoring the context.  Otherwise, there will need to be
+ * a special assembly routine which does something special in this
+ * case.  For many ports, simply adding a label to the restore path
+ * of @ref _CPU_Context_switch will work.  On other ports, it may be
+ * possibly to load a few arguments and jump to the restore path. It will
+ * not work if restarting self conflicts with the stack frame
+ * assumptions of restoring a context.
+ *
+ * Port Specific Information:
+ *
+ * On the v850, we require a special entry point to restart a task.
  */
 #define _CPU_Context_Restart_self( _the_context ) \
    _CPU_Context_restore( (_the_context) );
@@ -818,26 +819,26 @@ void _CPU_Context_Initialize(
 /* XXX this should be possible to remove */
 #if 0
 /**
- *  @ingroup CPUContext
- *  The purpose of this macro is to allow the initial pointer into
- *  a floating point context area (used to save the floating point
- *  context) to be at an arbitrary place in the floating point
- *  context area.
- *
- *  This is necessary because some FP units are designed to have
- *  their context saved as a stack which grows into lower addresses.
- *  Other FP units can be saved by simply moving registers into offsets
- *  from the base of the context area.  Finally some FP units provide
- *  a "dump context" instruction which could fill in from high to low
- *  or low to high based on the whim of the CPU designers.
- *
- *  @param[in] _base is the lowest physical address of the floating point
- *         context area
- *  @param[in] _offset is the offset into the floating point area
- *
- *  Port Specific Information:
- *
- *  XXX document implementation including references if appropriate
+ * @ingroup CPUContext
+ * The purpose of this macro is to allow the initial pointer into
+ * a floating point context area (used to save the floating point
+ * context) to be at an arbitrary place in the floating point
+ * context area.
+ *
+ * This is necessary because some FP units are designed to have
+ * their context saved as a stack which grows into lower addresses.
+ * Other FP units can be saved by simply moving registers into offsets
+ * from the base of the context area.  Finally some FP units provide
+ * a "dump context" instruction which could fill in from high to low
+ * or low to high based on the whim of the CPU designers.
+ *
+ * @param[in] _base is the lowest physical address of the floating point
+ *        context area
+ * @param[in] _offset is the offset into the floating point area
+ *
+ * Port Specific Information:
+ *
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Fp_start( _base, _offset ) \
    ( (void *) _Addresses_Add_offset( (_base), (_offset) ) )
@@ -846,22 +847,22 @@ void _CPU_Context_Initialize(
 /* XXX this should be possible to remove */
 #if 0
 /**
- *  This routine initializes the FP context area passed to it to.
- *  There are a few standard ways in which to initialize the
- *  floating point context.  The code included for this macro assumes
- *  that this is a CPU in which a "initial" FP context was saved into
- *  @a _CPU_Null_fp_context and it simply copies it to the destination
- *  context passed to it.
+ * This routine initializes the FP context area passed to it to.
+ * There are a few standard ways in which to initialize the
+ * floating point context.  The code included for this macro assumes
+ * that this is a CPU in which a "initial" FP context was saved into
+ * @a _CPU_Null_fp_context and it simply copies it to the destination
+ * context passed to it.
  *
- *  Other floating point context save/restore models include:
- *    -# not doing anything, and
- *    -# putting a "null FP status word" in the correct place in the FP context.
+ * Other floating point context save/restore models include:
+ *   -# not doing anything, and
+ *   -# putting a "null FP status word" in the correct place in the FP context.
  *
- *  @param[in] _destination is the floating point context area
+ * @param[in] _destination is the floating point context area
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 #define _CPU_Context_Initialize_fp( _destination ) \
   { \
@@ -873,13 +874,13 @@ void _CPU_Context_Initialize(
 /* Fatal Error manager macros */
 
 /**
- *  This routine copies _error into a known place -- typically a stack
- *  location or a register, optionally disables interrupts, and
- *  halts/stops the CPU.
+ * This routine copies _error into a known place -- typically a stack
+ * location or a register, optionally disables interrupts, and
+ * halts/stops the CPU.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  Move the error code into r10, disable interrupts and halt.
+ * Move the error code into r10, disable interrupts and halt.
  */
 #define _CPU_Fatal_halt( _error ) \
   do { \
@@ -893,75 +894,73 @@ void _CPU_Context_Initialize(
 /* Bitfield handler macros */
 
 /**
- *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
+ * @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
  *
- *  This set of routines are used to implement fast searches for
- *  the most important ready task.
+ * This set of routines are used to implement fast searches for
+ * the most important ready task.
  */
+/**@{**/
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the generic bitfield
- *  manipulation implementation.
+ * This definition is set to TRUE if the port uses the generic bitfield
+ * manipulation implementation.
  */
 #define CPU_USE_GENERIC_BITFIELD_CODE TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This definition is set to TRUE if the port uses the data tables provided
- *  by the generic bitfield manipulation implementation.
- *  This can occur when actually using the generic bitfield manipulation
- *  implementation or when implementing the same algorithm in assembly
- *  language for improved performance.  It is unlikely that a port will use
- *  the data if it has a bitfield scan instruction.
- *
- *  Port Specific Information:
- *
- *  There is no single v850 instruction to do a bit scan so there is
- *  no CPU specific implementation of bit field scanning. The empty
- *  stub routines are left as a place holder in case someone figures
- *  out how to do a v850 implementation better than the generic algorithm.
+ * This definition is set to TRUE if the port uses the data tables provided
+ * by the generic bitfield manipulation implementation.
+ * This can occur when actually using the generic bitfield manipulation
+ * implementation or when implementing the same algorithm in assembly
+ * language for improved performance.  It is unlikely that a port will use
+ * the data if it has a bitfield scan instruction.
+ *
+ * Port Specific Information:
+ *
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning. The empty
+ * stub routines are left as a place holder in case someone figures
+ * out how to do a v850 implementation better than the generic algorithm.
  */
 #define CPU_USE_GENERIC_BITFIELD_DATA TRUE
 
 /**
- *  @ingroup CPUBitfield
- *  This routine sets @a _output to the bit number of the first bit
- *  set in @a _value.  @a _value is of CPU dependent type
- *  @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
- *  wide although only the 16 least significant bits will be used.
- *
- *  There are a number of variables in using a "find first bit" type
- *  instruction.
- *
- *    -# What happens when run on a value of zero?
- *    -# Bits may be numbered from MSB to LSB or vice-versa.
- *    -# The numbering may be zero or one based.
- *    -# The "find first bit" instruction may search from MSB or LSB.
- *
- *  RTEMS guarantees that (1) will never happen so it is not a concern.
- *  (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
- *  @ref _CPU_Priority_bits_index.  These three form a set of routines
- *  which must logically operate together.  Bits in the _value are
- *  set and cleared based on masks built by @ref _CPU_Priority_Mask.
- *  The basic major and minor values calculated by @ref _Priority_Major
- *  and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
- *  to properly range between the values returned by the "find first bit"
- *  instruction.  This makes it possible for @ref _Priority_Get_highest to
- *  calculate the major and directly index into the minor table.
- *  This mapping is necessary to ensure that 0 (a high priority major/minor)
- *  is the first bit found.
- *
- *  This entire "find first bit" and mapping process depends heavily
- *  on the manner in which a priority is broken into a major and minor
- *  components with the major being the 4 MSB of a priority and minor
- *  the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
- *  priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
- *  to the lowest priority.
- *
- *  If your CPU does not have a "find first bit" instruction, then
- *  there are ways to make do without it.  Here are a handful of ways
- *  to implement this in software:
+ * This routine sets @a _output to the bit number of the first bit
+ * set in @a _value.  @a _value is of CPU dependent type
+ * @a Priority_bit_map_Control.  This type may be either 16 or 32 bits
+ * wide although only the 16 least significant bits will be used.
+ *
+ * There are a number of variables in using a "find first bit" type
+ * instruction.
+ *
+ *   -# What happens when run on a value of zero?
+ *   -# Bits may be numbered from MSB to LSB or vice-versa.
+ *   -# The numbering may be zero or one based.
+ *   -# The "find first bit" instruction may search from MSB or LSB.
+ *
+ * RTEMS guarantees that (1) will never happen so it is not a concern.
+ * (2),(3), (4) are handled by the macros @ref _CPU_Priority_Mask and
+ * @ref _CPU_Priority_bits_index.  These three form a set of routines
+ * which must logically operate together.  Bits in the _value are
+ * set and cleared based on masks built by @ref _CPU_Priority_Mask.
+ * The basic major and minor values calculated by @ref _Priority_Major
+ * and @ref _Priority_Minor are "massaged" by @ref _CPU_Priority_bits_index
+ * to properly range between the values returned by the "find first bit"
+ * instruction.  This makes it possible for @ref _Priority_Get_highest to
+ * calculate the major and directly index into the minor table.
+ * This mapping is necessary to ensure that 0 (a high priority major/minor)
+ * is the first bit found.
+ *
+ * This entire "find first bit" and mapping process depends heavily
+ * on the manner in which a priority is broken into a major and minor
+ * components with the major being the 4 MSB of a priority and minor
+ * the 4 LSB.  Thus (0 << 4) + 0 corresponds to priority 0 -- the highest
+ * priority.  And (15 << 4) + 14 corresponds to priority 254 -- the next
+ * to the lowest priority.
+ *
+ * If your CPU does not have a "find first bit" instruction, then
+ * there are ways to make do without it.  Here are a handful of ways
+ * to implement this in software:
  *
 @verbatim
       - a series of 16 bit test instructions
@@ -978,16 +977,16 @@ void _CPU_Context_Initialize(
         _number += bit_set_table[ _value ]
 @endverbatim
 
- *    where bit_set_table[ 16 ] has values which indicate the first
- *      bit set
+ *   where bit_set_table[ 16 ] has values which indicate the first
+ *     bit set
  *
- *  @param[in] _value is the value to be scanned
- *  @param[in] _output is the first bit set
+ * @param[in] _value is the value to be scanned
+ * @param[in] _output is the first bit set
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  There is no single v850 instruction to do a bit scan so there is
- *  no CPU specific implementation of bit field scanning.
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning.
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 #define _CPU_Bitfield_Find_first_bit( _value, _output ) \
@@ -999,14 +998,14 @@ void _CPU_Context_Initialize(
 /* end of Bitfield handler macros */
 
 /**
- *  This routine builds the mask which corresponds to the bit fields
- *  as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
- *  for that routine.
+ * This routine builds the mask which corresponds to the bit fields
+ * as searched by @ref _CPU_Bitfield_Find_first_bit.  See the discussion
+ * for that routine.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  There is no single v850 instruction to do a bit scan so there is
- *  no CPU specific implementation of bit field scanning.
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning.
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1016,18 +1015,17 @@ void _CPU_Context_Initialize(
 #endif
 
 /**
- *  @ingroup CPUBitfield
- *  This routine translates the bit numbers returned by
- *  @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
- *  a major or minor component of a priority.  See the discussion
- *  for that routine.
+ * This routine translates the bit numbers returned by
+ * @ref _CPU_Bitfield_Find_first_bit into something suitable for use as
+ * a major or minor component of a priority.  See the discussion
+ * for that routine.
  *
- *  @param[in] _priority is the major or minor number to translate
+ * @param[in] _priority is the major or minor number to translate
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  There is no single v850 instruction to do a bit scan so there is
- *  no CPU specific implementation of bit field scanning.
+ * There is no single v850 instruction to do a bit scan so there is
+ * no CPU specific implementation of bit field scanning.
  */
 #if (CPU_USE_GENERIC_BITFIELD_CODE == FALSE)
 
@@ -1038,30 +1036,36 @@ void _CPU_Context_Initialize(
 
 /* end of Priority handler macros */
 
+/** @} */
+
 /* functions */
 
 /**
- *  @brief CPU Initialize
- *  This routine performs CPU dependent initialization.
+ * @brief CPU initialize.
+ * This routine performs CPU dependent initialization.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  This is implemented in C.
+ * This is implemented in C.
  *
- *  v850 CPU Dependent Source
+ * v850 CPU Dependent Source
  */
 void _CPU_Initialize(void);
 
 /**
- *  @ingroup CPUContext
- *  This routine switches from the run context to the heir context.
+ * @addtogroup CPUContext
+ */
+/**@{**/
+
+/**
+ * This routine switches from the run context to the heir context.
  *
- *  @param[in] run points to the context of the currently executing task
- *  @param[in] heir points to the context of the heir task
+ * @param[in] run points to the context of the currently executing task
+ * @param[in] heir points to the context of the heir task
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  This is implemented in assembly on the v850.
+ * This is implemented in assembly on the v850.
  */
 void _CPU_Context_switch(
   Context_Control  *run,
@@ -1069,17 +1073,16 @@ void _CPU_Context_switch(
 );
 
 /**
- *  @ingroup CPUContext
- *  This routine is generally used only to restart self in an
- *  efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
+ * This routine is generally used only to restart self in an
+ * efficient manner.  It may simply be a label in @ref _CPU_Context_switch.
  *
- *  @param[in] new_context points to the context to be restored.
+ * @param[in] new_context points to the context to be restored.
  *
- *  @note May be unnecessary to reload some registers.
+ * @note May be unnecessary to reload some registers.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  This is implemented in assembly on the v850.
+ * This is implemented in assembly on the v850.
  */
 void _CPU_Context_restore(
   Context_Control *new_context
@@ -1088,18 +1091,17 @@ void _CPU_Context_restore(
 /* XXX this should be possible to remove */
 #if 0
 /**
- *  @ingroup CPUContext
- *  This routine saves the floating point context passed to it.
+ * This routine saves the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
- *  point context area
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area
  *
- *  @return on output @a *fp_context_ptr will contain the address that
- *  should be used with @ref _CPU_Context_restore_fp to restore this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_restore_fp to restore this context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_save_fp(
   Context_Control_fp **fp_context_ptr
@@ -1109,56 +1111,57 @@ void _CPU_Context_save_fp(
 /* XXX this should be possible to remove */
 #if 0
 /**
- *  @ingroup CPUContext
- *  This routine restores the floating point context passed to it.
+ * This routine restores the floating point context passed to it.
  *
- *  @param[in] fp_context_ptr is a pointer to a pointer to a floating
- *  point context area to restore
+ * @param[in] fp_context_ptr is a pointer to a pointer to a floating
+ * point context area to restore
  *
- *  @return on output @a *fp_context_ptr will contain the address that
- *  should be used with @ref _CPU_Context_save_fp to save this context.
+ * @return on output @a *fp_context_ptr will contain the address that
+ * should be used with @ref _CPU_Context_save_fp to save this context.
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  XXX document implementation including references if appropriate
+ * XXX document implementation including references if appropriate
  */
 void _CPU_Context_restore_fp(
   Context_Control_fp **fp_context_ptr
 );
 #endif
 
+/** @} */
+
 /* FIXME */
 typedef CPU_Interrupt_frame CPU_Exception_frame;
 
 void _CPU_Exception_frame_print( const CPU_Exception_frame *frame );
 
 /**
- *  @ingroup CPUEndian
- *  The following routine swaps the endian format of an unsigned int.
- *  It must be static because it is referenced indirectly.
+ * @ingroup CPUEndian
+ * The following routine swaps the endian format of an unsigned int.
+ * It must be static because it is referenced indirectly.
  *
- *  This version will work on any processor, but if there is a better
- *  way for your CPU PLEASE use it.  The most common way to do this is to:
+ * This version will work on any processor, but if there is a better
+ * way for your CPU PLEASE use it.  The most common way to do this is to:
  *
- *     swap least significant two bytes with 16-bit rotate
- *     swap upper and lower 16-bits
- *     swap most significant two bytes with 16-bit rotate
+ *    swap least significant two bytes with 16-bit rotate
+ *    swap upper and lower 16-bits
+ *    swap most significant two bytes with 16-bit rotate
  *
- *  Some CPUs have special instructions which swap a 32-bit quantity in
- *  a single instruction (e.g. i486).  It is probably best to avoid
- *  an "endian swapping control bit" in the CPU.  One good reason is
- *  that interrupts would probably have to be disabled to ensure that
- *  an interrupt does not try to access the same "chunk" with the wrong
- *  endian.  Another good reason is that on some CPUs, the endian bit
- *  endianness for ALL fetches -- both code and data -- so the code
- *  will be fetched incorrectly.
+ * Some CPUs have special instructions which swap a 32-bit quantity in
+ * a single instruction (e.g. i486).  It is probably best to avoid
+ * an "endian swapping control bit" in the CPU.  One good reason is
+ * that interrupts would probably have to be disabled to ensure that
+ * an interrupt does not try to access the same "chunk" with the wrong
+ * endian.  Another good reason is that on some CPUs, the endian bit
+ * endianness for ALL fetches -- both code and data -- so the code
+ * will be fetched incorrectly.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 has a single instruction to swap endianness on a 32 bit quantity.
+ * The v850 has a single instruction to swap endianness on a 32 bit quantity.
  */
 static inline uint32_t CPU_swap_u32(
   uint32_t value
@@ -1185,15 +1188,15 @@ static inline uint32_t CPU_swap_u32(
 }
 
 /**
- *  @ingroup CPUEndian
- *  This routine swaps a 16 bir quantity.
+ * @ingroup CPUEndian
+ * This routine swaps a 16 bir quantity.
  *
- *  @param[in] value is the value to be swapped
- *  @return the value after being endian swapped
+ * @param[in] value is the value to be swapped
+ * @return the value after being endian swapped
  *
- *  Port Specific Information:
+ * Port Specific Information:
  *
- *  The v850 has a single instruction to swap endianness on a 16 bit quantity.
+ * The v850 has a single instruction to swap endianness on a 16 bit quantity.
  */
 static inline uint16_t CPU_swap_u16( uint16_t value )
 {
diff --git a/cpukit/score/cpu/v850/rtems/score/cpu_asm.h b/cpukit/score/cpu/v850/rtems/score/cpu_asm.h
index 49a44a93a1..bc22bc199b 100644
--- a/cpukit/score/cpu/v850/rtems/score/cpu_asm.h
+++ b/cpukit/score/cpu/v850/rtems/score/cpu_asm.h
@@ -1,11 +1,10 @@
 /**
- * @file rtems/score/cpu_asm.h
- */
-
-/*
- *  Very loose template for an include file for the cpu_asm.? file
- *  if it is implemented as a ".S" file (preprocessed by cpp) instead
- *  of a ".s" file (preprocessed by gm4 or gasp).
+ * @file
+ *
+ * @brief V850 Assembly File
+ * Very loose template for an include file for the cpu_asm.? file
+ * if it is implemented as a ".S" file (preprocessed by cpp) instead
+ * of a ".s" file (preprocessed by gm4 or gasp).
  */
 
 /*
diff --git a/cpukit/score/cpu/v850/rtems/score/types.h b/cpukit/score/cpu/v850/rtems/score/types.h
index 32ff881898..e831b2dc13 100644
--- a/cpukit/score/cpu/v850/rtems/score/types.h
+++ b/cpukit/score/cpu/v850/rtems/score/types.h
@@ -1,11 +1,13 @@
 /**
- * @file rtems/score/types.h
+ * @file
+ *
+ * @brief V850 CPU Type Definitions
+ *
+ * This include file contains type definitions pertaining to the
+ * v850 processor family.
  */
 
 /*
- *  This include file contains type definitions pertaining to the
- *  v850 processor family.
- *
  *  COPYRIGHT (c) 1989-2011.
  *  On-Line Applications Research Corporation (OAR).
  *
diff --git a/cpukit/score/cpu/v850/rtems/score/v850.h b/cpukit/score/cpu/v850/rtems/score/v850.h
index 3e9bec56f3..df35925c7b 100644
--- a/cpukit/score/cpu/v850/rtems/score/v850.h
+++ b/cpukit/score/cpu/v850/rtems/score/v850.h
@@ -1,8 +1,12 @@
-/*
- *  This file sets up basic CPU dependency settings based on
- *  compiler settings.  For example, it can determine if
- *  floating point is available.  This particular implementation
- *  is specified to the Renesas v850 port.
+/**
+ * @file
+ *
+ * @brief V850 Set up Basic CPU Dependency Settings Based on Compiler Settings
+ *
+ * This file sets up basic CPU dependency settings based on
+ * compiler settings.  For example, it can determine if
+ * floating point is available.  This particular implementation
+ * is specified to the Renesas v850 port.
  */
 
 /*
author	Joel Sherrill <joel.sherrill@oarcorp.com>	2013-02-02 15:19:01 -0600
committer	Joel Sherrill <joel.sherrill@oarcorp.com>	2013-02-02 15:19:01 -0600
commit	dd7b83550dfb73f5ec1b7dec3b21d730779ddeb2 (patch)
tree	3db0eac5b55ed5edcf985baed9f19736c931de47 /cpukit/score/cpu
parent	Merge branch 'master' of ssh://git.rtems.org/data/git/rtems (diff)
parent	fstests/fsrdwr: Free allocated memory (diff)
download	rtems-dd7b83550dfb73f5ec1b7dec3b21d730779ddeb2.tar.bz2