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author | Christian Mauderer <Christian.Mauderer@embedded-brains.de> | 2017-09-06 07:42:06 +0200 |
---|---|---|
committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2017-09-07 09:26:05 +0200 |
commit | f7f420e11ac4b01714a63a6d979a2c8e28b10d4f (patch) | |
tree | 892520a2ff1a17c96431975ac4a53a6540dc6bc1 | |
parent | Implement clock() (diff) | |
download | rtems-f7f420e11ac4b01714a63a6d979a2c8e28b10d4f.tar.bz2 |
bsp/atsam: Fix MPU sections.
The nocache section has been hard coded which could lead to problems
when a bigger region should be used. Fix that.
The internal SRAM has not been set up correctly. A duplicate external
SDRAM has been set up instead.
Remove a lot of other hard coded sections too.
3 files changed, 92 insertions, 4 deletions
diff --git a/c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_lowlevel.c b/c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_lowlevel.c index a13a3b312c..cbdf41ba73 100644 --- a/c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_lowlevel.c +++ b/c/src/lib/libbsp/arm/atsam/libraries/libboard/source/board_lowlevel.c @@ -92,18 +92,28 @@ void _SetupMemoryRegion(void) START_Addr:- 0x00000000UL END_Addr:- 0x003FFFFFUL ****************************************************/ + dwRegionBaseAddr = ITCM_START_ADDRESS | MPU_REGION_VALID | MPU_DEFAULT_ITCM_REGION; // 1 +#ifdef __rtems__ + if (ITCM_END_ADDRESS + 1 != ITCM_START_ADDRESS) { +#endif /* __rtems__ */ dwRegionAttr = MPU_AP_PRIVILEGED_READ_WRITE | MPU_CalMPURegionSize(ITCM_END_ADDRESS - ITCM_START_ADDRESS) | MPU_REGION_ENABLE; +#ifdef __rtems__ + } else { + dwRegionAttr = MPU_REGION_DISABLE; + } +#endif /* __rtems__ */ MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr); + /**************************************************** Internal flash memory region --- Normal read-only (update to Strongly ordered in write accesses) @@ -136,14 +146,23 @@ void _SetupMemoryRegion(void) MPU_REGION_VALID | MPU_DEFAULT_DTCM_REGION; //3 +#ifdef __rtems__ + if (DTCM_END_ADDRESS + 1 != DTCM_START_ADDRESS) { +#endif /* __rtems__ */ dwRegionAttr = MPU_AP_PRIVILEGED_READ_WRITE | INNER_NORMAL_NOCACHE_TYPE(NON_SHAREABLE) | MPU_CalMPURegionSize(DTCM_END_ADDRESS - DTCM_START_ADDRESS) | MPU_REGION_ENABLE; +#ifdef __rtems__ + } else { + dwRegionAttr = MPU_REGION_DISABLE; + } +#endif /* __rtems__ */ MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr); + /**************************************************** SRAM Cacheable memory region --- Normal START_Addr:- 0x20400000UL @@ -183,6 +202,12 @@ void _SetupMemoryRegion(void) MPU_REGION_ENABLE; MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr); +#else /* __rtems__ */ + /* NOTE: The first SRAM region is increased so it covers the whole SRAM. If + * the SRAM is something odd (like 384k on the SAME70Q21), the next higher + * power of two will be used (in the example: 512k). That removes the need of + * the second SRAM region. There is currently no memory after the SRAM so that + * shouldn't be a problem. */ #endif /* __rtems__ */ #ifdef MPU_HAS_NOCACHE_REGION @@ -218,6 +243,20 @@ void _SetupMemoryRegion(void) MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr); +#ifdef __rtems__ + dwRegionBaseAddr = + SYSTEM_START_ADDRESS | + MPU_REGION_VALID | + MPU_SYSTEM_REGION; + + dwRegionAttr = MPU_AP_FULL_ACCESS | + MPU_REGION_EXECUTE_NEVER | + SHAREABLE_DEVICE_TYPE | + MPU_CalMPURegionSize(SYSTEM_END_ADDRESS - SYSTEM_START_ADDRESS) + | MPU_REGION_ENABLE; + + MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr); +#endif /* __rtems__ */ /**************************************************** External EBI memory memory region --- Strongly Ordered @@ -267,11 +306,19 @@ void _SetupMemoryRegion(void) MPU_REGION_VALID | MPU_QSPIMEM_REGION; //8 +#ifdef __rtems__ + if (QSPI_END_ADDRESS + 1 != QSPI_START_ADDRESS) { +#endif /* __rtems__ */ dwRegionAttr = MPU_AP_FULL_ACCESS | INNER_NORMAL_WB_NWA_TYPE(SHAREABLE) | MPU_CalMPURegionSize(QSPI_END_ADDRESS - QSPI_START_ADDRESS) | MPU_REGION_ENABLE; +#ifdef __rtems__ + } else { + dwRegionAttr = MPU_REGION_DISABLE; + } +#endif /* __rtems__ */ MPU_SetRegion(dwRegionBaseAddr, dwRegionAttr); @@ -301,7 +348,11 @@ void _SetupMemoryRegion(void) | SCB_SHCSR_USGFAULTENA_Msk); /* Enable the MPU region */ +#ifndef __rtems__ MPU_Enable(MPU_ENABLE | MPU_PRIVDEFENA); +#else /* __rtems__ */ + MPU_Enable(MPU_ENABLE); +#endif /* __rtems__ */ memory_sync(); } diff --git a/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h b/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h index cef031aa4c..06f70d5d62 100644 --- a/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h +++ b/c/src/lib/libbsp/arm/atsam/libraries/libchip/include/mpu.h @@ -54,6 +54,7 @@ #if defined MPU_HAS_NOCACHE_REGION #define MPU_NOCACHE_SRAM_REGION (11) #endif +#define MPU_SYSTEM_REGION (12) #define MPU_REGION_VALID (0x10) #define MPU_REGION_ENABLE (0x01) @@ -101,10 +102,17 @@ */ /********* IFLASH memory macros *********************/ +#ifdef __rtems__ +#define ITCM_START_ADDRESS ((uintptr_t) atsam_memory_itcm_begin) +#define ITCM_END_ADDRESS ((uintptr_t) atsam_memory_itcm_end - 1) +#define IFLASH_START_ADDRESS ((uintptr_t) atsam_memory_intflash_begin) +#define IFLASH_END_ADDRESS ((uintptr_t) atsam_memory_intflash_end - 1) +#else /* !__rtems__ */ #define ITCM_START_ADDRESS 0x00000000UL #define ITCM_END_ADDRESS 0x003FFFFFUL #define IFLASH_START_ADDRESS 0x00400000UL #define IFLASH_END_ADDRESS 0x005FFFFFUL +#endif /* __rtems__ */ #define IFLASH_PRIVILEGE_START_ADDRESS (IFLASH_START_ADDRESS) @@ -114,24 +122,36 @@ #define IFLASH_UNPRIVILEGE_END_ADDRESS (IFLASH_END_ADDRESS) /**************** DTCM *******************************/ +#ifdef __rtems__ +#define DTCM_START_ADDRESS ((uintptr_t) atsam_memory_dtcm_begin) +#define DTCM_END_ADDRESS ((uintptr_t) atsam_memory_dtcm_end - 1) +#else /* !__rtems__ */ #define DTCM_START_ADDRESS 0x20000000UL #define DTCM_END_ADDRESS 0x203FFFFFUL +#endif /* __rtems__ */ /******* SRAM memory macros ***************************/ +#ifdef __rtems__ +#define SRAM_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin) +#define SRAM_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1) +#else /* !__rtems__ */ #define SRAM_START_ADDRESS 0x20400000UL #define SRAM_END_ADDRESS 0x2045FFFFUL +#endif /* __rtems__ */ +#ifndef __rtems__ #if defined MPU_HAS_NOCACHE_REGION #define NOCACHE_SRAM_REGION_SIZE 0x1000 #endif +#endif /* __rtems__ */ /* Regions should be a 2^(N+1) where 4 < N < 31 */ #ifdef __rtems__ -#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin) -#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1) -#else /* __rtems__ */ +#define SRAM_FIRST_START_ADDRESS ((uintptr_t) atsam_memory_intsram_begin) +#define SRAM_FIRST_END_ADDRESS ((uintptr_t) atsam_memory_intsram_end - 1) +#else /* !__rtems__ */ #define SRAM_FIRST_START_ADDRESS (SRAM_START_ADDRESS) #define SRAM_FIRST_END_ADDRESS (SRAM_FIRST_START_ADDRESS + 0x3FFFF) // (2^18) 256 KB #endif /* __rtems__ */ @@ -140,7 +160,8 @@ #ifdef __rtems__ #define SRAM_NOCACHE_START_ADDRESS ((uintptr_t) atsam_memory_nocache_begin) #define SRAM_NOCACHE_END_ADDRESS ((uintptr_t) atsam_memory_nocache_end - 1) -#else /* __rtems__ */ + #define NOCACHE_SRAM_REGION_SIZE (SRAM_NOCACHE_END_ADDRESS - SRAM_NOCACHE_START_ADDRESS) +#else /* !__rtems__ */ #define SRAM_SECOND_START_ADDRESS (SRAM_FIRST_END_ADDRESS+1) #define SRAM_SECOND_END_ADDRESS (SRAM_END_ADDRESS - NOCACHE_SRAM_REGION_SIZE) // (2^17) 128 - 0x1000 KB #define SRAM_NOCACHE_START_ADDRESS (SRAM_SECOND_END_ADDRESS + 1) @@ -155,18 +176,32 @@ /************** Peripherals memory region macros ********/ #define PERIPHERALS_START_ADDRESS 0x40000000UL #define PERIPHERALS_END_ADDRESS 0x5FFFFFFFUL +#ifdef __rtems__ +#define SYSTEM_START_ADDRESS 0xE0000000UL +#define SYSTEM_END_ADDRESS 0xFFFFFFFFUL +#endif /* __rtems__ */ /******* Ext EBI memory macros ***************************/ #define EXT_EBI_START_ADDRESS 0x60000000UL #define EXT_EBI_END_ADDRESS 0x6FFFFFFFUL /******* Ext-SRAM memory macros ***************************/ +#ifdef __rtems__ +#define SDRAM_START_ADDRESS ((uintptr_t) atsam_memory_sdram_begin) +#define SDRAM_END_ADDRESS ((uintptr_t) atsam_memory_sdram_end - 1) +#else /* !__rtems__ */ #define SDRAM_START_ADDRESS 0x70000000UL #define SDRAM_END_ADDRESS 0x7FFFFFFFUL +#endif /* __rtems__ */ /******* QSPI macros ***************************/ +#ifdef __rtems__ +#define QSPI_START_ADDRESS ((uintptr_t) atsam_memory_qspiflash_begin) +#define QSPI_END_ADDRESS ((uintptr_t) atsam_memory_qspiflash_end - 1) +#else /* !__rtems__ */ #define QSPI_START_ADDRESS 0x80000000UL #define QSPI_END_ADDRESS 0x9FFFFFFFUL +#endif /* __rtems__ */ /************** USBHS_RAM region macros ******************/ #define USBHSRAM_START_ADDRESS 0xA0100000UL diff --git a/c/src/lib/libbsp/arm/atsam/startup/linkcmds.memory.in b/c/src/lib/libbsp/arm/atsam/startup/linkcmds.memory.in index d304031f01..de4d818283 100644 --- a/c/src/lib/libbsp/arm/atsam/startup/linkcmds.memory.in +++ b/c/src/lib/libbsp/arm/atsam/startup/linkcmds.memory.in @@ -8,6 +8,8 @@ MEMORY { QSPIFLASH : ORIGIN = 0x80000000, LENGTH = @ATSAM_MEMORY_QSPIFLASH_SIZE@ } +/* Must be used only for MPU definitions */ + atsam_memory_itcm_begin = ORIGIN (ITCM); atsam_memory_itcm_end = ORIGIN (ITCM) + LENGTH (ITCM); atsam_memory_itcm_size = LENGTH (ITCM); |