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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-04-19 13:50:34 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2013-04-23 09:59:56 +0200 |
| commit | e79e9048be54ee612f9410e863aa46fd83639e1a (patch) | |
| tree | f1e70f4aa01b2c7b9cae11c2c1bf0093ab7dd11e | |
| parent | bsp/mpc5200: Change ADREN register defines (diff) | |
| download | rtems-e79e9048be54ee612f9410e863aa46fd83639e1a.tar.bz2 | |
bsp/mpc5200: Move comment
| -rw-r--r-- | c/src/lib/libbsp/powerpc/gen5200/start/start.S | 10 |
1 files changed, 9 insertions, 1 deletions
diff --git a/c/src/lib/libbsp/powerpc/gen5200/start/start.S b/c/src/lib/libbsp/powerpc/gen5200/start/start.S index 3d57dc924d..35e9390d7f 100644 --- a/c/src/lib/libbsp/powerpc/gen5200/start/start.S +++ b/c/src/lib/libbsp/powerpc/gen5200/start/start.S @@ -154,6 +154,14 @@ /* Some fixed values for MPC5x00 registers */ .set CSBOOTROM_VAL, 0x0101D910 .set CSCONTROL_VAL, 0x91000000 + +/* + * The DDR_MODE bit is a read-only status and should be written as 0. + * + * XLB_CLK = FVCO / 4 + * IPB_CLK = XLB_CLK / 2 + * PCI_CLK = IPB_CLK + */ .set CFG_VAL, 0x00000100 .extern boot_card @@ -274,7 +282,7 @@ start: LWI r30, CFG_VAL /* get CFG register content */ - lwz r30, CFG(r31) /* set SDRAM single data rate / XLB_CLK=FVCO/4 / IPB_CLK=XLB_CLK/2 / PCICLK=IPB_CLK */ + lwz r30, CFG(r31) /* set CFG register */ |