rtems: Use size_t for cache line size

A cache line cannot have a negative size.

5 files changed, 8 insertions, 8 deletions

diff --git a/c/src/lib/libcpu/bfin/network/ethernet.c b/c/src/lib/libcpu/bfin/network/ethernet.c
index 873d105250..8903e0355a 100644
--- a/c/src/lib/libcpu/bfin/network/ethernet.c
+++ b/c/src/lib/libcpu/bfin/network/ethernet.c
@@ -629,7 +629,7 @@ static void initializeHardware(struct bfin_ethernetSoftc *sc) {
      including other status structures, so we can safely manage both the
      processor and DMA writing to them.  So this rounds up the structure
      sizes to a multiple of the cache line size. */
-  cacheAlignment = rtems_cache_get_data_line_size();
+  cacheAlignment = (int) rtems_cache_get_data_line_size();
   if (cacheAlignment == 0)
      cacheAlignment = 1;
   rxStatusSize = cacheAlignment * ((sizeof(rxStatusT) + cacheAlignment - 1) /
diff --git a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c
index fc144e3e24..3b9d06ff60 100644
--- a/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c
+++ b/c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_alignment.c
@@ -21,7 +21,7 @@ int ppc_exc_alignment_handler(BSP_Exception_frame *frame, unsigned excNum)
 
   /* Do we have a dcbz instruction? */
   if ((opcode & 0xffe007ff) == 0x7c0007ec) {
-    unsigned clsz = (unsigned) rtems_cache_get_data_line_size();
+    unsigned clsz = rtems_cache_get_data_line_size();
     unsigned a = (opcode >> 16) & 0x1f;
     unsigned b = (opcode >> 11) & 0x1f;
     unsigned *regs = &frame->GPR0;
diff --git a/c/src/lib/libcpu/shared/src/cache_manager.c b/c/src/lib/libcpu/shared/src/cache_manager.c
index c2c460a0d6..8fa0477748 100644
--- a/c/src/lib/libcpu/shared/src/cache_manager.c
+++ b/c/src/lib/libcpu/shared/src/cache_manager.c
@@ -149,7 +149,7 @@ rtems_cache_invalidate_entire_data( void )
 /*
  * This function returns the data cache granularity.
  */
-int
+size_t
 rtems_cache_get_data_line_size( void )
 {
 #if defined(CPU_DATA_CACHE_ALIGNMENT)
@@ -264,7 +264,7 @@ rtems_cache_invalidate_entire_instruction( void )
 /*
  * This function returns the instruction cache granularity.
  */
-int
+size_t
 rtems_cache_get_instruction_line_size( void )
 {
 #if defined(CPU_INSTRUCTION_CACHE_ALIGNMENT)
diff --git a/cpukit/rtems/include/rtems/rtems/cache.h b/cpukit/rtems/include/rtems/rtems/cache.h
index a8520d7e4e..2faf620e24 100644
--- a/cpukit/rtems/include/rtems/rtems/cache.h
+++ b/cpukit/rtems/include/rtems/rtems/cache.h
@@ -47,7 +47,7 @@ extern "C" {
  * @retval 0 No data cache is present.
  * @retval positive The data cache line size in bytes.
  */
-int rtems_cache_get_data_line_size( void );
+size_t rtems_cache_get_data_line_size( void );
 
 /**
  * @brief Returns the instruction cache line size in bytes.
@@ -58,7 +58,7 @@ int rtems_cache_get_data_line_size( void );
  * @retval 0 No instruction cache is present.
  * @retval positive The instruction cache line size in bytes.
  */
-int rtems_cache_get_instruction_line_size( void );
+size_t rtems_cache_get_instruction_line_size( void );
 
 /**
  * @brief Flushes multiple data cache lines.
diff --git a/testsuites/sptests/spcache01/init.c b/testsuites/sptests/spcache01/init.c
index d9eb05327a..f3028371b6 100644
--- a/testsuites/sptests/spcache01/init.c
+++ b/testsuites/sptests/spcache01/init.c
@@ -165,7 +165,7 @@ static void test_timing(void)
   uint64_t d[3];
 
   printf(
-    "data cache line size %i bytes\n",
+    "data cache line size %zi bytes\n",
     rtems_cache_get_data_line_size()
   );
 
@@ -290,7 +290,7 @@ static void test_timing(void)
   );
 
   printf(
-    "instruction cache line size %i bytes\n",
+    "instruction cache line size %zi bytes\n",
     rtems_cache_get_instruction_line_size()
   );