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| author | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-19 14:45:47 +0200 |
|---|---|---|
| committer | Sebastian Huber <sebastian.huber@embedded-brains.de> | 2018-07-25 10:07:43 +0200 |
| commit | dda6e06edb366812659652e1c8d93660c76973df (patch) | |
| tree | 0446e26d7fe12e24d298217c7a11b1c65dccb631 | |
| parent | bsp/riscv: Add and use riscv_fdt_get_address() (diff) | |
| download | rtems-dda6e06edb366812659652e1c8d93660c76973df.tar.bz2 | |
bsp/riscv: Add reset via for SiFive Test Finisher
Update #3433.
| -rw-r--r-- | bsps/riscv/riscv/start/bsp_fatal_halt.c | 23 |
1 files changed, 18 insertions, 5 deletions
diff --git a/bsps/riscv/riscv/start/bsp_fatal_halt.c b/bsps/riscv/riscv/start/bsp_fatal_halt.c index 5c81cac539..af9e2ac7c6 100644 --- a/bsps/riscv/riscv/start/bsp_fatal_halt.c +++ b/bsps/riscv/riscv/start/bsp_fatal_halt.c @@ -1,8 +1,8 @@ -/* @ingroup riscv_generic - * @brief riscv_generic BSP Fatal_halt handler. +/* + * Copyright (c) 2018 embedded brains GmbH * - * Copyright (c) 2015 University of York. - * Hesham Almatary <hesham@alumni.york.ac.uk> + * Copyright (c) 2015 University of York. + * Hesham Almatary <hesham@alumni.york.ac.uk> * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -27,14 +27,27 @@ */ #include <bsp/riscv.h> +#include <bsp/fdt.h> + +#include <libfdt.h> void _CPU_Fatal_halt(uint32_t source, uint32_t error) { + const char *fdt; + int node; + volatile uintptr_t *sifive_test; + #if RISCV_ENABLE_HTIF_SUPPORT != 0 htif_poweroff(); #endif + fdt = bsp_fdt_get(); + node = fdt_node_offset_by_compatible(fdt, -1, "sifive,test0"); + sifive_test = riscv_fdt_get_address(fdt, node); + while (true) { - /* Do nothing */ + if (sifive_test != NULL) { + *sifive_test = 0x5555; + } } } |